Power supply device

Abstract

When a current is supplied to a load 1 from a driving power supply VB via a FET 4a, an I / V conversion circuit 6 converts a current based on the current into a voltage by energizing a detection resistor. An A / D converter 12 converts the voltage converted by the I / V conversion circuit 6 into a data value. When the calculated value based on the data value exceeds a threshold, an output control unit 15 performs a protection operation for stopping the supply of current to the load 1 by the FET 4a. A sink-side current source unit 16 is configured so that an offset current Ioffset can be superimposed in multiple stages with respect to a current flowing in the detection resistor.

Description

power supply device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2023-107120, filed on June 29, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a power supply apparatus including a power device that supplies current from a driving power supply to a load.

[0003] For example, Patent Documents 1 and 2 propose methods for implementing a fuse function using a semiconductor switch to protect a wire harness and a load. Hereinafter, such a protection function may be referred to as eFuse control. To achieve eFuse control, a large current must be interrupted in a short time due to the thermal time constant of the wire harness. On the other hand, to reduce costs by using thinner wires in the harness, it is necessary to improve the accuracy of current detection near the limit current that can steadily flow through the harness.

[0004] Patent No. 4624400 Patent No. 4762044

[0005] To improve current detection accuracy, one approach involves providing two types of I / V conversion resistors for the output used to monitor the current flowing through a semiconductor switch and switching them depending on the current range. In this case, the current measurement resolution decreases in the current range where measurement is required by switching from high resistance to low resistance, resulting in the need for protection by shutting off the fuse earlier than the ideal fusing characteristic. Furthermore, for the high resistance side, a resistance value must be selected that ensures current detection accuracy near the current that can steadily flow through the harness. Due to the reduced measurement resolution and A / D conversion error in the low load current range, it is difficult to determine the quality of the load and grasp the load status, such as wake-up / sleep. However, increasing the number of resistor values ​​as a solution to this problem increases costs.

[0006] The present disclosure has been made in consideration of the above circumstances, and an object of the present disclosure is to provide a power supply device that can improve the resolution of current detection while suppressing an increase in cost.

[0007] According to the power supply device disclosed herein, when a current is supplied from a drive power supply (VB) to a load via a power device, an I / V conversion circuit converts a current based on the current into a voltage by passing it through a detection resistor. The power device is a semiconductor element capable of switching relatively large amounts of power and constituting a power conversion circuit such as an inverter. The data converter converts the voltage converted by the I / V conversion circuit into a data value based on predetermined characteristics. If a calculated value based on the data value exceeds a threshold, the protection operation unit performs a protection operation to stop the power device from supplying current to the load. The multiple sink-side current sources are configured to be able to superimpose an offset value on the current passed through the detection resistor in multiple stages.

[0008] With this configuration, by varying the offset value applied to the current flowing through the detection resistor by the multiple sink-side current sources, the voltage input to the data converter can be further reduced, thereby making it possible to virtually improve the resolution of data conversion in the data converter.

[0009] Furthermore, according to the power supply device of the present disclosure, the plurality of sink-side current sources are set at the boundary for switching the offset value so that the voltage converted by the I / V conversion circuit before and after the switching falls within the input range of the data converter. As a result, if the output characteristics of the sink-side current sources become nonlinear in a region where the voltage converted by the I / V conversion circuit is small by adding an offset value, the offset value can be switched to a smaller value so that the output characteristics of the sink-side current sources become linear, thereby making the output characteristics linear across the entire output characteristics.

[0010] Furthermore, according to the power supply device of the present disclosure, the difference between the data values ​​when switching between the plurality of sink-side current sources is stored in advance in the storage unit. When switching between the plurality of sink-side current sources, the control unit reads the corresponding difference value from the storage unit and subtracts it. This simplifies the calculation process when switching between the sink-side current sources to be used.

[0011] According to the power supply device of the present disclosure, the I / V conversion circuit is configured to be able to switch between energizing two or more detection resistors with different resistance values. First, a first data conversion is performed with no offset value applied and with the detection resistor with the lowest resistance energized. Then, a second data conversion is performed with a detection resistor with a higher resistance than the detection resistor selected based on the results of the first data conversion energized. The offset value to be superimposed is determined based on the results of the previous data conversion. This allows current detection to be performed with high accuracy through at most two data conversions.

[0012] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is a diagram showing the configuration of a power supply device in a first embodiment, Fig. 2 is a diagram showing an offset current Ioffset applied depending on the on / off states of switches SW1 to SW4, Fig. 3 is a diagram showing the relationship between the load current and the A / D conversion value when the resistance value of the I / V conversion circuit is only low resistance, Fig. 4 is a diagram showing the relationship between the load current and the A / D conversion value when the resistance value of the I / V conversion circuit is switchable between low resistance and high resistance, and Fig. 5 is a diagram showing the relationship between the load current and the A / D conversion value when the resistance value of the I / V conversion circuit is switched and the offset current Ioffset is applied depending on the on / off states of switches SW1 to SW4. 6 is a diagram showing the configuration of a power supply device in a second embodiment; FIG. 7 is a diagram showing the offset current Ioffset applied depending on the on / off states of switches sw1 to sw4; FIG. 8 is a diagram showing the configuration of a power supply device in a third embodiment; FIG. 9 is a diagram showing the relationship between the load current via a constant current circuit and the A / D conversion value; and FIG. 10 is a diagram showing the relationship between the load current Ioffset applied depending on the on / off states of switches sw1 to sw4 and the A / D conversion value when the resistance value of the I / V conversion circuit is switched. 11 is a flowchart showing the processing contents of the control unit in the fourth embodiment; FIG. 12 is a diagram showing the relationship between the load current and the A / D conversion value when the resistance value of the I / V conversion circuit is switched and the value of the offset current Ioffset is switched; FIG. 13 is a diagram showing the configuration of a power supply device in the fifth embodiment; FIG. 14 is a diagram showing the relationship between the load current and the A / D conversion value when a positive offset current is superimposed on the sense MOS; 16 is a diagram showing the relationship between the load current and the A / D conversion value when the resistance value of the I / V conversion circuit is switched and the value of the offset current Ioffset is switched; FIG. 17 is a diagram (part 1) showing the configuration of a power supply device in the sixth embodiment; FIG. 18 is a diagram (part 2) showing the configuration of the same power supply device; FIG. 19 is a flowchart showing the processing content of the control unit; and FIG. 20 is a diagram (part 3) showing the configuration of a power supply device in the seventh embodiment.FIG. 22 is a diagram showing an example of a table used to determine the type of IPD; FIG. 23 is a diagram (part 2) showing the configuration of the power supply device; FIG. 24 is a flowchart showing the processing by the control unit in the eighth embodiment; FIG. 25 is a diagram explaining the process of correcting the A / D conversion result by applying a linear function; FIG. 26 is a diagram showing the configuration of the power supply device in the ninth embodiment; and FIG. 27 is a flowchart showing the processing by the control unit.

[0013] First Embodiment As shown in FIG. 1 , a power supply device according to this embodiment supplies current to a load 1, one end of which is connected to ground, from a power source VB via an IPD 2 and a harness 3. The IPD 2 has N-channel MOSFETs 4a and 4b, each of which has a drain connected to the power source VB and a gate connected in common. The source of FET 4a, an example of a power device, is connected to the load 1 via the harness 3, while the source of FET 4b is connected to ground via a P-channel MOSFET 5 and an I / V conversion circuit 6. The source of FET 4b, together with the source of FET 5, is connected to the inverting input terminal of an operational amplifier 7, the non-inverting input terminal of which is connected to the source of FET 4a. FETs 4a and 4b form a transistor pair 4. FET 4b is a so-called sense MOS, and FETs 4b and 5, along with the operational amplifier 7, form a current output circuit 8.

[0014] The I / V conversion circuit 6 is composed of a combination of seven resistance elements, each of which is a resistor for detecting a resistance value R, and a P-channel MOSFET 9. A series circuit of two resistance elements R is connected between the source of FET 4b and ground. A series circuit of two resistance elements R and a MOSFET 9 is connected in parallel to this series circuit. In addition, three resistance elements R are connected in parallel to the two resistance elements R. The gates of the transistor pair 4 and FET 9 are driven by the control unit 11. The resistance value of the I / V conversion circuit 6 is 2R when FET 9 is off, and R / 4 when FET 9 is on. Hereinafter, the former may be referred to as "high resistance" and the latter as "low resistance."

[0015] Inside the control unit 11, an A / D converter 12, an eFuse (I ２ , t) characteristic calculation unit 13, interruption determination unit 14, and output control unit 15 are connected in series. The input terminal of an A / D converter 12, which is an example of a data converter, is connected to a common connection point of the IPD 2 and the I / V conversion circuit 6. The data converted by the A / D converter 12 is stored in an eFuse (I ２ , t) are input to the characteristic calculation unit 13. The calculation result of the calculation unit 13 is input to the trip determination unit 14, and the determination result of the trip determination unit 14 is input to the output control unit 15.

[0016] eFuse (I ２ , t) The characteristics calculation unit 13 calculates and outputs the data converted by the A / D converter 12 based on data proportional to the square of the detected current, as in the "multiplication circuit 200" shown in Figure 1 of Japanese Patent Laid-Open No. 2023-18957. This is based on the fact that the smoking time t of the harness 3 has a characteristic that depends on the square of the current flowing through it, as described in the publication.

[0017] The shutdown determination unit 14 compares the data calculated as described above with a threshold value to determine whether to issue a shutdown instruction. The output control unit 15 drives the gates of the transistor pair 4 of the IPD 2 in response to an output instruction input from a higher-level control device (not shown). When a shutdown instruction is input from the shutdown determination unit 14, the output control unit 15, which corresponds to a protection operation unit, turns off the transistor pair 4.

[0018] A sink-side current source unit 16 is connected between the input terminal of the A / D converter 12 and the ground. The sink-side current source unit 16 has a series circuit in which a sink-side current source I is connected to each of the switches SW1 to SW4. The on / off control of the FET 9 and the switches SW1 to SW4 is performed by an eFuse (I ２ , t) are performed by the characteristic calculation unit 13. The power supply device 17 is made up of the components described above excluding the harness 3 and the load 1.

[0019] Next, the operation of this embodiment will be described. In the sink-side current source unit 16, the offset current that flows to ground due to the operation of the current source I is defined as Ioffset. The current Ioffset reduces the current that flows from the IPD 2 to ground via the I / V conversion circuit 6. As shown in FIG. 2, by selectively turning on switches SW1 to SW4, the current Ioffset varies within the range of -I to -4I.

[0020] As shown in Figure 3, in the load current-I / V conversion characteristics when the current Ioffset is not flowing and the I / V conversion circuit 6 is in a low resistance state, in region (1) where the load current value is small, it is difficult to determine whether the load is good or bad and whether it is in a wake-up or sleep state due to the influence of errors caused by A / D conversion. Furthermore, in region (2), the current measurement resolution is low, so it becomes necessary to perform protective operation by shutting off the IPD 2 earlier than the ideal fusing characteristic of the harness 3. Region (3) indicates the current value that can steadily flow through the harness 3. Note that the numbers in parentheses correspond to the circled numbers in the figure.

[0021] If the characteristics when the I / V conversion circuit 6 is in a high resistance state are added to those in Figure 3, they become as shown in Figure 4. In this way, even when switched to a high resistance state, it is necessary to select a resistance value so that the current detection accuracy in the vicinity of region (3) can be ensured.

[0022] When the current Ioffset is changed as in this embodiment, the load current-I / V conversion characteristics are as shown in Figure 5. Here, if the load current is IL, the monitor current flowing to the I / V conversion circuit 6 side is IS, and the current ratio of the I / V conversion circuit 6 is KILIS, the relationship between the currents IL and IS is (IL = KILIS x IS). If the voltage generated in the I / V conversion circuit 6 is Vs, when the I / V conversion circuit 6 is selected on the high resistance side, Vs = (IL / KILIS + Ioffset) x 2R. When the I / V conversion circuit 6 is selected on the low resistance side, Vs = (IL / KILIS + offset) x R / 4. If the upper limit current for detection is ILMAX, Vs = (ILMAX / KILIS) x R / 4 = V_ADMAX.

[0023] If the offset current Ioffset is not added, the load current IL can only be detected in the range of IL = 0 to 0.125 / ILMAX. In contrast, in this embodiment, the current I of the current source is set to (= V_ADMAX / 2R), the I / V conversion circuit 6 is selected on the high resistance side, and the offset current Ioffset is increased in stages from 0 to -I, -2I, and -3I.

[0024] When the current Ioffset is set to -I, the load current IL can be detected in the range of IL = 0.125 × ILMAX to 0.25 × ILMAX. Furthermore, when the current Ioffset is set to -2I or -3I, the range of IL = 0.25 × ILMAX to 0.5 × ILMAX can be detected, and when the current Ioffset is set to -4I, the range of 0.75 × ILMAX can be detected. In other words, while the conventional method only provided four times the resolution when switching to low resistance in the range of IL = 0 to 0.25 × ILMAX, the method of this embodiment can increase the current detection resolution to eight times in all of regions (1) to (3), thereby reducing the impact of errors in the A / D converter 12.

[0025] As described above, according to this embodiment, when current is supplied from drive power supply VB to load 1 via FET 4a and harness 3, I / V conversion circuit 6 converts a current based on that current into a voltage by passing a current through a detection resistor. A / D converter 12 converts the voltage converted by I / V conversion circuit 6 into a data value. When a calculated value based on the data value exceeds a threshold, output control unit 15 performs a protective operation to stop current supply to load 1 by FET 4a. Then, sink-side current source unit 16 is configured to be able to superimpose an offset current Ioffset on the current passed through the detection resistor in multiple stages.

[0026] With this configuration, by varying the current Ioffset applied to the current flowing through the detection resistor using the multiple current sources I, it is possible to further reduce the voltage input to the A / D converter 12. This makes it possible to virtually improve the resolution of data conversion in the A / D converter 12.

[0027] Second Embodiment Hereinafter, the same components as those in the first embodiment will be denoted by the same reference numerals, and a description thereof will be omitted, and only the differences will be described. As shown in FIG. 6, a power supply device 21 of the second embodiment includes a sink-side current source section 22 instead of the sink-side current source section 16. In the sink-side current source section 22, sink-side current sources I, 2I, 4I, and 8I are connected to switches sw1 to sw4, respectively. With this configuration, as shown in FIG. 7, by changing the on / off states of switches sw1 to sw4 to correspond to 4-bit data of "1 to 15," the current Ioffset can be changed in the range of "-I to -15I" accordingly.

[0028] Third Embodiment As shown in FIG. 8 , a power supply device 23 of the third embodiment includes a sink-side current source unit 24 instead of the sink-side current source unit 16. The sink-side current source unit 24 is composed of four current sources Iδ, each with a constant current value Iδ = (I-δ). Here, δ is the voltage Vsat obtained by adding the on-resistance of FET 4b to the minimum resistance value of the I / V conversion circuit 6 and multiplying the result by the current flowing therethrough. When the potential of the ground to which the I / V conversion circuit 6 is connected is displaced higher than 0 V, the displaced voltage is Vdiff, and the result is set as follows: δ > (Vsat + Vdiff) / (2R). The constant current value I is (= V_ADMAX / 2R), the same as in the first embodiment.

[0029] Generally, a constant current circuit such as the current output circuit 8 cannot operate at a constant current in a region where the input voltage is low, due to the on-resistance and saturation voltage of the transistors and the voltage generated in the ground-side resistors as described above, as shown in Fig. 9. Therefore, by setting each current source Iδ of the sink-side current source section 24 to (I-δ) and overlapping the range below the voltage Vsat as shown in Fig. 10, it becomes possible to convert to a voltage in a region where everything is linear by switching the current Ioffset to 0, -Iδ, -2Iδ, -3Iδ, ...

[0030] (Fourth Embodiment) As shown in FIG. 11, the fourth embodiment shows the control details of the control unit 11. When processing starts, the resistance value of the I / V conversion circuit 6 is set to the low side (R / 4) (S1), and A / D conversion is performed with a current Ioffset of 0 (S2). This corresponds to the first data conversion. The A / D conversion result is then compared with each of the conversion values ​​adl4 to adl1 shown in FIG. 12, and it is determined whether or not each of the conversion values ​​adl4 to adl1 is equal to or greater than the corresponding one (S3 to S6).

[0031] If the A / D conversion result is equal to or greater than the conversion value adl4 (S3; Yes), it belongs to the current region E (IL4 to ILMAX) shown in Fig. 12. If the ratio between the low resistance value and the high resistance value of the I / V conversion circuit 6 is KR, the A / D conversion result is multiplied by KR to obtain the final digital value corresponding to the detected current (S19). In the fourth embodiment, KR = 8. Note that the "case of ideal characteristics" shown in the figure ignores, for simplicity of explanation, the case where the conversion characteristics become nonlinear in the low current region, as in the third embodiment.

[0032] If the A / D conversion result is less than the conversion value adl1 (S5; No), the current falls within current range A (0 to IL1), and the resistance of the I / V conversion circuit 6 is switched to the higher resistance of 2R (S7), and A / D conversion is performed as in step S2 (S8). The A / D conversion result is then used as the final digital value (S9). If the A / D conversion result is less than the conversion value adl2 but greater than or equal to the conversion value adl1 (S5; Yes), the current falls within current range B (IL1 to IL2), and processing similar to step S7 is performed (S10), followed by A / D conversion with a current Ioffset = -I (S11). The A / D conversion result is then subtracted by the conversion value adh1 corresponding to the high resistance value of 2R from the conversion value adl1, and the result is added to the highest conversion value ADMAX to create a digital value that continues into current range A (S12).

[0033] If the A / D conversion result is equal to or greater than the conversion value adl2 and less than the conversion value adl3 (S6; No), it belongs to current region C (IL2 to IL3), and the same process as in step S7 is performed (S13), and A / D conversion is performed with a current Ioffset of -2I (S14).Then, from the A / D conversion result, the conversion value adh1 and the conversion value adl2 are subtracted by the conversion value adh2 corresponding to the high resistance value 2R, and the result is added to twice the maximum conversion value ADMAX, thereby creating a digital value that continues into current region B (S15).

[0034] If the A / D conversion result is less than conversion value adl4 and greater than or equal to conversion value adl3 (S6; Yes), it belongs to current region D (IL3-IL4), and the same process as in step S7 is performed (S16), followed by A / D conversion with a current Ioffset of -3I (S17). Then, from the A / D conversion result, conversion values ​​adh1 and adh2, and conversion value adl3 are subtracted by conversion value adh3 corresponding to the high resistance value 2R, and the result is added to a value three times the maximum conversion value ADMAX, thereby creating a digital value that continues into current region C (S15). Steps S8, S11, S14, and S17 correspond to the second data conversion.

[0035] The digital value in step S19, the A / D conversion result at low resistance multiplied by KR, is equal to the result of subtracting the conversion values ​​adh1 to adh3 from four times the maximum conversion value ADMAX, then subtracting the conversion value adl1 from the A / D conversion result at low resistance, and multiplying this result by KR. The conversion values ​​adh1 to adh3 are the differences in the A / D conversion values ​​when the sink-side current source unit 16 switches the current Ioffset to transition between current regions A to C, and these are stored in advance in a memory unit 11M (not shown) provided in the control unit 11.

[0036] As described above, according to the fourth embodiment, the A / D conversion values ​​adl1 to adl4 obtained when the I / V conversion circuit 6 is set to a low resistance value are pre-stored. The actual A / D conversion results are compared with these values ​​to separate current ranges A to E. For current ranges A to D, the I / V conversion circuit 6 is switched to a high resistance value and A / D conversion is performed again. Furthermore, the conversion values ​​adh1 to adh3 corresponding to the A / D conversion values ​​adl1 to adl3 obtained when the I / V conversion circuit 6 is set to a low resistance value are also pre-stored. The conversion values ​​adh1 to adh3 are subtracted from the result of the second A / D conversion to obtain a final digital value. This allows for a pseudo-enhancement of the conversion resolution in current ranges A to D by performing A / D conversion up to two times. Here, exception handling is omitted in steps S11 and S17. However, if the input voltage exceeds the upper limit of the input voltage of the A / D converter 12, a digital value may be obtained using the method of step S19.

[0037] (Fifth embodiment) As shown in Fig. 13, a power supply device 25 of the fifth embodiment includes a source-side current source 26 and a sink-side current source 27 as correction current supply sources in a control unit 11C. The source-side current source 26 is connected between a power supply VB and an input terminal of an A / D converter 12, and the sink-side current source 27 is connected between the input terminal and ground. Both of the current sources 26 and 27 are configured so that the constant current value can be changed. This change is controlled by an eFuse (I ２ , t) are performed by the characteristic calculation unit 13.

[0038] In the IPD 2, when a positive offset current Ioffset_IPD is superimposed on the FET 4b, which is a sense MOS, the relationship between the load current IL and the monitor current output IS is IL = KILIS × IS + Ioffset_IPD. Therefore, as shown by the dashed line in Figure 14, when the resistance value of the I / V conversion circuit 6 is high, 2R, an offset voltage (Ioffset_IPD × 2R) is generated when the load current IL = 0 A, and the dynamic range is compressed.

[0039] In contrast to this, if the offset voltage is reduced by adjusting the sink current Ioffset_trim to (≈-Ioffset_IPD) using the sink-side current source 27, which has an adjustable constant current value, the dynamic range can be expanded.

[0040] Furthermore, if a negative offset current Ioffset_IPD is superimposed on FET 4b, the relationship between the load current IL and the monitor current output IS is expressed as follows: IL = KILIS × IS - Ioffset_IPD. Therefore, as shown by the dashed line in FIG. 15, the A / D conversion value is nearly zero when the load current IL is in the range of 0 A to Ioffset_IPD, and even when the load current IL is greater than that, the A / D conversion value is lower than the intended value. This results in a shift in the protection function for preventing burnout due to overcurrent in the harness 3, making it less effective. Therefore, by adjusting the source current Ioffset_trim to (≈ -Ioffset_IPD) using the source-side current source 26, which has an adjustable constant current value, the protection function of the harness 3 can be maintained without degradation.

[0041] Furthermore, when controlling the current value of the sink-side current source unit 16 to -I, -2I, ..., if variations such as -I+α, -2I+β, ... occur in the I value of each current source, the value of Ioffset_trim in the sink-side current source 27 is dynamically controlled to -Ioffset_IPD, -Ioffset_IPD-α, -Ioffset_IPD-β, ... to absorb the variations. This prevents the occurrence of a region that cannot be correctly converted to a digital value, as shown by (4) in Figure 16, and expands the current range in which the load current IL can be detected with high resolution. Note that the sink-side current source 27 and the sink-side current source unit 16 may be adjusted in cooperation with each other, or the adjustment steps of the sink-side current source unit 16 may be set finely to accommodate such variations.

[0042] 17 and 18, power supply devices 28I and 28R of the sixth embodiment include source-side current supply sources 29I and 29R as correction current supply sources in control units 11I and 11R, respectively. The source-side current supply source 29I is configured with a series circuit of a current source 30 and a switch 31 connected between a power supply VB and ground, and the source-side current supply source 29R is configured by replacing the current source 30 with a resistance element 32. The on / off control of the switch 31 is performed by an eFuse (I ２ , t) are performed by the characteristic calculation unit 13.

[0043] Next, the operation of the sixth embodiment will be described. As shown in FIG. 19, processing begins in a self-check mode with the output control unit 15 turning off the IPD 2 or putting it in standby mode. First, the switch 31 of the source-side current supply source 29I or 29R is turned on to pass current through the resistive element of the I / V conversion circuit 6 (S21). It is desirable to initially set the resistance value of the I / V conversion circuit 6 to the low resistance side. Then, A / D conversion is performed by the A / D converter 12, and the resistance value that can be read from the conversion result is determined (S22).

[0044] If the determined resistance value is equal to or greater than the upper threshold (S23; Yes), it is suspected that the I / V conversion circuit 6 is open or shorted to the power supply, and therefore it is determined to be abnormal (S30). Then, for example, a command to execute a diagnosis is sent to a higher-level control device, or the IPD 2 is maintained in the off state (S31).

[0045] If the determined resistance value is equal to or less than the lower threshold value (S24; Yes), a ground fault is suspected in the connection of the I / V conversion circuit 6, and therefore a determination is made that an abnormality has occurred (S28). Then, the same process as in step S31 is performed (S29). On the other hand, if the determined resistance value exceeds the lower threshold value (S24; No), the circuit is determined to be normal (S25). Then, if a start condition is met, for example, by a command from a higher-level control device (S26; Yes), the IPD 2 is turned on and eFuse control is initiated (S27).

[0046] In this way, by determining the resistance value when a source current is passed through the I / V conversion circuit 6 via the source-side current supply source 29 with the IPD 2 turned off, it is possible to determine whether the connection of the I / V conversion circuit 6 is normal or abnormal. Furthermore, the resistance value of the I / V conversion circuit 6 is first set to low resistance and the above determination is made. If the determination result is normal, the resistance value is switched to high resistance and a similar determination is made. By comparing the first A / D conversion result after switching to high resistance with the A / D conversion result at low resistance, it is possible to determine whether the former A / D conversion result is appropriate. If there is an abnormality, only the connection on the high resistance side can be determined to be abnormal.

[0047] 20 , a power supply device 33 of the seventh embodiment is a combination of the control unit 11I of the sixth embodiment and an I / V conversion circuit 6A. The I / V conversion circuit 6A includes a resistor R1 as a detection resistor and a resistor R2 connected together with an FET 9, and is configured to switch the resistance value between R1 and a parallel value R1 / / R2 of R1 and R2. In the seventh embodiment, the type of IPD 2 connected to the I / V conversion circuit 6A is determined based on the resistance values ​​of the resistors R1 and R2.

[0048] Next, the operation of the seventh embodiment will be described. As shown in Figure 21, when processing is started in the self-check mode under the same conditions as in the sixth embodiment, the resistance value of the I / V conversion circuit 6A is switched to the high resistance R1 (S41). The switch 31 of the source-side current supply source 29I is turned on to pass current through the resistive element of the I / V conversion circuit 6 (S42). Then, A / D conversion is performed by the A / D converter 12, and the conversion result is obtained as resistance value data ValR1 (S43).

[0049] Next, the resistance value of the I / V conversion circuit 6A is switched to the low resistance side R1 / / R2 (S44), and A / D conversion is performed by the A / D converter 12, and the conversion result is obtained as resistance value data ValR1_R2 (S45). Then, a control parameter is set based on the combination of the resistance value data ValR1 and ValR1_R2 (S46).

[0050] The control unit 11I holds a data table for determining the type of IPD 2, such as that shown in FIG. 22. This figure also shows an example of the determination method used in step S46. For example, if the resistance value R1 is 6.55 kΩ or less, the IPD 2 part number corresponds to "1, 2." Furthermore, if the resistance values ​​R1 / R2 are 0.97 kΩ or less, the IPD 2 part number corresponds to "2, 3." From these results, part number "2" is identified. Since the resistance ratio KILIS for part number "2" is "1000," the resistance ratio KILIS = 1000 is set as a parameter used in eFuse control. Other control parameters include, for example, the wire harness size, allowable current, time constant of the interruption characteristics, and overcurrent threshold.

[0051] 21 may be performed when the power is turned on, and the default operation of turning the IPD 2 on or off at startup may be switched depending on the determined product number of the IPD 2. Furthermore, FIG. 23 shows a configuration using a control unit 35 in which a microcomputer 34 is added to the control unit 11I. In this case, the microcomputer 34 may be provided with a function for monitoring the output control unit 15, and parameters may be set to determine the operation to be performed when the microcomputer 34 detects an abnormality, such as forcing the IPD 2 on or off, or maintaining the previous operation. Furthermore, as shown in the sixth embodiment, a source-side current supply source 29R may be used instead of the source-side current supply source 29I.

[0052] 24, in the eighth embodiment, the connection state of the I / V conversion circuit 6 is determined in the same manner as in the sixth embodiment. After steps S28 and S30 are executed, it is determined whether the start-up conditions are met (S32), as in step S26. If the start-up conditions are met (Yes), for example, when correcting the A / D conversion result using a linear function, the intercept (offset) parameter Bh shown in FIG. 25 is changed to a value larger than the normally used value (S33).

[0053] When the IPD 2 subsequently starts to conduct current, the correction value of the A / D conversion result can be used to recognize that a large current is flowing, regardless of the actual load current IL. As a result, the eFuse control function or the power monitoring function operates in a short time to provide protection by cutting off the current, thereby safely protecting the load 1.

[0054] (Ninth Embodiment) The ninth embodiment is a variation of the eighth embodiment. As shown in Fig. 26, a normally closed switch 36 is inserted between the input terminal of the A / D converter 12 and the sink-side current source unit 16, and the source-side current source 29I of the sixth embodiment is connected to the common connection point between the input terminal and the switch 36. The on / off control of the switch 36 is performed by an eFuse (I ２ , t) is performed by the characteristics calculation unit 13. Then, as shown in Fig. 27, if the determination is "Yes" in step S32, the switch 36 is turned off and the switch 31 of the source side current source 29I is turned on (S34).

[0055] As a result, when the IPD 2 starts to conduct electricity thereafter, it is recognized that a large current is flowing regardless of the actual load current IL, as in the eighth embodiment. As a result, the eFuse control function or the power amount monitoring function operates in a short time to provide protection by cutting off the current, thereby safely protecting the load 1.

[0056] (Other embodiments) The resistance value in the I / V conversion circuit may be changed in three or more stages. Also, it is not necessary to change the resistance value. The number of current sources provided in the sink side current source section may be "3" or less or "5" or more. ２ , t) characteristic calculation unit 13 may be integrated to configure a data converter that outputs a conversion result according to the two-wire characteristic of the current. For example, the third embodiment may be applied to the second, fourth to ninth embodiments, and the like, and the applicable embodiments may be appropriately combined and implemented.

[0057] In addition to the inventions described in the claims, this application also includes the following inventions: [1] A power supply device comprising: a power device (4a) that supplies current to a load (1) from a drive power supply (VB); an I / V conversion circuit (6, 6A) that converts a current based on the current into a voltage by passing it through detection resistors (R, R1, R2) and detects the voltage; a data converter (12) that converts the voltage converted by the I / V conversion circuit into a data value based on predetermined characteristics; a protection operation unit (13-15) that performs a protection operation to stop the power device from supplying current to the load when a calculated value based on the data value exceeds a threshold; and multiple sink-side current sources (I, Iδ, 2I, 3I, 4I) that are configured to be able to superimpose offset values ​​on the current passed through the detection resistors in multiple stages. [2] The power supply device according to [1], wherein the multiple sink-side current sources (Iδ) are set so that the voltage converted by the I / V conversion circuit before and after switching the offset value falls within the input range of the data converter at the boundary for switching the offset value. [3] The power supply device according to [1] or [2], comprising: a storage unit (11M) in which a difference in data values ​​when switching the plurality of sink-side current sources is stored in advance; and a control unit (15) that reads the corresponding difference value from the storage unit and subtracts it when switching the plurality of sink-side current sources. [4] The power supply device according to any one of [1] to [3], wherein the I / V conversion circuit is configured to be able to switch between energizing two or more detection resistors with different resistance values, and when a first data conversion is performed without applying the offset value and with the detection resistor with the lowest resistance value energized, the power supply device determines an offset value to be superimposed on the offset value according to the result of the first data conversion when a second data conversion is performed with the detection resistor with a resistance higher than the detection resistor selected according to the result of the first data conversion energized. [5] The power supply device according to any one of [1] to [4], comprising: a current output circuit (8) that outputs a current proportional to a load current flowing through the power device, and comprising a correction current supply source for correcting an offset current generated in the current output circuit.[6] The power supply device according to any one of [1] to [5], further comprising a source-side current supply source (29I, 29R) for supplying current to the detection resistor while the power device is not supplying current to the load, wherein the control unit determines whether there is an abnormality in the detection resistor based on a result of data conversion associated with the supply of current. [7] The power supply device according to [6], further comprising a correction unit that corrects output data of the data converter, wherein the control unit sets a correction parameter for the correction unit so that the protection operation unit starts protection operation more quickly upon determining an abnormality in the detection resistor. [8] The power supply device according to [6], further comprising: a control unit that sets an input voltage of the data converter to a high potential upon determining an abnormality in the detection resistor. [9] The power supply device according to any one of [1] to [8], further comprising a source-side current supply source (29I, 29R) for supplying current to the detection resistor when the power device stops supplying current to the load, wherein the control unit determines the type of the connected power device based on the result of data conversion accompanying the power supply, and sets control parameters according to the determined type.

[0058] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. A power supply device comprising: a power device (4a) that supplies current to a load (1) from a drive power source (VB); an I / V conversion circuit (6, 6A) that converts a current based on the current into a voltage by passing it through detection resistors (R, R1, R2) and detects it; a data converter (12) that converts the voltage converted by the I / V conversion circuit into a data value based on a predetermined characteristic; a protection operation unit (13-15) that performs a protection operation to stop the supply of current to the load by the power device when a calculated value based on the data value exceeds a threshold value; and a plurality of sink-side current sources (I, Iδ, 2I, 3I, 4I) that are configured to be able to superimpose an offset value for the current passed through the detection resistor in multiple stages.

2. A power supply device as described in claim 1, wherein the plurality of sink side current sources (Iδ) are set so that at the boundary where the offset value is switched, the voltage converted by the I / V conversion circuit before and after switching falls within the input range of the data converter.

3. A power supply device as claimed in claim 1 or 2, further comprising: a memory unit (11M) in which the difference in data values ​​when switching between the plurality of sink side current sources is stored in advance; and a control unit (15) which, when switching between the plurality of sink side current sources, reads out the corresponding difference value from the memory unit and subtracts it.

4. A power supply device as claimed in claim 1 or 2, wherein the I / V conversion circuit is configured to be able to switch between passing current through two or more detection resistors having different resistance values, and when a first data conversion is performed with current passing through the detection resistor with the lowest resistance value without applying the offset value, and then a second data conversion is performed with current passing through a detection resistor with a higher resistance value than the detection resistor, selected in accordance with the result of the first data conversion, an offset value onto which the offset value is superimposed is determined in accordance with the result of the first data conversion.

5. A power supply device according to claim 1 or 2, further comprising a current output circuit (8) that outputs a current proportional to a load current flowing through the power device, and further comprising a correction current supply source for correcting an offset current generated in the current output circuit.

6. A power supply device as claimed in claim 1 or 2, further comprising a source-side current supply source (29I, 29R) for passing current through the detection resistor when the current flow through the power device to the load is stopped, and determining whether or not there is an abnormality in the detection resistor based on the result of data conversion associated with the current flow.

7. The power supply device according to claim 6, further comprising a correction section which corrects the output data of the data converter, and which sets a correction parameter of the correction section so that the protective operation section starts protective operation more quickly when an abnormality is detected in the detection resistor.

8. The power supply device according to claim 6, wherein, when an abnormality is detected in said detection resistor, the input voltage of said data converter is set to a potential higher than a normal input range.

9. A power supply device as claimed in claim 1 or 2, further comprising a source-side current supply source (29I, 29R) for passing current through the detection resistor when the power device is stopped from passing current through the load, wherein the control unit determines the type of the connected power device based on the result of data conversion associated with the current passing, and sets control parameters according to the determined type.

Images