Shift register unit, gate driving circuit, and display apparatus

Abstract

A shift register unit, a gate driving circuit, and a display apparatus. The shift register unit comprises an input module, a first control module, a second control module, a third control module, a first output module, a second output module, a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3). The input module controls the potential of a first node (N1), the first control module controls the potential of a second node (N2), the third control module controls the potential of a third node (N3), and a fourth control module controls the potentials of a fourth node (N4) and the second node (N2). The first capacitor (C1) is connected between the first node (N1) and an output end. The second capacitor (C2) is connected between the second node (N2) and a first voltage signal lead. The third capacitor (C3) is connected between the third node (N3) and the fourth node (N4). The potentials of the first node (N1) and the second node (N2) are independently updated without mutual pinning, so that correct and effective waveforms of output signals of the output end can be ensured.

Description

A shift register unit, gate drive circuit and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register unit, a gate drive circuit and a display device. Background Art

[0002] The display device includes not only a display panel, but also a gate drive circuit (also called a row drive circuit) and a source drive circuit (also called a column drive circuit) for controlling the display of the display panel having a pixel array. The display panel adopts a row-by-row scanning display mode, in which the gate drive circuit is used to generate a scanning signal to turn on each row of pixels in turn, and the source drive circuit is used to provide a data signal to it when a row of pixels is turned on to realize the display of the pixels.

[0003] The gate drive circuit includes a shift register, which includes multiple cascaded shift register units, where each level of the shift register unit is usually mainly composed of several transistors. By inputting the clock signal CK and the input signal IN / in (that is, the start pulse signal) into the circuit, a level signal (that is, the Gout signal) is output at the output end.

[0004] Chinese patent CN105989797A discloses a shift register unit. Figure 1 shows a schematic diagram of the on-off state of the shift register unit disclosed in Chinese patent CN105989797A at time t2', where "H" represents a high-level signal and "L" represents a low-level signal. Figure 2 shows a driving timing diagram of the shift register unit disclosed in Chinese patent CN105989797A. As shown in Figure 1, at time t2', the shift register unit outputs a low-level first clock signal CK1' through the eighth transistor T8'. Under normal circumstances, when the shift register unit enters time t3', the second clock signal CK2' turns on the fourth transistor T4' at a low level, and the first node N1' changes from the original high level to a low level, thereby turning on the fifth transistor T5' and the seventh transistor T7'. The second node N2' turns to a high level due to the turning on of the fifth transistor T5', and the eighth transistor T8' is turned off. The seventh transistor T7' turns on and outputs a high-level VDD' signal. However, if, at time t3', the impedance of the CK2' wiring is too large, or if the threshold voltages of the second and fourth transistors T2' and T4' shift after prolonged operation, the potential written to the first node N1' is too high, causing the fifth transistor T5' to turn on slowly or fail to turn on. As a result, the potential of the second node N2' at the second time t2' cannot be updated, remaining at a low potential. The sixth transistor T6' remains on, allowing VDD' to be written to the first node N1'. This increases the potential of the first node N1', further increasing the gate voltage of the fifth transistor T5'. This in turn causes the seventh transistor T7' to turn off and the eighth transistor T8' to turn on. Gout' then continues to output the abnormal CK1' waveform (the Abnormal Gout waveform shown in FIG2 ), resulting in a display failure. Therefore, the fifth and sixth transistors T5' need to be mutually restrained to address the abnormal output of the shift register unit caused by the abnormal potential update of the first and second nodes N1' and N2'.

[0005] Summary of the Invention

[0006] In view of the problems in the prior art, an object of the present invention is to provide a shift register unit, a gate driving circuit and a display device to ensure that the shift register unit outputs correct and effective signals.

[0007] An embodiment of the present invention provides a shift register unit, comprising:

[0008] an input module, configured to transmit a signal at an input end of the shift register unit to a first node in response to a second clock signal;

[0009] a first control module, configured to transmit the second clock signal to a second node in response to a signal from the first node;

[0010] a second control module, configured to transmit a first voltage signal or a first clock signal to a third node in response to a signal at the input terminal; and to transmit a second voltage signal to the third node in response to a first clock signal;

[0011] a third control module, configured to transmit the second voltage signal to a fourth node in response to the second clock signal; and to transmit the second voltage signal or the signal of the second node to the fourth node in response to a signal of the third node; and to transmit the second voltage signal to the second node in response to the second clock signal and the signal of the third node;

[0012] a first output module, configured to transmit the first voltage signal to an output end of the shift register unit in response to a signal at the second node;

[0013] a second output module, configured to transmit the first clock signal to the output terminal in response to a signal from the first node;

[0014] a first capacitor connected between the first node and the output terminal;

[0015] a second capacitor connected between the second node and the first voltage signal lead;

[0016] The third capacitor is connected between the third node and the fourth node.

[0017] In some embodiments, the input module includes a first transistor, a control terminal of the first transistor is electrically connected to the second clock signal lead, a first terminal of the first transistor is electrically connected to the input terminal, and a second terminal of the first transistor is electrically connected to the first node.

[0018] In some embodiments, the input module further includes a second transistor and a third transistor, wherein the control terminal of the second transistor is electrically connected to the second voltage signal lead, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor;

[0019] The control terminal of the third transistor is electrically connected to the second voltage signal lead, and the second terminal of the third transistor is electrically connected to the first node.

[0020] In some embodiments, the first control module includes a fourth transistor, a control terminal of the fourth transistor is electrically connected to the first node, a first terminal of the fourth transistor is electrically connected to the second clock signal lead, and a second terminal of the fourth transistor is electrically connected to the second node.

[0021] In some embodiments, the second control module includes a fifth transistor, a control terminal of the fifth transistor is electrically connected to the input terminal, a first terminal of the fifth transistor is electrically connected to the first voltage signal lead, and a second terminal of the fifth transistor is electrically connected to the third node.

[0022] In some embodiments, the second control module further includes a sixth transistor, the control end of the sixth transistor is electrically connected to the first clock signal lead, the first end of the sixth transistor is electrically connected to the second voltage signal lead, and the second end of the sixth transistor is electrically connected to the third node.

[0023] In some embodiments, the third control module includes a seventh transistor, a control terminal of the seventh transistor is electrically connected to the third node, a first terminal of the seventh transistor is electrically connected to the fourth node, and a second terminal of the seventh transistor is electrically connected to the second node.

[0024] In some embodiments, the third control module also includes an eighth transistor, the control end of the eighth transistor is electrically connected to the second clock signal lead, the first end of the eighth transistor is electrically connected to the second voltage signal lead, and the second end of the eighth transistor is electrically connected to the fourth node.

[0025] In some embodiments, the first output module includes a ninth transistor, a control terminal of the ninth transistor is electrically connected to the second node, a first terminal of the ninth transistor is electrically connected to the first voltage signal lead, and a second terminal of the ninth transistor is electrically connected to the output terminal;

[0026] The second output module includes a tenth transistor, a control terminal of the tenth transistor is electrically connected to the first node, a first terminal of the tenth transistor is electrically connected to the first clock signal lead, and a second terminal of the tenth transistor is electrically connected to the output terminal.

[0027] An embodiment of the present invention provides a gate driving circuit, including the shift register unit described above.

[0028] An embodiment of the present invention further provides a display device, comprising the gate driving circuit as described above.

[0029] The shift register unit, gate drive circuit, and display device provided by the present invention have the following advantages:

[0030] In the present invention, an input module controls the potential of a first node, a first control module controls the potential of a second node, a second control module controls the potential of a third node, and a third control module controls the potential of both the fourth node and the second node. A first capacitor is connected between the first node and the output terminal; a second capacitor is connected between the second node and the first voltage signal lead; and a third capacitor is connected between the third node and the fourth node. The potentials of the first and second nodes are updated independently without interfering with each other, ensuring that the output signal waveform at the output terminal is correct and effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0032] FIG1 is a schematic diagram of a shift register unit disclosed in the prior art;

[0033] FIG2 is a driving timing diagram of a shift register unit disclosed in the prior art;

[0034] FIG3 is a schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0035] FIG4 is a driving timing diagram of a shift register unit provided by an embodiment of the present invention;

[0036] 5 to 10 are schematic diagrams showing on-off circuits of a shift register unit in a first time period t1 to a sixth time period t6 according to an embodiment of the present invention;

[0037] FIG11 is a schematic diagram of a gate drive circuit provided in one embodiment of the present invention;

[0038] FIG. 12 is a schematic diagram of a shift register unit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, identical reference numerals denote identical or similar structures, and thus repetitive descriptions thereof will be omitted. The use of "or" and "either" in this specification may mean "and" or "or."

[0040] In the description of this application, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and integrate different embodiments or examples described in this application, as well as features of different embodiments or examples, unless otherwise contradictory.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include at least one such feature. In the context of this application, "plurality" means two or more, unless otherwise specifically defined.

[0042] To solve the problems of the prior art, an embodiment of the present invention provides a shift register unit, as shown in FIG3 , wherein the shift register unit includes:

[0043] an input module, configured to transmit an input signal IN at an input end of the shift register unit to a first node N1 in response to a second clock signal CK2;

[0044] a first control module, configured to transmit the second clock signal CK2 to a second node N2 in response to a signal at the first node N1;

[0045] a second control module for transmitting the first voltage signal VDD to the third node N3 in response to the input signal IN; and for transmitting the second voltage signal VEE to the third node N3 in response to the first clock signal CK1;

[0046] a third control module, configured to transmit the second voltage signal VEE to a fourth node N4 in response to the second clock signal CK2; and to transmit the signal at the second node N2 to the fourth node N4 in response to the signal at the third node N3; and to transmit the signal at the fourth node N4 to the second node N2 in response to the second clock signal CK2 and the signal at the third node N3;

[0047] a first output module, configured to transmit a first voltage signal VDD to an output end of the shift register unit in response to a signal at the second node N2;

[0048] a second output module, configured to transmit the first clock signal CK1 to the output end in response to the signal of the first node N1;

[0049] A first capacitor C1 is connected between the first node N1 and the output end;

[0050] a second capacitor C2 connected between the second node N2 and the first voltage signal lead;

[0051] The third capacitor C3 is connected between the third node N3 and the fourth node N4.

[0052] The first clock signal CKV1 and the second clock signal CKV2 have the same frequency and opposite phases. The first voltage signal VDD is a positive voltage signal, and the second voltage signal VEE is a negative voltage signal.

[0053] The input module controls the potential of the first node, the first control module controls the potential of the second node, the second control module controls the potential of the third node, and the third control module controls the potential of the fourth node and the second node. A first capacitor is connected between the first node and the output terminal; a second capacitor is connected between the second node and the first voltage signal lead; and a third capacitor is connected between the third node and the fourth node. The first node and the second node independently update their potentials without interfering with each other, thereby ensuring that the output signal waveform at the output terminal is correct and effective.

[0054] 3 , the input module includes a first transistor T1 , a control end of the first transistor T1 is electrically connected to the second clock signal lead, a first end of the first transistor T1 is electrically connected to the input end, and a second end of the first transistor T1 is electrically connected to the first node N1 .

[0055] The input module further includes a second transistor T2 and a third transistor T3. The control terminal of the second transistor T2 is electrically connected to the second voltage signal lead, the first terminal of the second transistor T2 is electrically connected to the second terminal of the first transistor T1, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the third transistor T3. The second terminal of the third transistor T3 is electrically connected to the first node N1. In other embodiments, only one of the second transistor T2 and the third transistor T3 may be selected to reduce the number of transistors in the circuit and ease the difficulty of circuit layout.

[0056] The first control module includes a fourth transistor T4, a control end of the fourth transistor T4 is electrically connected to the first node N1, a first end of the fourth transistor T4 is electrically connected to the second clock signal, and a second end of the fourth transistor T4 is electrically connected to the second node N2.

[0057] The second control module includes a fifth transistor T5, a control end of the fifth transistor T5 is electrically connected to the input end, a first end of the fifth transistor T5 is electrically connected to the first voltage signal lead, and a second end of the fifth transistor T5 is electrically connected to the third node N3.

[0058] The second control module further includes a sixth transistor T6, a control end of the sixth transistor T6 is electrically connected to the first clock signal lead, a first end of the sixth transistor T6 is electrically connected to the second voltage signal lead, and a second end of the sixth transistor T6 is electrically connected to the third node N3.

[0059] The third control module includes a seventh transistor T7, a control end of the seventh transistor T7 is electrically connected to the third node N3, a first end of the seventh transistor T7 is electrically connected to the fourth node N4, and a second end of the seventh transistor T7 is electrically connected to the second node N2.

[0060] The third control module further includes an eighth transistor T8, a control end of the eighth transistor T8 is electrically connected to the second clock signal lead, a first end of the eighth transistor T8 is electrically connected to the second voltage signal lead, and a second end of the eighth transistor T8 is electrically connected to the fourth node N4.

[0061] The first output module includes a ninth transistor T9, a control end of the ninth transistor T9 is electrically connected to the second node N2, a first end of the ninth transistor T9 is electrically connected to the first voltage signal lead, and a second end of the ninth transistor T9 is electrically connected to the output end.

[0062] The second output module includes a tenth transistor T10, a control terminal of the tenth transistor T10 is electrically connected to the first node N1, a first terminal of the tenth transistor T10 is electrically connected to the first clock signal lead, and a second terminal of the tenth transistor T10 is electrically connected to the output terminal.

[0063] In this embodiment, the first transistor T1 to the tenth transistor T10 are all PMOS transistors, wherein the control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain; the on-level of the PMOS transistor is a low level, and the off-level is a high level. In other embodiments, those skilled in the art will readily appreciate that the shift register unit provided by the present invention can be easily modified to include all N-type transistors. Alternatively, the shift register unit provided by the present invention can be easily modified to include all CMOS transistors, etc.

[0064] Figure 4 shows a timing diagram of the shift register unit, and the working principle of the shift register provided by the embodiment of the present invention is described in conjunction with Figure 4. It should be noted that, for ease of understanding, high-level signals are represented by "H" and low-level signals are represented by "L".

[0065] FIG4 shows the driving timing of the shift register unit during the first time period t1; FIG5 shows a schematic diagram of the circuit on-off of the shift register unit during the first time period t1. Combining FIG4 and FIG5, it can be seen that during the first time period t1, the input signal IN is at a low level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The first transistor T1, the fifth transistor T5, and the eighth transistor T8 are turned on, and the sixth transistor T6 is turned off. The second voltage signal VEE is a continuously low-level signal. Therefore, when the second voltage signal VEE is continuously output, the second transistor T2 and the third transistor T3 are continuously turned on. The reasons for the conduction of the second transistor T2 and the third transistor T3 will not be explained in the following stages. The first voltage signal VDD is transmitted to the third node N3 through the fifth transistor T5. When the signal at the third node N3 is high, the seventh transistor T7 is turned off. The second voltage signal VEE is transmitted to the fourth node N4 through the eighth transistor T8. When the signal at the fourth node N4 is low, the third capacitor C3 is charged. A low-level input signal IN is transmitted to the first node N1 through the first transistor T1, the second transistor T2, and the third transistor T3. The signal at the first node N1 is low, and the fourth transistor T4 and the tenth transistor T10 are turned on. The second clock signal CK2 is transmitted to the second node N2 through the fourth transistor T4. The signal at the second node N2 is low, and the ninth transistor T9 is turned on. The second capacitor C2 is charged by the first voltage signal VDD and the second node N2. The first voltage signal VDD is transmitted to the output terminal through the ninth transistor T9; the first clock signal CK1 is transmitted to the output terminal through the tenth transistor T10. At this time, the output terminal outputs a high-level first voltage signal and a high-level first clock signal, and the output signal at the output terminal is high. The first capacitor C1 is charged by the first node N1 and the output terminal.

[0066] Figure 4 shows the driving timing of the shift register unit in the first time period t2; Figure 6 shows a schematic diagram of the circuit on and off in the shift register unit in the second time period t2. Combining Figures 4 and 6, it can be seen that in the second time period t2, the input signal IN is at a high level, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. When the first end of the first capacitor C1 is at a low level, the fourth transistor T4 and the tenth transistor T10 are still turned on, and the second clock signal CK2 is transmitted to the second node N2 through the fourth transistor T4, that is, the high-level second clock signal CK2 updates the potential of the second node N2. The signal at the second node N2 is at a high level, and the ninth transistor T9 is turned off; the first clock signal CK1 is transmitted to the output terminal through the tenth transistor T10, and the output signal of the output terminal is the high-level first clock signal CK1.

[0067] FIG4 shows the driving timing of the shift register unit during the third time period t3; FIG7 shows a schematic diagram of the circuit on-off of the shift register unit during the third time period t3. Combining FIG4 and FIG7, it can be seen that during the third time period t3, the input signal IN is high, the first clock signal CK1 is low, and the second clock signal CK2 is high. The first transistor T1, the fifth transistor T5, and the eighth transistor T8 are turned off, and the sixth transistor T6 is turned on. Under the action of the low signal at the first end of the first capacitor C1, the fourth transistor T4 and the tenth transistor T10 are turned on. The second clock signal CK2 is transmitted to the second node N2 via the fourth transistor T4. The signal at the second node N2 is high, and the ninth transistor T9 remains off. The first clock signal CK1 is transmitted to the output terminal via the tenth transistor T10. The second voltage signal VEE is transmitted to the third node N3 via the sixth transistor T6. The signal at the third node N3 is low. Under the action of the third node N3, the seventh transistor T7 is turned on. The high signal at the second node N2 is transmitted to the fourth node N4, and the third capacitor C3 is charged. At this time, the output signal of the output terminal is the first clock signal CK1 at a low level.

[0068] Figure 4 shows the driving timing during the fourth time period t4; Figure 8 shows a schematic diagram of the circuit on-off within the shift register unit during the fourth time period t4. Combining Figures 4 and 8, it can be seen that during the fourth time period t4, the input signal IN is high, the first clock signal CK1 is high, the second clock signal CK2 is high, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are off. Under the action of the first capacitor C1, the fourth transistor T4 and the tenth transistor T10 are turned on, and the second clock signal CK2 is transmitted to the second node N2. Under the action of the second node N2, the ninth transistor T9 is turned off. Under the action of the third capacitor C3, the seventh transistor T7 is turned on, and the signal from the second node N2 is transmitted to the fourth node N4 through the seventh transistor T7, and the third capacitor C3 is charged. The first clock signal CK1 is transmitted to the output terminal through the tenth transistor T10, and the signal at the output terminal is the high-level first clock signal CK1.

[0069] Figure 4 shows the driving timing during the fifth time period t5; Figure 9 shows a schematic diagram of the circuit on-off state within the shift register unit during the fifth time period t5. Combining Figures 4 and 9, it can be seen that during the fifth time period t5, the input signal IN is high, the first clock signal CK1 is high, the second clock signal CK2 is low, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are off, and the first transistor T1 and the eighth transistor T8 are on. The input signal IN is transmitted to the first node N1 via the first transistor T1. When the signal at the first node N1 is high, the tenth transistor T10 is off. The second voltage signal VEE is transmitted to the fourth node N4 via the eighth transistor T8. When the signal at the fourth node N4 is low, the signal potential at the third node N3 is further reduced due to capacitor bootstrapping, and the signal at the third node N3 is low, turning the seventh transistor T7 on. The second voltage signal VEE is transmitted to the second node N2 via the seventh transistor T7. When the signal at the second node N2 is low, the ninth transistor T9 turns on, and the first voltage signal VDD is transmitted to the output terminal via the ninth transistor T9. The output signal Gout at the output terminal is the high-level first voltage signal VDD. The second capacitor C2 is charged by the second node N2 and the first voltage signal VDD. During the fifth time period t5, the potential of the second node N2 is updated by the second voltage signal VEE, the potential of the first node N1 is updated to a high level by the input signal IN, the tenth transistor T10 turns off, the potential of the second node N2 is updated to a low level by the second voltage signal VEE, and the ninth transistor T9 turns on, ensuring that only the first voltage signal VDD is transmitted to the output terminal via the ninth transistor, while the tenth transistor T10 turns off. The potential updates of the first node N1 and the second node N2 do not affect or constrain each other, ensuring the correct output waveform.

[0070] Figure 4 shows the driving timing during the sixth time period t6; Figure 10 shows a schematic diagram of the circuit switching within the shift register unit during the sixth time period t6. Combining Figures 4 and 10, it can be seen that when the first clock signal CK1 is a low-level signal, the second clock signal CK2 is a high-level signal, and the input signal IN is high, the first transistor T1, the fifth transistor T5, and the eighth transistor T8 are turned off, and the sixth transistor T6 is turned on. The first node N1 remains at a high-level signal under the action of the first capacitor C1, and the tenth transistor T10 is turned off. The second voltage signal VEE is transmitted to the third node N3 through the sixth transistor T6, and the seventh transistor T7 is turned on under the action of the third node N3. Under the action of the third node N3, the fourth node N4 remains at a low-level signal, and the signal from the fourth node N4 is transmitted to the second node N2 through the seventh transistor T7. The potential of the second node N2 is low, and the ninth transistor T9 is turned on. The first voltage signal VDD is transmitted to the output terminal through the ninth transistor T9, and the output signal Gout at the output terminal is the high-level first voltage signal VDD. The update of the potential of the second node N2 is not affected by the first node N1, which can ensure that the output waveform is correct and effective.

[0071] The shift register unit repeats the fifth time period t5 and the sixth time period t6 in subsequent working steps, which will not be repeated here, until the next frame of the picture starts to be displayed and the working steps t1 to t4 are started again.

[0072] As shown in FIG11 , an embodiment of the present invention further provides a gate drive circuit comprising the shift register unit described above. The gate drive circuit comprises a plurality of the shift register units described above, wherein the plurality of shift register units are electrically connected in cascade, and the input terminal of the first stage of the shift register unit is connected to a low-level start pulse signal, and the output signal terminal of each stage of the shift register unit, except for the last stage of the shift register unit, is connected to the input signal terminal of the next stage of the shift register unit.

[0073] The plurality of shift register units are electrically connected in a cascade manner, wherein the input signal of the first-stage shift register unit is connected to the revelation pulse signal, and except for the last-stage shift register, the output signal ends of each of the remaining shift register units are connected to the input ends of the next-stage shift register unit.

[0074] Specifically, in Figure 11, four cascaded shift register units are taken as an example. The input signal IN of the input terminal in of the first-stage shift register unit SR1 is the start pulse signal; the output signal Eout1 of the output terminal out of the first-stage shift register unit SR1 serves as the input signal of the second-stage shift register unit SR2, and the output terminal out of the first-stage shift register unit SR1 is connected to the input terminal in of the second-stage shift register unit SR2; the output signal Eout2 of the second-stage shift register unit SR2 serves as the input signal of the third-stage shift register unit SR3, and the output terminal out of the second-stage shift register unit SR2 is connected to the input terminal in of the third-stage shift register unit SR3; the output signal Eout3 of the third-stage shift register unit SR3 serves as the input signal of the fourth-stage shift register unit SR4, and the output terminal of the third-stage shift register unit SR3 is connected to the input terminal in of the fourth-stage shift register unit SR4… This is repeated to form a gate drive circuit.

[0075] As shown in FIG11 , the gate driving circuit further includes a clock signal generating unit (not shown in the figure), and the clock signal generating unit is configured to generate a first clock signal CK1 and a second clock signal CK2 . Specifically, the first clock signal CK1 and the second clock signal CK2 in the first-stage shift register unit SR1 are respectively the first clock signal CK1 and the second clock signal CK2 generated by the clock signal generating unit; the first clock signal CK1 and the second clock signal CK2 in the second-stage shift register unit SR2 are respectively the second clock signal CK2 and the first clock signal CK1 generated by the clock signal generating unit; the first clock signal CK1 and the second clock signal CK2 in the third-stage shift register unit SR3 are respectively the first clock signal CK1 and the second clock signal CK2 generated by the clock signal unit; the first clock signal CK1 and the second clock signal CK2 in the fourth-stage shift register unit SR4 are respectively the second clock signal CKE1 and the first clock signal CK2 generated by the clock signal unit; and so on, the first clock signal CK1 and the second clock signal CK2 in the n-stage shift register unit SRn are respectively the first clock signal CK1 and the second clock signal CK2 generated by the clock signal generating unit; the first clock signal CK1 and the second clock signal CK2 in the (n+1)-stage shift register unit SRn+1 are respectively the second clock signal CK2 and the first clock signal CK1 generated by the clock signal generating unit.

[0076] As shown in FIG12 , an embodiment of the present invention further provides another shift register unit, which differs from the shift register unit in the previous embodiment in that the first end of the first transistor T1 in the second control module is electrically connected to the first clock signal lead, and the second control module is used to respond to the signal at the input end to transmit the first clock signal CK1 to the third node N3. The shift register unit provided in FIG12 can achieve the same technical effect as the shift register unit in the previous embodiment, and will not be described in detail here. When the shift register is working, only the working steps in the first time period t1 are different from those in the previous embodiment, and the remaining working steps are the same as those of the shift register in the previous embodiment. In the first time period t1, the first clock signal CK1 is transmitted to the third node N3 through the fifth transistor T5, and the signal at the third node N3 is high.

[0077] An embodiment of the present invention further provides a display device including the gate driving circuit as described above, which can achieve the technical effects of the above embodiment.

[0078] The shift register unit, gate drive circuit, and display device provided by the present invention have the following advantages:

[0079] In the present invention, an input module controls the potential of a first node, a first control module controls the potential of a second node, a second control module controls the potential of a third node, and a third control module controls the potential of a fourth node and a second node. A first capacitor is connected between the first node and an output terminal; a second capacitor is connected between the second node and a first voltage signal lead; and a third capacitor is connected between the third node and the fourth node. The potentials of the first and second nodes can be updated independently without interfering with each other, ensuring that the output signal waveform at the output terminal is correct and effective, and that the display device displays normally.

[0080] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A shift register unit, characterized in that: include: An input module, configured to transmit a signal at an input end of the shift register unit to a first node in response to a second clock signal; A first control module, configured to transmit the second clock signal to a second node in response to a signal from the first node; A second control module, configured to transmit a first voltage signal or a first clock signal to a third node in response to a signal at the input terminal; and for transmitting a second voltage signal to the third node in response to the first clock signal; a third control module, configured to transmit the second voltage signal to a fourth node in response to the second clock signal; and for transmitting the second voltage signal or the signal of the second node to the fourth node in response to the signal of the third node; and for transmitting a second voltage signal to the second node in response to the second clock signal and the signal of the third node; a first output module, configured to transmit the first voltage signal to an output end of the shift register unit in response to a signal of the second node; a second output module, configured to transmit the first clock signal to the output terminal in response to the signal of the first node; A first capacitor connected between the first node and the output end; A second capacitor connected between the second node and the first voltage signal lead; The third capacitor is connected between the third node and the fourth node.

2. The shift register unit according to claim 1, characterized in that: The input module includes a first transistor, a control terminal of the first transistor is electrically connected to the second clock signal lead, a first terminal of the first transistor is electrically connected to the input terminal, and a second terminal of the first transistor is electrically connected to the first node.

3. The shift register unit according to claim 2, characterized in that: The input module further includes a second transistor and a third transistor, wherein the control end of the second transistor is electrically connected to the second voltage signal lead, the first end of the second transistor is electrically connected to the second end of the first transistor, and the second end of the second transistor is electrically connected to the first end of the third transistor; The control terminal of the third transistor is electrically connected to the second voltage signal lead, and the second terminal of the third transistor is electrically connected to the first node.

4. The shift register unit according to claim 2, characterized in that: The first control module includes a fourth transistor, a control end of the fourth transistor is electrically connected to the first node, a first end of the fourth transistor is electrically connected to a second clock signal lead, and a second end of the fourth transistor is electrically connected to the second node.

5. The shift register unit according to claim 4, characterized in that: The second control module includes a fifth transistor, a control end of the fifth transistor is electrically connected to the input end, a first end of the fifth transistor is electrically connected to the first voltage signal lead, and a second end of the fifth transistor is electrically connected to the third node.

6. The shift register unit according to claim 5, characterized in that: The second control module also includes a sixth transistor, a control end of the sixth transistor is electrically connected to the first clock signal lead, a first end of the sixth transistor is electrically connected to the second voltage signal lead, and a second end of the sixth transistor is electrically connected to the third node.

7. The shift register unit according to claim 6, characterized in that: The third control module includes a seventh transistor, a control end of the seventh transistor is electrically connected to the third node, a first end of the seventh transistor is electrically connected to the fourth node, and a second end of the seventh transistor is electrically connected to the second node.

8. The shift register unit according to claim 7, characterized in that: The third control module also includes an eighth transistor, a control end of the eighth transistor is electrically connected to the second clock signal lead, a first end of the eighth transistor is electrically connected to the second voltage signal lead, and a second end of the eighth transistor is electrically connected to the fourth node.

9. The shift register unit according to claim 8, characterized in that: The first output module includes a ninth transistor, a control terminal of the ninth transistor is electrically connected to the second node, a first terminal of the ninth transistor is electrically connected to the first voltage signal lead, and a second terminal of the ninth transistor is electrically connected to the output terminal; The second output module includes a tenth transistor, a control end of the tenth transistor is electrically connected to the first node, a first end of the tenth transistor is electrically connected to the first clock signal lead, and a second end of the tenth transistor is electrically connected to the output end.

10. A gate drive circuit, characterized in that: The invention comprises a shift register unit as claimed in any one of claims 1 to 9.

11. A display device, characterized in that: Comprising the gate driving circuit as claimed in claim 10.

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