Shift register unit, gate drive circuit, and display device

Abstract

A shift register unit, a gate drive circuit, and a display device. The shift register unit comprises an input module, a first control module, a second control module, a third control module, a first output module, a second output module, a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3); the input module controls the potential of a first node (N1); the first control module controls the potential of a second node (N2); the second control module and the third control module control the potential of a third node (N3); one end of the first capacitor (C1) is connected to the first node (N1); one end of the second capacitor (C2) is connected to the second node (N2); and one end of the third capacitor (C3) is connected to the third node (N3). By optimizing the voltage waveform of the first node (N1), the output signal waveform of the shift register unit is optimized, and abnormal output of a signal of the shift register unit is avoided, thereby avoiding abnormal display of pictures.

Description

A shift register unit, gate drive circuit and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register unit, a gate drive circuit and a display device. Background Art

[0002] A display device includes not only a display panel but also a gate driver circuit (also called a row driver circuit) and a source driver circuit (also called a column driver circuit) with a pixel array that control the display of the display panel. The display panel uses a row-by-row scanning display method, in which the gate driver circuit is used to generate a scanning signal to turn on each row of pixels in sequence, while the source driver circuit is used to provide a data signal to each row of pixels when it is turned on to realize the display of the pixels.

[0003] The gate drive circuit includes a shift register, which includes multiple cascaded shift register units, where each level of shift register unit is usually mainly composed of several transistors. By inputting a clock signal and an input signal (that is, a start pulse signal) into the circuit, a level signal is output at the output end.

[0004] Chinese patent CN105741749B discloses a shift register unit. Figure 1 shows a voltage waveform at the fourth node N4 in the shift register unit described in CN105741749B, with time plotted on the horizontal axis and voltage plotted on the vertical axis. As shown in Figure 1, the voltage at node N4 transitions with the high and low levels of clock signal c1, synchronously forming a pull-up and pull-down waveform as shown in the dashed box. This circuit presents a risk: if the pull-down level of clock signal c1 is too high, transistor M2 may abnormally open, causing an abnormal output signal at the output of the shift register unit and, consequently, an abnormal display.

[0005] Summary of the Invention

[0006] In view of the problems in the prior art, the present invention aims to provide a shift register unit, a gate driving circuit and a display device. The shift register unit provided can optimize the waveform of the output signal, avoid abnormal output of the shift register unit signal, and avoid abnormal display of the display screen.

[0007] An embodiment of the present invention provides a shift register unit, comprising:

[0008] An input module, configured to transmit a signal at an input terminal to a first node in response to a first clock signal;

[0009] a first control module, configured to transmit a first voltage signal to a second node in response to the first clock signal; and to transmit the first clock signal to the second node in response to a signal at the input terminal;

[0010] a second control module, configured to transmit the first voltage signal to a third node in response to a second clock signal;

[0011] a third control module, configured to transmit a second voltage signal to the third node in response to the signal of the first node;

[0012] a first output module, configured to transmit the second voltage signal to an output terminal in response to a signal at the third node;

[0013] a second output module, configured to transmit the first voltage signal to the output terminal in response to the signal of the first node;

[0014] a first capacitor connected between the first node and a second voltage signal lead;

[0015] a second capacitor connected between the second clock signal lead and the second node;

[0016] The third capacitor is connected between the second voltage signal lead and the third node.

[0017] In some embodiments, the input module includes a first transistor, a control terminal of the first transistor is connected to a first clock signal lead, a first terminal of the first transistor is connected to the input terminal, and a second terminal of the first transistor is connected to the first node.

[0018] In some embodiments, the input module further includes a second transistor, a control end of the second transistor is connected to the first voltage signal lead, a first end of the second transistor is connected to the second end of the first transistor, and a second end of the second transistor is connected to the first node.

[0019] In some embodiments, the input module includes a third transistor, the control end of the third transistor is connected to the second node, the first end of the third transistor is connected to the second voltage signal lead, and the second end of the third transistor is connected to the first end of the first capacitor.

[0020] In some embodiments, the input module further includes a fourth transistor and a fifth transistor, wherein the control terminal of the fourth transistor is connected to the second clock signal lead, the first terminal of the fourth transistor is connected to the second voltage signal lead, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor;

[0021] The control terminal of the fifth transistor is connected to the second node, and the second terminal of the fifth transistor is connected to the first node.

[0022] In some embodiments, the first control module includes a sixth transistor, a control terminal of the sixth transistor is connected to the first clock signal lead, a first terminal of the sixth transistor is connected to the first voltage signal lead, and a second terminal of the sixth transistor is connected to the second node.

[0023] In some embodiments, the first control module further includes a seventh transistor, the control end of the seventh transistor is connected to the first voltage signal lead, the first end of the seventh transistor is connected to the second node, and the second end of the seventh transistor is connected to the second end of the second capacitor.

[0024] In some embodiments, the first control module further includes an eighth transistor, the control end of the eighth transistor is connected to the input end, the first end of the eighth transistor is connected to the first clock signal lead, and the second end of the eighth transistor is connected to the second node.

[0025] In some embodiments, the second control module includes a ninth transistor, the control end of the ninth transistor is connected to the first end of the second capacitor and to the second clock signal lead, the first end of the ninth transistor is connected to the first voltage signal lead, and the second end of the ninth transistor is connected to the third node.

[0026] In some embodiments, the second control module further includes a tenth transistor, the control end of the tenth transistor is connected to the second end of the second capacitor, the first end of the tenth transistor is connected to the second end of the ninth transistor, and the second end of the tenth transistor is connected to the third node.

[0027] In some embodiments, the third control module includes an eleventh transistor, the control end of the eleventh transistor is connected to the first node, the first end of the eleventh transistor is connected to the second voltage signal lead, and the second end of the eleventh transistor is connected to the third node.

[0028] In some embodiments, a twelfth transistor is further included, wherein the control end of the twelfth transistor is connected to the first node, the first end of the twelfth transistor is connected to the second clock signal lead, and the second end of the twelfth transistor is connected to the second end of the first capacitor.

[0029] In some embodiments, the first output module includes a thirteenth transistor, a control terminal of the thirteenth transistor is connected to the third node, a first terminal of the thirteenth transistor is connected to the second voltage signal lead, and a second terminal of the thirteenth transistor is connected to the output terminal;

[0030] The second output module includes a fourteenth transistor, a control end of the fourteenth transistor is connected to the first node, a first end of the fourteenth transistor is connected to the first voltage signal lead, and a second end of the fourteenth transistor is connected to the output end.

[0031] An embodiment of the present invention further provides a gate driving circuit, comprising the shift register unit described above.

[0032] An embodiment of the present invention further provides a display device, comprising the gate driving circuit as described above.

[0033] The shift register unit, gate drive circuit, and display device provided by the present invention have the following advantages:

[0034] The shift register unit provided by the present invention optimizes the voltage waveform of the first node, thereby optimizing the output signal waveform of the shift register unit, thereby avoiding abnormal output of the shift register unit signal and abnormal display of the screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0036] FIG1 is a voltage waveform diagram of the fourth node of a shift register unit in the prior art;

[0037] FIG2 is a circuit diagram of a shift register unit provided by an embodiment of the present invention;

[0038] 3 is a timing diagram of a shift register unit according to an embodiment of the present invention;

[0039] 4 to 9 are schematic diagrams of the shift register unit in FIG. 2 during each step of circuit control on and off;

[0040] FIG10 is a waveform diagram of an output signal of the first node N1 in the shift register unit in FIG2 ;

[0041] FIG11 is a schematic diagram of a gate drive circuit provided in one embodiment of the present invention;

[0042] FIG12 is a signal waveform diagram output by the gate drive circuit of FIG11;

[0043] FIG. 13 is a circuit diagram of a shift register unit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0044] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, identical reference numerals denote identical or similar structures, and thus repetitive descriptions thereof will be omitted. The use of "or" and "either" in this specification may mean "and" or "or."

[0045] In the description of this application, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and integrate different embodiments or examples described in this application, as well as features of different embodiments or examples, unless otherwise contradictory.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include at least one such feature. In the context of this application, "plurality" means two or more, unless otherwise specifically defined.

[0047] The transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. According to the characteristics of the transistors, transistors can be divided into N-type and P-type. The following embodiments are described using P-type transistors. The control end in the embodiments of the present invention is the source, the first end is the source, and the second end is the drain. When a low level is input to the gate of the P-type transistor, the source and drain are turned on. It should be noted here that in the embodiments of the present invention, all transistors are P-type transistors as an example, then the working level refers to the effective level at which the P-type transistor turns on, that is, a low level, and the non-working level refers to a high level.

[0048] To solve the problems of the prior art, the present invention provides a shift register unit, as shown in FIG2 , wherein the shift register unit comprises:

[0049] an input module, configured to transmit a signal STE at an input end to a first node N1 in response to a first clock signal CKE1;

[0050] a first control module, configured to transmit the first voltage signal VEE to the second node N2 in response to the first clock signal CKE1; and to transmit the first clock signal CKE1 to the second node N2 in response to the signal STE at the input terminal;

[0051] a second control module, configured to transmit the first voltage signal VEE to a third node N3 in response to a second clock signal CKE2;

[0052] a third control module, configured to transmit a second voltage signal VDD to the third node N3 in response to a signal at the first node N1;

[0053] a first output module, configured to transmit the second voltage signal VDD to an output end in response to a signal at the third node N3;

[0054] a second output module, configured to transmit the first voltage signal VEE to the output terminal in response to a signal at the first node N1;

[0055] A first capacitor C1 is connected between the first node N1 and a second voltage signal lead;

[0056] A second capacitor C2 is connected between the second clock signal lead and the second node;

[0057] The third capacitor C3 is connected between the second voltage signal lead and the third node.

[0058] The first voltage signal VEE is a low-level signal, the second voltage signal VDD is a high-level signal, and the first clock signal and the second clock signal are pulse signals with the same frequency and opposite phases.

[0059] Please continue to refer to Figure 2. Specifically, the input module includes a first transistor T1, the control end of the first transistor T1 is connected to the first clock signal lead, the first end of the first transistor T1 is connected to the input end, and the second end of the first transistor T1 is connected to the first node N1.

[0060] The input module further includes a second transistor T2, a control end of the second transistor T2 is connected to the first voltage signal lead, a first end of the second transistor T2 is connected to the second end of the first transistor T1, and a second end of the second transistor T2 is connected to the first node N1.

[0061] The input module includes a third transistor T3, a control end of the third transistor T3 is connected to the second node, a first end of the third transistor T3 is connected to the second voltage signal lead, and a second end of the third transistor T3 is connected to the first end of the first capacitor C1.

[0062] The input module further includes a fourth transistor T4 and a fifth transistor T5, wherein the control end of the fourth transistor T4 is connected to the second clock signal lead, the first end of the fourth transistor T4 is connected to the second voltage signal lead, and the second end of the fourth transistor T4 is connected to the first end of the fifth transistor T5;

[0063] The control terminal of the fifth transistor T5 is connected to the second node N2 , and the second terminal of the fifth transistor T5 is connected to the first node N1 .

[0064] The first control module includes a sixth transistor T6, a control end of the sixth transistor T6 is connected to the first clock signal lead, a first end of the sixth transistor T6 is connected to the first voltage signal lead, and a second end of the sixth transistor T6 is connected to the second node N2.

[0065] The first control module further includes a seventh transistor T7, a control end of the seventh transistor T7 is connected to the first voltage signal lead, a first end of the seventh transistor T7 is connected to the second node N2, and a second end of the seventh transistor T7 is connected to the second end of the second capacitor C2.

[0066] The first control module further includes an eighth transistor T8, a control end of the eighth transistor T8 is connected to the input end, a first end of the eighth transistor T8 is connected to the first clock signal lead, and a second end of the eighth transistor T8 is connected to the second node N2.

[0067] The second control module includes a ninth transistor T9, a control end of the ninth transistor T9 is connected to the first end of the second capacitor C2 and to the second clock signal lead, a first end of the ninth transistor T9 is connected to the first voltage signal lead, and a second end of the ninth transistor T9 is connected to the third node N3.

[0068] The second control module further includes a tenth transistor T10, a control end of the tenth transistor T10 is connected to the second end of the second capacitor C2 and the second end of the seventh transistor T7, a first end of the tenth transistor T10 is connected to the second end of the ninth transistor T9, and a second end of the tenth transistor T10 is connected to the third node N3.

[0069] The third control module includes an eleventh transistor T11, a control end of the eleventh transistor T11 is connected to the first node N1, a first end of the eleventh transistor T11 is connected to the second voltage signal lead, and a second end of the eleventh transistor T11 is connected to the third node N3.

[0070] The shift register unit further includes a twelfth transistor T12, a control end of the twelfth transistor T12 is connected to the first node N1, a first end of the twelfth transistor T12 is connected to the second clock signal lead, and a second end of the twelfth transistor T12 is connected to the second end of the first capacitor C1.

[0071] The first output module includes a thirteenth transistor T13, a control end of the thirteenth transistor T13 is connected to the third node N3, a first end of the thirteenth transistor T13 is connected to the second voltage signal lead, and a second end of the thirteenth transistor T13 is connected to the output end;

[0072] The second output module includes a fourteenth transistor T14 , a control end of the fourteenth transistor T14 is connected to the first node N1 , a first end of the fourteenth transistor T14 is connected to the first voltage signal lead, and a second end of the fourteenth transistor T14 is connected to the output end.

[0073] Figure 3 shows a timing diagram of the shift register unit, and the working principle of the shift register unit is described in conjunction with Figure 3. It should be noted that, for ease of understanding, high-level signals are represented by "H" and low-level signals are represented by "L".

[0074] Figure 4 shows a schematic diagram of the on / off control circuitry within the shift register unit during the first step, Step 1. As shown in Figure 4, the input signal STE is high, the first clock signal CKE1 is low, and the second clock signal CKE2 is high. When the signal STE is high, the eighth transistor T8 is turned off; when the second clock signal CKE2 is high, the fourth transistor T4 and the ninth transistor T9 are turned off. When the first clock signal CKE1 is low, the first transistor T1 and the sixth transistor T6 are turned on; the first voltage signal VEE is a continuously low signal, so the second transistor T2 and the seventh transistor T7 remain on. The first transistor T1 and the second transistor T2 are turned on, and the high-level input signal STE is transmitted through the first transistor T1 and the second transistor T2 to the first node N1. At this time, the first node N1 is high. The high level of the first node N1 keeps the twelfth transistor T12 and the fourteenth transistor T14 off during this phase. The sixth transistor T6 and the seventh transistor T7 are turned on, and the first voltage signal VEE is transmitted to the second node N2 through the sixth transistor T6 and the seventh transistor T7. The second node N2 is connected to the second end of the second capacitor C2, and the second clock signal CKE2 is connected to the first end of the second capacitor C2. Under the action of the second clock signal CKE2 and the first voltage signal VEE, the second capacitor C2 is charged, the first end of the second capacitor C2 is at a high level, and the second end of the second capacitor C2 is at a low level. When the second node N2 is at a low level, the third transistor T3, the fifth transistor T5, and the tenth transistor T10 are turned on. The second voltage signal VDD is transmitted to the first end of the first capacitor C1 through the third transistor T3. At this time, the first end of the first capacitor C1 and the second end of the first capacitor C1 are both at a high level. At the previous moment, the thirteenth transistor T13 is in the off state. Therefore, in the first step Step1, the first output module and the second output module of the shift register unit have no signal output, and the output signal Eout remains at the low potential at the previous moment.

[0075] Figure 5 shows a schematic diagram of the on-off control of the circuit within the shift register unit during the first step, Step 2. At this moment, the first clock signal CKE1 is high, the second clock signal CKE2 is low, the signal STE at the input terminal is high, and the second node N2 remains low due to the action of the second capacitor C2. Similar to the principle in Step 1, when the first clock signal CKE1 is high, the first transistor T1 and the sixth transistor T6 are turned off; when STE is high, the eighth transistor T8 is turned off. When the second clock signal CKE2 and the second node N2 are low, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on, and the second voltage signal VDD is transmitted to the first node N1. The first node N1 may still be high at this time, and the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 are turned off. Under the action of the second clock signal CKE2 and the low level of the second node N2, the first voltage signal VEE is transmitted to the third node N3, the third capacitor C3 is charged, the first end of the third capacitor C3 is at a high level, the second end of the third capacitor C3 is at a low level, the third node N3 is at a low potential, the thirteenth transistor T13 is turned on, the second voltage signal VDD is transmitted to the output end through the thirteenth transistor T13, and the signal Eout at the output end is output as a high level signal VDD.

[0076] The potential of the first node N1 that controls the turning on of the fourteenth transistor T14 will continue to receive the high-level signal VDD transmitted through the fourth transistor T4 and the fifth transistor T5 in the Step 2 stage, and the first end of the first capacitor C1 will continue to transmit the high-level signal VDD through the third transistor T3. Therefore, when the first node N1 operates in the Step 2 stage, it will continue to maintain a high level without a pull-down effect, and the fourteenth transistor can be controlled to remain in the off state in the Step 2 stage.

[0077] FIG6 shows a schematic diagram of the on-off control of the circuit within the shift register unit during the third step, Step 3. At this moment, the first clock signal CKE1 is a low-level signal, the second clock signal CKE2 is a high-level signal, and the signal STE at the input terminal is a high-level signal. The operating principle is the same as in Step 1 and will not be described in detail here. At this moment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the thirteenth transistor T13 are turned on, and the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 are turned on. The high-level input signal STE is transmitted to the first node N1 through the first transistor T1 and the second transistor T2. The potential of the second node N2 is low, and the potential of the third node N3 is low due to the action of the third capacitor C3. Therefore, the second voltage signal VDD is transmitted to the output terminal through the thirteenth transistor, and the signal Eout at the output terminal is output as a high-level signal VDD.

[0078] The first node N1 is kept at a high level continuously in the Step 3 phase without any pull-down effect, and the fourteenth transistor can be controlled to be kept in a closed state continuously in the Step 3 phase.

[0079] Figure 7 shows a schematic diagram of the on-off control of the circuit within the shift register unit during Step 4. At this moment, the first clock signal CKE1 is a high-level signal, the second clock signal CK2 is a low-level signal, and the signal STE at the input terminal is a high-level signal. The operating principle is the same as in Step 1 and will not be repeated here. At this moment, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, and the thirteenth transistor T13 are turned on; the first transistor T1, the sixth transistor T6, the eighth transistor T8, the eleventh transistor T11, and the fourteenth transistor T14 are turned off. At this moment, a high-level signal VDD is continuously output to the first node N1 via the fourth transistor T4 and the fifth transistor T5. The potential of the second node N2 is low, and the potential of the third node N3 is low. The second voltage signal VDD is transmitted to the output terminal via the thirteenth transistor T13, and the signal Eout at the output terminal is output as a high-level signal VDD.

[0080] The first node N1 is kept at a high level in the Step 4 phase without any pull-down effect, and the fourteenth transistor can be controlled to be kept in a closed state in the Step 4 phase.

[0081] Figure 8 shows a schematic diagram of the on-off control of the circuit within the shift register unit during Step 5. At this moment, the first clock signal CKE1 is a low-level signal, the second clock signal CKE2 is a high-level signal, and the signal STE at the input terminal is a low-level signal. The principle is the same as in Step 1 and will not be repeated here. At this moment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 are turned on, while the fourth transistor T4, the ninth transistor T9, and the thirteenth transistor T13 are turned off. At this moment, the first node N1 is low-level, the second node is low-level, and the third node is high-level. The first voltage signal VEE is transmitted to the output terminal through the fourteenth transistor T14, and the signal Eout at the output terminal is output as a low-level signal VEE.

[0082] FIG9 shows a schematic diagram of the on-off control of the circuit within the shift register unit during step 6. At this moment, the first clock signal CKE1 is a high-level signal, the second clock signal CKE2 is a low-level signal, and the signal STE at the input terminal is a low-level signal. The principle is the same as in Step 1 and will not be repeated here. At this moment, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, and the thirteenth transistor T13 are turned off, while the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 are turned on. At this moment, the first node N1 is low-level, the second node N2 is high-level, and the third node N3 is high-level. The first voltage signal VEE is transmitted to the output terminal through the fourteenth transistor T14, and the signal Eout at the output terminal is output as a low-level signal VEE.

[0083] The shift register unit repeats Step 5 and Step 6 in subsequent working steps, which will not be described in detail here, until the next frame of the picture starts to be displayed and the working steps of Step 1 to Step 4 are started again.

[0084] To further explore the technical effects achieved by the shift register unit provided by the embodiments of the present invention, a simulation experiment was conducted to test the voltage waveform of the first node N1 during operation. FIG10 shows the voltage waveform of the first node N1 during the operation phase. As shown in FIG10 , during the phase in which the shift register unit outputs a high-level signal (the dotted box shown in FIG10 ), the voltage waveform output by the first node N1 does not exhibit a significant pull-down waveform. Therefore, the fourteenth transistor T14 is not abnormally turned on, and the shift register unit does not output a signal abnormally.

[0085] As shown in Figure 11, an embodiment of the present invention further provides a gate drive circuit, including the shift register unit as described above, wherein a plurality of the shift register units are electrically connected in a cascade manner, wherein the input end in of the first-stage shift register unit is connected to the start pulse signal STE, and except for the last-stage shift register unit, the output end out of each of the remaining stages of the shift register unit is connected to the input end in of the next-stage shift register unit.

[0086] Specifically, in Figure 11, four cascaded shift register units are taken as an example. The input signal STE of the input terminal in of the first-stage shift register unit SR1 is the start pulse signal; the output signal Eout1 of the output terminal out of the first-stage shift register unit SR1 serves as the input signal of the second-stage shift register unit SR2, and the output terminal out of the first-stage shift register unit SR1 is connected to the input terminal in of the second-stage shift register unit SR2; the output signal Eout2 of the second-stage shift register unit SR2 serves as the input signal of the third-stage shift register unit SR3, and the output terminal out of the second-stage shift register unit SR2 is connected to the input terminal in of the third-stage shift register unit SR3; the output signal Eout3 of the third-stage shift register unit SR3 serves as the input signal of the fourth-stage shift register unit SR4, and the output terminal out of the third-stage shift register unit SR3 is connected to the input terminal in of the fourth-stage shift register unit SR4… and this is repeated to form a gate drive circuit.

[0087] As shown in FIG11 , the gate drive circuit further includes a clock signal generating unit (not shown in the figure), which is used to generate a first clock signal CKE1 and a second clock signal CKE2. Specifically, the first clock signal CKE1 and the second clock signal CKE2 in the first-stage shift register unit SR1 are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal generating unit; the first clock signal CKE1 and the second clock signal CKE2 in the second-stage shift register unit SR2 are respectively the second clock signal CKE2 and the first clock signal CKE1 generated by the clock signal generating unit; the first clock signal CKE1 and the second clock signal CKE2 in the third-stage shift register unit SR3 are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal generating unit; and the fourth-stage shift register unit SR4 is respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal generating unit. The first clock signal CKE1 and the second clock signal CKE2 in the shift register unit SR4 are respectively the second clock signal CKE1 and the first clock signal CKE2 generated by the clock signal unit; by analogy, the first clock signal CKE1 and the second clock signal CKE2 in the n-th stage shift register unit SRn are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal unit; the first clock signal CKE1 and the second clock signal CKE2 in the (n+1)-th stage shift register unit SRn+1 are respectively the second clock signal CKE2 and the first clock signal CKE1 generated by the clock signal generating unit.

[0088] FIG12 shows an output signal waveform diagram of the four-stage shift register unit in the gate driving circuit shown in FIG11 . As shown in FIG12 , the voltage waveform output of the four-stage shift register unit is normal and effective, and thus does not cause abnormal display of the display screen.

[0089] An embodiment of the present invention further provides a display device comprising the gate drive circuit described above, wherein the gate scan lines in the display device are activated row by row using the signals output by the shift register units. Specifically, the signals output by the output signal terminals of the shift register units serve as gate scan line signals for each row of pixel units. Furthermore, the display device further comprises a source drive circuit for providing data voltages to the corresponding pixel units when the gate scan lines are activated.

[0090] FIG13 shows another embodiment of the present invention providing a shift register unit. Compared to the shift register unit shown in FIG2 , the shift register unit in FIG13 eliminates the fourth transistor T4 and the fifth transistor T5, but can achieve the same technical effects as the shift register unit in the embodiment of FIG2 . However, due to the reduction in the number of transistors in the shift register unit, the circuit layout area is reduced, thereby reducing the size of the OLED screen frame, thereby achieving a narrow frame effect for the display device.

[0091] The shift register unit, gate drive circuit, and display device provided by the present invention have the following advantages:

[0092] The shift register unit provided by the present invention optimizes the voltage waveform of the first node to thereby optimize the output signal waveform of the shift register unit, thereby avoiding abnormal output of the shift register unit signal and abnormal display of the screen.

[0093] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A shift register unit, characterized in that: include: An input module, configured to transmit a signal at an input terminal to a first node in response to a first clock signal; A first control module, configured to transmit a first voltage signal to a second node in response to the first clock signal; and for transmitting the first clock signal to the second node in response to a signal at the input terminal; a second control module, configured to transmit the first voltage signal to a third node in response to a second clock signal; A third control module, configured to transmit a second voltage signal to the third node in response to the signal of the first node; A first output module, configured to transmit the second voltage signal to an output terminal in response to a signal of the third node; a second output module, configured to transmit the first voltage signal to the output terminal in response to the signal of the first node; A first capacitor connected between the first node and a second voltage signal lead; A second capacitor connected between the second clock signal lead and the second node; The third capacitor is connected between the second voltage signal lead wire and the third node.

2. The shift register unit according to claim 1, characterized in that: The input module includes a first transistor, a control terminal of the first transistor is connected to a first clock signal lead, a first terminal of the first transistor is connected to the input terminal, and a second terminal of the first transistor is connected to the first node.

3. The shift register unit according to claim 2, characterized in that: The input module further includes a second transistor, a control end of the second transistor is connected to the first voltage signal lead, a first end of the second transistor is connected to the second end of the first transistor, and a second end of the second transistor is connected to the first node.

4. The shift register unit according to claim 2, characterized in that: The input module includes a third transistor, a control end of the third transistor is connected to the second node, a first end of the third transistor is connected to the second voltage signal lead, and a second end of the third transistor is connected to the first end of the first capacitor.

5. The shift register unit according to claim 4, characterized in that: The input module further includes a fourth transistor and a fifth transistor, wherein the control end of the fourth transistor is connected to the second clock signal lead, the first end of the fourth transistor is connected to the second voltage signal lead, and the second end of the fourth transistor is connected to the first end of the fifth transistor; The control terminal of the fifth transistor is connected to the second node, and the second terminal of the fifth transistor is connected to the first node.

6. The shift register unit according to claim 4, characterized in that: The first control module includes a sixth transistor, a control end of the sixth transistor is connected to the first clock signal lead, a first end of the sixth transistor is connected to the first voltage signal lead, and a second end of the sixth transistor is connected to the second node.

7. The shift register unit according to claim 6, characterized in that: The first control module also includes a seventh transistor, a control end of the seventh transistor is connected to the first voltage signal lead, a first end of the seventh transistor is connected to the second node, and a second end of the seventh transistor is connected to the second end of the second capacitor.

8. The shift register unit according to claim 7, characterized in that: The first control module also includes an eighth transistor, a control end of the eighth transistor is connected to the input end, a first end of the eighth transistor is connected to the first clock signal lead, and a second end of the eighth transistor is connected to the second node.

9. The shift register unit according to claim 8, characterized in that: The second control module includes a ninth transistor, a control end of the ninth transistor is connected to the first end of the second capacitor and to the second clock signal lead, a first end of the ninth transistor is connected to the first voltage signal lead, and a second end of the ninth transistor is connected to the third node.

10. The shift register unit according to claim 9, characterized in that: The second control module also includes a tenth transistor, a control end of the tenth transistor is connected to the second end of the second capacitor, a first end of the tenth transistor is connected to the second end of the ninth transistor, and a second end of the tenth transistor is connected to the third node.

11. The shift register unit according to claim 10, characterized in that: The third control module includes an eleventh transistor, a control end of the eleventh transistor is connected to the first node, a first end of the eleventh transistor is connected to the second voltage signal lead, and a second end of the eleventh transistor is connected to the third node.

12. The shift register unit according to claim 11, characterized in that: It also includes a twelfth transistor, wherein the control end of the twelfth transistor is connected to the first node, the first end of the twelfth transistor is connected to the second clock signal lead, and the second end of the twelfth transistor is connected to the second end of the first capacitor.

13. The shift register unit according to claim 12, characterized in that: The first output module includes a thirteenth transistor, a control end of the thirteenth transistor is connected to the third node, a first end of the thirteenth transistor is connected to the second voltage signal lead, and a second end of the thirteenth transistor is connected to the output end; The second output module includes a fourteenth transistor, a control end of the fourteenth transistor is connected to the first node, a first end of the fourteenth transistor is connected to the first voltage signal lead, and a second end of the fourteenth transistor is connected to the output end.

14. A gate drive circuit, characterized in that: It comprises the shift register unit as claimed in any one of claims 1 to 13.

15. A display device, characterized in that: Comprising the gate driving circuit as claimed in claim 14.

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