Control circuit and memory

Abstract

Embodiments of the present disclosure provide a control circuit and a memory. The control circuit comprises: a command decoding circuit used for, on the basis of a first clock signal, performing command decoding processing on a first pulse of a chip select signal and a command address signal to obtain a first command signal; an address decoding circuit used for, on the basis of the first command signal and the first clock signal, performing row address decoding processing on a second pulse of the chip select signal and the command address signal to obtain n second command signals; and a logic processing circuit used for performing logic processing on the basis of the n second command signals to obtain n segment activation signals. A storage array comprises m repositories, each repository comprising n segments, and m and n both are positive integers; and the segment activation signals are used for indicating whether segments of at least one corresponding repository among the m repositories are activated, thereby achieving the objective of power saving.

Description

A control circuit and a memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 3, 2023, with application number 202310815315.0 and application name “A Control Circuit and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a control circuit and a memory. Background Art

[0003] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memories that can transmit data at double the data rate (DDR) have emerged.

[0004] Take dynamic random access memory (DRAM) as an example. DRAM stores data and is periodically refreshed to maintain data integrity. As DRAM density and speed increase, the refresh operation has an increasingly significant impact on DRAM's overall performance and power consumption.

[0005] Summary of the Invention

[0006] The present disclosure provides a control circuit and a memory, which can achieve the purpose of saving power.

[0007] In a first aspect, an embodiment of the present disclosure provides a control circuit, comprising a command decoding circuit, an address decoding circuit, and a logic processing circuit, wherein the command decoding circuit is connected to the address decoding circuit, and the address decoding circuit is further connected to the logic processing circuit, wherein:

[0008] a command decoding circuit, configured to receive a command address signal, a chip select signal, and a first clock signal, and perform command decoding on a first pulse of the chip select signal and the command address signal according to the first clock signal to obtain a first command signal; wherein the first command signal is configured to indicate whether to activate m memory banks in the memory array, where m is a positive integer;

[0009] an address decoding circuit for receiving a first command signal, a first clock signal, a chip select signal, and a command address signal, and performing row address decoding on a second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals; wherein the second command signal is used to indicate whether to activate a segment of the m memory banks, where n is a positive integer;

[0010] A logic processing circuit is configured to receive n second command signals and perform logic processing based on the n second command signals to obtain n segment activation signals, wherein the segment activation signals are configured to indicate whether a segment corresponding to at least one memory bank in the m memory banks has been activated; wherein the storage array includes m memory banks, each memory bank includes n segments, and there is a corresponding relationship between the n segments and the n segment activation signals.

[0011] In some embodiments, the first command signal includes m first command sub-signals, and the m first command sub-signals have a corresponding relationship with m storage libraries, wherein: if the first command sub-signal is in a first level state, it is determined that the storage library corresponding to the first command sub-signal is activated; if the first command sub-signal is in a second level state, it is determined that the storage library corresponding to the first command sub-signal is not activated.

[0012] In some embodiments, the address decoding circuit is further used to perform row address decoding on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n third command signals; wherein the second command signal and the third command signal are in anti-phase relationship with each other; the logic processing circuit is used to receive n second command signals and n third command signals, and perform logic processing according to the n second command signals and n third command signals to obtain n segment activation signals.

[0013] In some embodiments, the logic processing circuit includes n segment processing sub-circuits, wherein: the i-th segment processing sub-circuit is used to receive the i-th second command signal and the i-th third command signal, and perform logic processing according to the i-th second command signal and the i-th third command signal to obtain the i-th segment activation signal; wherein the i-th segment activation signal is used to indicate whether there is at least one storage bank in the m storage banks whose corresponding i-th segment has been activated, and i is an integer greater than or equal to 0 and less than n.

[0014] In some embodiments, the second command signal includes m second command sub-signals; the third command signal includes m third command sub-signals; wherein the second command sub-signals and the third command sub-signals are in anti-phase relationship with each other, and the kth second command sub-signal in the second command signal and the kth third command sub-signal in the third command signal both have a corresponding relationship with the kth storage memory, and k is an integer greater than or equal to 0 and less than m.

[0015] In some embodiments, the i-th segment processing subcircuit includes m logic subcircuits and a control subcircuit, wherein: the j-th logic subcircuit is used to receive a ground signal, a j-th second command sub-signal, and a j-th third command sub-signal, and the output end of the j-th logic subcircuit is used to output the j-th first intermediate signal, where j is an integer greater than or equal to 0 and less than m; the first input end of the control subcircuit is connected to the output ends of the m logic subcircuits, the second input end of the control subcircuit is used to receive a power-on signal, and the output end of the control subcircuit is used to output the i-th segment activation signal; wherein the chip select signal indicates that the target chip is selected, and the power-on signal indicates that all power supplies of the target chip are started up.

[0016] In some embodiments, the jth logic sub-circuit includes a jth latch module and a jth gating buffer module, the output end of the jth latch module is connected to the input end of the jth gating buffer module, and the control end of the jth gating buffer module is used to receive the jth third command sub-signal; wherein: the jth latch module is used to receive the ground signal and the jth second command sub-signal, and control the latch state of the jth latch module according to the jth second command sub-signal to generate the jth second intermediate signal; the jth gating buffer module is used to receive the jth second intermediate signal and the jth third command sub-signal, and control the conduction state of the jth gating buffer module according to the jth third command sub-signal to generate the jth first intermediate signal.

[0017] In some embodiments, the jth logic sub-circuit is used to determine that the jth second intermediate signal is in the second level state and the jth gated buffer module is in the on state when the jth second command sub-signal is in the first level state and the jth third command sub-signal is in the second level state, so that the jth first intermediate signal is in the second level state.

[0018] In some embodiments, the jth logic sub-circuit is used to determine that the jth gated buffer module is in the off state when the jth second command sub-signal is in the second level state and the jth third command sub-signal is in the first level state, so that the output of the jth gated buffer module is in a high impedance state.

[0019] In some embodiments, the control subcircuit includes a first OR gate, a first buffer and an mth gated buffer module, wherein: the first input end of the first OR gate is respectively connected to the output ends of the m logic subcircuits and the output end of the mth gated buffer module, the second input end of the first OR gate is used to receive a power-on signal, the output end of the first OR gate is respectively connected to the input end of the mth gated buffer module and the input end of the first buffer, the control end of the mth gated buffer module is used to receive a power-on signal, and the output end of the first buffer is used to output the i-th segment activation signal.

[0020] In some embodiments, the control circuit further includes a mode register and an output circuit, wherein: the mode register is configured to output n initial segment mask signals, wherein the initial segment mask signal is configured to indicate whether a mask refresh is to be performed on a segment of the m memory banks as set by the mode register; the output circuit is configured to receive n segment activation signals and n initial segment mask signals, and perform an OR logic operation on the n segment activation signals and the n initial segment mask signals to generate n target segment mask signals; wherein:

[0021] If the i-th target segment mask signal is in a first level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to at least one storage bank in the m storage banks is shielded; if the i-th target segment mask signal is in a second level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to all storage banks in the m storage banks is not shielded.

[0022] In some embodiments, the first level state is a high level, and the second level state is a low level.

[0023] In some embodiments, the output circuit includes n second OR gates, wherein: the first input end of the pth second OR gate is used to receive the pth segment activation signal, and the second input end of the pth second OR gate is used to receive the pth initial segment mask signal; the output end of the pth second OR gate is used to output the pth target segment mask signal; wherein p is an integer greater than or equal to 0 and less than n.

[0024] In some embodiments, the output circuit includes n second OR gates and n second buffers, and the input end of the pth second buffer is connected to the output end of the pth second OR gate, wherein: the pth second OR gate is used to receive the pth segment activation signal and the pth initial segment mask signal, and perform an OR logic operation on the pth segment activation signal and the pth initial segment mask signal to obtain the pth intermediate segment mask signal; the pth second buffer is used to perform drive enhancement processing on the pth intermediate segment mask signal to obtain the pth target segment mask signal; wherein p is an integer greater than 0 and less than or equal to n.

[0025] In a second aspect, an embodiment of the present disclosure provides a memory, which at least includes the control circuit as described in the first aspect.

[0026] The present disclosure provides a control circuit and a memory, the control circuit comprising a command decoding circuit, an address decoding circuit, and a logic processing circuit. The command decoding circuit is configured to perform command decoding processing on a first pulse of a chip select signal and a command address signal according to a first clock signal to obtain a first command signal, the first command signal being used to indicate whether to activate m memory banks in a memory array, where m is a positive integer. The address decoding circuit is configured to perform row address decoding processing on a second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals and n third command signals, the second command signals and the third command signals being in anti-phase with each other, and the second command signal being used to indicate whether to activate a segment of the m memory banks, where n is a positive integer. The logic processing circuit is configured to perform logic processing on the n second command signals and the n third command signals to obtain n segment activation signals. The memory array comprises m memory banks, each of which comprises n segments, and there is a correspondence between the n segments and the n segment activation signals, the segment activation signals being used to indicate whether at least one segment corresponding to the memory bank in the m memory banks has been activated. In this way, if it can be determined based on the segment activation signal that the segments corresponding to certain storage libraries have been activated, which means that the segments corresponding to these storage libraries have been accessed, then the segments need to be periodically refreshed during the refresh operation phase; otherwise, if it can be determined based on the segment activation signal that the segments corresponding to certain storage libraries have not been activated, which means that the segments corresponding to these storage libraries have not been accessed, then refresh shielding can be performed on the segments during the refresh operation phase; in this way, not only can the data integrity in the storage library be maintained, but also the power consumption can be reduced, thereby achieving the purpose of power saving, and ultimately improving the memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic diagram of a structure of a control circuit according to an embodiment of the present disclosure;

[0028] FIG2 is a schematic diagram of the structure of a logic processing circuit provided in an embodiment of the present disclosure;

[0029] FIG3 is a schematic diagram of the structure of a segmented processing subcircuit provided in an embodiment of the present disclosure;

[0030] FIG4 is a schematic diagram of the structure of a logic sub-circuit provided in an embodiment of the present disclosure;

[0031] FIG5 is a schematic diagram of the structure of a control subcircuit provided in an embodiment of the present disclosure;

[0032] FIG6 is a second schematic diagram of the structure of a control circuit provided in an embodiment of the present disclosure;

[0033] FIG7 is a first schematic diagram of the structure of an output circuit provided in an embodiment of the present disclosure;

[0034] FIG8 is a second schematic diagram of the structure of an output circuit provided in an embodiment of the present disclosure;

[0035] FIG9 is a schematic diagram of the architecture of a memory provided by an embodiment of the present disclosure;

[0036] FIG10 is a schematic diagram of a local detailed structure of a control circuit provided in an embodiment of the present disclosure;

[0037] FIG11 is a second schematic diagram of a local detailed structure of a control circuit provided in an embodiment of the present disclosure;

[0038] FIG12 is a schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

[0039] FIG13 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the relevant applications and are not intended to limit the relevant applications. It should also be noted that for ease of description, only the portions relevant to the relevant applications are shown in the drawings.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0042] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0044] It should also be noted that the high level and low level used in the signals involved in the embodiments of the present disclosure refer to the logic level of the signal. There is a difference between a signal having a high level and a signal having a low level. For example, a high level may correspond to a signal having a first voltage, and a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. In addition, the logic level of the signal may be different from or opposite to the described logic level. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

[0045] Understandably, dynamic random access memory (DRAM) requires refresh operations to maintain data in the memory array. Each refresh operation opens at least one bank in the memory array and performs a refresh operation on the enabled bank. However, as DRAM density and speed increase, the impact of refresh operations on overall DRAM performance and power consumption becomes increasingly significant.

[0046] In the embodiment of the present disclosure, for a storage library in a storage array, each storage library can be divided into multiple segments (Segments / Sections). The storage density corresponds to the number of segments. For example, if the storage density is 8GB, it can be divided into 8 segments; if the storage density is 6GB, it can be divided into 6 segments; if the storage density is 4GB, it can be divided into 4 segments; however, this is not specifically limited here.

[0047] In some embodiments, assume that the memory array includes eight memory banks, specifically Bank0, Bank1, Bank2, ..., Bank7. Regardless of whether a self-refresh operation is in progress, the segments corresponding to each of these eight memory banks can be independently configured. Taking Mode Register 23 (MR23) as an example, MR23 can be accessed via a Mode Register Write (MRW) command to indicate the masking status of each segment. Table 1 shows an example of a segment masking application.

[0048] Table 1

[0049] Here, each memory bank can have up to 8 segments, specifically: Segment 0, Segment 1, Segment 2, ..., Segment 7. The segment mask is used to control whether a segment of the entire storage array is refreshed. When a segment is masked via the MRW command, the self-refresh operation of the entire segment is blocked, and the data retention of the segment cannot be guaranteed in the self-refresh mode. As can be seen from Table 1, the segment mask corresponding to Segment 2 and Segment 7 is 1. At this time, in Bank 0 to Bank 7, the refresh operations of Segment 2 and Segment 7 are both masked (Masked, M).

[0050] In actual applications, whether to perform refresh shielding on the segments of the storage library is determined. If a segment has not been accessed (i.e., no read or write operations have been performed, etc.), then the data in the segment is not of great value. At this time, the segment can be refreshed without performing a refresh operation, i.e., the segment can be refresh shielded.

[0051] Based on this, an embodiment of the present disclosure provides a control circuit, which includes a command decoding circuit, an address decoding circuit, and a logic processing circuit. In which, the storage array includes m storage banks, each storage bank includes n segments, and there is a corresponding relationship between the n segments and the n segment activation signals. The segment activation signal is used to indicate whether there is at least one segment corresponding to the storage bank in the m storage banks that has been activated. In this way, if it can be determined according to the segment activation signal that the segments corresponding to some storage banks have been activated, it means that the segments corresponding to these storage banks have been accessed, then it is necessary to perform periodic refresh on the segments during the refresh operation phase; otherwise, if it can be determined according to the segment activation signal that the segments corresponding to some storage banks have not been activated, it means that the segments corresponding to these storage banks have not been accessed, then refresh shielding can be performed on the segments during the refresh operation phase; in this way, not only can the data integrity in the storage bank be maintained, but also the power consumption can be reduced, thereby achieving the purpose of power saving, and ultimately improving the memory performance.

[0052] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0053] In one embodiment of the present disclosure, referring to FIG1 , a schematic diagram of the structure of a control circuit provided by an embodiment of the present disclosure is shown. As shown in FIG1 , the control circuit 10 may include a command decoding circuit 101, an address decoding circuit 102, and a logic processing circuit 103. The command decoding circuit 101 is connected to the address decoding circuit 102, and the address decoding circuit 102 is further connected to the logic processing circuit 103.

[0054] The command decoding circuit 101 is configured to receive a command address signal, a chip select signal, and a first clock signal, and perform command decoding on the first pulse of the chip select signal and the command address signal according to the first clock signal to obtain a first command signal. The first command signal is configured to indicate whether to activate m memory banks in the memory array, where m is a positive integer.

[0055] The address decoding circuit 102 is configured to receive a first command signal, a first clock signal, a chip select signal, and a command address signal, and perform row address decoding on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to generate n second command signals; wherein the second command signal is used to indicate whether to activate a segment of the m memory banks, where n is a positive integer;

[0056] The logic processing circuit 103 is used to receive n second command signals, perform logic processing according to the n second command signals, and obtain n segment activation signals, which are used to indicate whether a segment corresponding to at least one storage library in the m storage libraries has been activated.

[0057] It should be noted that the control circuit 10 of the disclosed embodiment is applied to a memory and can solve the problem that the refresh operation has a significant impact on the overall performance and power consumption of the memory. Specifically, in the disclosed embodiment, the control circuit 10 can be a refresh control circuit, and during the refresh operation phase, it can reduce power consumption, thereby achieving the purpose of power saving.

[0058] It should also be noted that in the disclosed embodiment, the storage array may include m memory banks, each of which may include n segments, and there is a corresponding relationship between the n segments and the n segment activation signals. That is, the i-th segment activation signal indicates whether the i-th segment of at least one memory bank among all the memory banks has been activated; where i is an integer greater than or equal to 0 and less than n.

[0059] For example, assuming that m is equal to 16 and n is equal to 8, there are a total of 16 storage banks, specifically Bank0, Bank1, Bank2, ..., Bank15; each storage bank can include 8 segments, specifically Segment 0, Segment 1, Segment 2, ..., Segment 7. Accordingly, the segment activation signals generated here are also 8, and the i-th segment activation signal can be represented by ActSegMsk Indicates that the segment activation signals corresponding to the 8 segments are: ActSegMsk <0> 、ActSegMsk <1> 、ActSegMsk <2> ,…,ActSegMsk <7> Here, if ActSegMsk The signal is in the first level state, indicating that the i-th segment of all memory banks in the storage array has not been activated; if ActSegMsk If the signal is in the second level state, it indicates that the i-th segment of at least one memory bank in the memory array has been activated.

[0060] It should also be noted that, in the embodiment of the present disclosure, since the segment activation signal can determine whether the segments corresponding to certain storage libraries have been activated, specifically, if the segments corresponding to these storage libraries have been activated, it means that this segment has been accessed and the data stored in the segment is valid. In order to ensure data integrity, this segment cannot be shielded and refreshed during the refresh operation phase; if the segments corresponding to these storage libraries have not been activated, it means that this segment has not been accessed and the data stored in the segment is not important. In this case, this segment can be shielded and refreshed during the refresh operation phase, thereby reducing the refresh current and refresh power consumption, thereby achieving the purpose of saving power.

[0061] In some embodiments, the first command signal may include m first command sub-signals, and the m first command sub-signals have a corresponding relationship with m storage banks, wherein:

[0062] If the first command sub-signal is in a first level state, determining that the storage bank corresponding to the first command sub-signal performs an activation operation;

[0063] If the first command sub-signal is in the second level state, it is determined that the memory bank corresponding to the first command sub-signal does not perform an activation operation.

[0064] It should be noted that, in the embodiment of the present disclosure, the first command signal can be used to indicate which storage bank to activate, and the first command signal can be represented by ActBnk1. In addition, the first command signal is not a single signal, but represents a group of signals. Here, the number of first command sub-signals in the first command signal is the same as the number of storage banks, that is, each storage bank corresponds to a first command sub-signal. Among them, the lth first command sub-signal corresponding to the lth storage bank can be represented by ActBnk1. <l>It means that l is an integer greater than or equal to 0 and less than m.

[0065] It should also be noted that, in the embodiment of the present disclosure, the first level state may be a high level, such as logic 1; the second level state may be a low level, such as logic 0, but this is not specifically limited.

[0066] That is, in the embodiment of the present disclosure, if the lth first command sub-signal is at a high level, then it can be determined that the lth storage bank performs an activation operation; if the lth first command sub-signal is at a low level, then it can be determined that the lth storage bank does not perform an activation operation.

[0067] It can be understood that in the embodiment of the present disclosure, the command address signal can be represented by CA<6:0>. It should be noted that the command address signal here is not a single signal, but represents a group of signals, specifically CA0, CA1, CA2, CA3, CA4, CA5 and CA6. The chip select signal can be represented by CS, and the chip select signal indicates that the target chip is selected. In this way, for the first command signal, it can be obtained by the command decoding circuit 101 performing command decoding processing on the first pulse of the chip select signal and the command address signal according to the first clock signal.

[0068] In some embodiments, the address decoding circuit 102 is further configured to perform row address decoding on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n third command signals; wherein the second command signal and the third command signal are in anti-phase relationship with each other;

[0069] The logic processing circuit 103 is configured to receive n second command signals and n third command signals, and perform logic processing according to the n second command signals and the n third command signals to obtain n segment activation signals.

[0070] It should be noted that in the disclosed embodiment, the third command signal is the inverted signal of the second command signal. In other words, the third command signal can be obtained by inverting the second command signal. Therefore, the third command signal can be generated in the address decoding circuit 102 or in the logic processing circuit 103, without specific limitation.

[0071] In some embodiments, as for the logic processing circuit 103, referring to FIG. 2 , the logic processing circuit 103 may include n segment processing sub-circuits, wherein:

[0072] an i-th segment processing sub-circuit, configured to receive the i-th second command signal and the i-th third command signal, and perform logic processing according to the i-th second command signal and the i-th third command signal to obtain an i-th segment activation signal;

[0073] The i-th segment activation signal is used to indicate whether the i-th segment corresponding to at least one storage bank in the m storage banks has been activated, and i is an integer greater than or equal to 0 and less than n.

[0074] It should be noted that in the disclosed embodiment, the i-th segment processing subcircuit can be represented by segment processing subcircuit i. Thus, in Figure 2, the n segment processing subcircuits may include: segment processing subcircuit 0, segment processing subcircuit 1, ..., segment processing subcircuit n-1. Each segment processing subcircuit can be used to process a segment corresponding to m storage banks. Specifically, each segment activation signal can be used to indicate whether a segment corresponding to at least one storage bank in the m storage banks has been activated.

[0075] It should also be noted that in the embodiments of the present disclosure, the i-th second command signal is not a single signal, but represents a group of signals. The i-th third command signal is also not a single signal, but represents a group of signals. In some embodiments, for each second command signal and each third command signal, the second command signal may include m second command sub-signals, and the third command signal may include m third command sub-signals.

[0076] Among them, the second command sub-signal and the third command sub-signal are in anti-phase relationship with each other, and the kth second command sub-signal in the second command signal and the kth third command sub-signal in the third command signal both have a corresponding relationship with the kth storage memory, and k is an integer greater than or equal to 0 and less than m.

[0077] It can be understood that in the embodiment of the present disclosure, for the address decoding circuit 102, the second command signal and the third command signal generated are in anti-phase relationship with each other. <m-1:0>Indicates that the qth third command signal can be used SegqActN <m-1:0>"N" represents inversion, and q is an integer greater than or equal to 0 and less than n.

[0078] For example, assuming that the value of m is 16, then for the qth second command signal, it may include SegqAct <0> 、SegqAct <1> ,…, SegqAct <15> For the qth third command signal, it may include SegqActN <0> 、SegqActN <1> ,…,SegqActN <15> So, for Bank0, SegqAct <0> and SegqActN <0> It has a corresponding relationship with Bank0; for Bank1, SegqAct <1> and Segq ActN <1> It has a corresponding relationship with Bank1; and so on, for Bank15, SegqAct <15> and SegqActN <15> Corresponding to Bank15.

[0079] In some embodiments, for a segment processing sub-circuit i, referring to FIG3 , the i-th segment processing sub-circuit may include m logic sub-circuits 301 and a control sub-circuit 302 , where:

[0080] Among the m logic sub-circuits 301, the j-th logic sub-circuit is used to receive the ground signal, the j-th second command sub-signal, and the j-th third command sub-signal, and the output end of the j-th logic sub-circuit is used to output the j-th first intermediate signal, where j is an integer greater than or equal to 0 and less than m;

[0081] The first input terminal of the control subcircuit 302 is connected to the output terminals of the m logic subcircuits 302 , the second input terminal of the control subcircuit 302 is used to receive a power-on signal, and the output terminal of the control subcircuit 302 is used to output the i-th segment activation signal.

[0082] It should be noted that, in the embodiment of the present disclosure, the chip select signal indicates that the target chip is selected, and the power-on signal indicates that all power supplies of the target chip have been started.

[0083] It should also be noted that in the embodiment of the present disclosure, in the m logic sub-circuits 301, the jth logic sub-circuit can be U j 3 includes the 0th logic subcircuit (also called "logic subcircuit 0") U0, the 1st logic subcircuit (also called "logic subcircuit 1") U1, ..., the m-1th logic subcircuit (also called "logic subcircuit m-1") U m-1 There are m logic sub-circuits in total.

[0084] In some embodiments, for the jth logic sub-circuit U j As shown in FIG4 , the j-th logic subcircuit U j It can include the jth latch module A j and the jth gated buffer module B j , the jth latch module A j The output end and the j-th gate buffer module B j The input terminal of the j-th gate buffer module B j The control terminal is used to receive the j-th third command sub-signal; wherein:

[0085] The jth latch module A j , used to receive the ground signal and the jth second command sub-signal, and control the jth latch module A according to the jth second command sub-signal j The latch state of , generates the jth second intermediate signal;

[0086] The jth gated buffer module B j , for receiving the jth second intermediate signal and the jth third command sub-signal, and controlling the jth gate buffer module B according to the jth third command sub-signal j is in the on state, generating the jth first intermediate signal.

[0087] It should be noted that, in the embodiment of the present disclosure, for each latch module, the latch module may include a clock terminal (CK), an input terminal (D), and an output terminal (Q). The latch module here is different from a D-type flip-flop. The D-type flip-flop is clock-edge triggered, while the latch module controls whether it is turned on or off based on the level state. For example, the jth latch module A j For example, only when the jth second command sub-signal is in a high level state can the jth latch module A be j The ground signal connected to the D terminal is transmitted to the jth latch module A j The Q terminal of the latch module is switched to the low level state. In addition, the initial value of the Q terminal of each latch module is the high level state.

[0088] It should also be noted that, in the disclosed embodiments, each gated buffer module may include an input terminal, an output terminal, and a control terminal. The control terminal of the gated buffer module is configured to receive a control signal. The gated buffer module is only turned on when the control signal is low, transmitting the signal received at the input terminal of the gated buffer module to the output terminal of the gated buffer module.

[0089] It should also be noted that, in the embodiment of the present disclosure, each logic sub-circuit includes a gated buffer module. Since the gated buffer module has an additional control signal compared to an ordinary buffer, it indicates that data will be transmitted only when the control signal is at a low level. In this way, although the first input terminal of the control sub-circuit 302 is connected to the output terminals of m logic sub-circuits 302, so that multiple first intermediate signals are simultaneously connected to the input of the control sub-circuit 302, there will be signal conflicts at this time. However, this situation can be avoided by adding a gated buffer module, because for the segments of the storage library that have not been accessed, the corresponding gated buffer module is not turned on, so that these first intermediate signals have no driving capability for the input of the connected control sub-circuit 302.

[0090] It can also be understood that in the embodiment of the present disclosure, since the gated buffer module is affected by its own control terminal, it can include two states: conductive and non-conductive, which leads to different outputs of the gated buffer module. j The two output situations are described in detail.

[0091] In one possible implementation, the jth logic subcircuit U j , used to determine that the jth second intermediate signal is in the second level state and the jth gate buffer module B is in the second level state when the jth second command sub-signal is in the first level state and the jth third command sub-signal is in the second level state j is in a conducting state, so that the jth first intermediate signal is in a second level state.

[0092] In another possible implementation, the j-th logic sub-circuit U j , used to determine the jth gate buffer module B when the jth second command sub-signal is in the second level state and the jth third command sub-signal is in the first level state j In the off state, so that the j-th gate buffer module B j The output is in high impedance state.

[0093] It should be noted that, in the embodiment of the present disclosure, the first level state may be a high level, such as logic 1; the second level state may be a low level, such as logic 0, but this is not specifically limited.

[0094] It should also be noted that, in the embodiment of the present disclosure, the j-th logic sub-circuit U j For example, if the jth second command sub-signal is high, then the latch module A j A logic 0 at its input can be transferred to latch module A j The output end of the gate buffer module B is low level. Since the jth third command sub-signal is low level, the gate buffer module B j In the on state, that is, the jth first intermediate signal is low. Or, if the jth second command sub-signal is low, then the latch module A j Unable to transmit logic 0 at its input to latch module A j The output end of the j-th second intermediate signal maintains the initial state (high level at this time); since the j-th third command sub-signal is high level, the gate buffer module B j Not conducting, that is, gated buffer module B j The output is in high impedance state.

[0095] For example, assuming that m is 16, taking the 0th segment as an example, the 16 second command sub-signals may include: Seg0Act <0> 、Seg0Act <1> ,…,Seg0Act <15> For the 16 third command sub-signals, they may include: Seg0ActN <0> 、Seg0ActN <1> ,…,Seg0ActN <15> If Seg0Act <0> is low, Seg0ActN <0> = is high, which means that the 0th segment of the 0th memory bank has not been accessed, so the latch module A0 and the gate buffer module B0 do not transmit data. <0> There is a pulse, Seg0Act <0> The latch module A0 can output logic 0, and the gated buffer module B0 will also output logic 0 in Seg0ActN. <0> is turned on under the control of a low level, and transmits logic 0 to the first input terminal of the control sub-circuit 302. In addition, for the 0th segment of the rth memory bank that has not been accessed, Seg0 Act <r>is low, Seg0ActN <r>When the gated buffer module is high, the gated buffer module is not conducting, and the output is in a high-impedance state. It has no driving capability for the first input terminal of the control sub-circuit 302, thereby avoiding signal conflict caused by 16 gated buffer modules simultaneously controlling the first input terminal of the sub-circuit 302. Here, r = 0, 1, 2, ..., 15.

[0096] In some embodiments, as for the control sub-circuit 302, referring to FIG5, the control sub-circuit 302 may include a first OR gate 601, a first buffer 602, and an mth gated buffer module 603, wherein:

[0097] The first input end of the first OR gate 601 is respectively connected to the output end of the m logic sub-circuits 301 and the output end of the m-th gate-controlled buffer module 603, the second input end of the first OR gate 601 is used to receive a power-on signal, the output end of the first OR gate 601 is respectively connected to the input end of the m-th gate-controlled buffer module 603 and the input end of the first buffer 602, the control end of the m-th gate-controlled buffer module 603 is used to receive a power-on signal, and the output end of the first buffer 602 is used to output the i-th segment activation signal.

[0098] It should be noted that in the disclosed embodiments, the power-on signal can be represented by PwrUp. The power-on signal indicates that all power supplies of the target chip have been started, or that initialization of the target chip has been completed. If the power-on signal is high, it indicates that the target chip is being powered on; if the power-on signal becomes low, it indicates that power-on of the target chip is complete.

[0099] It should also be noted that, in the embodiment of the present disclosure, before power-on is completed and just after power-on is completed, the i-th segment activation signal is at a high level (i.e., logic 1). Specifically, before power-on is completed, the power-on signal is at a high level, and the power-on signal and the signals at the output ends of the m logic sub-circuits 301 are subjected to an OR logic operation through the first OR gate 601, and the i-th segment activation signal that is ultimately output is at a high level; since power-on has not yet been completed, no segment in the storage library will be activated. In addition, just after power-on is completed, since the power-on signal has just flipped to a low level, before the activation operation occurs, the i-th segment activation signal that is ultimately output is also at a high level.

[0100] In short, before power-on is completed and immediately after power-on is completed, for all segments in the memory bank (eg, segment 0 to segment 7), each segment is not activated at this time, so all segment activation signals ActSegMsk<7:0> are at a high level.

[0101] In some embodiments, based on the control circuit 10 shown in FIG1 , referring to FIG6 , the control circuit 10 may further include a mode register 104 and an output circuit 105 , wherein:

[0102] The mode register 104 is used to output n initial segment mask signals, wherein the initial segment mask signal is used to indicate whether to perform mask refresh on a segment of the m memory banks set by the mode register;

[0103] The output circuit 105 is configured to receive n segment activation signals and n initial segment mask signals, and perform OR logic processing on the n segment activation signals and the n initial segment mask signals to generate n target segment mask signals.

[0104] It should be noted that, in the embodiment of the present disclosure, the i-th initial segment mask signal can be represented by MRSeg Msk Mode register 104 may be mode register MR23. The i-th initial segment mask signal is specifically used to indicate whether mode register MR23 is set to mask the refresh operation for the i-th segment. See Table 1 above. If mode register MR23 is set to mask the i-th segment, then the i-th segment will definitely mask the refresh operation. Thus, an i-th target segment mask signal can be generated by performing an OR logic operation based on the i-th segment activation signal and the i-th initial segment mask signal.

[0105] In some embodiments, if the i-th target segment mask signal is in a first level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to at least one storage bank among the m storage banks is masked; if the i-th target segment mask signal is in a second level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to all storage banks among the m storage banks is not masked.

[0106] It should be noted that, in the embodiment of the present disclosure, the first level state may be a high level, such as logic 1; the second level state may be a low level, such as logic 0, but this is not specifically limited.

[0107] It should also be noted that, in the embodiment of the present disclosure, the target segment mask signal is used to indicate whether to mask the refresh operation of a certain segment corresponding to at least one of the m memory banks. Specifically, during the refresh operation phase, if the target segment mask signal is high, then the refresh operation of a certain segment corresponding to at least one of the m memory banks can be masked; otherwise, if the target segment mask signal is low, then there is no need to mask the refresh operation of a certain segment corresponding to all of the m memory banks, that is, at this time, the refresh operation needs to be performed on a certain segment corresponding to all of the m memory banks.

[0108] For example, taking the i-th segment as an example, the i-th target segment mask signal can be represented by SegMsk If SegMsk The signal is high, then the refresh operation of the i-th segment corresponding to at least one bank in the m banks can be shielded; if SegMsk If the signal is at a low level, a refresh operation needs to be performed on the i-th segment corresponding to all the memory banks in the m memory banks.

[0109] In one possible implementation, referring to FIG7 , the output circuit 105 may include n second OR gates, where:

[0110] The first input end of the pth second OR gate is used to receive the pth segment activation signal, the second input end of the pth second OR gate is used to receive the pth initial segment mask signal; the output end of the pth second OR gate is used to output the pth target segment mask signal.

[0111] In the embodiment of the present disclosure, p is an integer greater than or equal to 0 and less than n.

[0112] It should also be noted that in FIG7, the n second OR gates are respectively represented by D0, D1, ..., D n-1 Indicates that for the pth segment, the pth second OR gate D p The first input terminal is used to receive the p-th segment activation signal ActSegMsk , the pth second OR gate D p The second input terminal is used to receive the p-th initial segment mask signal MRSegMsk ; The pth second OR gate D p The output terminal is used to output the pth target segment mask signal SegMsk .

[0113] In another possible implementation, referring to FIG8 , the output circuit 105 may include n second OR gates and n second buffers, and the input end of the p-th second buffer is connected to the output end of the p-th second OR gate, wherein:

[0114] a pth second OR gate, configured to receive the pth segment activation signal and the pth initial segment mask signal, and perform an OR logic operation on the pth segment activation signal and the pth initial segment mask signal to obtain a pth intermediate segment mask signal;

[0115] The pth second buffer is used to perform drive enhancement processing on the pth intermediate segment mask signal to obtain the pth target segment mask signal.

[0116] In the embodiment of the present disclosure, p is an integer greater than or equal to 0 and less than n.

[0117] It should also be noted that in FIG8, n second OR gates are respectively represented by D0, D1, ..., D n-1 Indicates that n second buffers are represented by F0, F1, ..., F n-1 Indicates that for the pth segment, the pth second OR gate D p The first input terminal is used to receive the p-th segment activation signal ActSegMsk , the pth second OR gate D p The second input terminal is used to receive the p-th initial segment mask signal MRSeg Msk ; The pth second OR gate D p The output terminal of the pth second buffer F p The input terminal of the pth second buffer F p The output terminal is used to output the pth target segment mask signal SegMsk .

[0118] Simply put, Figure 7, compared to Figure 8, simply adds a second buffer at the output end, which not only provides a delay function but also enhances the signal driving capability. Specifically, for the p-th target segment mask signal and the p-th intermediate segment mask signal, the p-th target segment mask signal has a stronger driving capability than the p-th intermediate segment mask signal. In addition, it should be noted that if the second buffer is adjusted to a gated buffer (i.e., an additional control signal is added), then the control signal can also play a role in controlling transmission.

[0119] This embodiment provides a control circuit, wherein a command decoding circuit is configured to perform command decoding processing on the first pulse of a chip select signal and a command address signal based on a first clock signal to obtain a first command signal; an address decoding circuit is configured to perform row address decoding processing on the second pulse of the chip select signal and the command address signal based on the first command signal and the first clock signal to obtain n second command signals and n third command signals; and a logic processing circuit is configured to perform logic processing on the n second command signals and the n third command signals to obtain n segment activation signals. A corresponding relationship exists between the n segments of each memory bank and the n segment activation signals, and the segment activation signals are configured to indicate whether a segment corresponding to at least one memory bank among the m memory banks has been activated. In this way, if it can be determined based on the segment activation signal that the segments corresponding to certain storage libraries have been activated, which means that the segments corresponding to these storage libraries have been accessed, then periodic refresh needs to be performed on the segments during the refresh operation phase; otherwise, if it can be determined based on the segment activation signal that the segments corresponding to certain storage libraries have not been activated, which means that the segments corresponding to these storage libraries have not been accessed, then refresh shielding can be performed on the segments during the refresh operation phase; in this way, not only the data integrity in the storage library can be maintained, but also the power consumption can be reduced, thereby achieving the purpose of saving power.

[0120] In another embodiment of the present disclosure, refer to Figure 9, which shows a schematic diagram of the architecture of a memory provided by an embodiment of the present disclosure. As shown in Figure 9, the memory 1000 may include a control circuit 10 and a storage array 1001, and the storage array 1001 may include a plurality of storage banks, specifically Bank0, Bank1, Bank2, ..., Bank15. Among them, the control circuit 10 is used to output the target segment mask signal SegMsk<7:0>, and then the target segment mask signal SegMsk<7:0> is sent to each storage bank in the storage array 1001 to control the refresh operation of each storage bank. For example, taking Table 1 as an example, if the segment mask signals corresponding to segment 2 and segment 7 are both 1, then the refresh operations of segment 2 and segment 7 in these storage banks are all masked.

[0121] Furthermore, in the embodiment of the present disclosure, the control circuit 10 here can be a power-saving refresh operation control circuit. Based on the description of the aforementioned embodiment, the control circuit 10 at least includes a logic processing circuit, a mode register, and an output circuit. Among them, the logic processing circuit is used to output the segment activation signal ActSeg Msk<7:0>, the mode register is used to output the initial segment mask signal MRSegMsk<7:0>, and the output circuit is used to perform OR logic processing on the segment activation signal ActSegMsk<7:0> and the initial segment mask signal MRSegMsk<7:0>, and finally generate the target segment mask signal SegMsk<7:0>, and then the target segment mask signal SegMsk<7:0> can be sent to each memory bank in the storage array 1001.

[0122] In a specific embodiment, assuming that the value of m is 16 and the value of n is 8, based on the refinement and integration of the aforementioned embodiments, FIG10 is a schematic diagram of a partially refined structure of a control circuit 10 provided by an embodiment of the present disclosure. As shown in FIG10 , a command decoding circuit 101 and an address decoding circuit 102 may be included. The input of the command decoding circuit 101 includes the command address signal CA<6:0>, the chip select signal CS, and the first clock signal Clk, and the output of the command decoding circuit 101 is the first command signal ActBnk1; here, in the command decoding circuit 101, the first pulse of the chip select signal CS and the command address signal CA<6:0> are command-decoded according to the first clock signal Clk to obtain the first command signal ActBnk1, and the first command signal ActBnk1 is used to indicate whether to activate the 16 memory banks in the memory array; the input of the address decoding circuit 102 may include the command address signal CA<6:0>, the chip select signal CS, the first command signal ActBnk1, and the first clock signal Clk In the address decoding circuit 102, the second pulse of the chip select signal CS and the command address signals CA<6:0> are decoded according to the first command signal ActBnk1 and the first clock signal Clk to output seven second command signals and seven third command signals. The second command signals indicate whether to activate a segment of the 16 memory banks, and the third command signals are inverted versions of the second command signals. Specifically, the second command signals are Seg0Act<15:0>, Seg1Act<15:0>, ..., Seg7Act<15:0>, and the third command signals are Seg0ActN<15:0>, Seg1ActN<15:0>, ..., Seg7ActN<15:0>. For example, taking Seg0Act<15:0> as an example, this signal indicates whether to activate the 0th segment of the 16 memory banks.

[0123] Furthermore, taking the 0th segment as an example, FIG11 is a schematic diagram of a detailed partial structure of the logic processing circuit in the control circuit 10. As shown in FIG11 , this may include 16 logic sub-circuits 301 and control sub-circuits 302, wherein each logic sub-circuit may be composed of a latch module and a gated buffer module, and the control sub-circuit 302 may be composed of a first OR gate 601, a first buffer 602, and an mth gated buffer module 603. For a detailed connection relationship, see FIG11 .

[0124] In the embodiment of the present disclosure, for the power-saving control circuit 10 in the refresh operation mode, on the one hand, according to the technical standards formulated by the Joint Electron Device Engineering Council (JEDEC), the segmentation can be performed according to different storage densities, and the access status of each segment of each memory bank can be obtained through the command decoding circuit 101 and the address decoding circuit 102. On the other hand, the SegxAct<15:0> / SegxActN<15:0> generated according to the ActBnk1 command will be sent to the logic processing circuit in the control circuit 10 to generate the segment activation signal ActSegMsk<7:0>, where x=0,1,2,…,7. Among them, at the xth segment activation signal ActSegMsk <x>When it is low, it means that the xth segment of the 16 memory banks has been accessed. Then the refresh operation cannot be blocked during the refresh operation. At this time, the refresh operation needs to be performed on the xth segment of all the memory banks in the 16 memory banks. The xth segment activation signal ActSegMsk <x>When it is at a high level, it means that the xth segment corresponding to at least one memory bank has not been accessed. Therefore, when performing a refresh operation, the refresh operation of the xth segment of at least one memory bank among the 16 memory banks can be shielded, thereby achieving the purpose of power saving.

[0125] Based on the control circuit 10 of the aforementioned embodiment, FIG12 is a signal timing diagram provided by the embodiment of the present disclosure. As shown in FIG12, Clk is the first clock signal, CS is the chip select signal, CA<6:0> is the command address signal, and PwrUp is the power-on signal. Here, taking the y-th memory bank and the 0-th segment as an example, based on the first pulse of the chip select signal CS, the first pulse of the chip select signal CS and the command address signal CA<6:0> can be command-decoded according to the first clock signal Clk to obtain the first command signal ActBnk1 to indicate whether the y-th memory bank in the storage array is to be activated; then, based on the second pulse of the chip select signal CS, the second pulse of the chip select signal CS and the command address signal CA<6:0> can be row-decoded according to the first command signal ActBnk1 and the first clock signal Clk to obtain the second command sub-signal Seg0Act. <y>and the third command sub-signal Seg0ActN <y>; Among them, the second command sub-signal Seg0Act <y>The third command sub-signal Seg0ActN is used to indicate whether to activate the 0th segment of the yth memory bank. <y>The second command sub-signal Seg0Act <y>Inverted signal; in this way, after obtaining the second command sub-signal Seg0Act<15:0> and the third command sub-signal Seg0ActN<15:0> of all memory banks, these second command sub-signals Seg0Act<15:0> and the third command sub-signal Seg0ActN<15:0> are logically processed by the latch module and the gate buffer module to obtain the first intermediate signal; then logical processing is performed according to the power-up signal PwrUp and the first intermediate signal to obtain the segmented activation signal ActSegMsk <0> , where the segment activation signal is used to indicate whether the 0th segment corresponding to the yth storage bank has been activated.

[0126] Specifically, in FIG12, if the second command sub-signal Seg0Act <y>From low level to high level, the third command sub-signal Seg0ActN <y>Then it changes from high level to low level, at this time, the 0th segment of the yth memory bank has been accessed, that is, the 0th segment of the yth memory bank is activated. In this way, for the 0th segment of the 16 memory banks, if the second command sub-signal Seg0Act <y>The high level pulse means that the 0th segment of the yth memory bank has been accessed. Although the first input terminal of the control sub-circuit 302 is connected to the output terminals of the 16 gated buffer modules, only when the second command sub-signal Seg0Act <y>When a high-level pulse appears, the latch module corresponding to the y-th memory bank outputs a low-level signal. At this time, the gated buffer module connected to the latch module can be turned on to transmit the low-level signal received at the input end of the gated buffer module to the output end of the gated buffer module. For the segments of other memory banks that have not been accessed, the corresponding gated buffer modules are not turned on at this time. Therefore, the first intermediate signal received at the first input end of the control subcircuit 302 is a low-level signal. According to the power-on signal PwrUp and the first intermediate signal, an OR logic process is performed. Since the power-on signal PwrUp and the first intermediate signal are both low-level, the segment activation signal ActSegMsk is finally obtained. <0> In addition, the segment activation signal ActSeg Msk <0> The falling edge of the second command signal Seg0Act <y>There is a slight delay time between the rising edges of , which is generated by logic devices such as the latch module, the gate buffer module, the first OR gate and the first buffer in the segment processing sub-circuit.

[0127] Thus, in the embodiment of the present disclosure, for the memory 1000 shown in FIG9 , before and immediately after power-on, the state of the segment activation signal ActSegMsk<7:0> is high. When the i-th segment of the corresponding memory bank is accessed, the corresponding segment activation signal ActSegMsk<7:0> is high. It will become a low level, and then the segment activation signal ActSegMsk<7:0> is logically ORed with the initial segment mask signal MRSegMsk<7:0> set by the mode register to obtain the final target segment mask signal SegMsk<7:0>; then the target segment mask signal SegMsk<7:0> is sent to the storage array 1001 for controlling the mask refresh operation, thereby reducing power consumption and achieving the purpose of saving power.

[0128] In another embodiment of the present disclosure, referring to Figure 13, which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. As shown in Figure 13, the memory 1000 at least includes the control circuit 10 as described in the above embodiment.

[0129] In some embodiments, the memory 1000 may include a DRAM chip. The DRAM chip may conform not only to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited herein.

[0130] In the embodiment of the present disclosure, for the memory 1000, since the segment activation signal is used to indicate whether the segment corresponding to at least one memory bank among the multiple memory banks has been activated, if it can be determined based on the segment activation signal that the segments corresponding to certain memory banks have been activated, it means that the segments corresponding to these memory banks have been accessed, and then it is necessary to perform periodic refresh on these segments during the refresh operation phase; otherwise, if it can be determined based on the segment activation signal that the segments corresponding to certain memory banks have not been activated, it means that the segments corresponding to these memory banks have not been accessed, and then refresh masking can be performed on these segments during the refresh operation phase; in this way, not only can the data integrity in the memory banks be maintained, but also power consumption can be reduced, achieving the purpose of saving power, and ultimately improving memory performance.

[0131] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0132] It should be noted that, in this disclosure, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0133] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0134] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0135] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0136] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0137] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / x> < / x> < / r> < / r> < / l>

Claims

1. A control circuit (10), characterized in that: The control circuit (10) comprises a command decoding circuit (101), an address decoding circuit (102) and a logic processing circuit (103), wherein the command decoding circuit (101) is connected to the address decoding circuit (102), and the address decoding circuit (102) is also connected to the logic processing circuit (103), wherein: The command decoding circuit (101) is used to receive a command address signal, a chip select signal and a first clock signal, and perform command decoding processing on the first pulse of the chip select signal and the command address signal according to the first clock signal to obtain a first command signal; wherein the first command signal is used to indicate whether to activate m memory banks in the storage array (1001), where m is a positive integer; The address decoding circuit 102 is used to receive the first command signal, the first clock signal, the chip select signal and the command address signal, and perform row address decoding processing on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals; wherein the second command signal is used to indicate whether to activate a certain segment of the m memory banks, and n is a positive integer; The logic processing circuit (103) is used to receive the n second command signals, perform logic processing according to the n second command signals, and obtain n segment activation signals, wherein the segment activation signals are used to indicate whether a segment corresponding to at least one storage bank in the m storage banks has been activated; The storage array (1001) includes m storage bins, each of which includes n segments, and there is a corresponding relationship between the n segments and the n segment activation signals.

2. The control circuit (10) according to claim 1, characterized in that: The first command signal includes m first command sub-signals, and the m first command sub-signals have a corresponding relationship with the m storage bins, wherein: If the first command sub-signal is in a first level state, determining that the storage bank corresponding to the first command sub-signal performs an activation operation; If the first command sub-signal is in the second level state, it is determined that the storage memory corresponding to the first command sub-signal does not perform an activation operation.

3. The control circuit (10) according to any one of claims 1 to 2, characterized in that: The address decoding circuit (102) is further used to perform row address decoding processing on the second pulse of the chip selection signal and the command address signal according to the first command signal and the first clock signal to obtain n third command signals; wherein the second command signal and the third command signal are in anti-phase relationship with each other; The logic processing circuit (103) is used to receive the n second command signals and the n third command signals, and perform logic processing according to the n second command signals and the n third command signals to obtain n segment activation signals.

4. The control circuit (10) according to claim 3, characterized in that: The logic processing circuit (103) comprises n segment processing sub-circuits, wherein: an i-th segment processing subcircuit, configured to receive an i-th second command signal and an i-th third command signal, and perform logic processing according to the i-th second command signal and the i-th third command signal to obtain an i-th segment activation signal; The i-th segment activation signal is used to indicate whether the i-th segment corresponding to at least one storage bank in the m storage banks has been activated, and i is an integer greater than or equal to 0 and less than n.

5. The control circuit (10) according to claim 4, characterized in that: The second command signal includes m second command sub-signals; The third command signal includes m third command sub-signals; Among them, the second command sub-signal and the third command sub-signal are in anti-phase relationship with each other, and the kth second command sub-signal in the second command signal and the kth third command sub-signal in the third command signal both have a corresponding relationship with the kth storage memory, and k is an integer greater than or equal to 0 and less than m.

6. The control circuit (10) according to claim 5, characterized in that: The i-th segment processing subcircuit comprises m logic subcircuits (301) and a control subcircuit (302), wherein: The jth logic subcircuit (U j ) is used to receive a ground signal, the jth second command sub-signal and the jth third command sub-signal, the jth logic sub-circuit (U j ) is used to output the j-th first intermediate signal, where j is an integer greater than or equal to 0 and less than m; The first input end of the control subcircuit (302) is connected to the output ends of the m logic subcircuits (301), the second input end of the control subcircuit (302) is used to receive a power-on signal, and the output end of the control subcircuit (302) is used to output the i-th segment activation signal; The chip select signal indicates that the target chip is selected, and the power-on signal indicates that all power supplies of the target chip have been started.

7. The control circuit (10) according to claim 6, characterized in that: The jth logic subcircuit (U j ) includes the jth latch module (A j ) and the jth gated buffer module (B j ), the jth latch module (A j ) output terminal and the jth gated buffer module (B j ) is connected to the input end of the jth gate buffer module (B j ) is used to receive the jth third command sub-signal; wherein: The jth latch module (A j ), for receiving the ground signal and the j-th second command sub-signal, and controlling the j-th latch module (A) according to the j-th second command sub-signal j ) is latched to generate the jth second intermediate signal; The jth gated buffer module (B j ), for receiving the jth second intermediate signal and the jth third command sub-signal, and controlling the jth gate buffer module (B) according to the jth third command sub-signal j ) is in the on state to generate the jth first intermediate signal.

8. The control circuit (10) according to claim 7, characterized in that: The jth logic subcircuit (U j ), used to determine that the jth second intermediate signal is in the second level state and the jth gated buffer module (B) is in the first level state and the jth third command sub-signal is in the second level state when the jth second command sub-signal is in the first level state and the jth third command sub-signal is in the second level state j ) is in a conducting state so that the j-th first intermediate signal is in a second level state.

9. The control circuit (10) according to any one of claims 7 to 8, characterized in that: The jth logic subcircuit (U j ), used for determining the jth gated buffer module (B) when the jth second command sub-signal is in the second level state and the jth third command sub-signal is in the first level state. j ) is in the off state, so that the jth gated buffer module (B j ) output is in high impedance state.

10. The control circuit (10) according to any one of claims 7 to 9, characterized in that: The control subcircuit (302) comprises a first OR gate (601), a first buffer (602) and the mth gated buffer module (603), wherein: The first input end of the first OR gate (601) is respectively connected to the output ends of the m logic sub-circuits (301) and the output end of the m-th gated buffer module (603); the second input end of the first OR gate (601) is used to receive the power-on signal; the output end of the first OR gate (601) is respectively connected to the input end of the m-th gated buffer module (603) and the input end of the first buffer (602); the control end of the m-th gated buffer module (603) is used to receive the power-on signal; and the output end of the first buffer (602) is used to output the i-th segmented activation signal.

11. The control circuit (10) according to any one of claims 1 to 10, characterized in that: The control circuit (10) further comprises a mode register (104) and an output circuit (105), wherein: The mode register (104) is used to output n initial segment mask signals, wherein the initial segment mask signal is used to indicate whether to perform mask refresh on a certain segment of the m storage banks set by the mode register (104); The output circuit (105) is used to receive the n segment activation signals and the n initial segment mask signals, and perform OR logic processing on the n segment activation signals and the n initial segment mask signals to generate n target segment mask signals; wherein: If the i-th target segment mask signal is in the first level state, then when performing a refresh operation, the refresh operation of the i-th segment corresponding to at least one storage bank in the m storage banks is shielded; If the i-th target segment mask signal is in the second level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to all the storage banks in the m storage banks is not masked.

12. The control circuit (10) according to claim 2, 8, 9 or 11, characterized in that: The first level state is a high level, and the second level state is a low level.

13. The control circuit (10) according to any one of claims 11 to 12, characterized in that: The output circuit (105) comprises n second OR gates, wherein: The pth second OR gate (D p ) is used to receive the p-th segment activation signal, and the p-th second OR gate (D p ) is used to receive the pth initial segment mask signal; the pth second OR gate (D p ) is used to output the p-th target segment mask signal; Here, p is an integer greater than or equal to 0 and less than n.

14. The control circuit (10) according to any one of claims 11 to 12, characterized in that: The output circuit (105) comprises n second OR gates and n second buffers, and the pth second buffer (F p ) and the input terminal of the pth second OR gate (D p ) output terminal connection, where: The pth second OR gate (D p ), used for receiving the p-th segment activation signal and the p-th initial segment mask signal, performing an OR logic operation on the p-th segment activation signal and the p-th initial segment mask signal to obtain a p-th intermediate segment mask signal; The pth second buffer (F p ), used to perform drive enhancement processing on the p-th intermediate segment mask signal to obtain the p-th target segment mask signal; Here, p is an integer greater than 0 and less than or equal to n.

15. A memory (1000), characterized in that: The memory (1000) comprises at least the control circuit (10) according to any one of claims 1 to 14.

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