Linear motor control apparatus

Abstract

This linear motor control apparatus (100) comprises: a plurality of inverters (1) for supplying power to a stator winding (20) of a linear motor (200); a plurality of PWM signal generation units (10) for operating the plurality of inverters (1), respectively; carrier signal generation circuits (4) for generating a carrier signal (Cw) to be used for generating a PWM signal (Pw); and a phase control device (11) comprising a clock circuit (6) and counter circuits (6) for outputting timing signals (Tm) to the plurality of carrier signal generation circuits (4), respectively. When receiving the timing signals (Tm), the carrier signal generation circuits (4) generate carrier signals (Cw) having different phases and supply the carrier signals (Cw) to the plurality of PWM signal generation units (10), respectively, and the plurality of PWM signal generation units (10) use the carrier signals (Cw) to generate PWM signals (Pw) having different phases, and output the PWM signals to the plurality of inverters (1), respectively, for operation thereof.

Description

Linear motor control device

[0001] The present disclosure relates to a linear motor control device.

[0002] In motor control devices equipped with inverters, neutral point potential fluctuations occur during inverter switching operations, causing common-mode noise currents to flow to the reference ground via stray capacitance that inevitably arises between the power cable or motor windings and the reference ground. This noise current can flow to the power grid and cause interference with other electronic devices sharing the same power source, a phenomenon known as conducted interference. Furthermore, noise currents flowing through the power cable can interfere with other circuit functions within the device, particularly communication circuits, through electromagnetic coupling and other factors, potentially causing malfunctions. This phenomenon is sometimes called auto-poisoning. In a motor control device equipped with multiple synchronized inverters, when each inverter is switched in phase, the time waveforms of the common-mode currents generated by each inverter are also in phase. However, when these currents flow into the same reference ground, they reinforce each other. This generates noise currents with high peak values, increasing the risk of conducted interference and auto-poisoning. To solve this problem, a method has been proposed in which the phases of the function control signals that switch each inverter are shifted so that the switching operations of multiple inverters are not performed in the same phase (see, for example, Patent Documents 1 and 2).

[0003] In Patent Document 1, in order to suppress conduction noise, control signals with a phase difference of 180° are output to multiple inverters, and approximately half of the inverters are operated with the same phase control signal and the remaining half with the opposite phase control signal.

[0004] In Patent Document 2, a phase control unit is provided that determines the phases of N carrier signals supplied to multiple inverters that control each of multiple motors so that the sum of N vectors represented by the amount of noise related to each of the N motors is zero, thereby suppressing the peak value of the noise current.

[0005] Japanese Patent No. 4143833 Japanese Patent Application Laid-Open No. 2022-137360

[0006] However, applying the conventional method to a linear motor control device having multiple stator windings and corresponding inverters for each winding poses the following problems: First, in the method of Patent Document 1, in a motor control device having many inverters, about half of the inverters are in the same phase, so the problem remains unresolved.

[0007] In Patent Document 2, the phase control unit performs calculations so that the sum of N vectors represented by the amounts of noise relating to the N motors becomes zero, and therefore the calculation load increases as the number of motors increases.

[0008] The present disclosure discloses a technology for solving the above-mentioned problems, and aims to enable noise suppression in a linear motor control device having a large number of stator windings and a plurality of corresponding inverters by using a simple phase control device to operate the plurality of inverters at different phases.

[0009] The linear motor control device disclosed herein is a linear motor control device that controls a linear motor having N (N is a natural number of 2 or more) stator windings, and includes: N inverters that supply power to the N corresponding stator windings; N PWM signal generation units that generate PWM signals to operate the inverters and supply the generated PWM signals to each of the N corresponding inverters; n (n is a natural number of 2 or more and N or less) carrier signal generation circuits that generate carrier signals used to generate the PWM signals; and a phase control unit that controls the phase of the carrier signals, wherein the phase control unit includes: a clock circuit that outputs a synchronization signal, and n counter circuits that receive the synchronization signal and output timing signals to the n corresponding carrier signal generation circuits at at least two or more predetermined times that differ from the time of reception, wherein the n carrier signal generation circuits output the carrier signal of a predetermined period when they receive a timing signal from the corresponding counter circuit, and each of the PWM signal generation units is supplied with the carrier signal from one of the n carrier signal generation circuits.

[0010] According to the present disclosure, it is possible to control multiple inverters to operate at different phases, and the generated noise currents also have different phases, making it possible to suppress an increase in noise current due to noise currents overlapping in the same phase.

[0011] 1 is a block diagram showing the configuration of a linear motor system including a linear motor control device according to embodiment 1. FIG. 2 is a block diagram showing the configuration of a linear motor control device according to embodiment 1. FIG. 3 is a diagram explaining carrier signals of different phases. FIG. 4 is a diagram explaining the relationship between a carrier signal generation circuit and a PWM signal generation unit in a linear motor control device according to embodiment 3. FIG. 5 is a diagram explaining carrier signals of opposite phases in a linear motor control device according to embodiment 4. FIG. 6 is a conceptual diagram showing the phase relationship between in-phase PWM signals and noise generated from an inverter, which is a comparative example, in which (a) shows the waveforms of PWM signals 1 and 2, (b) shows the noise current waveform generated from an inverter operated by PWM signals 1 and 2, and (c) shows the combined noise current. FIG. 7 is a conceptual diagram showing the phase relationship between out-of-phase PWM signals and noise generated from an inverter in a linear motor control device according to embodiment 4, in which (a) shows the waveforms of PWM signals 1 and 2, (b) shows the noise current waveform generated from an inverter operated by PWM signals 1 and 2, and (c) shows the combined noise current. 1 is a diagram illustrating a state in which a generated noise current flows to a reference ground. 2 is a diagram illustrating an example of a hardware configuration of an inverter control device of a linear motor control device according to first to fourth embodiments.

[0012] Hereinafter, an embodiment of a linear motor control device will be described with reference to the drawings. In each drawing, the same reference numerals indicate the same or corresponding parts. Therefore, detailed descriptions thereof may be omitted to avoid duplication.

[0013] Embodiment 1. A linear motor control device according to embodiment 1 will be described below with reference to the drawings. Fig. 1 is a block diagram showing the general configuration of a linear motor system equipped with a linear motor control device according to embodiment 1, and Fig. 2 is a functional block diagram showing the configuration of the linear motor control device. In Fig. 1, the linear motor system includes a linear motor 200 and a linear motor control device 100 for driving the linear motor 200.

[0014] <Configuration of Linear Motor 200> First, the configuration of the linear motor 200 will be described. The linear motor 200 generates magnetic force by passing current through the stator windings 20, and the mover 22 equipped with a permanent magnet is driven along a guide rail 23. Therefore, no power cable is required for the mover 22. The multiple stator windings 20 are housed in a housing 24. Power is supplied to each stator winding 20 from the linear motor control device 100 via a power cable 21. The number of stator windings 20 is N, which is the same as the number of inverters 1, which will be described later.

[0015] 1 and 2 , the linear motor control device 100 includes a plurality of N inverters 1 (N is a natural number of 2 or more) that each supply power to a stator winding 20 of a linear motor 200 via a power cable 21, a PWM (Pulse Width Modulation) signal generation unit 10 that generates a PWM signal Pw and transmits it to the inverters 1, a carrier signal generation unit 12 that generates a carrier signal Cw and transmits it to the PWM signal generation unit 10, and a phase control unit 11 that generates a timing signal Tm and transmits it to the carrier signal generation unit 12. The PWM signal generation unit 10, the carrier signal generation unit 12, and the phase control unit 11 constitute an inverter control device 101.

[0016] <Configuration of Inverter 1> Each of the N inverters 1_1, 1_2, ..., 1_N (collectively referred to as inverter 1) is a single-phase inverter circuit including a circuit for power conversion, such as a semiconductor switching element, among the components required to realize the inverter function. Each of the N inverters 1 receives power from a common power supply circuit, but the power supply circuit, rectifier circuit, power cable, and the like are not shown. Examples of the semiconductor switching element include elements such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and an IGBT (Insulated-Gate-Bipolar-Transistor). These semiconductor switching elements may be formed of a semiconductor made of silicon (Si), or may be a wide-bandgap semiconductor formed of a semiconductor material with a wider bandgap than silicon (Si), such as silicon carbide (SiC) or gallium nitride (GaN). Each of the inverters 1_1, 1_2, . . . , 1_N corresponds to a respective stator winding 20 of the linear motor 200, and is electrically connected via a power cable 21.

[0017] 1 and 2 , the number of PWM signal generators 10_1, 10_2, ..., 10_N (collectively referred to as PWM signal generators 10) is N, the same as the number of inverters 1. Each PWM signal generator 10_1, 10_2, ..., 10_N corresponding to each inverter 1_1, 1_2, ..., 1_N transmits a PWM signal Pw. Each PWM signal generator 10 includes a command signal generator 3 and a comparator 2. Taking PWM signal generator 10_1 as an example, command signal generator 3_1 generates a command signal Sc based on a signal from control unit 7 and transmits it to comparator 2_1. Comparator 2_1 compares carrier signal Cw generated by carrier signal generator circuit 4_1 with command signal Sc to generate PWM signal Pw. Carrier signal Cw is, for example, a triangular wave having a preset period T.

[0018] Here, the control unit 7 determines the value of the current to be passed through each stator winding 20 based on a command from the higher-level device 110. A command signal Sc is generated in the command signal generation unit 3 based on the calculation results in the control unit 7 inside the linear motor control device 100. This command signal Sc is a voltage command signal for setting the switching operation of the inverter 1 corresponding to the stator winding 20. Note that the control unit 7 does not necessarily have to be provided inside the linear motor control device 100.

[0019] 2 , the carrier signal generating unit 12 includes n carrier signal generating circuits 4_1, 4_2, ..., 4_n (collectively referred to as carrier signal generating circuits 4). Here, n is a natural number satisfying 2≦n≦N. The phase of each carrier signal Cw generated by the carrier signal generating circuit 4 is determined by a timing signal Tm transmitted from the phase controlling unit 11.

[0020] The phase control unit 11 includes a plurality of n counter circuits 5_1, 5_2, ... 5_n (collectively referred to as counter circuits 5) and a clock circuit 6. Here, the number of carrier signal generation circuits 4 and the number of counter circuits 5 are the same. When n = 1, there is only one counter circuit 5, and carrier signals Cw of different phases cannot be generated, so 1 is excluded as a value of n. Therefore, n is 2 or greater. Furthermore, when n is greater than the number of inverters N, there will be a surplus of carrier signal generation circuits, so such a case is also excluded. Therefore, candidates for the natural number n are limited to a range between 2 and N.

[0021] Each counter circuit 5_1, 5_2, ..., 5_n is a digital circuit that outputs a timing signal Tm after a predetermined time t1, t2, ..., tn has elapsed since time t0 when the counter circuit 6 receives the synchronization signal CLK. The synchronization signal CLK is an electrical signal that determines the start timing of the counter circuit 5 and synchronizes the operation of the counter circuit 5. While the specific format of the synchronization signal CLK is not important, it is generally a repetitive electrical signal with an arbitrary frequency. The synchronization signal CLK is common to all counter circuits 5. The timing signal Tm can be any format as long as it is an electrical signal, for example, it may output a digital signal fixed at 1 (high) or 0 (low) for a fixed period of time. The specific configuration of the clock circuit 6 is also not important, but it is typically composed of a quartz oscillator and peripheral circuits. The clock circuit 6 does not need to be dedicated to the phase control unit 11; a clock circuit used in other circuits may also be used. The carrier signal generating circuit 4 and counter circuit 5 shown here may be configured with discrete components, but may also be implemented in a programmable logic device such as an FPGA (Field Programmable Gate Array).

[0022] The count circuits 5_1, 5_2, ..., 5_n are connected one-to-one to the corresponding carrier signal generation circuits 4_1, 4_2, ..., 4_n, respectively, and supply a timing signal Tm. Upon receiving the timing signal Tm from the count circuits 5_1, 5_2, ..., 5_n, the carrier signal generation circuits 4_1, 4_2, ..., 4_n start outputting a carrier signal Cw with a period T. In other words, the count circuits 5_1, 5_2, ..., 5_n have the function of determining the relative phases of the n different carrier signals Cw.

[0023] 3 is a diagram showing carrier signals with different phases. Carrier signals generated at two arbitrarily selected times tk and tl after receiving synchronization signal CLK from clock circuit 6 are designated as carrier signals Cw_k and Cw_l, respectively. By determining times t1, t2, ... tn so that the value of tk-tl is not an integer multiple (including negative numbers) of the carrier signal period T, it is possible to generate carrier signals Cw with up to n different phases. In the following explanation, "different phases" has the meaning described above.

[0024] Here, when the value of tk-tl is an integer multiple of the period T of the carrier signal, although time tk and time tl are different times, the phase difference between the two generated carrier signals Cw_k and Cw_l is an integer multiple of 360°, and there is no substantial phase difference. In other words, the phase difference α is expressed as an angle greater than or equal to 0° and less than 360° (0°≦α<360°), and the relationship with the period T of the carrier signal Cw can be clearly expressed as tk-tl=T×α / 360×m (m is an integer excluding 0).

[0025] Furthermore, it is possible for any of the preset times t1, t2, ... tn after receiving the synchronization signal CLK from the clock circuit 6 to have the same value, but since the carrier signals Cw are supplied at that time in duplicated numbers, the number of carrier signals Cw with different phases is reduced. Therefore, the times t1, t2, ... tn are different by at least two or more times.

[0026] When the N inverters 1_1, 1_2, ..., 1_N of the linear motor control device 100 are all operated at different phases, the number n of counter circuits 5 and carrier signal generation circuits 4 is set to the same number N of inverters 1, and the above-mentioned times t1, t2, ..., tn are all set to be different. A timing signal Tm set in this way is transmitted from counter circuit 5_k, and PWM signal generation unit 10_k outputs a PWM signal Pw to inverter 1_k based on a carrier signal Cw supplied by carrier signal generation circuit 4_k that has received this timing signal Tm. Because the N inverters 1_1, 1_2, ..., 1_N of the linear motor control device 100 can all be operated at different phases, the problem of noise currents generating at different times and therefore having large peak values ​​can be avoided.

[0027] As described above, according to the first embodiment, the linear motor control device is a linear motor control device that controls a linear motor having N (N is a natural number of 2 or more) stator windings, and is equipped with N inverters that supply power to the corresponding N stator windings, N PWM signal generation units that generate PWM signals to operate the inverters and supply the signals to each of the corresponding N inverters, n (n is a natural number of 2 or more and N or less) carrier signal generation circuits that generate carrier signals used to generate the PWM signals, and a phase control unit that controls the phase of the carrier signals. The phase control unit includes a clock circuit that outputs a synchronization signal, and n counter circuits that receive the synchronization signal output from the clock circuit and output timing signals to the n corresponding carrier signal generation circuits at times that are at least two or more predetermined times different from the time of reception, and each of the n carrier signal generation circuits outputs a carrier signal of a predetermined period when it receives a timing signal from its corresponding counter circuit, and each of the PWM signal generation units is supplied with a carrier signal from one of the n carrier signal generation circuits, so that multiple inverters can operate using PWM signals generated based on carrier signals of different phases, and the problem of noise currents occurring at the same time increasing in peak value can be avoided.

[0028] In this case, the times at which the counter circuits output timing signals are set so that the difference between any two times is not an integer multiple of the period of the carrier signal, making it possible to operate the inverters with PWM signals generated based on carrier signals of different phases.Furthermore, when n counter circuits all output timing signals Tm at different times, and n=N, all inverters operate with PWM signals generated based on carrier signals of different phases, which contributes most to noise suppression.

[0029] The number of counter circuits and carrier signal generation circuits can be reduced by setting the number n of counter circuits and carrier signal generation circuits to 2≦n<N and making it less than the number N of inverters and PWM signal generation units. In this case, too, by generating multiple carrier signals with different phases, it is possible to prevent the timing of noise current generation from overlapping, and to avoid the problem of noise current generation timings overlapping and resulting in an increase in peak value.

[0030] Second Embodiment A linear motor control device according to a second embodiment will be described below with reference to the drawings. In the first embodiment, an example was described in which the number n of counter circuits 5 and carrier signal generation circuits 4 is the same as the number N of inverters 1, and the N inverters 1_1, 1_2, ... 1_N of the linear motor control device 100 all operate at different phases. In the second embodiment, an example will be described in which the number n of counter circuits 5 and carrier signal generation circuits 4 is smaller than the number N of inverters 1. The configuration and operation of the linear motor control device 100 are the same as those of the first embodiment.

[0031] When the number n of counter circuits 5 and carrier signal generation circuits 4 is smaller than the number N of inverters 1, carrier signal generation circuits 4_1, 4_2, ... 4_n supply carrier signals Cw of the same phase as at least the difference (N-n) to the PWM signal generation unit 10. Note that multiple carrier signals Cw are never supplied to one PWM signal generation unit 10. This is also the case in the first embodiment.

[0032] Here, when N-n = 1, if the carrier signal Cw generated by the carrier signal generation circuit 4_1 is transmitted to the PWM signal generation units 10_1 and 10_2, inverters 1_1 and 1_2 will operate in phase if the command signals are the same. The larger the difference between N-n, the greater the number of inverters operating in phase. A large number of inverters operating in phase results in superimposed noise currents, increasing their peak value. However, even if the difference between N-n is large, by distributing the destinations of the same carrier signal as evenly as possible to prevent multiple inverters 1 from operating in phase, it is possible to minimize the increase in peak value due to the superimposition of noise currents. For example, if there are 12 inverters and four counter circuits and four carrier signal generation circuits, the number of inverters operating in phase can be reduced to 12 / 4 = 3. Even if it is not possible to operate all inverters in different phases, the number of inverters operating in phase can be sufficiently reduced, which is expected to reduce the peak value of the noise current.

[0033] On the other hand, in a linear motor system, there are a large number of stator windings 20, and therefore the linear motor control device 100 is equipped with a large number of inverters 1 to operate them. Compared to other motor control devices, such as control devices for multi-axis motors, the number of inverters included in a single device is significantly larger. Therefore, providing the same number of counter circuits 5 and carrier signal generation circuits 4 as the inverters 1 increases the number of components and complicates the wiring on the electronic circuit board, resulting in disadvantages in terms of design and manufacturing costs. Furthermore, when implementing the counter circuits 5 and carrier signal generation circuits 4 in an FPGA, there are limitations on the capacity of the FPGA, so it may not be possible to implement many counter circuits 5 and carrier signal generation circuits 4 even if desired.

[0034] That is, there is a trade-off between simplifying the design and suppressing the effects of noise currents by making the number n of counter circuits 5 and carrier signal generation circuits 4 closer to the number N of inverters 1. Therefore, by making the number n of counter circuits 5 and carrier signal generation circuits 4 smaller than the number N of inverters 1, it is possible to simplify the design and reduce costs, while operating the inverters 1_1, 1_2, ..., 1_N with the greatest possible number of different phases, which also makes it possible to obtain the effect of suppressing an increase in peak value due to the superposition of noise currents.

[0035] As described above, according to the second embodiment, by making the number n of counter circuits 5 and carrier signal generating circuits 4 smaller than the number N of inverters 1, it is possible to simplify the design and reduce costs while also achieving the effect of suppressing an increase in peak value due to the superposition of noise currents.

[0036] Third Embodiment A linear motor control device according to a third embodiment will be described below with reference to the drawings. In this third embodiment, as in the second embodiment, the number n of counter circuits 5 and carrier signal generation circuits 4 is set smaller than the number N of inverters 1, and the same carrier signal Cw is supplied from each carrier signal generation circuit 4 to at least two or more PWM signal generation units 10. The configuration and operation of the linear motor control device 100 are the same as those of the first embodiment.

[0037] 4 is a diagram for explaining the relationship between the carrier signal generation circuit 4 and the PWM signal generation unit 10 in the linear motor control device 100 according to embodiment 3. Although the comparator 2 in the PWM signal generation unit 10 is omitted in FIG. 4, the carrier signal Cw from the carrier signal generation circuit 4 is input to the comparator 2 in the PWM signal generation unit 10.

[0038] 4, the carrier signal Cw of the carrier signal generation circuit 4_1 is supplied to two PWM signal generation units 10_1 and 10_2, the carrier signal Cw of the carrier signal generation circuit 4_2 is supplied to two PWM signal generation units 10_3, 10_4, and 10_5, and the carrier signal Cw of the carrier signal generation circuit 4_n is supplied to two PWM signal generation units 10_N-1 and 10_N. In this way, if each carrier signal generation circuit 4 supplies the carrier signal Cw to two PWM signal generation units 10, n=N / 2, and the number of counter circuits 5 and carrier signal generation circuits 4 can be reduced to half the number of inverters 1. In the example shown in FIG. 4, adjacent inverters (e.g., 1_1 and 1_2) operate in phase, but this connection is not necessary. Carrier signal generation circuit 4_1 may be connected to PWM signal generation units 10_1 and 10_3 so that inverters located at distant positions (e.g., 1_1 and 1_3) operate in phase.

[0039] 4, each carrier signal generating circuit 4 supplies the carrier signal Cw to two PWM signal generating units 10, but this is not limitative and each carrier signal generating circuit 4 may supply the carrier signal Cw to three or more PWM signal generating units 10. However, in either case, carrier signals Cw are not supplied from multiple carrier signal generating circuits 4 to one PWM signal generating unit 10.

[0040] Regardless of the number n of carrier signal generation circuits 4, the number of inverters 1 operating in the same phase can be reduced as long as the phases of the carrier signals Cw generated by the n carrier signal generation circuits 4 are all different as described in embodiment 1. In the example of FIG. 4, the number of inverters 1 operating in the same phase is reduced to two.

[0041] As described above, according to the third embodiment, each carrier signal generating circuit supplies the same carrier signal Cw to at least two or more PWM signal generating units, thereby reducing the number of counter circuits and carrier signal generating circuits and simplifying and reducing the cost of the phase control unit 11. Furthermore, because the phase control unit generates carrier signals of different phases, it is possible to control the switching operations of multiple inverters 1 so that they do not overlap, and it is also possible to shift the timing of noise generation. This makes it possible to suppress an increase in the peak value of the noise current.

[0042] Fourth Embodiment A linear motor control device according to a fourth embodiment will be described below with reference to the drawings. In this fourth embodiment, an example will be described in which the number n of carrier signal generation circuits 4 and counter circuits 5 is an even number. The configuration and operation of the linear motor control device 100 are the same as those in the first embodiment.

[0043] By setting the number n of carrier signal generation circuits 4 and counter circuits 5 to an even number, it is possible to create pairs of carrier signals Cw that are opposite in phase to a given carrier signal Cw. FIG. 5 is a diagram illustrating carrier signals that are opposite in phase to each other. Here, "opposite phase" refers to when the times at which any two counter circuits 5_k and 5_l output timing signals Tm are times tk and tl, respectively, and the value of tk-tl is a half-integer multiple of the period T of the carrier signal Cw. In other words, this occurs when tk-tl = T / 2×m (m is an integer other than 0). The phase difference α, expressed as an angle, is 180° or an odd multiple thereof. As long as the number n of carrier signal generation circuits 4 and counter circuits 5 is an even number, it is possible to create pairs of carrier signals Cw that are opposite in phase to each other. Figure 5 shows an example in which the phase difference between carrier signal Cw_k generated upon receiving time tk at which timing signal Tm is output and carrier signal Cw_l generated upon receiving time tl at which timing signal Tm is output is 180°.

[0044] Here, when n = 2, it is obvious that the phase angle values ​​of the two carrier signals Cw can be selected as 0° and 180°, and they are opposite phases to each other. When n = 4, the phase angle values ​​of the four carrier signals Cw can be selected as 0°, 90°, 180°, and 270°, and pairs of 0° and 180° and 90° and 270° are opposite phases. When n = 6, the phase angle values ​​of the six carrier signals Cw can be selected as 0°, 60°, 120°, 180°, 240°, and 300°, and pairs of 0° and 180°, 60° and 240°, and 120° and 300° are opposite phases, respectively. Of course, the phases selected for a given number n can be freely determined. For example, when n = 4, unlike the above example, pairs with a phase difference of 180° can be selected, such as 0°, 180°, 100°, and 280°.

[0045] Next, the effect of creating a pair of carrier signals Cw with a phase difference of 180° will be described. Figures 6 and 7 are conceptual diagrams showing the phase relationship between PWM signals and noise generated from inverters operated by those PWM signals. In the figures, (a) shows the waveforms of PWM signals 1 and 2, (b) shows in-phase noise current waveforms generated from inverters 1_1 and 1_2 operated by PWM signals 1 and 2, and (c) shows the noise current obtained by adding up the noise currents generated from each inverter. As a comparative example, Figure 6 shows (a) PWM signals 1 and 2 generated by two carrier signals Cw with a phase difference of 0, (b) shows in-phase noise current waveforms generated from inverters 1_1 and 1_2 by PWM signals 1 and 2, and (c) shows the added noise current. It can be seen that the noise currents generated from inverters operated by carrier signals with a phase difference of 0 are in-phase, and the added noise current increases as if the waveforms were superimposed.

[0046] 7 relates to the fourth embodiment, and (a) in the figure shows the pair of opposite-phase carrier signals Cw to generate PWM signals 1 and 2 of opposite phases. As can be seen from (b) in the figure, the noise currents generated from inverters 1_1 and 1_2 by the opposite-phase PWM signals 1 and 2 are also of opposite phase, and therefore the waveforms of the combined noise currents are superimposed as shown in (c), and cancel each other out.

[0047] Fig. 8 is a schematic diagram showing how noise currents flow in a circuit and explains how the generated noise currents flow to a reference ground. In Fig. 8, a system power supply 32 is provided upstream of inverter 1. A stator winding 20_1 of linear motor 200, which receives power from inverter 1_1, and a stator winding 20_2, which receives power from inverter 1_2, inevitably have stray capacitance 30 between themselves and reference ground 31. As shown in Fig. 7, when inverters 1_1 and 1_2 are operated by PWM signals of opposite phases, noise currents generated by inverters 1_1 and 1_2 flow from stator windings 20_1 and 20_2 to reference ground 31 via stray capacitance 30, but the noise currents are out of phase and flow in opposite directions. Therefore, as shown in Fig. 7(c), the noise currents flowing to reference ground 31 cancel each other out.

[0048] As described above, the fourth embodiment achieves the same effects as the first to third embodiments. Furthermore, by setting the number n of carrier signal generation circuits and counter circuits to an even number, it is possible to create a pair of carrier signals Cw with a phase difference of 180°. This makes the phases of the noise currents generated by the inverters opposite to each other, making it possible to suppress the noise currents flowing to the reference ground. This further reduces the risk of conducted interference.

[0049] An example of the configuration of the inverter control device 101 according to the first to fourth embodiments is shown in Fig. 9. As shown in Fig. 9, the inverter control device 101 includes, for example, a processor 1000 and a storage device 1100 as processing circuits. The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), an FPGA, various logic circuits, various signal processing circuits, etc. Furthermore, a plurality of processors 1000 of the same type or different types may be provided, and each process may be shared and executed by the processors 1000. The storage device 1100 includes a RAM (Random Access Memory) configured to be able to read and write data from the processor 1000, and a ROM (Read Only Memory) configured to be able to read data from the processor 1000. The processor 1000 executes a program input from the storage device 1100 such as a ROM.

[0050] Although an example has been shown above in which the carrier signal generating circuit 4 and counter circuit 5 of the inverter control device 101 are mounted on an FPGA, these may be configured separately or may be integrated into a hardware configuration as the inverter control device 101.

[0051] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0052] 1: Inverter, 2: Comparator, 3: Command signal generation unit, 4: Carrier signal generation circuit, 5: Counter circuit, 6: Clock circuit, 7: Control unit, 10: PWM signal generation unit, 11: Phase control unit, 12: Carrier signal generation unit, 20: Stator winding, 21: Power cable, 22: Mover, 23: Guide rail, 24: Housing, 30: Stray capacitance, 31: Reference ground, 32: System power supply, 100: Linear motor control device, 101: Inverter control device, 110: Upper device, 200: Linear motor, 1000: Processor, 1100: Storage device, Pw: PWM signal, Sc: Command signal, Cw: Carrier signal, Tm: Timing signal, CLK: Synchronization signal.

Claims

1. A linear motor control device for controlling a linear motor having N stator windings (N is a natural number of 2 or more), comprising: N inverters for supplying power to the N corresponding stator windings; N PWM signal generation units for generating PWM signals to operate the inverters and supplying the generated PWM signals to each of the N corresponding inverters; n carrier signal generation circuits (n is a natural number between 2 and N) for generating carrier signals used in generating the PWM signals; and a phase control unit for controlling the phase of the carrier signal, wherein the phase control unit comprises: a clock circuit for outputting a synchronization signal; and n counter circuits for receiving the synchronization signal output from the clock circuit and outputting timing signals to the n corresponding carrier signal generation circuits at at least two or more preset times different from the time of reception, wherein the n carrier signal generation circuits output the carrier signal of a preset period when they receive a timing signal from their corresponding counter circuit, and each of the PWM signal generation units is supplied with the carrier signal from one of the n carrier signal generation circuits.

2. The linear motor control device according to claim 1, wherein each of said n carrier signal generating circuits supplies said carrier signal to at least two or more of said PWM signal generating sections.

3. The linear motor control device according to claim 1 or 2, wherein n, the number of said carrier signal generating circuits and said counter circuits, is an even number.

4. A linear motor control device as claimed in any one of claims 1 to 3, wherein the time at which the counter circuit outputs a timing signal is set so that the difference between any two of the times is not an integer multiple of the period of the carrier signal.

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