Phase-locked loop, imaging device, and electronic circuit

Abstract

The invention enables reduction of jitter while suppressing circuit-scale augmentation of a phase-locked loop.　This phase-locked loop is provided with: a sample-and-hold circuit that sub-samples an input signal on the basis of a reference signal; a voltage-to-time converter that converts the voltage of the input signal that has been sub-sampled in the sample-and-hold circuit into a time difference; and a time-to-digital converter that detects the time difference that has been converted in the voltage-to-time converter. The sample-and-hold circuit, the voltage-to-time converter, and the time-to-digital converter may constitute a time-domain ADC. A digital control oscillator for generating input signals may be further provided.

Description

Phase-locked loop circuit, imaging device and electronic circuit

[0001] The present technology relates to a phase locked loop circuit, an imaging device, and an electronic circuit. More specifically, the present technology relates to a phase locked loop circuit, an imaging device, and an electronic circuit that use an ADPLL (All Digital PLL).

[0002] In an ADPLL, a time-to-digital converter (TDC) detects the phase difference (time difference) between a reference clock and an output signal of a digitally controlled oscillator (DCO) in the time domain. For example, a digital PLL circuit has been proposed that includes a sample-and-hold circuit that samples the phase difference between the output signal of the DCO and the reference signal as a voltage (see, for example, Patent Document 1).

[0003] JP 2016-140021 A

[0004] However, in the above-mentioned conventional technology, subsampling is performed using an analog-to-digital converter (ADC) to reduce jitter, which may result in an increase in circuit size and power consumption.

[0005] The present technology was developed in light of these circumstances, and aims to reduce jitter while suppressing an increase in the circuit scale of a phase locked loop.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a phase-locked loop circuit including a sample-and-hold circuit that subsamples an input signal based on a reference signal, a voltage-to-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference, and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter, thereby providing an effect that the time resolution of the input signal is set based on the voltage resolution of the input signal.

[0007] In the first aspect, the sample-and-hold circuit, the voltage-to-time converter, and the time-to-digital converter may form a time-domain ADC (Analog to Digital Converter), thereby providing an effect that the time resolution of the input signal is set based on AD.

[0008] In the first aspect, the time resolution of the time domain ADC may be higher than the time resolution of the time-to-digital converter, thereby reducing jitter caused by limitations on the time resolution of the time-to-digital converter.

[0009] In addition, in the first aspect, the power supply may further include a digitally controlled oscillator that generates the input signal, thereby providing an effect that the frequency of the input signal is adjusted based on control of a digital code input to a digitally controlled oscillator voltage.

[0010] In the first aspect, the digitally controlled oscillator may further include an accumulator that sets a count-up value for each period of the reference signal based on a frequency command word (FCW), a counter that counts up for each period of the input signal, a calculator that subtracts an output of the counter and an output of the time-to-digital converter from an output of the accumulator, and a loop filter that band-limits an input to the digitally controlled oscillator, thereby providing an effect of configuring a phase-locked loop using a time-domain ADC.

[0011] In addition, in the first aspect, the digital signal processing device may further include a frequency divider that divides the frequency of the input signal generated by the digitally controlled oscillator, thereby providing an effect that the frequency-divided input signal is input to the time-domain ADC.

[0012] In addition, in the first aspect, a digital time converter that delays the reference signal may be further provided, thereby providing an effect of adjusting a fractional phase shift in a fractional PLL (Phase Locked Loop).

[0013] In the first aspect, the time-to-digital converter may further include a selector that switches between input of the time difference converted by the voltage-to-time converter and input of the reference signal and the input signal, thereby achieving both an expansion of the lock range of the phase-locked loop and an improvement of the time resolution.

[0014] In addition, in the first aspect, the selector may input the time difference converted by the voltage-to-time converter to the time-digital converter when the sub-sampling mode is specified, and input the reference signal and the input signal to the time-digital converter when the normal mode is specified, thereby providing an effect of switching between the sub-sampling mode and the normal mode.

[0015] In addition, in the first aspect, the normal mode may be operated intermittently during operation in the sub-sampling mode, thereby providing an effect of improving time resolution while stabilizing phase synchronization.

[0016] In the first aspect, the phase-locked loop may be calibrated, thereby improving the stability of phase locking.

[0017] A second aspect is an imaging device including an imaging unit having a plurality of pixels and a phase-locked loop circuit that generates a clock signal that sets the operation timing of the imaging unit, the phase-locked loop circuit including a sample-and-hold circuit that subsamples the clock signal based on a reference clock, a voltage-to-time converter that converts the voltage of the clock signal subsampled by the sample-and-hold circuit into a time difference, and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter, thereby providing an effect that the time resolution of the clock signal used in the imaging device is set based on the voltage resolution of the clock signal.

[0018] A third aspect is an electronic circuit including a circuit unit that operates based on a clock signal and a phase-locked loop circuit that generates a clock signal that sets the operation timing of the circuit unit, the phase-locked loop including a sample-and-hold circuit that subsamples the clock signal based on a reference clock, a voltage-to-time converter that converts the voltage of the clock signal subsampled by the sample-and-hold circuit into a time difference, and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter, thereby providing the effect that the time resolution of the clock signal used in the electronic circuit is set based on the voltage resolution of the clock signal.

[0019] 10 is a block diagram showing an example of the configuration of a phase locked loop circuit according to a first embodiment. FIG. 11 is a timing chart showing waveforms of each part of the phase locked loop circuit according to the first embodiment. FIG. 12 is a timing chart showing the relationship between a clock signal and a reference clock of the phase locked loop circuit according to the first embodiment. FIG. 13 is a diagram showing a first example of the relationship between the offset frequency and phase noise of the phase locked loop circuit according to the first embodiment. FIG. 14 is a diagram showing a second example of the relationship between the offset frequency and phase noise of the phase locked loop circuit according to the first embodiment. FIG. 15 is a diagram showing an example of the configuration of a time-to-digital converter according to the first embodiment. FIG. 16 is a diagram showing an example of the configuration of a digital-to-time converter according to the first embodiment. FIG. 17 is a diagram showing an example of the configuration of a digital-to-time converter according to the first embodiment. FIG. 18 is a flowchart showing the operation of the phase locked loop circuit according to the first embodiment. FIG. 19 is a flowchart showing the operation of the phase locked loop circuit according to the second embodiment. FIG. 19 is a block diagram showing an example of the configuration of a phase locked loop circuit according to a third embodiment. FIG. 19 is a flowchart showing the operation of the phase locked loop circuit according to the third embodiment. FIG. 19 is a block diagram showing an example of the configuration of a phase locked loop circuit according to a fourth embodiment. FIG. 19 is a block diagram showing an example of the configuration of a phase locked loop circuit according to a fifth embodiment. FIG. 19 is a block diagram showing an example of the configuration of an imaging device to which a phase locked loop circuit according to a sixth embodiment is applied. FIG. 19 is a block diagram showing an example of the configuration of a solid-state imaging device according to the sixth embodiment. FIG. 19 is a perspective view showing an example of a stack of pixel array units according to a seventh embodiment. FIG. 19 is a block diagram showing a schematic example of the configuration of a vehicle control system. FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0020] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which the voltage of a clock signal subsampled by a sample-and-hold circuit is converted into a time difference by a voltage-to-time converter, and the time difference is detected by a time-to-digital converter) 2. Second embodiment (an example in which a phase-locked loop is calibrated after a mode is set) 3. Third embodiment (an example in which operation is performed only in subsampling mode) 4. Fourth embodiment (an example in which a reference clock is input to a selector without using a digital-to-time converter) 5. Fifth embodiment (an example in which a clock signal output from a digitally controlled oscillator is divided) 6. Sixth embodiment (an example in which a phase-locked circuit is applied to an imaging device) 7. Seventh embodiment (an example in which pixel array units are stacked) 8. Example of application to a moving body

[0021] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of a phase locked loop circuit according to a first embodiment.

[0022] In the figure, an ADPLL 200 is provided as a phase-locked loop. The ADPLL 200 forms a feedback loop based on phase synchronization and outputs a clock signal CLK. The frequency of the clock signal CLK can be determined based on a frequency command word (FCW). The FCW can specify the ratio of the frequency of the clock signal CLK to the frequency of the reference clock RCK. The FCW can include an integer (int) and a decimal (frc). The FCW can be provided from outside the ADPLL 200. The ADPLL 200 includes an accumulator 201, a calculator 202, a loop filter 203, a digitally controlled oscillator 204, a counter 206, a time-domain ADC 207, a digital-to-time converter 208, and a control unit 209.

[0023] The digitally controlled oscillator 204 generates a clock signal CLK based on its oscillation operation. The digitally controlled oscillator 204 can change its oscillation frequency based on an oscillator tuning word. The digitally controlled oscillator 204 may be a ring oscillator or an LC oscillator.

[0024] The counter 206 counts up for each clock of the clock signal CLK and outputs the count value to the arithmetic unit 202. At this time, the counter 206 can detect the phase in units of one cycle of the clock signal CLK.

[0025] The accumulator 201 sets a count-up value for each cycle of the reference clock RCK based on the FCW and outputs the value to the calculator 202. At this time, the FCW is input to the accumulator 201. The accumulator 201 can then output the integer int specified by the FCW to the calculator 202 and output the decimal frc specified by the FCW to a digital-to-time converter (DTC) 208.

[0026] The calculator 202 subtracts the output of the counter 206 and the output of the time-to-digital converter 214 from the output of the accumulator 201, and outputs the result to the loop filter 203. The output of the calculator 202 can indicate the phase error between the reference clock RCK and the clock signal CLK. At this time, the ADPLL 200 can operate the phase-locked loop so that the phase error approaches zero.

[0027] The loop filter 203 band-limits the input to the digitally controlled oscillator 204 to reduce the effect of quantization error. The gain of the loop filter 203 can be adjusted based on the calibration of the ADPLL 200.

[0028] The digital-to-time converter 208 delays the reference clock RCK and outputs it to the sample-and-hold circuit 211 and the selector 213. In a fractional PLL, a phase shift occurs by a decimal point each time the clock signal CLK is subsampled based on the reference clock RCK. Because the value of this phase shift is known, the digital-to-time converter 208 can set a delay time to correct this phase shift. By correcting the phase shift in the digital-to-time converter 208, it is not necessary to expand the range of the time-to-digital converter 214 to accommodate this phase shift. Therefore, the time-to-digital converter 214 only needs to cover a relatively narrow range that includes the resolution of the digital-to-time converter 208 and margins to accommodate jitter and other errors in the digitally controlled oscillator 204. Note that an integer PLL does not require the digital-to-time converter 208.

[0029] The time-domain ADC 207 performs AD conversion in the time domain. The time resolution of the time-domain ADC 207 can be higher than the time resolution of the time-to-digital converter 214. The time-domain ADC 207 includes a sample-and-hold circuit 211, a voltage-to-time converter 212, a selector 213, and a time-to-digital converter 214.

[0030] The sample-and-hold circuit 211 sub-samples the clock signal CLK based on the reference clock RCK, and then holds the sub-sampled sample-and-hold value SH and outputs it to a voltage-to-time converter (VTC) 212.

[0031] The voltage-to-time converter 212 converts the voltage of the clock signal CLK subsampled by the sample-and-hold circuit 211 into a time difference. At this time, the voltage-to-time converter 212 can set the time difference between the rising edges of the output voltages VP and VN based on the sample-and-hold value SH held in the sample-and-hold circuit 211.

[0032] The selector 213 switches between inputting the time difference converted by the voltage-time converter 212 and inputting the reference clock RCK and the clock signal CLK to the time-digital converter 214. The selector 213 can switch between the sub-sampling mode and the normal mode based on the mode setting signal MOD. In the sub-sampling mode, the selector 213 inputs the time difference converted by the voltage-time converter 212 to the time-digital converter 214. In the normal mode, the selector 213 inputs the reference clock RCK and the clock signal CLK to the time-digital converter 214.

[0033] In the sub-sampling mode, the time-to-digital converter (TDC) 214 detects the time difference converted by the voltage-to-time converter 212, digitizes it, and outputs it to the calculator 202. In the sub-sampling mode, the time difference detected by the time-to-digital converter 214 is expanded and input. In the normal mode, the time-to-digital converter 214 detects the time difference between the reference clock RCK and the clock signal CLK, digitizes it, and outputs it to the calculator 202. The time-to-digital converter 214 may be a delay line TDC.

[0034] The time difference detected by the time-to-digital converter 214 is magnified based on the gain from the input of the sample-and-hold circuit 211 to the input of the time-to-digital converter 214. The gain from the input of the sample-and-hold circuit 211 to the input of the time-to-digital converter 214 can be given as follows:

[0035] When the clock signal CLK is a sine wave with an amplitude Vck [V] and a frequency fck [Hz], the slope near the zero crossing is 2π fck Vck. Therefore, the voltage gain with respect to the time shift Δtck of the clock signal CLK is 2π fck Vck Δtck. The gain TG of the voltage-to-time converter 212 is a design value, and for example, 200 psec can be realized with an input of 100 mV.

[0036] Assuming that standard values ​​are Vck=1 [V] and fck=2 [GHz], the gain from the time lag Δtck at the input of the sample-and-hold circuit 211 to the time lag Δtvo at the output of the voltage-to-time converter 212 can be given by the following equation.

[0037] Δtvo=2π・fck・Vck・Δtck[V / sec]・TG[sec / V] =2π・2・10 ９ ・Δtck・200p / 100m Δtvo / Δtck=25.1

[0038] That is, by providing sample-and-hold circuit 211 and voltage-to-time converter 212 before time-to-digital converter 214, gain is provided in the time domain, and the time deviation near the zero crossing of clock signal CLK is amplified by 25.1 times before being input to time-to-digital converter 214. When the time resolution is converted into the input, if the TDC time resolution is 20 psec, the input-converted time resolution becomes approximately 0.8 psec, which is an equivalent improvement in time resolution.

[0039] The control unit 209 performs overall control of the ADPLL 200. For example, the control unit 209 can control the operation sequence of the ADPLL 200, supply an enable signal when the ADPLL 200 is started up, switch the mode of the ADPLL 200, and set the coefficient of the loop filter 203.

[0040] FIG. 2 is a timing chart showing waveforms at various parts of the phase locked loop circuit according to the first embodiment.

[0041] In the figure, when the reference clock RCK rises (t1), the sample-and-hold circuit 211 sub-samples the clock signal CLK and holds the sample-and-hold value SH.

[0042] Then, the voltage-time converter 212 raises the output voltage VN (t2) based on the sample-and-hold value SH held in the sample-and-hold circuit 211. Next, the voltage-time converter 212 raises the output voltage VP (t3) after a time difference DT corresponding to the sample-and-hold value SH has elapsed. The time difference DT may be proportional to the sample-and-hold value SH.

[0043] 3 is a timing chart showing the relationship between the clock signal and the reference clock of the phase locked loop circuit according to the first embodiment. Note that "a" in the figure shows an example of operation in normal mode, and "b" in the figure shows an example of operation in sub-sampling mode.

[0044] In the normal mode, the time-to-digital converter 214 detects the time difference between the reference clock RCK and the clock signal CLK, and can obtain a TDC time resolution of, for example, 20 psec.

[0045] In the normal mode, the time difference between the reference clock RCK and the clock signal CLK is directly detected, so that the time difference between the reference clock RCK and the clock signal CLK is not affected by the period of the clock signal CLK, ensuring a wide lock range LR1.

[0046] In the sub-sampling mode shown in FIG. 1B, the voltage-to-time converter 212 converts the voltage VD of the clock signal CLK sub-sampled by the sample-and-hold circuit 211 into a time difference. A time resolution of, for example, 0.8 psec can be obtained. For example, assume that the gain TG of the voltage-to-time converter 212 is 200 psec / 100 mV. In this case, the voltage resolution of the voltage-to-time converter 212 is TDC time resolution / TG = 10 mV. If the clock signal CLK is a sine wave, the time resolution of the time-domain ADC 207 can be 10 mV / 2πf [V / sec] = 0.8 psec.

[0047] In subsampling mode, the voltage VD of the clock signal CLK is converted into a time difference. Therefore, in subsampling, the time difference between the reference clock RCK and the clock signal CLK is affected by the period of the clock signal CLK, narrowing the lock range LR2. This lock range LR2 is limited to within ±π / 4 rad.

[0048] Therefore, in order to achieve both an expansion of the lock range of the phase locked loop and an improvement of the time resolution, it is effective to switch between the sub-sampling mode and the normal mode. For example, the normal mode may be operated intermittently during operation in the sub-sampling mode.

[0049] 4 is a diagram showing a first example of the relationship between the offset frequency and phase noise of the phase locked loop according to the first embodiment. This diagram shows the relationship between the offset frequency and phase noise in normal mode. Furthermore, L1 represents the phase noise of the OL-DCO, L2 represents the phase noise of the TDC, L3 represents the phase noise of the DCO, and L4 represents the total phase noise.

[0050] In the figure, when the TDC time resolution is 20 psec, the quantization noise of the time-to-digital converter 214 contributes greatly to the jitter of the ADPLL 200, resulting in a jitter of 1.8 psec.

[0051] 5 is a diagram showing a second example of the relationship between the offset frequency and the phase noise of the phase locked loop circuit according to the first embodiment, in which the relationship between the offset frequency and the phase noise is shown in the sub-sampling mode.

[0052] In the figure, if the TDC time resolution can be increased to 0.8 psec, the quantization noise of the time-to-digital converter 214 will be approximately 10 dB smaller than the other noises and will no longer be the dominant noise. As a result, the jitter of the ADPLL 200 will be reduced to 0.6 psec.

[0053] Because normal mode has a wide lock range LR1 and is robust, various calibrations can be performed in normal mode immediately after startup, and then switched to subsampling mode, allowing for safe startup. Although normal mode has larger jitter than subsampling mode, it is robust and consumes less power, allowing for the selection of an appropriate mode depending on the application. Furthermore, by inserting normal mode between subsampling modes, cycle slips during subsampling operation can be prevented, achieving both an expanded lock range and improved time resolution.

[0054] 6 is a diagram showing an example of the configuration of the time-to-digital converter according to the first embodiment. In this diagram, an example is shown in which the time-to-digital converter 214 is a delay line TDC.

[0055] In the figure, the time-to-digital converter 214 includes delay buffers 311 to 313 and flip-flops 321 to 323. The reference clock RCK is input via a buffer 301, delayed by an integer multiple of the buffer delay τ in the delay buffers 311 to 313, and input to the D terminals of the flip-flops 321 to 323, respectively.

[0056] The clock signal CLK is input to the CK terminal of each of the flip-flops 321 to 323 via the buffer 302. At this time, each of the flip-flops 321 to 323 captures the state of the reference clock RCK of the delay line at the rising edge of the clock signal CLK. This makes it possible to measure the time interval until the rising edge of the clock signal CLK corresponds to the number of buffer delay stages, and convert the time into a digital value. In this configuration, the buffer delay τ on the path of the reference clock RCK is the minimum time resolution.

[0057] 7 is a diagram showing an example of the configuration of a digital time converter according to the first embodiment, where a in the figure shows a first example of the digital time converter 208, b in the figure shows a second example of the digital time converter 208, and c in the figure shows a third example of the digital time converter 208.

[0058] In the figure, a first example of the digital-to-time converter 208 includes inverters 401 and 402, capacitors 411 to 413, and field-effect transistors 421 to 423. The inverters 401 and 402 are connected in series with each other. Each of the capacitors 411 to 413 is connected in series with a corresponding one of the field-effect transistors 421 to 423. The series circuits of each of the capacitors 411 to 413 and each of the field-effect transistors 421 to 423 are connected in parallel between the inverters 401 and 402. The series circuits of each of the capacitors 411 to 413 and each of the field-effect transistors 421 to 423 can be operated as variable capacitances.

[0059] 1B, a second example of the digital-to-time converter 208 includes inverters 431 to 433, capacitors 441 to 443, and a selector 403. Capacitors 441 to 443 are connected in parallel to the outputs of the inverters 431 to 433, respectively. The parallel circuits of the inverters 431 to 433 and the capacitors 441 to 443 can have different delay amounts. The selector 403 can select one of the outputs of the inverters 431 to 433.

[0060] In the figure, reference numeral c denotes a third example of the digital-to-time converter 208. The digital-to-time converter 208 includes wires 451 to 454 and a selector 404. The wires 451 to 454 can have different propagation delays. The selector 404 can select one of the wires 451 to 454.

[0061] FIG. 8 is a diagram illustrating an example of the configuration of the digital-to-time converter according to the first embodiment.

[0062] 1, the digital-to-time converter 208 includes switches 511, 521, 515, and 525, inverters 512 and 522, capacitors 513 and 523, and current sources 514 and 524. Switch 511 is connected in series to inverter 512. Switch 521 is connected in series to inverter 522. Current source 514 is connected in series to switch 515. Current source 524 is connected in series to switch 525. A series circuit of capacitor 513, current source 514, and switch 515 is connected in parallel between switch 511 and inverter 512. A series circuit of capacitor 523, current source 524, and switch 525 is connected in parallel between switch 521 and inverter 522. Each of switches 511 and 521 is turned on / off based on clock CL. Each of switches 515 and 525 is turned on / off based on inverted clock CB. Inverted clock CB is an inverted version of clock CL. At this time, the inputs PIN and NIN are input via switches 511 and 521, respectively, and the outputs POT and NOT are output via inverters 512 and 522, respectively.

[0063] FIG. 9 is a flowchart showing the operation of the phase locked loop according to the first embodiment.

[0064] In the figure, when the power supply of the ADPLL 200 is turned on (S101), the ADPLL 200 is initialized (S102).

[0065] Next, calibration and phase locking of the ADPLL 200 is started (S103). In the calibration, when switching between the normal path and the subsampling path, the gain of the normal path and the gain of the subsampling path are detected and reflected in the loop filter in order to prevent operational malfunctions and maintain low jitter while maintaining a constant loop gain. The following methods can be used to detect each gain.

[0066] In estimating the gain of the digital-to-time converter 208, an error can be detected using the correlation value between the output of the time-to-digital converter 214 and the input to the digital-to-time converter 208, and the delay amount (time) for the input code of the digital-to-time converter 208 can be calculated. In estimating the gain of the digital-to-time converter 208, the method disclosed in the following document may be used: Y.-H. Liu et al., "An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 5, pp. 1094-1105, May 2017, doi: 10.1109 / TCSI.2016.2625462.

[0067] The gain of the normal path can be determined by shifting the DTC input code and comparing the amount of shift with the amount of change in the TDC output code to determine the DTC input code for the TDC1 code. Since the relationship between the DTC input code and time is known, the time corresponding to the TDC1 code can be determined.

[0068] As with the gain of the normal path, the gain of the subsampling path can also be obtained by combining a sample-and-hold circuit 211, a voltage-to-time converter 212, and a time-to-digital converter 214 to determine the time corresponding to the TDC1 code.

[0069] Next, the ADPLL 200 determines whether the sub-sampling mode is specified (S104). If the sub-sampling mode is not specified, the ADPLL 200 continues to operate in the normal mode (S105). On the other hand, if the sub-sampling mode is specified, the ADPLL 200 sets the sub-sampling mode (S106).

[0070] By switching between normal mode and subsampling mode, the low robustness of subsampling mode can be compensated for. In normal mode, even if the phase of the clock signal CLK deviates significantly due to unexpected movements or disturbances, the phase deviation can be measured within the detection range of the time-to-digital converter 214, and normal operation can be restored. For example, during calibration immediately after startup, the phase may deviate more than expected because it is unknown how much the frequency of the digitally controlled oscillator 204 will move relative to the adjustment amount. Even in such cases, appropriate control is possible by designing the detection range of the time-to-digital converter 214 to be wide. The same effect can be obtained against unexpected disturbances.

[0071] On the other hand, in subsampling mode, the phase is detected based on the slope of the sine wave, so if the phase deviates by more than ±90 degrees from the clock signal CLK, the slope will invert and the system will become uncontrollable. Therefore, at startup, the system operates in normal mode, and the ADPLL 200 performs calibration, ensuring safe startup. Then, low-jitter operation is performed in subsampling mode, achieving both robustness and low-jitter operation.

[0072] Even during subsampling mode operation, by intermittently operating in normal mode, robustness can be ensured by the wide range of phase detection provided by normal mode against problems that may cause cycle slips in the input due to disturbances, etc.

[0073] Next, the ADPLL 200 performs phase acquisition and locking (S107) and continues operation (S108). Here, the ADPLL 200 can return to S104 during the ongoing operation and determine whether the sub-sampling mode is specified.

[0074] As described above, in the first embodiment, the voltage of the clock signal CLK subsampled by the sample-and-hold circuit 211 is converted into a time difference by the voltage-to-time converter 212, and the time difference is detected by the time-to-digital converter TDC. This allows the time resolution of the clock signal CLK to be set based on the voltage resolution of the clock signal CLK. By converting the voltage of the clock signal CLK into a time difference, the time difference detected by the time-to-digital converter 214 can be expanded. This improves the time resolution of the ADPLL 200 while addressing the constraints of the TDC time resolution. By providing the sample-and-hold circuit 211 and the voltage-to-time converter 212 in the time-domain ADC 207, subsampling using an ADC is unnecessary to expand the time difference detected by the time-to-digital converter 214. This allows jitter to be reduced while suppressing increases in the circuit size and power consumption of the phase-locked loop.

[0075] Furthermore, by making it possible to switch between the normal mode and the sub-sampling mode, it is possible to ensure the robustness of the normal mode while achieving low jitter in the sub-sampling mode.

[0076] 2. Second Embodiment In the first embodiment described above, the calibration of the phase-locked loop is performed before the mode is set, whereas in this second embodiment, the calibration of the phase-locked loop is performed after the mode is set.

[0077] FIG. 10 is a flowchart showing the operation of the phase locked loop circuit according to the second embodiment.

[0078] In this flow, calibration and phase locking of the ADPLL 200 (S103) is started after the mode is set (S105, S106). Other steps in the second embodiment are the same as those in the first embodiment. By performing calibration after the mode is set, calibration can be performed while the normal mode is still in operation, and calibration can be stabilized.

[0079] In this way, in the second embodiment described above, by carrying out calibration of the phase locked loop after the mode is set, it is possible to stabilize the calibration.

[0080] 3. Third Embodiment In the first embodiment described above, it is possible to switch between the sub-sampling mode and the normal mode via the selector 213. In this third embodiment, the selector 213 is removed, and the phase locked loop operates only in the sub-sampling mode.

[0081] FIG. 11 is a block diagram showing an example of the configuration of a phase locked loop circuit according to the third embodiment.

[0082] In the figure, an ADPLL 600 includes a time-domain ADC 607 instead of the time-domain ADC 207 of the first embodiment. Other configurations of the ADPLL 600 of the third embodiment are similar to the configuration of the ADPLL 200 of the first embodiment.

[0083] The time-domain ADC 607 is obtained by removing the selector 213 from the time-domain ADC 207 of the first embodiment described above. At this time, the clock signal CLK is input to the sample-and-hold circuit 211, and the reference clock RCK is input to the sample-and-hold circuit 211 via the digital-to-time converter 208. The output voltages VP and VN of the voltage-to-time converter 212 are input to the time-to-digital converter 214. At this time, the ADPLL 600 can operate only in the sub-sampling mode. Other configurations of the time-domain ADC 607 of the third embodiment are the same as those of the time-domain ADC 207 of the first embodiment described above.

[0084] FIG. 12 is a flowchart showing the operation of the phase locked loop circuit according to the third embodiment.

[0085] In this flow, the processes of S104 and S105 in the second embodiment are omitted. After the initial setting (S102), the sub-sampling mode is set (S106), and calibration and phase acquisition are started (S103).

[0086] In this way, in the third embodiment described above, the phase locked loop operates only in the sub-sampling mode, which makes it possible to eliminate the need for the selector 213 and the mode switching control, thereby simplifying the control and reducing the circuit size.

[0087] 4. Fourth Embodiment In the first embodiment described above, the reference clock RCK is input to the selector 213 via the digital time converter 208. In this fourth embodiment, the reference clock RCK is input to the selector 213 without the digital time converter 208 being interposed therebetween.

[0088] FIG. 13 is a block diagram showing an example of the configuration of a phase locked loop circuit according to the fourth embodiment.

[0089] In the figure, an ADPLL 700 operates as an integer PLL. The ADPLL 700 is provided with a time-domain ADC 707 instead of the time-domain ADC 207 of the first embodiment. The other configurations of the ADPLL 700 of the fourth embodiment are the same as the configurations of the ADPLL 200 of the first embodiment.

[0090] In the time domain ADC 707, the reference clock RCK is input to the selector 213 without the digital-to-time converter 208. Other configurations of the time domain ADC 707 of the fourth embodiment are similar to the configuration of the time domain ADC 207 of the first embodiment described above.

[0091] In this way, in the fourth embodiment described above, the reference clock RCK can be input directly to the selector 213 by inputting the reference clock RCK to the selector 213 without using the digital time converter 208.

[0092] 5. Fifth Embodiment In the first embodiment described above, the clock signal CLK output from the digitally controlled oscillator 204 is input to the time domain ADC 207. In this fifth embodiment, the clock signal CLK output from the digitally controlled oscillator 204 is divided and then input to the time domain ADC 207.

[0093] FIG. 14 is a block diagram showing an example of the configuration of a phase locked loop circuit according to the fifth embodiment.

[0094] In the figure, an ADPLL 800 is the same as the ADPLL 800 of the first embodiment described above, except that a frequency divider 205 is added. Other configurations of the ADPLL 800 of the fifth embodiment are the same as the configuration of the ADPLL 200 of the first embodiment described above.

[0095] The frequency divider 205 is connected to the rear stage of the digitally controlled oscillator 204. At this time, the frequency divider 205 divides the frequency of the clock signal CLK generated by the digitally controlled oscillator 204, and outputs the divided signal to the counter 206, the sample-and-hold circuit 211, and the selector 213.

[0096] As described above, in the fifth embodiment, the frequency divider 205 is connected to the rear stage of the digitally controlled oscillator 204. This allows the operating frequencies of the counter 206 and the time domain ADC 207 to be lowered, thereby achieving lower power consumption.

[0097] In the above embodiment, an example has been shown in which the ADPLL is provided with the counter 206 for use in initial frequency adjustment, but the counter 206 is not necessarily required. For example, a driver and a PFD (Phase Frequency Detector) may be provided instead of the counter 206.

[0098] 6. Sixth Embodiment In the first embodiment described above, the voltage of the clock signal CLK subsampled by the sample-and-hold circuit 211 is converted into a time difference by the voltage-to-time converter 212, and the time difference is detected by the time-to-digital converter TDC. In this sixth embodiment, a phase-locked loop circuit is applied to an imaging device.

[0099] FIG. 15 is a block diagram showing an example of the configuration of an imaging apparatus according to the sixth embodiment.

[0100] In the figure, the imaging device includes an optical system 11, a solid-state imaging device 12, a controller 13, an optical system driving unit 14, and an LCD (Liquid Crystal Display) 15. The imaging device also includes a storage medium 16, a flash memory 17, an SDRAM (Synchronous Dynamic Random Access Memory) 18, and an operation unit 19. The imaging device may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, an electric vehicle (EV), or a drone.

[0101] The optical system 11 forms an optical image on the imaging surface of the solid-state imaging device 12. The optical system 11 includes a focus lens 21, a zoom lens 22, and an aperture 23. The focus lens 21 adjusts the focus position on the imaging surface of the solid-state imaging device 12. The zoom lens 22 adjusts the magnification of the subject image formed on the imaging surface. The aperture 23 adjusts the amount of light incident on the imaging surface of the solid-state imaging device 12.

[0102] The solid-state imaging device 12 detects an optical image formed on an imaging surface for each pixel, converts the detected image into an electrical signal, and digitizes and outputs the pixel signal corresponding to the amount of light in the optical image. The solid-state imaging device 12 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The phase-locked loop circuit according to any one of the first to fifth embodiments can be used to generate a clock signal that sets the operation timing of the solid-state imaging device 12.

[0103] The controller 13 performs overall control of the entire imaging device. The controller 13 may include a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). The processor may be a single-core processor or a multi-core processor. The controller 13 may also include a hardware circuit (e.g., an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit)) such as an accelerator that performs part of the processing. Note that the phase-locked loop circuit of any of the first to fifth embodiments described above can be used to generate a clock signal that operates the controller 13.

[0104] The controller 13 includes an image processing unit 31, an imaging control unit 32, an optical system control unit 34, an LCD driver 35, a storage medium control unit 36, a flash memory control unit 37, and an SDRAM control unit 38. The controller 13 also includes an AE (Auto Exposure) processing unit 61, an AF (Auto Focus) processing unit 62, a sequence control unit 63, and a compression / decompression unit 64. The image processing unit 31, the imaging control unit 32, the optical system control unit 34, the LCD driver 35, the storage medium control unit 36, the flash memory control unit 37, the SDRAM control unit 38, the AE processing unit 61, the AF processing unit 62, the sequence control unit 63, and the compression / decompression unit 64 are connected to one another via a bus 39.

[0105] The image processing unit 31 performs image processing based on pixel signals generated by the solid-state imaging device 12. The image processing unit 31 includes a luminance / color signal generation unit 101, a luminance gamma unit 102, a luminance gain unit 103, a WB (White Balance) correction unit 104, a color gamma unit 105, a color difference conversion unit 106, and a color difference gain unit 107.

[0106] The luminance / color signal generator 101 performs a matrix operation based on the pixel signals generated by the solid-state imaging device 12 to generate luminance signals and color signals. The luminance signal can indicate, for example, the luminance value of each pixel. The color signal can indicate, for example, the magnitude of the RGB components of each pixel.

[0107] The luminance gamma unit 102 corrects the luminance of the luminance signal in accordance with the display characteristics of the image. For example, the luminance gamma unit 102 can correct the luminance of the luminance signal in accordance with the luminance characteristics of the LCD 15. The luminance gain unit 103 performs gain processing on the luminance signal.

[0108] The WB correction unit 104 corrects the white balance of the color signals. The color gamma unit 105 corrects the color tones of the color signals in accordance with the display characteristics of the image. For example, the color gamma unit 105 can correct the color tones of the color signals in accordance with the color characteristics of the LCD 15. The color difference conversion unit 106 converts the color signals of RGB composition into color difference signals based on a matrix operation. The color difference gain unit 107 performs gain processing on the color difference signals.

[0109] The imaging control unit 32 controls imaging by the solid-state imaging device 12. The imaging control unit 32 includes an exposure control unit 181, a WB control unit 182, a gamma control unit 183, and a gain control unit 184.

[0110] The exposure control unit 181 controls the exposure of the solid-state imaging device 12. At this time, the exposure control unit 181 can control the exposure time, exposure amount, shutter timing, etc. of the solid-state imaging device 12 based on, for example, the processing result of the AE processing unit 61. The exposure control unit 181 can use the AE evaluation value as the processing result of the AE processing unit 61.

[0111] The WB control unit 182 controls the gain amount for each RGB component in the WB correction unit 104 based on input information input via the operation unit 19. The gamma control unit 183 controls the gamma characteristics of the luminance signal in the luminance gamma unit 102 and the gamma characteristics of the color signals in the color gamma unit 105 based on input information input via the operation unit 19. The gain control unit 184 controls the gain of the luminance signal in the luminance gain unit 103 and the gain of the color difference signals in the color difference gain unit 107 based on input information input via the operation unit 19.

[0112] The optical system control unit 34 controls the driving of the optical system driving unit 14 based on the processing results of the AE processing unit 61 and the processing results of the AF processing unit 62. The optical system control unit 34 includes an AF control unit 191, a zoom control unit 192, and an aperture control unit 193. The AF control unit 191 drives the AF motor 41 based on the processing results of the AF processing unit 62. The AF control unit 191 can use the AF evaluation value as the processing result of the AF processing unit 62. The zoom control unit 192 drives the zoom motor 42 based on the zoom operation of the operation unit 19. The aperture control unit 193 drives the aperture motor 43 based on the processing result of the AE processing unit 61. The aperture control unit 193 can use the AE evaluation value as the processing result of the AE processing unit 61.

[0113] The LCD driver 35 drives the LCD 15. The LCD driver 35 converts the image data processed by the image processing unit 31 and the image data expanded by the compression / expansion unit 64 into a video signal, and causes the LCD 15 to display an image based on this video signal.

[0114] The storage medium control unit 36 ​​controls reading and writing of data from and to the storage medium 16. The flash memory control unit 37 controls reading and writing of data from and to the flash memory 17. The SDRAM control unit 38 controls reading and writing of data from and to the SDRAM 18.

[0115] The AE processing unit 61 calculates an AE evaluation value for each predetermined region of the image data generated by the solid-state imaging device 12. The AF processing unit 62 calculates an AF evaluation value for each predetermined region of the image data generated by the solid-state imaging device 12.

[0116] The sequence control unit 63 systematically controls the processing of the imaging device. At this time, the sequence control unit 63 can control a series of flows from image processing of image data generated by the solid-state imaging device 12 to display on the LCD 15. The sequence control unit 63 can also control a series of flows from image processing of image data generated by the solid-state imaging device 12 to compression by the compression / decompression unit 64 and storage in the storage medium 16. The sequence control unit 63 can also perform interrupt processing based on operation of the operation unit 19.

[0117] The compression / decompression unit 64 compresses and decompresses the image data that has been image-processed by the image processing unit 31 using a compression method such as the JPEG (Joint Photographic Experts Group) method.

[0118] The optical system driving unit 14 drives the optical system 11 based on control from the optical system control unit 34. The optical system driving unit 14 includes an AF motor 41, a zoom motor 42, and an aperture motor 43. The AF motor 41 moves the focus lens 21 in the optical axis direction based on control from the AF control unit 191. The zoom motor 42 moves the zoom lens 22 in the optical axis direction based on control from the zoom control unit 192. The aperture motor 43 adjusts the opening diameter of the aperture 23 based on control from the aperture control unit 193.

[0119] The LCD 15 displays the captured image and various information that supports the image capturing operation.

[0120] The storage medium 16 stores images captured by the imaging device, etc. The storage medium 16 may be detachable, and may be, for example, a memory card or a USB (Universal Serial Bus) memory.

[0121] The flash memory 17 stores various control programs executed by the controller 13, parameters used to execute the various control programs, etc.

[0122] The SDRAM 18 temporarily stores data generated in the processing of the controller 13. The SDRAM 18 may include a buffer memory that stores image data for one frame.

[0123] The operation unit 19 provides a user interface for operating the imaging device. The operation unit 19 may include, for example, buttons, dials, and switches provided on the imaging device. The operation unit 19 may be configured as a touch panel together with the LCD 15.

[0124] Depending on the type of camera, some of the above functions may not be included, or conversely, functions not disclosed may be included.

[0125] FIG. 16 is a block diagram showing an example of the configuration of a solid-state imaging device according to the sixth embodiment.

[0126] In the figure, the solid-state imaging device 12 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit .

[0127] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along a row direction (also referred to as the horizontal direction) and a column direction (also referred to as the vertical direction). Each pixel 120 can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 for each row when reading out a signal from each pixel 120. The vertical signal line 132 transmits a potential based on a current flowing when reading out a signal from the pixel 120 to the column signal processing unit 114 for each column.

[0128] The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using a vertical register.

[0129] The column readout circuit 113 can form a source follower between itself and each pixel 120 when reading out a signal from the pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120.

[0130] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output an imaging signal Gout.

[0131] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel 120 and the reference signal.

[0132] The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0133] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

[0134] 7. Seventh Embodiment In the first embodiment described above, a phase locked loop circuit is applied to an imaging device. In this seventh embodiment, semiconductor chips each having a pixel array section in which pixels are arranged in a matrix are stacked.

[0135] FIG. 17 is a perspective view showing an example of a stack of pixel array units according to the seventh embodiment.

[0136] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0137] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0138] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillation circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The oscillation circuit 928 can be provided with any of the phase locked loop circuits described in the first to fifth embodiments.

[0139] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0140] As described above, in the sixth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0141] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0142] FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0143] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 18, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0144] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0145] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0146] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0147] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0148] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0149] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0150] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0151] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0152] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 18, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0153] FIG. 19 is a diagram showing an example of the installation position of the imaging unit 12031.

[0154] In FIG. 19, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0155] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0156] 19 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0157] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0158] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0159] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0160] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0161] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031 among the above-described configurations. Specifically, for example, the phase-locked loop circuit of the above-described embodiment can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031. By applying the technology disclosed herein to the vehicle control system 12000, it is possible to improve the time resolution in digital processing.

[0162] In addition, the phase locked loop circuit according to any one of the first to fifth embodiments described above can be applied to an imaging device, and may also be applied to electronic circuits used in communication devices, display devices, data processing devices, control devices, measuring devices, printing devices, etc.

[0163] Furthermore, the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0164] The present technology may also be configured as follows: (1) A phase locked loop circuit comprising: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-to-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter. (2) The phase locked loop circuit according to (1), wherein the sample-and-hold circuit, the voltage-to-time converter, and the time-to-digital converter form a time-domain ADC (Analog to Digital Converter). (3) The phase locked loop circuit according to (2), wherein the time resolution of the time-domain ADC is higher than the time resolution of the time-to-digital converter. (4) The phase locked loop circuit according to any one of (1) to (3), further comprising: a digitally controlled oscillator that generates the input signal. (5) The phase locked loop circuit according to (4), further comprising: an accumulator that sets a count-up value for each period of the reference signal based on an FCW (Frequency Command Word), a counter that counts up for each period of the input signal, an arithmetic unit that subtracts the output of the counter and the output of the voltage-to-time converter from the output of the accumulator, and a loop filter that band-limits the input to the digitally controlled oscillator. (6) The phase locked loop circuit according to (4) or (5), further comprising: a frequency divider that divides the frequency of the input signal generated by the digitally controlled oscillator. (7) The phase locked loop circuit according to any of (1) to (6), further comprising: a digital-to-time converter that delays the reference signal. (8) The phase locked loop circuit according to any of (1) to (7), further comprising: a selector that switches between an input of the time difference converted by the voltage-to-time converter and an input of the reference signal and the input signal to the time-to-digital converter. (9) The phase-locked loop circuit according to (8), wherein the selector inputs the time difference converted by the voltage-to-time converter to the time-to-digital converter when a sub-sampling mode is specified, and inputs the reference signal and the input signal to the time-to-digital converter when a normal mode is specified.(10) The phase locked loop circuit according to (9), wherein the normal mode is operated intermittently while operating in the subsampling mode. (11) The phase locked loop circuit according to any one of (1) to (10), wherein calibration of a phase locked loop is performed. (12) An imaging device comprising: an imaging unit provided with a plurality of pixels; and a phase locked loop circuit that generates a clock signal that sets the operation timing of the imaging unit, wherein the phase locked loop comprises: a sample and hold circuit that subsamples the clock signal based on a reference clock; a voltage-to-time converter that converts the voltage of the clock signal subsampled by the sample and hold circuit into a time difference; and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter. (13) An electronic circuit comprising: a circuit unit that operates based on a clock signal; and a phase locked loop circuit that generates a clock signal that sets the operation timing of the circuit unit, wherein the phase locked loop comprises: a sample and hold circuit that subsamples the clock signal based on a reference clock; a voltage-to-time converter that converts the voltage of the clock signal subsampled by the sample and hold circuit into a time difference; and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter.

[0165] 200 ADPLL 201 Accumulator 202 Arithmetic unit 203 Loop filter 204 Digitally controlled oscillator 206 Counter 207 Time domain ADC 208 Digital-to-time converter 209 Control unit 211 Sample-and-hold circuit 212 Voltage-to-time converter 213 Selector 214 Time-to-digital converter

Claims

1. A phase-locked loop circuit comprising: a sample-and-hold circuit that sub-samples an input signal based on a reference signal; a voltage-to-time converter that converts the voltage of the input signal sub-sampled by the sample-and-hold circuit into a time difference; and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter.

2. The phase locked loop circuit according to claim 1, wherein the sample and hold circuit, the voltage-to-time converter and the time-to-digital converter constitute a time domain ADC (Analog to Digital Converter).

3. The phase locked loop circuit according to claim 2, wherein the time resolution of the time domain ADC is higher than the time resolution of the time to digital converter.

4. The phase locked loop of claim 1, further comprising: a digitally controlled oscillator for generating said input signal.

5. The phase locked loop circuit according to claim 4, further comprising: an accumulator that sets a count-up value for each period of the reference signal based on a Frequency Command Word (FCW); a counter that counts up for each period of the input signal; an arithmetic unit that subtracts the output of the counter and the output of the voltage-to-time converter from the output of the accumulator; and a loop filter that band-limits the input to the digitally controlled oscillator.

6. The phase locked loop circuit according to claim 4, further comprising a frequency divider for dividing the frequency of the input signal generated by the digitally controlled oscillator.

7. The phase locked loop of claim 1, further comprising: a digital time converter that delays the reference signal.

8. The phase locked loop circuit according to claim 1, further comprising a selector for switching between an input of the time difference converted by the voltage-to-time converter and an input of the reference signal and the input signal to the time-to-digital converter.

9. The phase-locked loop circuit according to claim 8, wherein the selector inputs the time difference converted by the voltage-to-time converter to the time-to-digital converter when a subsampling mode is specified, and inputs the reference signal and the input signal to the time-to-digital converter when a normal mode is specified.

10. The phase locked loop circuit according to claim 9, wherein the normal mode is operated intermittently during operation in the sub-sampling mode.

11. The phase locked loop circuit according to claim 1, which performs calibration of the phase locked loop.

12. An imaging device comprising: an imaging section having a plurality of pixels; and a phase synchronization circuit that generates a clock signal that sets the operation timing of the imaging section, the phase synchronization circuit comprising: a sample-and-hold circuit that sub-samples the clock signal based on a reference clock; a voltage-to-time converter that converts the voltage of the clock signal sub-sampled by the sample-and-hold circuit into a time difference; and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter.

13. An electronic circuit comprising: a circuit section that operates based on a clock signal; and a phase-locked loop circuit that generates a clock signal that sets the operation timing of the circuit section, wherein the phase-locked loop circuit comprises: a sample-and-hold circuit that sub-samples the clock signal based on a reference clock; a voltage-to-time converter that converts the voltage of the clock signal sub-sampled by the sample-and-hold circuit into a time difference; and a time-to-digital converter that detects the time difference converted by the voltage-to-time converter.

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