Semiconductor device and imaging apparatus

Abstract

This semiconductor device comprises: an MIM structure that includes a lower electrode and an upper electrode; an upper wiring layer; and a via that connects the upper electrode and the upper wiring layer. The upper wiring layer includes: a first wiring pattern that extends so as not to cover the via; and a second wiring pattern that has a width narrower than the width of the first wiring pattern and protrudes and extends from the first wiring pattern, so as to cover the via. The via connects the upper electrode and the second wiring pattern.

Description

Semiconductor device and imaging device

[0001] The present disclosure relates to a semiconductor device and an imaging device.

[0002] For example, Patent Document 1 discloses a semiconductor device having an MIM capacitor including a lower electrode and an upper electrode.

[0003] Japanese Patent Application Laid-Open No. 2021-48340

[0004] To provide electrical contact to an MIM structure, such as an MIM capacitor, a via is provided connecting the wiring pattern of an upper wiring layer to the top electrode of the MIM structure. This configuration can result in a widening facet of the via as it extends upward, which can degrade the electrical performance of the MIM structure.

[0005] One aspect of the present disclosure suppresses faceting.

[0006] A semiconductor device according to one aspect of the present disclosure comprises an MIM structure including a lower electrode and an upper electrode, an upper wiring layer, and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes a first wiring pattern extending so as not to cover the via, and a second wiring pattern having a width narrower than that of the first wiring pattern and extending to protrude from the first wiring pattern so as to cover the via, and the via connects the upper electrode and the second wiring pattern.

[0007] An imaging device according to one aspect of the present disclosure comprises an MIM structure including a lower electrode and an upper electrode, an upper wiring layer, and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes a first wiring pattern extending so as not to cover the via, and a second wiring pattern having a width narrower than that of the first wiring pattern and extending to protrude from the first wiring pattern so as to cover the via, and the via connects the upper electrode and the second wiring pattern.

[0008] 1 is a diagram illustrating an example of a schematic configuration of a semiconductor device 1 according to an embodiment. FIG. 1 is a diagram illustrating an example of a schematic configuration of a semiconductor device 1 according to an embodiment. FIG. 2 is a diagram illustrating an example of a manufacturing method of the semiconductor device 1. FIG. 3 is a diagram illustrating an example of a manufacturing method of the semiconductor device 1. FIG. 4 is a diagram illustrating an example of a manufacturing method of the semiconductor device 1. FIG. 5 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. FIG. 6 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. FIG. 7 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. FIG. 8 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. FIG. 9 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. FIG. 10 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. FIG. 11 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. FIG. 12 is a diagram illustrating a modified example of the wiring pattern of the upper wiring layer 4. 1 is a diagram showing an example of a schematic configuration of a semiconductor device 1 having a stack structure.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the same elements are designated by the same reference numerals, and redundant description will be omitted.

[0010] The present disclosure will be described in the following order: 1. Embodiment 2. Modification 3. Summary

[0011] 1 to 3 are diagrams showing an example of a schematic configuration of a semiconductor device 1 according to an embodiment. The semiconductor device 1 includes a lower wiring layer 2, a metal-insulator-metal (MIM) layer 3, an upper wiring layer 4, vias 5, vias 6, and an insulating material 7.

[0012] An XYZ coordinate system is also shown. The X-axis direction and Y-axis direction (XY plane direction) correspond to the surface directions of the lower wiring layer 2, MIM layer 3, and upper wiring layer 4. The Z-axis direction corresponds to the thickness direction (height direction) of the layers. The Z-axis direction is also referred to as the up-down direction. The positive direction of the Z-axis corresponds to the upward direction, and the negative direction of the Z-axis corresponds to the downward direction. The lower wiring layer 2, MIM layer 3, and upper wiring layer 4 are located in this order in the positive direction of the Z-axis.

[0013] Fig. 1 shows a schematic planar layout of several elements when the semiconductor device 1 is viewed in a plan view (as viewed in the negative direction of the Z axis). Fig. 2 and Fig. 3 show schematic cross sections when viewed along lines II-II and III-III in Fig. 1. For ease of understanding, wiring patterns 41, 42, and insulating material 7 (all of which will be described later) are shown hatched in Fig. 1 as well.

[0014] The lower wiring layer 2 is a wiring layer located below (on the negative side of the Z axis) the MIM layer 3, and in this example, is provided on the opposite side of the MIM layer 3 from the upper wiring layer 4. Examples of wiring patterns included in the lower wiring layer 2 include a wiring pattern 21 and a wiring pattern 22. The material (metal material) of the wiring pattern of the lower wiring layer 2 is copper (Cu), aluminum (Al), tungsten (W), etc.

[0015] The MIM layer 3 is provided between the lower wiring layer 2 and the upper wiring layer 4. The MIM layer 3 includes an MIM structure 30.

[0016] The MIM structure 30 includes a lower electrode 31, a dielectric 32, and an upper electrode 33. The lower electrode 31, the dielectric 32, and the upper electrode 33 are stacked in this order in the positive direction of the Z axis. The dielectric 32 is provided between the lower electrode 31 and the upper electrode 33 so that the lower electrode 31 and the upper electrode 33 are capacitively coupled to each other while electrically isolating them. The MIM structure 30 can also be called an MIM capacitor, etc.

[0017] The MIM structure 30 includes a trench portion 300. The trench portion 300 is configured to bring the lower electrode 31 close to the lower wiring layer 2. The lower electrode 31 is connected to the wiring pattern 21 of the lower wiring layer 2 in the trench portion 300. To the extent that there is no contradiction, the term "connection" may be interpreted to include electrical connection.

[0018] The MIM layer 3 may include several films. One example of such a film is a metal diffusion prevention film. Films 34, 35, and 36 are shown in the figure, each designated by a reference numeral. The film 34 is provided to cover the upper surface (the surface on the positive Z-axis direction) of the lower wiring layer 2, except for the wiring pattern 21. The film 34 may be an insulating film such as a TEOS film. The film 35 is provided to cover the lower electrode 31. The film 35 may be a conductive film (e.g., SiC) and electrically connects the lower electrode 31 to the wiring pattern 21 of the lower wiring layer 2. The film 36 is provided to cover the upper electrode 33, except for the via 5. The film 36 may be an insulating film such as P-Sin, SiO2, SiN, or SiCN.

[0019] At the ends of the MIM structure 30 (ends in the XY plane), the ends of the lower electrode 31 and the upper electrode 33 are misaligned. Specifically, the lower electrode 31 extends further outward than the upper electrode 33. When the semiconductor device 1 is viewed in a plan view (when viewed in the negative Z-axis direction), the upper electrode 33 is located inside the lower electrode 31. The misalignment of the ends of the lower electrode 31 and the upper electrode 33 makes it easier to ensure electrical isolation between the lower electrode 31 and the upper electrode 33 than would be the case if they were aligned. However, for this reason, the MIM structure 30 has a step 30s at its end. At the step 30s, the lower electrode 31 extends further outward than the upper electrode 33.

[0020] The upper wiring layer 4 is a wiring layer located above (on the positive side of the Z axis) the MIM layer 3. The upper wiring layer 4 includes a wiring pattern 41, a wiring pattern 42, and a wiring pattern 43. When no particular distinction is made between these, they are simply referred to as the wiring patterns of the upper wiring layer 4. The material of the wiring patterns of the upper wiring layer 4 may be the same as the material of the wiring patterns of the lower wiring layer 2.

[0021] The wiring pattern 41 is a first wiring pattern that extends so as not to cover the via 5. The wiring pattern 42 is a second wiring pattern that extends so as to cover the via 5. The wiring pattern 42 has a width narrower than the width of the wiring pattern 41 (in this example, the length in the X-axis direction) and extends to protrude from the wiring pattern 41 (in this example, in the negative Y-axis direction). When viewed in a plan view, the wiring pattern 41 and the wiring pattern 42 can have a convex layout that protrudes toward the via 5 as a whole.

[0022] The wiring pattern 42 includes an extending portion 421 and a tip portion 422. Of the extending portion 421 and the tip portion 422, the tip portion 422 covers the via 5. The extending portion 421 is connected between the wiring pattern 41 and the tip portion 422.

[0023] The end faces on both sides of the tip portion 422 are referred to as side faces 422a and 422b and are illustrated as such. The side faces 422a and 422b are a pair of side faces facing each other. The end face at the tip of the tip portion 422 is referred to as tip face 422c and is illustrated as such. The tip face 422c connects the side faces 422a and 422b at the tip of the tip portion 422. Further details of the wiring pattern 42 will be described later.

[0024] The wiring pattern 43 is a third wiring pattern provided separately from the wiring patterns 41 and 42 .

[0025] The via 5 connects the upper electrode 33 of the MIM structure 30 to the wiring pattern 42 of the upper wiring layer 4. More specifically, the via 5 connects the upper electrode 33 to the tip 422 of the wiring pattern 42. The material of the via 5 may be the same as the material of the wiring patterns of the lower wiring layer 2 and the upper wiring layer 4.

[0026] The via 5 is connected to a portion of the upper electrode 33 of the MIM structure 30 other than the trench portion 300 (for example, a portion somewhat distant from the trench portion 300). In this example, the via 5 is connected to the upper electrode 33 near the end of the MIM structure 30.

[0027] The side surfaces of the via 5 are referred to as side surface 5a, side surface 5b, side surface 5c, and side surface 5d and are illustrated. The side surface 5a is the side surface of the via 5 on the trench portion 300 side (located on the trench portion 300 side). The side surfaces 5b and 5c are the side surfaces of the via 5 on the step portion 30s side.

[0028] In the semiconductor device 1, the wiring patterns 41 and 42 of the upper wiring layer 4 are provided so as to suppress faceting of the via 5. The facet indicates that the via 5 widens as it extends upward, and more specifically, may be understood to indicate the widened portion. The length of the facet (length in the XY plane direction) is also referred to as the "facet width." The facet width may be the length of the facet at the upper end of the via 5.

[0029] The principle will be described later, but the facet of the via 5 is suppressed at three side surfaces, namely, side surface 5a, side surface 5b, and side surface 5c of the via 5. The facet of the via 5 is not suppressed at side surface 5d of the via 5. The facet widths of the side surfaces 5a, 5b, and 5c of the via 5 are smaller than the facet width of the side surface 5d, and are substantially zero in the examples shown in FIGS. 2 and 3. The side surfaces 5a, 5b, and 5c extend in the same direction as the Z-axis direction. The side surface 5d extends at an angle with respect to the Z-axis direction.

[0030] Via 6 is a via different from via 5, and connects the wiring pattern 43 of the upper wiring layer 4 to the lower wiring layer 2. More specifically, via 6 connects the wiring pattern 43 of the upper wiring layer 4 to the wiring pattern 22 of the lower wiring layer 2. The material of via 6 may be the same as the materials of the lower wiring layer 2, the upper wiring layer 4, and via 5.

[0031] Via 6 has a height different from that of via 5 (length in the Z-axis direction), and more specifically, has a height greater than that of via 5. A portion of via 6 that is at the same height as via 5 is referred to as via 61. A portion of via 6 other than via 61 is referred to as via 62 and illustrated. Of vias 61 and 62, via 61 is connected to wiring pattern 43 of upper wiring layer 4. Via 62 is connected to wiring pattern 22 of lower wiring layer 2.

[0032] The insulating material 7 is provided so as to fill the spaces between the elements of the semiconductor device 1 described above. For example, the insulating material 7 is provided so as to fill the spaces between the wiring patterns of the lower wiring layer 2. The insulating material 7 is provided so as to fill the parts of the MIM layer 3 other than the MIM structure 30, the film 34, the film 35, and the film 36. The insulating material 7 is provided so as to fill the spaces between the wiring patterns of the upper wiring layer 4.

[0033] The wiring pattern 42 of the upper wiring layer 4 will now be described. When the semiconductor device 1 is viewed in plan, a tip surface 422c of the tip portion 422 of the wiring pattern 42 is adjacent to a corresponding side surface of the via 5, in this example, the side surface 5c (the side surface on the stepped portion 30s side).

[0034] The above-mentioned "adjacent" may mean that the distance between the tip surface 422c and the side surface 5c is smaller than the facet width of the side surface 5d described above. "Adjacent" may also be interpreted to mean that the distance between the tip surface 422c and the side surface 5c is substantially zero. For example, even if the design value of the distance between the tip surface 422c and the side surface 5c is zero, but the actual distance is not zero due to variation, the distance may be interpreted as being substantially zero.

[0035] In addition, a side surface 422a of the tip portion 422 of the wiring pattern 42 is adjacent to a corresponding side surface of the via 5, which in this example is the side surface 5a (the side surface on the trench portion 300 side). A side surface 422b of the tip portion 422 of the wiring pattern 42 is adjacent to a corresponding side surface of the via 5, which in this example is the side surface 5b (the side surface on the step portion 30s side).

[0036] The tip portion 422 of the wiring pattern 42 can also be said to have a rectangular shape in which the side surface 422a, the side surface 422b, and the tip surface 422c are in contact with the insulating material 7. The tip portion 422 of such wiring pattern 42 covers the via 5, thereby suppressing facets on the side surface 5a, the side surface 5b, and the side surface 5c of the via 5. The reason for this will be explained together with the manufacturing method of the semiconductor device 1.

[0037] 4 to 6 are diagrams showing an example of a method for manufacturing the semiconductor device 1. (A) and (B) in each diagram correspond to the portions of FIGS. 2 and 3 above.

[0038] It is assumed that the processes of preparing the lower wiring layer 2 and the MIM layer 3 and providing (e.g., depositing) the insulating material 7 so as to cover them have been completed. As will be explained next, dry etching is performed to obtain the shapes of the wiring patterns of the vias 6, 5, and the upper wiring layer 4. Hereinafter, the dry etching process may also be simply referred to as "processing."

[0039] 4, the insulating material 7 is processed to obtain the shape of the via 62 of the via 6. The void portion obtained by this processing is referred to as a void portion 62r and is shown in the figure.

[0040] As shown by the white arrows in Figure 5, the insulating material 7 is further processed to obtain the shape of via 5 and the shape of via 61 of via 6. The voids obtained by this processing are referred to as void 5r and void 61r and are illustrated. The void 61r is connected to void 62r, and these are collectively referred to as void 6r and are illustrated. The void 6r can correspond to the shape of via 6.

[0041] As indicated by the white arrows in FIG. 6 , the insulating material 7 is further processed, and the film 36 is also processed, to obtain the shapes of the wiring patterns 41, 42, and 43. The voids obtained by this processing are referred to as voids 41r, 42r, and 43r and are illustrated. The voids 41r and 42r are interconnected. More specifically, the void 42r includes voids 421r and 422r that correspond to the shapes of the extension 421 and tip 422 of the wiring pattern 42. The voids 421r and 422r are interconnected. The void 422r is interconnected with the void 5r. The void 43r is also interconnected with the void 61r of the void 6r.

[0042] 6, there is a possibility that the insulating material 7 will be scraped away from the periphery of the upper edges of the gaps 5r and 61r. Particularly with regard to the gap 5r, the portion of the insulating material 7 around the upper edge of the gap 5r that is susceptible to dry etching to obtain the gaps 421r and 41r that are connected to the gaps 422r is scraped away. In this example, the portion of the insulating material 7 around the upper edge of the gap 5r that is located below the gap 421r is scraped away. In this portion, the gap 5r has a shape that widens as it extends upward.

[0043] In other portions, the void 5r does not have a shape that widens upward. This is because, as previously described with reference to FIGS. 1 to 3 , the wiring pattern 42 (extension portion 421 and tip portion 422) extends from the wiring pattern 41 with a width narrower than that of the wiring pattern 41. This reduces the impact of the dry etching process for obtaining the shape of the wiring pattern 42 on the periphery of the upper edge of the void 5r compared to when the wiring pattern 42 has the same width as the wiring pattern 41. More specifically, as previously described, when the semiconductor device 1 is viewed in plan, the side surfaces 422a, 422b, and tip surface 422c of the tip portion 422 of the wiring pattern 42 are adjacent to the side surfaces 5a, 5b, and 5c of the via 5. The dry etching process for obtaining such a shape of the wiring pattern 42 does not remove the portions of the periphery of the upper edge of the void 5r that correspond to the side surfaces 5a, 5b, and 5c of the via 5.

[0044] As described above, dry etching is performed to obtain the voids 6r, 5r, 41r, 42r, and 43r. In other words, dry etching is performed to obtain the overall shapes of the vias 6, 5, and the wiring patterns 41, 42, and 43 of the upper wiring layer 4, as previously described with reference to FIGS. 1 to 3. Thereafter, a metal material is provided (deposited as a film, etc.) so as to fill the voids 6r, 5r, 41r, 42r, and 43r, thereby forming the vias 6, 5, wiring patterns 41, 42, and 43. Since the shape of the via 5 is the same as the shape of the void 5r, a via 5 with suppressed facets on the side surfaces 5a, 5b, and 5c is obtained, as described above.

[0045] The technical significance of suppressing facets of the via 5 will be described. If the facets are large (if the facet width is large), the upper electrode 33 and the lower electrode 31 of the MIM structure 30 may become conductive, resulting in a decrease in the electrical performance of the MIM structure 30. For example, if a facet is generated such that the via 5 spreads toward the step portion 30s of the MIM structure 30, interference of the via 5 with the step portion 30s may weaken the electrical isolation between the upper electrode 33 and the lower electrode 31 of the MIM structure 30, potentially resulting in leakage or the like. A similar problem may occur if a facet is generated such that the via 5 spreads toward the trench portion 300 of the MIM structure 30.

[0046] By suppressing the faceting of the via 5, it is possible to suppress the degradation of the electrical performance of the MIM structure 30 as described above. That is, by suppressing the faceting of the side surface 5a of the via 5, it is possible to suppress the faceting of the via 5 that widens toward the trench portion 300. By suppressing the faceting of the side surface 5b of the via 5, it is possible to suppress the faceting of the via 5 that widens toward the step portion 30s. By suppressing the faceting of the side surface 5c of the via 5, it is possible to suppress the faceting of the via 5 that widens toward the step portion 30s.

[0047] 2. Modifications The disclosed technology is not limited to the above-described embodiment. Some modifications will be described.

[0048] The wiring pattern of the upper wiring layer 4 may be designed in various layouts within a range that can obtain the effect of suppressing facets of the vias 5. Some examples will be described with reference to FIGS.

[0049] 7 to 22 are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. The area of ​​the wiring pattern 41 may be larger or smaller than the area of ​​the wiring pattern 41 shown in FIG. 1 described in the previous embodiment. The area of ​​the wiring pattern 41 is determined, for example, by the length in the X-axis direction, the length in the Y-axis direction, etc. FIGS. 7 to 21 show examples of various wiring patterns 41 having different lengths, particularly in the Y-axis direction. FIG. 22 shows an example of a wiring pattern 41 having different lengths in the X-axis direction.

[0050] The extending portion 421 of the wiring pattern 42 may be longer or shorter than the extending portion 421 shown in Fig. 1 described in the previous embodiment. For example, Fig. 8, Fig. 12 to Fig. 14, Fig. 17, and Fig. 18 show wiring patterns 42 having relatively long extending portions 421. The length of the extending portion 421 may be zero, and in that case, the wiring pattern 42 may include only a tip portion 422, as shown in Fig. 10, for example.

[0051] The extending direction of the extending portion 421 of the wiring pattern 42 is not limited, and the extending portion 421 may include a bent portion, a curved portion, etc. For example, as shown in Figures 11 to 18, the extending portion 421 of the wiring pattern 42 may protrude and extend from the wiring pattern 41, bend, and further extend.

[0052] The wiring pattern 42 may protrude in any direction from any portion of the wiring pattern 41. For example, as shown in Figures 15 to 18 and 21, the wiring pattern 42 may protrude in the positive direction of the Y axis from an edge of the wiring pattern 41 on the positive side of the Y axis. As shown in Figure 22, the wiring pattern 42 may protrude in the positive direction of the X axis from an edge of the wiring pattern 41 on the positive side of the X axis.

[0053] 19 and 20, the wiring pattern 42 may be connected to two different portions of the wiring pattern 41. Even with the wiring pattern 42 as shown in the drawings, facets on the two side surfaces of the via 5 are suppressed.

[0054] In the above embodiment, a case has been described in which, when the semiconductor device 1 is viewed from above, the side surface 422a of the tip portion 422 of the wiring pattern 42 is adjacent to the side surface 5c of the via 5 on the stepped portion 30s side. However, the side surface 422a of the tip portion 422 may be adjacent to the side surface of the via 5 on the trench portion 300 side.

[0055] In one embodiment, the semiconductor device 1 may be an imaging device. Hereinafter, the imaging device is assumed to be a solid-state imaging device such as an image sensor. For example, the semiconductor device 1 includes a pixel array unit including a plurality of pixel circuits, peripheral circuits that drive the pixel array unit and read pixel signals, and the like.

[0056] The pixel circuit is configured to include one or more photoelectric conversion units, one or more transistors, one or more capacitors, etc. The photoelectric conversion unit is configured to include a photoelectric conversion element such as a photodiode. The transistor discharges (resets) the charge accumulated in the photoelectric conversion unit, and converts the charge accumulated in the photoelectric conversion unit into a pixel signal and outputs it. The capacitor, for example, converts the charge of the photoelectric conversion unit into a voltage, or stores the charge in cooperation with the photoelectric conversion unit. The MIM structure 30 described above is used as at least some of the capacitors.

[0057] In one embodiment, the semiconductor device 1 may have a stack structure in which two semiconductor chips are stacked. The two semiconductor chips are bonded to each other so as to be electrically connected. This will be described with reference to FIG. 23 as well.

[0058] 23 is a diagram showing an example of a schematic configuration of a semiconductor device 1 having a stack structure. The semiconductor device 1 includes a semiconductor chip 100 and a semiconductor chip 200. The semiconductor chip 100 and the semiconductor chip 200 are stacked in the Z-axis direction.

[0059] The semiconductor chip 100 includes, for example, the pixel array section described above, and the MIM structure 30 described above is used as a capacitor therein.

[0060] The semiconductor chip 200 includes, for example, the peripheral circuits described above. Of the components of the semiconductor chip 200, the wiring layer 8 is illustrated with a reference numeral. Several wiring patterns included in the wiring layer 8 are illustrated and referred to as wiring pattern 81, wiring pattern 82, and wiring pattern 83. The material of the wiring pattern of the wiring layer 8 may be the same as the material of the wiring pattern of the lower wiring layer 2, the wiring pattern of the upper wiring layer 4, and the vias 5 and 6.

[0061] The semiconductor chips 100 and 200 are bonded together so that the wiring pattern of the upper wiring layer 4 of the semiconductor chip 100 and the wiring pattern of the wiring layer 8 of the semiconductor chip 200 are in surface contact with each other. In this example, the semiconductor chips 100 and 200 are bonded together so that the wiring patterns 41, 42, and 43 of the upper wiring layer 4 are in surface contact with the wiring patterns 81, 82, and 83 of the wiring layer 8.

[0062] The operating voltage of the semiconductor chip 100 and the operating voltage of the semiconductor chip 200 may be different from each other. For example, the operating voltage of the semiconductor chip 200 may be higher than the operating voltage of the semiconductor chip 100. The operation of the semiconductor chip 200 may affect the semiconductor chip 100. For example, an electromagnetic field generated in the semiconductor chip 200 may cause hot carriers or noise to be generated in the semiconductor chip 100.

[0063] In order to suppress the occurrence of the above-mentioned hot carriers, noise, etc., the semiconductor chip 100 is designed so that the wiring pattern of the upper wiring layer 4 covers as much area as possible (so that the area is large). In addition, only the wiring pattern 42 portion may be designed to have a narrower width than the wiring pattern 41 so that the facet of the via 5 can be suppressed.

[0064] 3. Summary The technology described above can be specified, for example, as follows. One of the disclosed technologies is a semiconductor device 1 (e.g., a solid-state imaging device). As described with reference to FIGS. 1 to 23 , the semiconductor device 1 includes an MIM structure 30 including a lower electrode 31 and an upper electrode 33, an upper wiring layer 4, and a via 5 connecting the upper electrode 33 to the upper wiring layer 4. The upper wiring layer 4 includes a wiring pattern 41 (first wiring pattern) extending so as not to cover the via 5, and a wiring pattern 42 (second wiring pattern) having a width narrower than the wiring pattern 41 and extending to protrude from the wiring pattern 41 so as to cover the via 5, and the via 5 connects the upper electrode 33 to the wiring pattern 42. For example, as described with reference to FIGS. 1 , 2 , and 7 to 22 , the wiring pattern 42 may include a tip portion 422 covering the via 5, and the via 5 may connect the upper electrode 33 to the tip portion 422 of the wiring pattern 42. Furthermore, as described with reference to Figures 1, 2, 8, 9, and 11 to 22, the wiring pattern 42 may include an extension portion 421 connected between the wiring pattern 41 and the tip portion 422.

[0065] According to the semiconductor device 1 described above, faceting of the via 5 can be suppressed more effectively than when the wiring pattern 42 has the same width as the wiring pattern 41, for example.

[0066] 1 and 2 , in plan view, the tip surface 422 c of the tip portion 422 of the wiring pattern 42 may be adjacent to the corresponding side surface 5 c of the via 5. This makes it possible to suppress faceting of the side surface 5 c of the via 5.

[0067] 1 and 2 , the MIM structure 30 includes a stepped portion 30s at its edge where the lower electrode 31 extends further outward than the upper electrode 33, and in plan view, a tip surface 422c of the tip portion 422 of the wiring pattern 42 may be adjacent to a side surface 5c of the via 5 on the stepped portion 30s side. This prevents the via 5 from forming a facet that widens toward the stepped portion 30s, and can prevent a deterioration in the electrical performance of the MIM structure 30 that may occur due to interference of the via 5 with the stepped portion 30s, etc.

[0068] 1 and 3 , in plan view, the side surface 422 a of the tip portion 422 of the wiring pattern 42 may be adjacent to the corresponding side surface 5 a of the via 5, and the side surface 422 b may be adjacent to the corresponding side surface 5 b of the via 5. This makes it possible to suppress faceting of the side surface 5 a of the via 5 and suppress faceting of the side surface 5 b.

[0069] 1 to 3 , the MIM structure 30 includes the trench portion 300, and in plan view, the side surface 422 a (one of the pair of side surfaces) of the tip portion 422 of the wiring pattern 42 may be adjacent to the side surface 5 a of the via 5 on the trench portion 300 side. This makes it possible to suppress facets in which the via 5 widens toward the trench portion 300 of the MIM structure 30, and to suppress degradation of the electrical performance of the MIM structure 30 that may occur due to interference of the via 5 with the trench portion 300, etc.

[0070] 1 and 3 , in plan view, the side surface 42 b (the other of the pair of side surfaces) of the tip portion 422 of the wiring pattern 42 may be adjacent to the side surface 5 b on the stepped portion 30 s side of the via 5. This makes it possible to suppress faceting of the via 5 that widens toward the stepped portion 30 s of the MIM structure 30, and to suppress degradation of the electrical performance of the MIM structure 30 that may occur due to interference of the via 5 with the stepped portion 30 s, etc.

[0071] 1 to 3 , the semiconductor device 1 includes an insulating material 7 provided so as to fill the gaps between the wiring patterns (e.g., the wiring pattern 41, the wiring pattern 42) of the upper wiring layer 4, and the tip portion 422 of the wiring pattern 42 may have a rectangular shape in which the side surfaces 422a and 422b (a pair of side surfaces) and the tip surface 422c are in contact with the insulating material 7. For example, by covering the via 5 with such a wiring pattern 42, it is possible to suppress facets on the side surfaces of the via 5 corresponding to the three sides of the side surfaces 422a, 422b, and the tip portion 422.

[0072] As described with reference to Figures 1 to 6, the semiconductor device 1 may include a lower wiring layer 2 provided on the opposite side of the MIM structure 30 from the upper wiring layer 4, the upper wiring layer 4 including a wiring pattern 43 (a third wiring pattern), and the semiconductor device 1 may include a via 6 (another via) connecting the wiring pattern 43 of the upper wiring layer 4 to the lower wiring layer 2. The via 6, the via 5, the wiring patterns 41, 42, and 43 of the upper wiring layer 4 may be formed by providing a metal material after performing dry etching to obtain their overall shapes. For example, this makes it possible to suppress faceting of the via 5, which may occur when the via 6, the via 5, the wiring patterns 41, 42, and 43 of the upper wiring layer 4 are formed simultaneously.

[0073] The effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0074] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0075] The present technology can also be configured as follows. (1) A semiconductor device comprising: an MIM structure including a lower electrode and an upper electrode; an upper wiring layer; and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes: a first wiring pattern extending so as not to cover the via; and a second wiring pattern extending to protrude from the first wiring pattern and covering the via, with a width narrower than that of the first wiring pattern, wherein the via connects the upper electrode and the second wiring pattern. (2) The semiconductor device according to (1), wherein the second wiring pattern includes a tip portion covering the via, and the via connects the upper electrode and the tip portion of the second wiring pattern. (3) The semiconductor device according to (2), wherein the second wiring pattern includes an extension portion connected between the first wiring pattern and the tip portion. (4) The semiconductor device according to (2) or (3), wherein, in a plan view, a tip surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via. (5) The semiconductor device according to (4), wherein the MIM structure includes a step portion at an edge thereof where the lower electrode extends outward beyond the upper electrode, and wherein, in a plan view, the tip surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the step portion side. (6) The semiconductor device according to any of (2) to (5), wherein, in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via. (7) The semiconductor device according to (6), wherein the MIM structure includes a trench portion, and wherein, in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the trench portion side. (8) The semiconductor device according to (6) or (7), wherein the MIM structure includes a step portion at its edge where the lower electrode extends further outward than the upper electrode, and when viewed in a plane, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the step portion side.(9) The semiconductor device according to any one of (6) to (8), wherein the MIM structure includes a stepped portion at an edge thereof where the lower electrode extends further outward than the upper electrode, the MIM structure includes a trench portion, and the side surfaces of the tip portion of the second wiring pattern are a pair of side surfaces, one of the pair of side surfaces is adjacent to a side surface of the via on the trench portion side, and the other of the pair of side surfaces is adjacent to a side surface of the via on the stepped portion side. (10) The semiconductor device according to any one of (2) to (9), wherein the semiconductor device includes an insulating material provided so as to fill the gaps between the wiring patterns of the upper wiring layer, and the tip portion of the second wiring pattern has a rectangular shape with the pair of side surfaces and tip surface in contact with the insulating material. (11) The semiconductor device according to any one of (1) to (10), further comprising a lower wiring layer provided on the opposite side of the upper wiring layer with the MIM structure interposed therebetween, the upper wiring layer including a third wiring pattern, and the semiconductor device further comprising another via connecting the third wiring pattern of the upper wiring layer and the lower wiring layer. (12) The semiconductor device according to (11), further comprising a metal material formed after dry etching to obtain the overall shapes of the other via, the via, and the wiring pattern of the upper wiring layer. (13) An imaging device comprising: an MIM structure including a lower electrode and an upper electrode; an upper wiring layer; and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes: a first wiring pattern extending so as not to cover the via; and a second wiring pattern having a width narrower than that of the first wiring pattern and extending to protrude from the first wiring pattern so as to cover the via, wherein the via connects the upper electrode and the second wiring pattern.

[0076] REFERENCE SIGNS LIST 1 semiconductor device (imaging device) 2 lower wiring layer 21 wiring pattern 22 wiring pattern 3 MIM layer 30 MIM structure 30s step portion 300 trench portion 31 lower electrode 32 dielectric 33 upper electrode 34 film 35 film 36 film 4 upper wiring layer 41 wiring pattern (first wiring pattern) 41r void portion 42 wiring pattern (second wiring pattern) 42r void portion 421 extension portion 421r void portion 422 tip portion 422a side surface 422b side surface 422c tip surface 422r void portion 43 wiring pattern (third wiring pattern) 43r void portion 5 via 5a side surface 5b side surface 5c side surface 5d side surface 5r void portion 6 Via (another via) 6r Void 61 Via 61r Void 62 Via 62r Void 7 Insulating material 8 Wiring layer 81 Wiring pattern 82 Wiring pattern 83 Wiring pattern 100 Semiconductor chip 200 Semiconductor chip

Claims

1. A semiconductor device comprising: an MIM structure including a lower electrode and an upper electrode; an upper wiring layer; and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes: a first wiring pattern extending so as not to cover the via; and a second wiring pattern extending and protruding from the first wiring pattern with a width narrower than that of the first wiring pattern so as to cover the via, and the via connects the upper electrode and the second wiring pattern.

2. The semiconductor device according to claim 1, wherein the second wiring pattern includes an end portion covering the via, and the via connects the upper electrode and the end portion of the second wiring pattern.

3. The semiconductor device according to claim 2, wherein the second wiring pattern includes an extension portion connected between the first wiring pattern and the tip portion.

4. The semiconductor device according to claim 2, wherein, in a plan view, a tip surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via.

5. The semiconductor device described in claim 4, wherein the MIM structure includes a step portion at its edge where the lower electrode extends further out than the upper electrode, and when viewed in a plane, the tip face of the tip portion of the second wiring pattern is adjacent to the side of the via facing the step portion.

6. The semiconductor device according to claim 2, wherein, in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via.

7. The semiconductor device according to claim 6, wherein the MIM structure includes a trench portion, and when viewed in a plane, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via facing the trench portion.

8. The semiconductor device described in claim 6, wherein the MIM structure includes a step portion at its edge where the lower electrode extends further out than the upper electrode, and when viewed in a plane, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via facing the step portion.

9. The semiconductor device described in claim 6, wherein the MIM structure includes a step portion at its edge where the lower electrode extends further out than the upper electrode, the MIM structure includes a trench portion, the side surfaces of the tip portion of the second wiring pattern are a pair of side surfaces, one of the pair of side surfaces is adjacent to the side of the via facing the trench portion, and the other of the pair of side surfaces is adjacent to the side of the via facing the step portion.

10. The semiconductor device according to claim 2, further comprising an insulating material provided so as to fill the spaces between the wiring patterns of the upper wiring layer, and the tip portion of the second wiring pattern has a rectangular shape with a pair of side surfaces and a tip surface in contact with the insulating material.

11. The semiconductor device according to claim 1, further comprising a lower wiring layer disposed on the opposite side of the upper wiring layer across the MIM structure, the upper wiring layer including a third wiring pattern, and the semiconductor device further comprising another via connecting the third wiring pattern of the upper wiring layer and the lower wiring layer.

12. The semiconductor device according to claim 11, wherein the another via, the via, and the wiring pattern of the upper wiring layer are formed by providing a metal material after performing dry etching to obtain their overall shapes.

13. An imaging device comprising: an MIM structure including a lower electrode and an upper electrode; an upper wiring layer; and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes: a first wiring pattern extending so as not to cover the via; and a second wiring pattern extending and protruding from the first wiring pattern with a width narrower than that of the first wiring pattern so as to cover the via, and the via connects the upper electrode and the second wiring pattern.

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