Semiconductor structure and forming method therefor, and memory

Abstract

Disclosed in embodiments of the present application are a semiconductor structure, a forming method for a semiconductor structure, and a memory. The forming method comprises: providing an initial stack structure (101), the initial stack structure (101) comprising first sacrificial layers (102) and second sacrificial layers (103) which are alternately stacked; forming a plurality of first trenches (104) penetrating through the initial stack structure (101); performing lateral etching along the first trenches (104) so as to remove a first portion of each first sacrificial layer (102) to form a plurality of first filling areas (106); forming a dielectric layer (107) in each first filling area (106); removing the second sacrificial layers (103) to form a plurality of second filling areas, and forming a bit line layer (108) in each second filling area; and removing a retained second portion of each first sacrificial layer (102) to form a plurality of cavities (110).

Description

Semiconductor structure and forming method thereof, and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202310889740.4, application date July 19, 2023, and invention name “Semiconductor structure and formation method thereof, memory”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0004] The integration level of two-dimensional semiconductor memory devices is primarily determined by the area occupied by the memory cells, and is therefore significantly influenced by the level of fine patterning technology. To overcome this limitation, three-dimensional semiconductor memory devices have recently been proposed, including memory cells arranged in three dimensions.

[0005] However, conventional three-dimensional semiconductor memory devices and their formation methods still have certain defects. How to further improve the performance of three-dimensional semiconductor memory devices has become an urgent problem that needs to be solved.

[0006] Summary of the Invention

[0007] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and a memory.

[0008] According to a first aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0009] Providing an initial stacking structure, the initial stacking structure comprising first sacrificial layers and second sacrificial layers stacked alternately;

[0010] forming a plurality of first trenches penetrating the initial stacked structure;

[0011] Laterally etching along the first trench to remove a first portion of each first sacrificial layer to form a plurality of first filling regions;

[0012] forming a dielectric layer in each of the first filling regions;

[0013] removing the second sacrificial layer to form a plurality of second filling regions, and forming a bit line layer in each of the second filling regions;

[0014] The remaining second portion of each first sacrificial layer is removed to form a plurality of cavities.

[0015] In the above scheme, multiple first grooves are arranged along the first direction, the distance between the side wall of the first groove parallel to the first direction and the edge of the initial stacking structure along the second direction is H1, the distance between two adjacent first grooves along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure.

[0016] In the above solution, the second sacrificial layer is removed to form a plurality of second filling regions, and a bit line layer is formed in each of the second filling regions, including:

[0017] Laterally etching along the first trench to remove a third portion of each second sacrificial layer to form a plurality of third filling regions;

[0018] A conductive material is filled in each of the third filling regions; the conductive material is filled between the fourth portions of each of the retained second sacrificial layers;

[0019] removing the fourth portion to form a plurality of fourth filling areas;

[0020] Each of the fourth filling regions is filled with the conductive material; and the conductive materials in the third filling region and the fourth filling region constitute the bit line layer.

[0021] In the above solution, after the dielectric layer is formed in each of the first filling regions, the dielectric layer is filled between the second portions of each of the retained first sacrificial layers;

[0022] The removing of the fourth part and the removing of the second part comprises:

[0023] After each of the third filling regions is filled with a conductive material, a second trench is formed penetrating the initial stacked structure; the second trench exposes a sidewall of the fourth portion and a sidewall of the second portion;

[0024] performing lateral etching along the second trench to remove the fourth portion;

[0025] Performing side etching along the second trench to remove the second portion.

[0026] In the above solution, the method further includes:

[0027] Before performing lateral etching along the first trench to remove the first portion of each first sacrificial layer, filling at least a portion of the first trench with a third sacrificial layer;

[0028] After a dielectric layer is formed in each of the first filling regions, the third sacrificial layer is removed to form a fourth trench, where the fourth trench exposes a sidewall of the second portion.

[0029] In the above solution, the second sacrificial layer is removed to form a plurality of second filling regions, and a bit line layer is formed in each of the second filling regions, including:

[0030] Filling the first trench with a fourth sacrificial layer, and laterally etching along the fourth trench to remove a fifth portion of each second sacrificial layer to form a plurality of fifth filling regions;

[0031] Filling each of the fifth filling regions with a conductive material;

[0032] removing the fourth sacrificial layer, and removing the sixth portion of each retained second sacrificial layer along the first trench to form a plurality of sixth filling regions;

[0033] Each of the sixth filling regions is filled with the conductive material; and the conductive materials in the fifth filling region and the sixth filling region constitute the bit line layer.

[0034] In the above solution, the plurality of first grooves are arranged along a first direction, and the method further includes:

[0035] After a dielectric layer is formed in each of the first filling regions, a third trench is formed between two adjacent first trenches, the third trench penetrating the initial stacking structure and exposing the sidewall of the second portion; a distance between the third trench and the adjacent first trench along the first direction is H3, a distance between the sidewall of the third trench or the first trench parallel to the first direction and the edge of the initial stacking structure along the second direction is H1, and a ratio of H3 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure.

[0036] In the above solution, the second sacrificial layer is removed to form a plurality of second filling regions, and a bit line layer is formed in each of the second filling regions, including:

[0037] Laterally etching along the third trench to remove a seventh portion of each second sacrificial layer to form a plurality of seventh filling regions;

[0038] Filling each of the seventh filling regions with a conductive material;

[0039] performing lateral etching along the first trench to remove an eighth portion of the retained second sacrificial layer to form a plurality of eighth filling regions;

[0040] The conductive material is filled in each of the eighth filling regions; the conductive materials in the seventh filling region and the eighth filling region constitute the bit line layer;

[0041] The removing of the retained second portion of each first sacrificial layer includes: performing lateral etching along the third trench to remove the retained second portion of each first sacrificial layer.

[0042] According to a second aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0043] A stacked structure comprising alternately stacked bit line layers and dielectric layers;

[0044] Wherein, the stack structure includes a plurality of first grooves penetrating the stack structure;

[0045] The bit line layer comprises a plurality of first bit line portions located on both sides of the first trench along a first direction and a second bit line portion located on one side of the plurality of first bit line portions along a second direction, wherein the second bit line portion extends along the first direction;

[0046] There is a cavity in the dielectric layer between adjacent first trenches.

[0047] In the above scheme, multiple first grooves are arranged along the first direction, the width of the second bit line portion along the second direction is H1, the width of the first bit line portion along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacking structure.

[0048] In the above scheme, the ratio of H2 to H1 ranges from 3 to 6.

[0049] In the above solution, the cavity is located between the first bit line portions adjacent to each other along the stacking direction, and a dielectric layer is provided between the cavity and two first trenches adjacent to each other along the first direction.

[0050] In the above scheme, the ratio of H2 to H1 is greater than 6, and the stacking structure also includes a third groove running through the stacking structure. The third groove is located between two adjacent first grooves, and the distance between the third groove and the adjacent first groove along the first direction is H3. The ratio of H3 to H1 is in the range of 3-6.

[0051] In the above scheme, the cavity is located between the first bit line portions adjacent to each other along the stacking direction and between the second bit line portions adjacent to each other along the stacking direction, and the cavity is located on both sides of the third groove along the first direction and on one side along the second direction. There is a dielectric layer between the first groove and the cavity, and the third groove is connected to the cavity.

[0052] According to a third aspect of the present disclosure, a memory is provided, comprising the semiconductor structure as described in any of the above solutions.

[0053] In an embodiment of the present disclosure, a first groove penetrating the initial stacking structure is formed in the initial stacking structure, a first portion of the first sacrificial layer is removed by lateral etching along the first groove, a dielectric layer is filled in the area where the first portion of the first sacrificial layer is removed, and after the second sacrificial layer is removed and a bit line layer is formed, the second portion of the first sacrificial layer is removed, thereby forming a cavity between two bit line layers adjacent along the stacking direction of the initial stacking structure. This can reduce the coupling effect between the two bit line layers adjacent along the stacking direction of the initial stacking structure, and can reduce the parasitic capacitance between the two bit line layers adjacent along the stacking direction of the initial stacking structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0055] 2 to 33 are schematic structural diagrams of a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure;

[0056] FIG34 is a first structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0057] FIG35 is a second structural schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] To make the technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0060] It will be understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0061] Furthermore, for ease of description, spatially relative terms such as "on," "over," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0062] In the embodiments of the present disclosure, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, silicon carbide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0063] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0064] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0065] The semiconductor structure involved in the embodiments of the present disclosure is at least a portion of a final device structure that will be used in subsequent manufacturing processes. The final device may include a memory, including but not limited to a dynamic random access memory (DRAM). The following description uses DRAM as an example.

[0066] In the currently proposed architecture of three-dimensional dynamic random access memory, horizontal bit lines and vertical word lines are the mainstream development direction due to their easier integration. However, due to the increasing demand for memory density, the distance between bit lines in the horizontal bit line architecture of three-dimensional dynamic random access memory is getting smaller and smaller. This leads to coupling effects between adjacent bit lines and the formation of parasitic capacitance. In addition, to ensure that the bit lines have low resistance, low-resistance materials such as metal are generally selected as the bit line materials. However, this exacerbates the coupling effects and parasitic capacitance problems between bit lines, seriously affecting the reliability of the memory. How to improve the coupling effects and reduce the parasitic capacitance between adjacent bit lines has become an urgent problem to be solved.

[0067] Based on the above problems, the present disclosure provides a method for forming a semiconductor structure. FIG1 is a flow chart of the method for forming a semiconductor structure provided by the present disclosure. As shown in FIG1 , the method for forming a semiconductor structure provided by the present disclosure includes the following steps:

[0068] S1100: Providing an initial stacking structure, the initial stacking structure comprising first sacrificial layers and second sacrificial layers alternately stacked;

[0069] S1200: forming a plurality of first trenches penetrating the initial stacked structure;

[0070] S1300: performing lateral etching along the first trench to remove a first portion of each first sacrificial layer to form a plurality of first filling regions;

[0071] S1400: forming a dielectric layer in each first filling region;

[0072] S1500: removing the second sacrificial layer to form a plurality of second filling regions, and forming a bit line layer in each of the second filling regions;

[0073] S1600: removing the second portion of each retained first sacrificial layer to form a plurality of cavities.

[0074] It should be understood that the steps shown in FIG1 are not exclusive, and other steps may be performed before, after or between any steps in the shown operation; the steps shown in FIG1 may be adjusted in order according to actual needs.

[0075] 2 to 33 are schematic diagrams of the process of forming a semiconductor structure according to an embodiment of the present disclosure. The method of forming a semiconductor structure according to an embodiment of the present disclosure will be described in detail below with reference to FIG1 and FIG2 to 33.

[0076] 2 , step S1100 is performed to provide an initial stacking structure 101 . The initial stacking structure 101 includes first sacrificial layers 102 and second sacrificial layers 103 that are alternately stacked.

[0077] It should be noted that the number of the first sacrificial layer 102 and the second sacrificial layer 103 shown in FIG. 2 is only an example, and the present disclosure does not limit the specific number of the first sacrificial layer 102 and the second sacrificial layer 103 in the initial stacking structure 101 .

[0078] In some specific examples, the first sacrificial layer 102 and the second sacrificial layer 103 can be formed by a deposition process or an epitaxy (EPI) process. First, a first sacrificial layer 102 is formed on a substrate (not shown in Figure 2), and then a second sacrificial layer 103 is formed on the first sacrificial layer 102. The process is repeated to form an initial stacking structure 101 in which the first sacrificial layer 102 and the second sacrificial layer 103 are alternately stacked.

[0079] It should be noted that the selection of materials for the first sacrificial layer 102 and the second sacrificial layer 103 must take into consideration how to minimize the impact on the second sacrificial layer 103 during the subsequent lateral removal of the first sacrificial layer 102, and how to minimize the impact on the first sacrificial layer 102 during the lateral removal of the second sacrificial layer 103. In some specific examples, the material of the first sacrificial layer 102 can be silicon germanium, and the material of the second sacrificial layer 103 can be silicon.

[0080] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0081] In some specific examples, as shown in FIG2 , the method further includes: forming a mask layer 133 on the initial stacked structure 101 . The mask layer 133 may be a composite layer or a single layer. Exemplarily, the mask layer 133 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0082] 3 , step S1200 is performed to form a plurality of first trenches 104 penetrating the initial stacked structure 101 .

[0083] In some specific examples, the method of forming the first trench 104 includes but is not limited to dry etching. Here, the dry etching process can be an etching process with good directionality, such as plasma etching, sputtering etching, ion beam etching, reactive ion etching, etc.

[0084] In the embodiment of the present disclosure, as shown in Figure 3, multiple first grooves 104 are arranged along the first direction, the distance between the side walls of the first grooves 104 parallel to the first direction and the edge of the initial stacking structure 101 along the second direction is H1, and the distance between two adjacent first grooves 104 along the first direction is H2. The first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure 101.

[0085] In the embodiment of the present disclosure, the first direction is the X direction, the second direction is the Y direction, and the stacking direction of the initial stacking structure 101 is the Z direction.

[0086] Here, the disclosed embodiments provide various scenarios for the corresponding relationship between H2 and H1, and the corresponding methods for forming the bit line layer, dielectric layer, and cavity are also different. The disclosed embodiments provide three solutions. The following will first describe Solution 1 in detail, taking the case where the ratio of H2 to H1 is greater than 2 and less than 6 as an example.

[0087] 4 , step S1300 is performed to perform lateral etching along the first trench 104 to remove a first portion of each first sacrificial layer 102 to form a plurality of first filling regions 106 .

[0088] In some specific examples, a method of removing the first portion of each first sacrificial layer 102 includes, but is not limited to, a wet etching process.

[0089] 4 , the remaining first sacrificial layer 102 is the second portion 109 of the first sacrificial layer 102 . The remaining second portion 109 of each first sacrificial layer 102 is located between adjacent first trenches 104 .

[0090] It is understood that when the first sacrificial layer 102 is laterally etched along the first trench 104, the first sacrificial layer 102 between two adjacent first trenches 104 is etched simultaneously from both sides along the first direction. Therefore, both sides of the second portion 109 along the first direction are the first filling regions 106. In the embodiment of the present disclosure, the ratio of H2 to H1 is greater than 2 and less than 6. This allows the first sacrificial layer 102 on both sides of the first trench 104 along the second direction to be completely removed when the first sacrificial layer 102 is laterally etched along the first trench 104, while retaining the second portion 109 of the first sacrificial layer 102 between two adjacent first trenches 104 along the first direction. Here, the retained second portion 109 of the first sacrificial layer 102 is located between the two adjacent first trenches 104 along the first direction, and the retained second portion 109 of the first sacrificial layer 102 can serve as a support.

[0091] 5 and 6 , step S1400 is performed to form a dielectric layer 107 in each first filling region 106 .

[0092] In some specific examples, the material of the dielectric layer 107 may be a low dielectric constant material, which includes but is not limited to one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride.

[0093] It is understandable that the dielectric layer 107 in the embodiment of the present disclosure uses a low dielectric constant material to reduce the coupling effect and parasitic capacitance between two adjacent bit line layers formed subsequently along the stacking direction of the initial stacking structure 101 .

[0094] It should be noted that the selection of the material for the dielectric layer 107 should take into account the reduction of the impact on the dielectric layer 107 when the remaining first sacrificial layer 102 , the remaining second sacrificial layer 103 and part of the conductive material layer are removed in subsequent processes.

[0095] In some specific examples, a dielectric material layer 129 can be first deposited on the sidewalls and top of the first filling area 106 and the initial stacking structure 101, and then an etching process is used to remove the dielectric material layer 129 on the sidewalls and top of the initial stacking structure 101, retaining the dielectric material layer 129 located in the first filling area 106 to form a dielectric layer 107.

[0096] 7 to 13 , step S1500 is performed to remove the second sacrificial layer 103 to form a plurality of second filling regions, and a bit line layer 108 is formed in each of the second filling regions.

[0097] In some embodiments, as shown in Figures 7 to 13, the second sacrificial layer 103 is removed to form multiple second filling areas, and a bit line layer 108 is formed in each second filling area, including: side etching along the first trench 104 to remove the third portion of each second sacrificial layer 103 to form multiple third filling areas 112; filling each third filling area 112 with a conductive material layer 113; filling the conductive material layer 113 between the retained fourth portions 114 of each second sacrificial layer 103; removing the fourth portions 114 to form multiple fourth filling areas 115; filling each fourth filling area 115 with a conductive material layer 113; the conductive material layer 113 in the third filling area 112 and the fourth filling area 115 constitute the bit line layer 108.

[0098] It is understood that the second sacrificial layer 103 in the embodiment of the present disclosure is removed in two steps. First, the third portion of each second sacrificial layer is removed to form a third filling region 112, which is then filled with a conductive material layer 113. Then, the fourth portion 114 of the second sacrificial layer 103 is removed to form a fourth filling region 115, which is then filled with a conductive material layer 113. When the third portion is removed, the fourth portion 114 can serve as a support, and when the fourth portion 114 is removed, the conductive material layer 113 filled in the third filling region 112 can serve as a support.

[0099] In some specific examples, the material of the conductive material layer 113 includes but is not limited to metal tungsten. The method of forming the conductive material layer includes but is not limited to a deposition process.

[0100] It is understandable that the use of tungsten as the material of the bit line layer 108 in the embodiment of the present disclosure can reduce the bit line resistance and improve the performance of the memory.

[0101] In some specific examples, as shown in Figures 8 and 9, after forming multiple third filling regions 112, a conductive material layer 113 can be first deposited on the side walls and top of the third filling regions 112 and the initial stacking structure 101, and then an etching process is used to remove the conductive material layer 113 on the side walls and top of the initial stacking structure 101 along the stacking direction of the initial stacking structure 101, retaining the conductive material layer 113 located in the third filling region 112.

[0102] It should be noted that, in order to more clearly illustrate the initial stacking structure 101 between adjacent first trenches 104 , FIG. 2 to FIG. 9 are only partial views. For example, FIG. 9 is a three-dimensional view of the upper half of FIG. 10 cut along the AA′ direction.

[0103] In some embodiments, as shown in Figures 9 to 12, after the dielectric layer 107 is formed in each first filling area 106, the dielectric layer 107 is filled between the second parts 109 of each retained first sacrificial layer 102; the fourth part 114 is removed, and the second part 109 is removed, including: after the conductive material layer 113 is filled in each third filling area 112, a second trench 116 is formed that penetrates the initial stacking structure 101; the second trench 116 exposes the sidewalls of the fourth part 114 and the sidewalls of the second part 109; the second trench 116 is laterally etched to remove the fourth part 114; and the second trench 116 is laterally etched to remove the second part 109.

[0104] In some specific examples, as shown in FIG. 11 , the second trench 116 extends along the first direction and communicates with the first trench 104 .

[0105] In some specific examples, the method of removing the fourth portion 114 includes, but is not limited to, a wet etching process.

[0106] It is understandable that, because both sidewalls of the second portion 109 of the first sacrificial layer 102 along the first direction are covered by the dielectric layer 107, and both sidewalls of the fourth portion 114 of the second sacrificial layer 103 along the first direction are covered by the conductive material layer 113, the first trench 104 does not expose the second portion 109 of the first sacrificial layer 102, nor does the first trench 104 expose the fourth portion 114 of the second sacrificial layer 103. Therefore, the second portion 109 and the fourth portion 114 cannot be removed through the first trench 104. In the embodiment of the present disclosure, by forming a second trench 116 penetrating the initial stacked structure 101, and exposing the sidewalls of the fourth portion 114 and the sidewalls of the second portion 109, the second portion 109 and the fourth portion 114 can be removed from the second trench 116.

[0107] 14 , step S1600 is performed to remove the remaining second portion 109 of each first sacrificial layer 102 to form a plurality of cavities 110 .

[0108] In some specific examples, the method of removing the second portion 109 includes, but is not limited to, wet etching.

[0109] In some specific examples, the method further includes: removing the mask layer 133 after forming the cavity 110 .

[0110] It can be understood that in the embodiment of the present disclosure, multiple cavities 110 are formed between two bit line layers 108 adjacent along the stacking direction of the initial stacking structure 101, so that the coupling effect of the two bit line layers adjacent along the stacking direction of the initial stacking structure 101 can be reduced, and the parasitic capacitance of the two bit line layers adjacent along the stacking direction of the initial stacking structure 101 can be reduced, thereby improving the performance of the memory.

[0111] When the ratio of H2 to H1 is greater than 2 and less than 6, the embodiment of the present disclosure further provides the following method for forming the bit line layer 108, the dielectric layer 107, and the cavity 110. The second solution will be described in detail below with reference to FIG.

[0112] In some embodiments, as shown in Figures 15 to 18, the method further includes: before laterally etching along the first trench 104 to remove the first portion of each first sacrificial layer 102, filling a third sacrificial layer 117 in at least a portion of the first trench 104; after forming a dielectric layer 107 in each first filling area 106, removing the third sacrificial layer 117 to form a fourth trench 118, and the fourth trench 118 exposing the sidewall of the second portion 109.

[0113] It should be noted that FIG. 15 merely exemplarily shows the case where the third sacrificial layer 117 is filled in one first trench 104 . The third sacrificial layer 117 may also be filled in a plurality of first trenches 104 continuous along the first direction.

[0114] It can be understood that in the above embodiment, the third sacrificial layer 117 is first filled in part of the first groove 104, and the first groove 104 not filled with the third sacrificial layer 117 is used to remove part of the first sacrificial layer 102, and then the third sacrificial layer is removed and the second part 109 of the first sacrificial layer 102 is removed using the fourth groove.

[0115] In some embodiments, as shown in Figures 19 to 23, the second sacrificial layer 103 is removed to form multiple second filling areas, and a bit line layer 108 is formed in each second filling area, including: filling a fourth sacrificial layer 119 in the first trench 104, and laterally etching along the fourth trench 118 to remove the fifth portion of each second sacrificial layer 103 to form multiple fifth filling areas 123; filling each fifth filling area 123 with a conductive material layer 113; removing the fourth sacrificial layer 119, and removing the retained sixth portion 120 of each second sacrificial layer 103 along the first trench 104 to form multiple sixth filling areas 121; filling each sixth filling area 121 with a conductive material layer 113; the fifth filling area 123 and the conductive material layer 113 in the sixth filling area 121 constitute the bit line layer 108.

[0116] As shown in FIG24 , the method further includes removing the remaining second portion 109 of each first sacrificial layer 102 to form a plurality of cavities 110 , wherein the cavities are connected to the fourth trench 118 .

[0117] In some specific examples, the method further includes: removing the mask layer 133 after forming the cavity 110 .

[0118] The ratio of H2 to H1 may also be greater than 6. The process of forming the bit line layer 108, the dielectric layer 107 and the cavity 110 in scheme three when the ratio of H2 to H1 is greater than 6 will be specifically described below with reference to Figures 25 to 33.

[0119] In some embodiments, as shown in Figures 25 to 28, multiple first trenches 104 are arranged along the first direction, and the method further includes: after forming a dielectric layer 107 in each first filling area 106, forming a third trench 124 between two adjacent first trenches 104, the third trench 124 passes through the initial stacking structure 101 and exposes the side wall of the second portion 109; the distance between the third trench 124 and the adjacent first trench 104 along the first direction is H3, and the distance between the side wall of the third trench 124 or the first trench 104 parallel to the first direction and the edge of the initial stacking structure 101 along the second direction is H1, and the ratio of H3 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure 101.

[0120] Here, after the third trench 124 is formed, the ratio of H3 to H1 is greater than 2 and less than 6.

[0121] It can be understood that compared with Scheme 1, when the ratio of H2 to H1 is greater than 6, in Scheme 3, after the first portion of the first sacrificial layer 102 is removed using the first trench 104, a larger amount of the first sacrificial layer 102 is retained between the two adjacent first trenches 104. After the dielectric layer 107 is formed in the first filling area 106, a third trench 124 is formed between the two adjacent first trenches 104. The third trench 124 exposes the sidewall of the second portion 109, so that the second portion 109 can be removed along the third trench 124 in the subsequent process.

[0122] In some embodiments, as shown in FIG29 to FIG32 , the second sacrificial layer 103 is removed to form a plurality of second filling regions, and a bit line layer 108 is formed in each of the second filling regions. The method includes: performing side etching along the third trench 124 to remove the seventh portion of each second sacrificial layer 103 to form a plurality of seventh filling regions 126; filling each of the seventh filling regions 126 with a conductive material layer 113; performing side etching along the first trench 104 to remove the eighth portion 127 of the remaining second sacrificial layer 103 to form a plurality of eighth filling regions 128; and filling each of the eighth filling regions 128 with a conductive material layer 113. The conductive material layers 113 in the seventh filling regions 126 and the eighth filling regions 128 constitute the bit line layer 108.

[0123] In some specific examples, when laterally etching along the third trench 124 to remove the seventh portion of each second sacrificial layer 103, a fifth sacrificial layer may be formed in the first trench 104, so that when laterally etching along the third trench 124, the first sacrificial layer 102 cannot be laterally etched along the first trench 104. After each seventh filling region 126 is filled with the conductive material layer 113, the fifth sacrificial layer in the first trench 104 is removed.

[0124] In some embodiments, as shown in FIG. 33 , removing the retained second portion 109 of each first sacrificial layer 102 includes: laterally etching along the third trench 124 to remove the retained second portion 109 of each first sacrificial layer 102 .

[0125] In an embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: providing an initial stacking structure 101, the initial stacking structure 101 comprising alternatingly stacked first sacrificial layers 102 and second sacrificial layers 103; forming a plurality of first trenches 104 penetrating the initial stacking structure 101; laterally etching along the first trenches 104 to remove a first portion of each first sacrificial layer 102 to form a plurality of first filling regions 106; forming a dielectric layer 107 in each first filling region 106; removing the second sacrificial layer 103 to form a plurality of second filling regions, and forming a bit line layer 108 in each second filling region; and removing the retained second portion 109 of each first sacrificial layer 102 to form a plurality of cavities 110. In the embodiment of the present disclosure, a first groove 104 is formed in the initial stacking structure 101, penetrating the initial stacking structure 101, and a first portion of the first sacrificial layer 102 is removed by lateral etching along the first groove 104. A dielectric layer 107 is filled in the area where the first portion of the first sacrificial layer 102 is removed. After the second sacrificial layer 103 is removed and the bit line layer 108 is formed, the second portion 109 of the first sacrificial layer 102 is removed, thereby forming a cavity 110 between two bit line layers 108 adjacent to each other along the stacking direction of the initial stacking structure 101. This can reduce the coupling effect between the two bit line layers 108 adjacent to each other along the stacking direction of the initial stacking structure 101, and can reduce the parasitic capacitance between the two bit line layers 108 adjacent to each other along the stacking direction of the initial stacking structure 101, thereby improving the performance of the semiconductor structure.

[0126] Based on the same technical concept as the aforementioned method for forming a semiconductor structure, embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure shown in FIG34 corresponds to solution 1 of the aforementioned method for forming a semiconductor structure, and the semiconductor structure shown in FIG35 corresponds to solutions 2 and 3 of the aforementioned method for forming a semiconductor structure.

[0127] As shown in Figures 34 and 35, the semiconductor structure includes: a stacked structure 130, including alternatingly stacked bit line layers 108 and dielectric layers 107; wherein the stacked structure 130 includes a plurality of first trenches 104 penetrating the stacked structure 130; the bit line layer 108 has a plurality of first bit line portions 131 located on both sides of the first trenches 104 along the first direction and a second bit line portion 132 located on one side of the plurality of first bit line portions 131 along the second direction, and the second bit line portion 132 extends along the first direction; and a cavity 110 is provided in the dielectric layer 107 between adjacent first trenches 104.

[0128] It can be understood that in the embodiment of the present disclosure, there is a cavity 110 between two bit line layers 108 adjacent along the stacking direction of the stacking structure 130, so that the coupling effect between the two bit line layers 108 adjacent along the stacking direction of the stacking structure 130 can be reduced, and the parasitic capacitance generated between the two bit line layers 108 adjacent along the stacking direction of the stacking structure 130 can be reduced, thereby effectively improving the performance of the memory.

[0129] In some specific examples, the material of the bit line layer 108 includes, but is not limited to, metal tungsten.

[0130] It is understandable that the use of tungsten as the material of the bit line layer 108 in the embodiment of the present disclosure can reduce the bit line resistance and improve the performance of the memory.

[0131] In some specific examples, the material of dielectric layer 107 can be a low-k material, including but not limited to one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. It will be appreciated that using a low-k material for dielectric layer 107 in the disclosed embodiments can further reduce the coupling effect and parasitic capacitance between two adjacent bit line layers 108 along the stacking direction of stack structure 130.

[0132] In some embodiments, as shown in Figure 34, multiple first grooves 104 are arranged along the first direction, the width of the second bit line portion 132 along the second direction is H1, the width of the first bit line portion 131 along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacking structure 130.

[0133] In some embodiments, the ratio of H2 to H1 ranges from 3-6.

[0134] In some embodiments, as shown in FIG. 34 , the cavity 110 is located between the first bit line portions 131 adjacent to each other along the stacking direction, and a dielectric layer 107 is provided between the cavity 110 and two first trenches 104 adjacent to each other along the first direction.

[0135] In some embodiments, as shown in Figure 35, the ratio of H2 to H1 is greater than 6, and the stacking structure 130 also includes a third groove 124 that penetrates the stacking structure 130. The third groove 124 is located between two adjacent first grooves 104. The distance between the third groove 124 and the adjacent first groove 104 along the first direction is H3, and the ratio of H3 to H1 is in the range of 3-6.

[0136] In some embodiments, the cavity 110 is located between the first bit line portions 131 adjacent to each other along the stacking direction and between the second bit line portions 132 adjacent to each other along the stacking direction, and the cavity 110 is located on both sides of the third trench 124 along the first direction and on one side along the second direction, a dielectric layer 107 is provided between the first trench 104 and the cavity 110, and the third trench 124 is connected to the cavity 110.

[0137] Based on the above semiconductor structure, an embodiment of the present disclosure further provides a memory, comprising the semiconductor structure of any one of the above embodiments.

[0138] In some specific examples, the memory includes but is not limited to dynamic random access memory, static random access memory (SRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM) and flash memory.

[0139] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not implemented. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0140] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0141] The present disclosure is not limited to the specific embodiments of the present disclosure. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. Industrial Applicability

[0142] In an embodiment of the present disclosure, a first groove penetrating the initial stacking structure is formed in the initial stacking structure, a first portion of the first sacrificial layer is removed by lateral etching along the first groove, a dielectric layer is filled in the area where the first portion of the first sacrificial layer is removed, and after the second sacrificial layer is removed and a bit line layer is formed, the second portion of the first sacrificial layer is removed, thereby forming a cavity between two bit line layers adjacent along the stacking direction of the initial stacking structure. This can reduce the coupling effect between the two bit line layers adjacent along the stacking direction of the initial stacking structure, and can reduce the parasitic capacitance between the two bit line layers adjacent along the stacking direction of the initial stacking structure, thereby improving the performance of the semiconductor structure.

Claims

1. A method for forming a semiconductor structure, comprising: Providing an initial stacking structure (101), wherein the initial stacking structure (101) comprises a first sacrificial layer (102) and a second sacrificial layer (103) which are alternately stacked; forming a plurality of first grooves (104) penetrating the initial stacking structure (101); Laterally etching along the first trench (104) to remove a first portion of each first sacrificial layer (102) to form a plurality of first filling regions (106); forming a dielectric layer (107) in each of the first filling regions (106); removing the second sacrificial layer (103) to form a plurality of second filling regions, and forming a bit line layer (108) in each of the second filling regions; The second portion (109) of each of the first sacrificial layers (102) that remains is removed to form a plurality of cavities (110).

2. The forming method according to claim 1, wherein: A plurality of first grooves (104) are arranged along a first direction (X); a distance between a side wall of the first groove (104) parallel to the first direction (X) and an edge of the initial stacking structure (101) along a second direction (Y) is H1; a distance between two adjacent first grooves (104) along the first direction (X) is H2, and a ratio of H2 to H1 is greater than 2; the first direction (X) is perpendicular to the second direction (Y) and both are perpendicular to a stacking direction (Z) of the initial stacking structure (101).

3. The forming method according to claim 1 or 2, wherein: The step of removing the second sacrificial layer (103) to form a plurality of second filling regions, and forming a bit line layer (108) in each of the second filling regions, comprises: Laterally etching along the first trench (104) to remove a third portion of each second sacrificial layer (103) to form a plurality of third filling regions (112); Filling each of the third filling regions (112) with a conductive material; the conductive material is filled between the fourth portions (114) of each of the retained second sacrificial layers (103); removing the fourth portion (114) to form a plurality of fourth filling regions (115); The conductive material is filled in each of the fourth filling regions (115); and the conductive material in the third filling region (112) and the fourth filling region (115) constitutes the bit line layer (108).

4. The forming method according to claim 3, wherein: After a dielectric layer (107) is formed in each of the first filling regions (106), the dielectric layer (107) is filled between the second portions (109) of each of the retained first sacrificial layers (102); The removing of the fourth portion (114) and the removing of the second portion (109) comprises: After each of the third filling regions (112) is filled with a conductive material, a second trench (116) is formed that penetrates the initial stacked structure (101); the second trench (116) exposes the sidewall of the fourth portion (114) and the sidewall of the second portion (109); performing lateral etching along the second groove (116) to remove the fourth portion (114); The second portion (109) is removed by etching laterally along the second trench (116).

5. The forming method according to claim 1 or 2, wherein: The method further comprises: Before performing lateral etching along the first trench (104) to remove a first portion of each first sacrificial layer (102), filling at least a portion of the first trench (104) with a third sacrificial layer (117); After forming a dielectric layer (107) in each of the first filling regions (106), the third sacrificial layer (117) is removed to form a fourth trench (118), wherein the fourth trench (118) exposes the sidewall of the second portion (109).

6. The forming method according to claim 5, wherein: The step of removing the second sacrificial layer (103) to form a plurality of second filling regions, and forming a bit line layer (108) in each of the second filling regions, comprises: Filling a fourth sacrificial layer (119) in the first trench (104), and performing lateral etching along the fourth trench (118) to remove a fifth portion of each second sacrificial layer (103) to form a plurality of fifth filling regions (123); Filling each of the fifth filling regions (123) with a conductive material; removing the fourth sacrificial layer (119), and removing the sixth portion (120) of each retained second sacrificial layer (103) along the first trench (104) to form a plurality of sixth filling regions (121); The conductive material is filled in each of the sixth filling regions (121); and the conductive materials in the fifth filling region (123) and the sixth filling region (121) constitute the bit line layer (108).

7. The forming method according to claim 1, wherein: The plurality of first grooves (104) are arranged along a first direction (X), and the method further comprises: After a dielectric layer (107) is formed in each of the first filling regions (106), a third groove (124) is formed between two adjacent first grooves (104), wherein the third groove (124) penetrates the initial stacking structure (101) and exposes the side wall of the second portion (109); the distance between the third groove (124) and the adjacent first groove (104) along the first direction (X) is H3, the distance between the side wall of the third groove (124) or the first groove (104) parallel to the first direction (X) and the edge of the initial stacking structure (101) along the second direction (Y) is H1, and the ratio of H3 to H1 is greater than 2; the first direction (X) is perpendicular to the second direction (Y) and is perpendicular to the stacking direction (Z) of the initial stacking structure (101).

8. The forming method according to claim 7, wherein: The step of removing the second sacrificial layer (103) to form a plurality of second filling regions, and forming a bit line layer (108) in each of the second filling regions, comprises: Laterally etching along the third trench (124) to remove a seventh portion of each second sacrificial layer (103) to form a plurality of seventh filling regions (126); Filling each of the seventh filling regions (126) with a conductive material; Laterally etching along the first trench (104) to remove the eighth portion (127) of the retained second sacrificial layer (103) to form a plurality of eighth filling regions (128); The conductive material is filled in each of the eighth filling regions (128); the conductive material in the seventh filling region (126) and the eighth filling region (128) constitutes the bit line layer (108); The step of removing the second portion (109) of each of the first sacrificial layers (102) that is retained comprises: performing lateral etching along the third trench (124) to remove the second portion (109) of each of the first sacrificial layers (102) that is retained.

9. A semiconductor structure comprising: A stacked structure (130) comprising alternately stacked bit line layers (108) and dielectric layers (107); Wherein, the stacked structure (130) comprises a plurality of first grooves (104) penetrating the stacked structure (130); The bit line layer (108) comprises a plurality of first bit line portions (131) located on both sides of the first trench (104) along a first direction (X) and a second bit line portion (132) located on one side of the plurality of first bit line portions (131) along a second direction (Y), wherein the second bit line portion (132) extends along the first direction (X); A cavity (110) is provided in the dielectric layer (107) between adjacent first grooves (104).

10. The semiconductor structure according to claim 9, wherein: A plurality of the first grooves (104) are arranged along a first direction (X), a width of the second bit line portion (132) along the second direction (Y) is H1, a width of the first bit line portion (131) along the first direction (X) is H2, and a ratio of H2 to H1 is greater than 2; the first direction (X) is perpendicular to the second direction (Y) and both are perpendicular to the stacking direction (Z) of the stacking structure (130).

11. The semiconductor structure according to claim 10, wherein: The ratio of H2 to H1 ranges from 3-6.

12. The semiconductor structure according to any one of claims 9 to 11, wherein: The cavity (110) is located between the first bit line portions (131) adjacent to each other along the stacking direction (Z), and a dielectric layer (107) is provided between the cavity (110) and two first trenches (104) adjacent to each other along the first direction (X).

13. The semiconductor structure according to claim 10, wherein: The ratio of H2 to H1 ranges from 6, and the stacking structure (130) also includes a third groove (124) running through the stacking structure (130). The third groove (124) is located between two adjacent first grooves (104). The distance between the third groove (124) and the adjacent first groove (104) along the first direction (X) is H3, and the ratio of H3 to H1 ranges from 3 to 6.

14. The semiconductor structure according to claim 13, wherein: The cavity (110) is located between the first bit line portions (131) adjacent to each other along the stacking direction (Z) and between the second bit line portions (132) adjacent to each other along the stacking direction (Z), and the cavity (110) is located on both sides of the third groove (124) along the first direction (X) and on one side along the second direction (Y), a dielectric layer (107) is provided between the first groove (104) and the cavity (110), and the third groove (124) is connected to the cavity (110).

15. According to the semiconductor structure according to any one of claims 9 to 11, the stacked structure (130) comprises a second trench (116) penetrating the stacked structure (130), the second trench (116) extending along a first direction (X) and connected to the first trench (104).

16. The semiconductor structure according to any one of claims 9 to 11, wherein the material of the bit line layer (108) comprises tungsten.

17. The semiconductor structure according to any one of claims 9 to 11, wherein the material of the dielectric layer (107) comprises one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride or silicon oxynitride.

18. A memory comprising the semiconductor structure according to any one of claims 9 to 17.

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