Vertical bidirectional SCR low-capacitance TVS device

Abstract

The present application belongs to the fields of electronic components, semiconductors and integrated circuits. Disclosed is a vertical bidirectional SCR low-capacitance TVS device, comprising: a substrate (000), and a first epitaxial layer (001) located on the substrate (000), wherein on the first epitaxial layer (001), a first buried layer (012) and a second buried layer (112) are respectively arranged at two sides; a second epitaxial layer (002) is manufactured on both the first buried layer (012) and the second buried layer (112); a first deep trench (003), a second deep trench (004) and a third deep trench (005) are arranged from surfaces of the second epitaxial layers (002) to inside the first epitaxial layer (001); a first implantation region (011) and a second implantation region (111) are manufactured on the surface of the second epitaxial layer (002) between the first deep trench (003) and the second deep trench (004); a first implantation region (011) and a second implantation region (111) are manufactured on the surface of the second epitaxial layer (002) between the second deep trench (004) and the third deep trench (005); and each second implantation region (111) is located at the side close to the second deep trench.

Description

Vertical bidirectional SCR low capacitance TVS device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 14, 2023, with application number 202310862502.4, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of electronic components, semiconductors, and integrated circuits, and relates to a vertical bidirectional silicon controlled rectifier (Silicon Controlled Rectifier, SCR) low-capacitance silicon controlled rectifier (Transient Voltage Suppressor, TVS) device. Background Art

[0003] A bidirectional SCR is a silicon-controlled rectifier with symmetrical electrical characteristics. The device has a PNPN (Shockley diode) structure in both the anode-to-cathode and cathode-to-anode directions. As shown in Figure 1, vertical devices can only achieve a PNPN structure in one direction, so traditional vertical device processes cannot implement this structure. However, vertical devices have many advantages over lateral devices in terms of discharge efficiency, current uniformity, and capacitance. Because the current in the device flows evenly from top to bottom (or bottom to top), vertical devices can achieve the maximum surge current resistance with the smallest area. Therefore, vertical devices can achieve the minimum PN junction area under the same current performance, thereby minimizing capacitance. As high-speed communication interfaces place increasingly stringent requirements on the capacitance of TVSs and the surge resistance requirements become increasingly demanding, it has become difficult to further optimize traditional lateral devices.

[0004] Summary of the Invention

[0005] The present application discloses a vertical bidirectional SCR low-capacitance TVS device, which transforms the traditional lateral SCR into a vertical SCR, thereby significantly enhancing the comprehensive performance of the junction capacitance and surge resistance of the thyristor rectifier.

[0006] The main technical solutions adopted in this application are:

[0007] A vertical bidirectional SCR low-capacitance TVS device comprising:

[0008] substrate;

[0009] a first epitaxial layer located above the substrate;

[0010] A first buried layer and a second buried layer are respectively provided on both sides of the first epitaxial layer;

[0011] A second epitaxial layer is formed above the first buried layer and the second buried layer;

[0012] A first deep trench, a second deep trench, and a third deep trench are provided from the surface of the second epitaxial layer to the body of the first epitaxial layer, and the first deep trench and the third deep trench are respectively located at two side edges of the second epitaxial layer as boundaries of the device, the second deep trench is located in the middle of the second epitaxial layer to divide the second epitaxial layer into two halves, and the first buried layer and the second buried layer are respectively located on two sides of the second deep trench;

[0013] A first implantation region and a second implantation region are formed on the surface of the second epitaxial layer between the first deep trench and the second deep trench, and the first implantation region and the second implantation region are tangent to each other;

[0014] A first implantation region and a second implantation region are formed on the surface of the second epitaxial layer between the second deep trench and the third deep trench, and the first implantation region and the second implantation region are tangent to each other;

[0015] The second implantation region is located on a side close to the second deep trench;

[0016] The substrate, the first epitaxial layer, the second epitaxial layer and the first injection region have the same doping type, the first buried layer and the second buried layer have opposite doping types, the first injection region and the second injection region have opposite doping types, and the first buried layer and the first injection region have the same doping type.

[0017] Optionally, a dielectric layer is also included, which covers the first injection area, the second injection area, the first deep trench, the second deep trench and the third deep trench. Contact holes are opened on the dielectric layer corresponding to the first injection area and the second injection area. Each group of tangent first injection areas and second injection areas are short-circuited through the metal layer through the contact holes to form the electrode of the device.

[0018] Optionally, a passivation layer is further included, and the passivation layer is located above the dielectric layer. The passivation layer has a hole at the metal layer to form a pad.

[0019] Optionally, the first deep trench, the second deep trench and the third deep trench have the same internal structure, and all include a trench oxide layer and polysilicon, and the trench oxide layer covers both sides and the bottom of the polysilicon.

[0020] Optionally, the substrate is an N-type substrate, the first epitaxial layer is a first N-type epitaxial layer, the second epitaxial layer is a second N-type epitaxial layer, the first injection region is an N+ injection region, the first buried layer is an N-type buried layer, the second buried layer is a P-type buried layer, and the second injection region is a P+ injection region.

[0021] Optionally, the substrate is a P-type substrate, the first epitaxial layer is a first P-type epitaxial layer, the second epitaxial layer is a second P-type epitaxial layer, the first injection region is a P+ injection region, the first buried layer is a P-type buried layer, the second buried layer is an N-type buried layer, and the second injection region is an N+ injection region.

[0022] Optionally, the substrate is floated and is not connected to any potential.

[0023] A method for manufacturing a vertical bidirectional SCR low-capacitance TVS device, comprising:

[0024] S1: performing an epitaxial process on an N-type substrate to form a first epitaxial layer, and implanting a first buried layer and a second buried layer into the surface of the first epitaxial layer respectively;

[0025] S2: performing a secondary epitaxial growth process on the surface of the device obtained in step S1 to form a second epitaxial layer;

[0026] S3: forming a first deep trench, a second deep trench, and a third deep trench on the device obtained in step S2, and growing a trench oxide layer and filling polysilicon in each deep trench, and then performing chemical mechanical planarization (CMP) for planarization;

[0027] S4: implanting a first implantation region and a second implantation region into corresponding positions on the surface of the device prepared in step S3;

[0028] S5: depositing a dielectric layer on the surface of the device obtained in step S4, etching contact holes on the dielectric layer, and then depositing a metal layer on the dielectric layer and in the contact holes. After photolithography, a passivation layer is deposited on the metal layer and etched to form a pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a structural diagram of a traditional vertical unidirectional SCR device;

[0030] FIG2 is a structural diagram of a vertical bidirectional SCR device according to Example 1;

[0031] FIG3 is a schematic diagram of the on-current path of the vertical bidirectional SCR device of Example 1;

[0032] FIG4 is a schematic diagram of implanting the first buried layer and the second buried layer in the vertical bidirectional SCR device in Example 1;

[0033] FIG5 is a schematic diagram of forming a second epitaxial layer on a vertical bidirectional SCR device in Example 1;

[0034] FIG6 is a schematic diagram of growing a trench oxide layer and filling polysilicon in a deep trench of a vertical bidirectional SCR device in Example 1;

[0035] FIG7 is a schematic diagram of injecting the first injection region and the second injection region into the vertical bidirectional SCR device in Example 1;

[0036] FIG8 is a schematic diagram of depositing a dielectric layer and a metal layer in a vertical bidirectional SCR device in Example 1;

[0037] In the figure: substrate 000, first epitaxial layer 001, second epitaxial layer 002, first buried layer 012, second buried layer 112, first deep trench 003, second deep trench 004, third deep trench 005, trench oxide layer 20, polysilicon 21, first implantation region 011, second implantation region 111, dielectric layer 22, contact hole 30, metal layer 31, passivation layer 40. DETAILED DESCRIPTION

[0038] The present application may be implemented or applied through different specific implementation methods, and the details in this specification may be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0039] Embodiment 1, as shown in FIG2 , is a vertical bidirectional SCR low-capacitance TVS device based on an N-type substrate, comprising:

[0040] Substrate 000;

[0041] A first epitaxial layer 001 located above the substrate 000;

[0042] Above the first epitaxial layer 001, as shown in FIG2 , a first buried layer 012 is designed on the left side, and a second buried layer 112 is designed on the right side;

[0043] A second epitaxial layer 002 is formed above the first buried layer 012 and the second type buried layer 112;

[0044] As shown in FIG2 , a first deep trench 003, a second deep trench 004, and a third deep trench 005 are provided within the second epitaxial layer 002 from the surface thereof to the first epitaxial layer 001. The first deep trench 003 and the third deep trench 005 are located at the edges of the second epitaxial layer 002, serving as device boundaries. The second deep trench 004 is located in the middle of the second epitaxial layer 002, bisecting the second epitaxial layer 002. The first buried layer 012 and the second buried layer 112 are located on either side of the second deep trench 004. The first deep trench 003, the second deep trench 004, and the third deep trench 005 have the same internal structure, each including a trench oxide layer 20 and filled polysilicon 21. The trench oxide layer 20 covers both sides and the bottom of the filled polysilicon 21.

[0045] As shown in FIG2 , a first implantation region 011 and a second implantation region 111 are formed on the surface of the second epitaxial layer 002 between the first deep trench 003 and the second deep trench 004 from left to right, and the first implantation region 011 and the second implantation region 111 are tangent to each other;

[0046] As shown in FIG2 , a first implantation region 011 and a second implantation region 111 are formed on the surface of the second epitaxial layer 002 between the second deep trench 004 and the third deep trench 005 , and the first implantation region 011 and the second implantation region 111 are tangent to each other;

[0047] The second implantation region 111 is located on a side close to the second deep trench 004;

[0048] The dielectric layer 22 covers the first injection area 011, the second injection area 111, the first deep trench 003, the second deep trench 004 and the third deep trench 005. Contact holes 30 are opened on the dielectric layer 22 corresponding to the first injection area 011 and the second injection area 111. Each group of tangent first injection areas 011 and second injection areas 111 are short-circuited through the contact hole 30 and the metal layer 31 to form an electrode of the device.

[0049] The passivation layer 40 is located above the dielectric layer 22 . The passivation layer 40 has a hole at the metal layer 31 to form a pad.

[0050] In Example 1, substrate 000 is floating and not connected to any potential. Substrate 000 is an N-type substrate, first epitaxial layer 001 is a first N-type epitaxial layer, second epitaxial layer 002 is a second N-type epitaxial layer, first implantation region 011 is an N+ implantation region, first buried layer 012 is an N-type buried layer, second buried layer 112 is a P-type buried layer, and second implantation region 111 is a P+ implantation region.

[0051] The main manufacturing process flow of the vertical bidirectional SCR low-capacitance TVS device structure in Example 1 of the present application is as follows:

[0052] S1: As shown in FIG4 , an N-type substrate 000 is subjected to an epitaxial process to form a first epitaxial layer 001 , and a first buried layer 012 and a second buried layer 112 are implanted into the surface of the first epitaxial layer 001 ;

[0053] S2: As shown in FIG5 , a secondary epitaxial growth process is performed on the surface of the device obtained in step S1 to form a second epitaxial layer 002;

[0054] S3: As shown in FIG6 , a first deep trench 003 , a second deep trench 004 and a third deep trench 005 are formed on the device obtained in step S2 , and a trench oxide layer 20 and a filling polysilicon 21 are grown in each deep trench, and then CMP planarization is performed;

[0055] S4: As shown in FIG7 , a first implantation region 011 and a second implantation region 111 are implanted into corresponding positions on the surface of the device obtained in step S3;

[0056] S5: As shown in FIG8 , a dielectric layer 22 is deposited on the surface of the device obtained in step S4, and a contact hole 30 is etched on the dielectric layer 22 . Subsequently, a metal layer 31 is deposited on the dielectric layer 22 and in the contact hole 30 . After the metal layer 31 is photolithographically etched, a passivation layer 40 is deposited and etched to form a pad.

[0057] The working principle of the device structure of Example 1 of the present application is shown in Figure 3. When a surge high voltage is applied to the left electrode and the right electrode is grounded, the first N-epitaxial growth (N-epi1) / P-type buried layer (PBL) junction will be broken down. After breakdown, the SCR of the P+ injection region / second N-type epitaxial growth (N-epi2)+N-type buried layer (NBL)+first N-type epitaxial layer (N-epi1) / P-type buried layer (PBL) / second N-type epitaxial layer (N-epi2)+N+ injection region path will be turned on, and a flyback discharge current will occur at the same time. Since the current path is mainly vertically distributed, the structure can be regarded as a vertical SCR. When the right electrode is grounded with a surge high voltage on the left, the second N-type epitaxial layer (N-epi2) / P-type buried layer (PBL) junction will be broken down. After the breakdown, the SCR of the P+ injection region / second N-type epitaxial layer (N-epi2) / P-type buried layer (PBL) / first N-type epitaxial layer (N-epi1) + N-type buried layer (NBL) + second N-type epitaxial layer (N-epi2) + N+ injection region path will be turned on, and a flyback discharge current will occur at the same time. Since the current path is mainly distributed vertically, the structure can also be regarded as a vertical SCR. In this way, a vertical SCR structure is monolithically integrated. In addition, since the pads of the two electrodes are on the surface, the device is compatible with all packages of traditional lateral devices of the same size. In this application, the current of the device flows vertically, but the electrodes are on the same plane, and the pads are located on the surface of the chip, which greatly enhances the packaging compatibility of the device with related ultra-low capacitance lateral SCR devices. It is an important implementation method for the next generation of SCR ultra-low capacitance TVS devices.

[0058] Compared to related lateral SCR structures, where a lateral SCR structure can achieve a capacitance of 0.5 pF and a surge capability of 10 A, the structure of Example 1 has a higher current capacity per unit area. Since capacitance is proportional to area, the vertical bidirectional SCR (vertical device) of Example 1 is very likely to require a smaller junction area than the lateral SCR structure when achieving a surge capability of 10 A. Therefore, the capacitance of the vertical device can theoretically be achieved to be less than 0.5 pF, thus breaking the parameter limit.

[0059] The vertical bidirectional SCR low-capacitance TVS device in this application uses a dual epitaxial process and buried trench isolation technology to achieve a monolithic bidirectional SCR device structure with vertical current flow. The PNPN current in both directions (anode to cathode, cathode to anode) of this device structure is vertically distributed, greatly increasing the area utilization and surge current resistance of the device, allowing the device to pass the maximum surge current at the minimum junction capacitance, achieving the optimal balance between low capacitance and large surge current.

[0060] Example 2, a vertical bidirectional SCR low-capacitance TVS device based on a P-type substrate, the structural setting of the device is the same as that of Example 1, wherein the substrate 000 is a P-type substrate, the first epitaxial layer 001 is a first P-type epitaxial layer, the second epitaxial layer 002 is a second P-type epitaxial layer, the first injection region 011 is a P+ injection region, the first buried layer 012 is a P-type buried layer, the second buried layer 112 is an N-type buried layer, and the second injection region 111 is an N+ injection region.

Claims

1. A vertical bidirectional silicon controlled rectifier low capacitance transient suppression diode device, comprising: Substrate (000); a first epitaxial layer (001) located above the substrate (000); A first buried layer (012) and a second buried layer (112) are respectively arranged on both sides above the first epitaxial layer (001); A second epitaxial layer (002) is formed above the first buried layer (012) and the second buried layer (112); A first deep trench (003), a second deep trench (004) and a third deep trench (005) are provided from the surface of the second epitaxial layer (002) to the body of the first epitaxial layer (001), and the first deep trench (003) and the third deep trench (005) are respectively located at the two side edges of the second epitaxial layer (002) as the boundaries of the device, the second deep trench (004) is located in the middle of the second epitaxial layer (002) to divide the second epitaxial layer (002) in half, and the first buried layer (012) and the second buried layer (112) are respectively located at the two sides of the second deep trench (004); A first implantation region (011) and a second implantation region (111) are formed on the surface of the second epitaxial layer (002) between the first deep trench (003) and the second deep trench (004), and the first implantation region (011) and the second implantation region (111) are tangent to each other; The first implantation region (011) and the second implantation region (111) are formed on the surface of the second epitaxial layer (002) between the second deep trench (004) and the third deep trench (005), and the first implantation region (011) and the second implantation region (111) are tangent to each other; The second implantation region (111) is located on a side close to the second deep trench (004); The substrate (000), the first epitaxial layer (001), the second epitaxial layer (002) and the first implantation region (011) have the same doping type, the first buried layer (012) and the second buried layer (112) have opposite doping types, and the first implantation region (011) and the second implantation region (111) have opposite doping types. The doping types are opposite, and the doping type of the first buried layer (012) is the same as the doping type of the first implanted region (011).

2. The device according to claim 1, further comprising a dielectric layer (22), wherein the dielectric layer (22) covers the first injection region (011), the second injection region (111), the first deep trench (003), the second deep trench (004) and the third deep trench (005), and contact holes (30) are opened on the dielectric layer (22) corresponding to the first injection region (011) and the second injection region (111), and each group of tangent first injection regions (011) and second injection regions (111) are short-circuited through the contact holes (30) via the metal layer (31) to form an electrode of the device.

3. The device according to claim 2, further comprising a passivation layer (40), wherein the passivation layer (40) is located above the dielectric layer (22), and the passivation layer (40) has a hole opened at the metal layer (31) to form a pad.

4. The device according to any one of claims 1 to 3, wherein: The first deep trench (003), the second deep trench (004) and the third deep trench (005) have the same internal structure, and all include a trench oxide layer (20) and polysilicon (21), and the trench oxide layer (20) covers both sides and the bottom of the polysilicon (21).

5. The device according to claim 4, wherein The substrate (000) is an N-type substrate, the first epitaxial layer (001) is a first N-type epitaxial layer, the second epitaxial layer (002) is a second N-type epitaxial layer, the first injection region (011) is an N+ injection region, the first buried layer (012) is an N-type buried layer, the second buried layer (112) is a P-type buried layer, and the second injection region (111) is a P+ injection region.

6. The device according to claim 4, wherein The substrate (000) is a P-type substrate, the first epitaxial layer (001) is a first P-type epitaxial layer, the second epitaxial layer (002) is a second P-type epitaxial layer, the first injection region (011) is a P+ injection region, the first buried layer (012) is a P-type buried layer, the second buried layer (112) is an N-type buried layer, and the second injection region (111) is an N+ injection region.

7. The device according to claim 1, wherein The substrate (000) is floated and is not connected to any potential.

8. A method for manufacturing a vertical bidirectional thyristor rectifier low-capacitance transient suppression diode device, comprising: S1: performing an epitaxial process on an N-type substrate (000) to form a first epitaxial layer (001), and implanting a first buried layer (012) and a second buried layer (112) on the surface of the first epitaxial layer (001); S2: performing a secondary epitaxial growth process on the surface of the device obtained in step S1 to form a second epitaxial layer (002); S3: making a first deep trench (003), a second deep trench (004) and a third deep trench (005) on the device obtained in step S2, growing a trench oxide layer (20) and filling polysilicon (21) in each deep trench, and then performing chemical mechanical polishing (CMP) planarization; S4: implanting a first implantation region (011) and a second implantation region (111) into corresponding positions on the surface of the device obtained in step S3; S5: depositing a dielectric layer (22) on the surface of the device obtained in step S4, and etching a contact hole (30) on the dielectric layer (22), then depositing a metal layer (31) on the dielectric layer (22) and in the contact hole (30), depositing a passivation layer (40) on the metal layer (31) after photolithography and etching, and etching to form a pad.

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