Array substrate and preparation method therefor, and display apparatus

Abstract

Provided is an array substrate, comprising: a base substrate; a first passivation layer arranged on the base substrate; a first conductive layer arranged on the side of the first passivation layer away from the base substrate; and a second passivation layer arranged on the side of the first conductive layer away from the base substrate. The first passivation layer comprises a first sub-passivation layer and a second sub-passivation layer, wherein the first sub-passivation layer is located on the base substrate, and the second sub-passivation layer is located on the side of the first sub-passivation layer away from the base substrate; the thickness of the first conductive layer is greater than the thickness of each of the first sub-passivation layer and the second sub-passivation layer; and the material of the first sub-passivation layer is the same as the material of the second sub-passivation layer, and the refractive index of the first sub-passivation layer is different from the refractive index of the second sub-passivation layer.

Description

Array substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display device, and a method for manufacturing the array substrate. Background Art

[0002] Light emitting diode (LED) technology has been developed for nearly three decades, and its application range continues to expand. For example, it can be used in the display field as a backlight source for display devices or in LED display screens. With the development of technology, sub-millimeter light emitting diodes (Mini LED) and micro light emitting diodes (Micro LED) have gradually become a research hotspot in the field of display technology. For example, Mini LED or Micro LED can be used in the light-emitting modules of liquid crystal display devices as the light-emitting elements of the light-emitting modules.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided, comprising: a base substrate; a first passivation layer disposed on the base substrate; a first conductive layer disposed on a side of the first passivation layer away from the base substrate; and a second passivation layer disposed on a side of the first conductive layer away from the base substrate, wherein the array substrate comprises a plurality of array units, the plurality of array units being distributed in an array on the base substrate, at least one of the array units comprising a light-emitting diode, the light-emitting diode comprising a first electrode and a second electrode; the array substrate comprising a plurality of pad pairs, the plurality of pad pairs being located in the first conductive layer, at least one of the pad pairs comprising a first pad and a second pad, the first pad being used to contact the The first electrode is electrically connected, and the second pad is used to be electrically connected to the second electrode; the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first sub-passivation layer is located on the base substrate, the second sub-passivation layer is located on the side of the first sub-passivation layer away from the base substrate, and at least a portion of the second sub-passivation layer contacts at least a portion of the multiple pad pairs located on the first conductive layer; the thickness of the first conductive layer is greater than the thickness of the first sub-passivation layer, and the thickness of the first conductive layer is greater than the thickness of the second sub-passivation layer; and the material of the first sub-passivation layer is the same as the material of the second sub-passivation layer, and the refractive index of the first sub-passivation layer is different from the refractive index of the second sub-passivation layer.

[0006] The array substrate may be an array substrate of a display panel, and accordingly, the array unit may be a pixel unit of the display panel; or the array substrate may be a substrate of a backlight module, and accordingly, the array unit may be a light-emitting unit of the backlight module.

[0007] According to some exemplary embodiments, a refractive index of the second sub-passivation layer is greater than a refractive index of the first sub-passivation layer.

[0008] According to some exemplary embodiments, a ratio of a thickness of the first sub-passivation layer to a thickness of the second sub-passivation layer is between 0.8 and 1.2.

[0009] According to some exemplary embodiments, a ratio of a sum of the thicknesses of the first sub-passivation layer and the second sub-passivation layer to a thickness of the first conductive layer is greater than 0.15.

[0010] According to some exemplary embodiments, a sum of thicknesses of the first sub-passivation layer and the second sub-passivation layer is greater than or equal to 4500 angstroms.

[0011] According to some exemplary embodiments, the thickness of the first conductive layer is greater than or equal to 1.8 micrometers.

[0012] According to some exemplary embodiments, the thickness of the first conductive layer is greater than or equal to 3 micrometers.

[0013] According to some exemplary embodiments, the surface roughness of the first conductive layer is between 8-15.

[0014] According to some exemplary embodiments, the first passivation layer includes a bottom surface close to the base substrate, a top surface away from the base substrate, and a side wall connecting the bottom surface and the top surface, and the side wall of the first passivation layer is inclined at a first inclination angle relative to the bottom surface, and the first inclination angle is less than or equal to 40°.

[0015] According to some exemplary embodiments, the first conductive layer has a stacked structure, and the stacked structure of the first conductive layer includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is located on the side of the first passivation layer away from the substrate, the second sub-conductive layer is located on the side of the first sub-conductive layer away from the substrate, and the third sub-conductive layer is located on the side of the second sub-conductive layer away from the substrate; the first sub-conductive layer and the third sub-conductive layer are made of the same material, and the second sub-conductive layer and the third sub-conductive layer are made of different materials; and the orthographic projection of the third sub-conductive layer on the substrate falls within the orthographic projection of the second sub-conductive layer on the substrate; and / or the orthographic projection of the second sub-conductive layer on the substrate falls within the orthographic projection of the first sub-conductive layer on the substrate.

[0016] According to some exemplary embodiments, the array substrate further includes a second conductive layer, the second conductive layer is located on a side of the first passivation layer close to the base substrate; and the thickness of the second conductive layer is smaller than that of the first conductive layer.

[0017] According to some exemplary embodiments, the array substrate further includes a plurality of terminals, the plurality of terminals being located in the first conductive layer, the plurality of terminals being used to be electrically connected to the pins of the driving chip; and the array substrate further includes a plurality of conductive connection parts, the plurality of conductive connection parts being located in the first conductive layer, at least one of the conductive connection parts electrically connecting at least one of the terminals with at least one of the first pads.

[0018] According to some exemplary embodiments, the array substrate further includes a plurality of traces, which are located in the second conductive layer; the array substrate further includes: a via located in the first passivation layer; and a conductive portion located in the first conductive layer; and one end of the conductive portion is electrically connected to at least one of the second pads, and at least one of the traces is electrically connected to the conductive portion through the via.

[0019] According to some exemplary embodiments, the multiple terminals include a first terminal, which is used to be electrically connected to the ground signal pin of the driver chip; the multiple routings include a first routing, which is used to transmit the ground signal; and the vias include multiple first vias, the conductive part includes a first conductive part, the first routing is electrically connected to the first conductive part through the multiple first vias, the other end of the first conductive part is electrically connected to the first terminal, and the orthographic projections of the multiple first vias on the substrate are arranged side by side along a first direction within the orthographic projection of the first conductive part on the substrate.

[0020] According to some exemplary embodiments, the array substrate also includes a grounding line, which is located in the first conductive layer, the grounding line extends along a first direction, the first routing line extends along a second direction, and the first direction and the second direction intersect; the via includes a plurality of second vias, the first routing line is electrically connected to the grounding line through the plurality of second vias, and the orthographic projections of the plurality of second vias on the base substrate are arranged side by side along the first direction within the orthographic projection of the grounding line on the base substrate.

[0021] According to some exemplary embodiments, the array unit is a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; the multiple terminals also include a second terminal, a third terminal and a fourth terminal, the multiple pad pairs include a first pad pair, a second pad pair and a third pad pair, the first pad and the second pad of the first pad pair are used to be electrically connected to the first electrode and the second electrode of the first light-emitting diode, respectively, the first pad and the second pad of the second pad pair are used to be electrically connected to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair are used to be electrically connected to the first electrode and the second electrode of the third light-emitting diode, respectively; and the conductive connecting portion includes a first conductive connecting portion, a second conductive connecting portion and a third conductive connecting portion, the second terminal is electrically connected to the first pad of the first pad pair through the first conductive connecting portion, the third terminal is electrically connected to the first pad of the second pad pair through the second conductive connecting portion, and the fourth terminal is electrically connected to the first pad of the third pad pair through the third conductive connecting portion.

[0022] According to some exemplary embodiments, the multiple routings further include a second routing and a third routing, the second routing being used to transmit a first voltage signal to the first light-emitting diode, and the third routing being used to transmit a second voltage signal to the second light-emitting diode and the third light-emitting diode; the vias include a third via and a plurality of fourth vias, the conductive portion includes a second conductive portion and a third conductive portion, the second routing is electrically connected to one end of the second conductive portion through the third via, the other end of the second conductive portion is electrically connected to the second pad of the first pad pair, the third routing is electrically connected to the third conductive portion through the plurality of fourth vias, the third conductive portion is electrically connected to the second pad of the second pad pair and the second pad of the third pad pair, and the orthographic projections of the plurality of fourth vias on the substrate are arranged side by side along the second direction within the orthographic projection of the third conductive portion on the substrate.

[0023] According to some exemplary embodiments, the array unit is a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; the multiple pad pairs include a first pad pair, a second pad pair and a third pad pair, the first pad and the second pad of the first pad pair are used to be electrically connected to the first electrode and the second electrode of the first light-emitting diode, respectively, the first pad and the second pad of the second pad pair are used to be electrically connected to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair are used to be electrically connected to the first electrode and the second electrode of the third light-emitting diode, respectively; and the array substrate includes a first voltage signal line and a second voltage signal line located in the first conductive layer, the first pad of the first pad pair is electrically connected to the first voltage signal line, the first pad of the second pad pair and the first pad of the third pad pair are both electrically connected to the second voltage signal line, and the first pad pair, the second pad pair and the third pad pair are located between the first voltage signal line and the second voltage signal line in the first direction.

[0024] In another aspect, an array substrate is provided, comprising: a base substrate; a first passivation layer disposed on the base substrate; a first conductive layer disposed on a side of the first passivation layer away from the base substrate; and a second passivation layer disposed on a side of the first conductive layer away from the base substrate, wherein the array substrate comprises a plurality of array units, the plurality of array units being distributed in an array on the base substrate, at least one of the array units comprising a light-emitting diode, the light-emitting diode comprising a first electrode and a second electrode; the array substrate comprising a plurality of pad pairs, the plurality of pad pairs being located in the first conductive layer, at least one of the pad pairs comprising a first pad and a second pad, the The first pad is used to be electrically connected to the first electrode, and the second pad is used to be electrically connected to the second electrode; the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first sub-passivation layer is located on the base substrate, the second sub-passivation layer is located on the side of the first sub-passivation layer away from the base substrate, and at least a portion of the second sub-passivation layer contacts at least a portion of the multiple pad pairs located on the first conductive layer; the thickness of the first conductive layer is greater than the thickness of the first sub-passivation layer, and the thickness of the first conductive layer is greater than the thickness of the second sub-passivation layer; and the first conductive layer is formed on the surface of the second sub-passivation layer away from the base substrate through an electroplating process.

[0025] According to some exemplary embodiments, the thickness of the first conductive layer is greater than or equal to 3 micrometers.

[0026] According to some exemplary embodiments, the surface roughness of the first conductive layer is between 8-15.

[0027] In yet another aspect, a display device is provided, wherein the display device includes the array substrate as described in any one of the above.

[0028] In another aspect, a method for preparing an array substrate is provided, the method comprising: providing a base substrate; forming a first passivation layer on the base substrate; forming a first conductive material layer on a side of the first passivation layer away from the base substrate; performing a patterning process on the first conductive material layer to form a plurality of pad pairs, wherein at least one of the pad pairs includes a first pad and a second pad, the first pad being used to be electrically connected to a first electrode of a light-emitting diode, and the second pad being used to be electrically connected to a second electrode of the light-emitting diode; and forming a second passivation layer on a side of the plurality of pad pairs away from the base substrate, wherein the first passivation layer formed on the base substrate is The passivation layer includes: forming a first sub-passivation material layer on the base substrate; forming a second sub-passivation material layer on a side of the first sub-passivation material layer away from the base substrate; performing a first etching on the second sub-passivation material layer to form a second sub-passivation layer; and performing a second etching on the first sub-passivation material layer to form a first sub-passivation layer, wherein the thickness of the first conductive layer is greater than the thickness of the first sub-passivation layer, and the thickness of the first conductive layer is greater than the thickness of the second sub-passivation layer; and the material of the first sub-passivation layer is the same as the material of the second sub-passivation layer, and the refractive index of the first sub-passivation layer is different from the refractive index of the second sub-passivation layer.

[0029] According to some exemplary embodiments, forming the first conductive material layer on the side of the first passivation layer away from the base substrate includes: electroplating a copper layer on a surface of the second sub-passivation layer away from the base substrate to form the first conductive material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0031] FIG1 is a schematic diagram of a partial structure of a display panel according to some exemplary embodiments of the present disclosure;

[0032] FIG2 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, showing an electrical connection relationship between a pad and a pixel unit;

[0033] FIG3 is a partial cross-sectional schematic diagram of a first passivation layer in some exemplary embodiments of the present disclosure;

[0034] FIG4 is a structural diagram of a first conductive layer according to some exemplary embodiments of the present disclosure;

[0035] FIG5 is a partial schematic plan view of a first conductive layer according to some embodiments of the present disclosure;

[0036] FIG6 is a schematic structural diagram of a display panel according to some other embodiments of the present disclosure, wherein the second conductive layer is shown;

[0037] FIG7 is a schematic plan view of a display panel according to some embodiments of the present disclosure, showing the electrical connection relationship among the pins, terminals, pads, and conductive connection parts of the driver chip;

[0038] FIG8 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among traces, conductive portions, and pads;

[0039] FIG9 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection between the traces and the conductive portion, and the electrical connection between the terminals and the driver chip. FIG9 also shows the electrical connection between the ground line and the first trace.

[0040] FIG10 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among pixels, terminals, pads, and conductive connection parts;

[0041] FIG11 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among traces, conductive portions, pads, and light-emitting diodes;

[0042] FIG12 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship between the first voltage signal line and the second voltage signal line and the pad;

[0043] FIG13 is a schematic structural diagram of some other embodiments of the present disclosure, in which a backlight module is used as a backlight source in a liquid crystal panel;

[0044] FIG14A shows a schematic structural diagram of a backlight module according to another embodiment of the present disclosure, and FIG14B shows a planar schematic diagram of a backlight module, wherein FIG14B shows an electrical connection relationship between a light-emitting unit and a pair of pads in a backlight module;

[0045] 15A and 15B are respectively a display device according to an exemplary embodiment of the present disclosure;

[0046] FIG. 16 is a diagram illustrating a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure; and

[0047] FIG. 17 is a flowchart of a patterning process performed on a first passivation layer according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0049] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0050] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0051] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0052] In this article, inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED represents an inorganic light-emitting element that is different from OLED. Specifically, inorganic light-emitting elements can include sub-millimeter light-emitting diodes (Mini Light Emitting Diode, abbreviated as Mini LED in English) and micro light-emitting diodes (Micro LED in English). Among them, micro light-emitting diodes (i.e. Micro LEDs) refer to ultra-small light-emitting diodes with a grain size of less than 100 microns, and sub-millimeter light-emitting diodes (i.e. Mini LEDs) refer to small light-emitting diodes with a grain size between Micro LEDs and traditional LEDs. For example, the grain size of Mini LEDs can be between 50 and 400 microns.

[0053] In current LCD displays, brightness is controlled by the deflection of liquid crystals, which takes time, typically in the microsecond range. Rapidly moving images can easily cause image streaking. Streaking occurs whenever the speed of an object exceeds the display device's maximum response speed. It's an inherent phenomenon in LCD systems, and overdriving is typically used to mitigate it, but it can't be eliminated. New display systems, such as Mini LED or Micro LED, overcome this phenomenon by directly utilizing light-emitting diodes to generate light. In new Mini LED or Micro LED displays, the conductive dielectric layer in the circuitry must possess excellent conductivity and high ductility. In actual manufacturing, increasing the thickness of the conductive dielectric layer to ensure high resolution in display panels is often used to improve its conductivity. However, increasing the thickness of the conductive dielectric layer increases stress accumulation between the conductive dielectric layer and the adjacent passivation layer, leading to warping of the conductive dielectric layer and, in turn, the substrate. When substrate warping exceeds a certain level, for example, 1 mm, subsequent processing can be disrupted. Therefore, in the preparation of a display panel, when increasing the thickness of the conductive dielectric layer, it is also necessary to prevent the conductive dielectric layer from warping, so as to facilitate the smooth development of subsequent processes and improve the yield of the display panel.

[0054] An embodiment of the present disclosure provides a display panel, which includes: a base substrate; a first passivation layer arranged on the base substrate; a first conductive layer arranged on a side of the first passivation layer away from the base substrate; and a second passivation layer arranged on a side of the first conductive layer away from the base substrate, wherein the display panel includes a plurality of pixel units, the plurality of pixel units are distributed in an array on the base substrate, at least one of the pixel units includes a light-emitting diode, and the light-emitting diode includes a first electrode and a second electrode; the display panel includes a plurality of pad pairs, the plurality of pad pairs are located in the first conductive layer, at least one of the pad pairs includes a first pad and a second pad, the first pad is used to connect to the The first electrode is electrically connected, and the second pad is used to be electrically connected to the second electrode; the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first sub-passivation layer is located on the base substrate, the second sub-passivation layer is located on the side of the first sub-passivation layer away from the base substrate, and at least a portion of the second sub-passivation layer contacts at least a portion of the multiple pad pairs located on the first conductive layer; the thickness of the first conductive layer is greater than the thickness of the first sub-passivation layer, and the thickness of the first conductive layer is greater than the thickness of the second sub-passivation layer; and the material of the first sub-passivation layer is the same as the material of the second sub-passivation layer, and the refractive index of the first sub-passivation layer is different from the refractive index of the second sub-passivation layer. In the embodiment of the present disclosure, by designing the structure of the first passivation layer, it is beneficial to achieve thickness and stress matching between the first passivation layer and the first conductive layer, thereby facilitating improving product yield.

[0055] It should be noted that in the embodiments of the present disclosure, the array substrate may be an array substrate of a display panel, and accordingly, the array units may be pixel units of the display panel; alternatively, the array substrate may be a substrate of a backlight module, and accordingly, the array units may be light-emitting units of the backlight module. In the following description, the array substrate according to the embodiments of the present disclosure is described in detail using a display panel and a backlight module as examples. It should be understood that such separate descriptions are merely for convenience of description; the structures of the display panel and the backlight module may be combined and referenced to each other unless there is a conflict.

[0056] FIG. 1 is a schematic diagram of a partial structure of a display panel according to some exemplary embodiments of the present disclosure.

[0057] 1 , the display panel 100 may include a plurality of film layers disposed on a base substrate 1. For example, the plurality of film layers include: a first passivation layer 2 disposed on the base substrate 1, a first conductive layer 3 disposed on a side of the first passivation layer 2 away from the base substrate, and a second passivation layer 4 disposed on a side of the first conductive layer 3 away from the base substrate.

[0058] For example, the material of the base substrate 1 may include but is not limited to glass, quartz, plastic, silicon, polyimide, etc.

[0059] Referring to Figure 1, in the disclosed embodiment, the first passivation layer 2 has a dual-layer structure, comprising a first sub-passivation layer 21 located on the base substrate 1, and a second sub-passivation layer 22 disposed on the side of the first sub-passivation layer 21 facing away from the base substrate 1. The display panel also includes a first conductive layer 3 disposed on the side of the second sub-passivation layer 22 facing away from the base substrate. Conductive components for connecting to light-emitting diodes or driver chips can be located in the first conductive layer 3, which can be made of a highly conductive material such as Cu.

[0060] The inventors have discovered that when the first passivation layer 2 beneath the first conductive layer 3 is relatively thin, the stress between the first conductive layer 3 and the first passivation layer 2 becomes concentrated during the process of increasing the thickness of the first conductive layer 3, causing the first conductive layer 3 and the first passivation layer 2 to gradually warp, which in turn causes the underlying supporting substrate 1 to warp. When the degree of warpage of the substrate 1 exceeds 1 mm, subsequent processes cannot proceed normally. Therefore, it is necessary to design a thickness and stress matching between the first passivation layer 2 and the first conductive layer 3 to ensure that, while increasing the thickness of the first conductive layer 3, the substrate 1 does not warp by more than 1 mm, allowing subsequent processes to proceed normally.

[0061] In the embodiment of the present disclosure, referring to FIG1 , the first passivation layer 2 adopts a double-layer structure, and the first passivation layer 2 includes a first sub-passivation layer 21 and a second sub-passivation layer 22. By adopting a double-layer structure, the thickness of the first passivation layer 2 can be increased, so that when the thickness of the first conductive layer 3 is increased, the stress between the first passivation layer 2 and the first conductive layer 3 is more matched. When the thickness of the first passivation layer 2 increases, the stress can be gradually released in the first passivation layer 2, avoiding excessive accumulation of stress in the local area between the first passivation layer 2 and the first conductive layer 3, ensuring that the warping degree of the first conductive layer 3 and the first passivation layer 2 is small, thereby reducing the warping degree of the underlying substrate 1, which is conducive to the normal progress of subsequent processes.

[0062] To achieve thickness and stress matching between the first passivation layer 2 and the first conductive layer 3, the thickness D3 of the first conductive layer 3 is greater than the thickness D1 of the first sub-passivation layer 21, and the thickness D3 of the first conductive layer 3 is greater than the thickness D2 of the second sub-passivation layer. The material of the first sub-passivation layer 21 is the same as that of the second sub-passivation layer 22, and the refractive index of the first sub-passivation layer is different from the refractive index of the second sub-passivation layer. The first sub-passivation layer 21 and the second sub-passivation layer 22 are prepared using a two-step process, forming a gradual thermal expansion coefficient gradient between the first conductive layer 3, the second sub-passivation layer 22, and the first sub-passivation layer 21. In other words, the thermal expansion coefficient of the second sub-passivation layer 22 is between the thermal expansion coefficients of the first conductive layer 3 and the first sub-passivation layer 21. This gradual thermal expansion coefficient gradient design facilitates the gradual release of stress between the first conductive layer 3, the second sub-passivation layer 22, and the first sub-passivation layer 21, reducing the resulting warping of the substrate 1 and facilitating the normal execution of subsequent processes.

[0063] For example, in some other embodiments of the present disclosure, the refractive index of the second sub-passivation layer 22 is greater than the refractive index of the first sub-passivation layer 21. Generally, in a certain material, when the material is subjected to force, its refractive index characteristics will also change due to the force. The greater the force, the greater the refractive index. In the embodiment of the present disclosure, the first sub-passivation layer 21 is located between the base substrate 1 and the second sub-passivation layer 22. Therefore, when the first conductive layer 3 is thickened, the stress formed will first be released through the second sub-passivation layer 22, and then through the first sub-passivation layer 21, and finally transmitted to the base substrate 1. When the refractive index of the first sub-passivation layer 21 is relatively small, the stress concentrated in the first sub-passivation layer 21 is also relatively small. Therefore, the stress transmitted to the base substrate 1 is also relatively small, and the degree of warping of the base substrate 1 is also correspondingly relatively small, which is conducive to the normal progress of subsequent processes.

[0064] For example, in some embodiments of the present disclosure, the ratio of the thickness D1 of the first sub-passivation layer 21 to the thickness D2 of the second sub-passivation layer 22 is between 0.8 and 1.2.

[0065] For example, in some embodiments of the present disclosure, the ratio of the sum of the thicknesses of the first sub-passivation layer 21 and the second sub-passivation layer 22 to the thickness of the first conductive layer 3 is greater than 0.15.

[0066] For example, in some embodiments of the present disclosure, the sum of the thicknesses of the first sub-passivation layer 21 and the second sub-passivation layer 22 is greater than or equal to 4500 angstroms.

[0067] By designing the thickness of the first sub-passivation layer and the second sub-passivation layer, when the thickness of the first conductive layer is thickened, the sum of the thickness of the first sub-passivation layer 21 and the second sub-passivation layer 22 can be more closely matched with the thickness of the first conductive layer 3, thereby reducing the stress accumulated between the first conductive layer 3, the second sub-passivation layer 22 and the first sub-passivation layer 21, and reducing the degree of warping of the substrate 1, so as to facilitate the normal progress of subsequent processes.

[0068] FIG. 2 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, showing an electrical connection relationship between a pad and a pixel unit.

[0069] 2 , the display panel may include a plurality of pixel units 5, which are distributed in an array on a substrate 1. At least one of the pixel units includes a light-emitting diode 51, and the light-emitting diode 51 includes a first electrode 511 and a second electrode 512. The display panel also includes a plurality of pad pairs 6, which are located in the first conductive layer 3. At least one of the pad pairs 6 includes a first pad 61 and a second pad 62. The first pad 61 is configured to electrically connect to the first electrode 511, and the second pad 62 is configured to electrically connect to the second electrode 512. The display panel also includes a second sub-passivation layer 22, at least a portion of which contacts at least a portion of the plurality of pad pairs 6 located in the first conductive layer 3.

[0070] In new display panels, as pixel density increases, the space for signal routing becomes smaller and smaller, so the line width of the conductive traces becomes narrower and narrower. In order to maintain sufficient conductivity of the signal traces to meet a sufficiently fast response speed, the thickness of the conductive traces needs to be relatively thick, thereby reducing the resistance of the conductive traces and ensuring that the display panel has a fast response speed.

[0071] Illustratively, in some embodiments of the present disclosure, the thickness D3 of the first conductive layer 3 is greater than or equal to 1.8 microns.

[0072] Illustratively, in some embodiments of the present disclosure, the thickness D3 of the first conductive layer 3 is greater than or equal to 3 micrometers.

[0073] For example, in some embodiments of the present disclosure, the surface roughness of the first conductive layer 3 is between 8-15.

[0074] By increasing the thickness of the first conductive layer 3 , the conductive traces can be narrowed while ensuring good conductivity, so that the conductive traces can quickly complete signal transmission and achieve rapid response of the display panel.

[0075] FIG. 3 is a partial cross-sectional schematic diagram of a first passivation layer according to some exemplary embodiments of the present disclosure.

[0076] 3 , the first passivation layer 2 includes a bottom surface L1 close to the base substrate, a top surface L2 away from the base substrate, and a side wall L3 connecting the bottom surface and the top surface. The side wall of the first passivation layer is inclined at a first inclination angle a1 relative to the bottom surface, and the first inclination angle a1 is less than or equal to 40°.

[0077] In order to reduce the warping problem of the substrate caused by the thickening of the first conductive layer, it is necessary to adjust the stress and thickness of the first passivation layer below the first conductive layer. With reference to Figure 1, the commonly used solution is to perform a plating treatment on the first passivation layer to form a double-layer structure, namely a first sub-passivation layer and a second sub-passivation layer. The first passivation layer and the second passivation layer can be prepared under different process conditions, such as physical vapor deposition coating, chemical vapor deposition coating or magnetron sputtering coating. After the first passivation layer is thickened, in order to prevent the first conductive layer prepared above the first passivation layer from having defects such as cracks or cracks at the edge of the first passivation layer due to the step difference of the film layer when the first conductive layer is prepared above the first passivation layer, it is necessary to adjust the etching process to form a gradually inclined angle at the edge of the first passivation layer, such as the first inclined angle a1 in Figure 3. With reference to Figure 3, by forming the first inclined angle a1 at the edge of the first passivation layer 2, the first conductive layer 3 prepared above the first passivation layer 2 has higher film quality and fewer defects, which is conducive to improving the conductive performance and stability of the first conductive layer 3 and improving the yield of the display panel.

[0078] FIG4 is a structural diagram of a first conductive layer according to some exemplary embodiments of the present disclosure; FIG5 is a partial schematic plan view of a first conductive layer according to some exemplary embodiments of the present disclosure.

[0079] 4 and 5 , the first conductive layer 3 has a stacked structure, and the stacked structure of the first conductive layer 3 includes a first sub-conductive layer 31, a second sub-conductive layer 32 and a third sub-conductive layer 33. The first sub-conductive layer 31 is located on the side of the first passivation layer 2 away from the substrate 1, the second sub-conductive layer 32 is located on the side of the first sub-conductive layer 31 away from the substrate 1, and the third sub-conductive layer 33 is located on the side of the second sub-conductive layer 32 away from the substrate 1; the first sub-conductive layer 31 and the third sub-conductive layer 33 are made of the same material, and the second sub-conductive layer 32 and the third sub-conductive layer 33 are made of different materials; and the orthographic projection of the third sub-conductive layer 33 on the substrate falls within the orthographic projection of the second sub-conductive layer 32 on the substrate; and / or the orthographic projection of the second sub-conductive layer 32 on the substrate falls within the orthographic projection of the first sub-conductive layer 31 on the substrate.

[0080] In the display manufacturing process, when the first conductive layer electrode is at a high temperature, the ions in the first conductive layer, for example, Cu ions, will diffuse across the gate insulating layer into the semiconductor, causing the performance of the thin film transistor to deteriorate, so it is usually necessary to add a diffusion barrier layer on the surface of the copper electrode. By designing the first conductive layer into a stacked structure, that is, wrapping the high conductivity layer with two layers of diffusion barrier layers to form the first conductive layer of the stacked structure. For example, referring to Figure 4, the first sub-conductive layer 31 and the third sub-conductive layer 33 of the first conductive layer 3 are diffusion barrier layers, wherein the material of the first sub-conductive layer 31 and the third sub-conductive layer 33 can be the same. The material of the first sub-conductive layer 31 can be a metal layer, a metal nitride layer, a metal alloy, etc., such as metal titanium (Ti), molybdenum (Mo), niobium molybdenum alloy (MoNb), etc. The material of the second sub-conductive layer 32 is different from that of the first sub-conductive layer 31. The first sub-conductive layer 31 is located between the first passivation layer 2 and the second sub-conductive layer 32. When the thickness of the first sub-conductive layer 31 is relatively thick, for example, the thickness of the first sub-conductive layer 31 is 300 angstroms, the first sub-conductive layer 31 can better prevent the second sub-conductive layer 32 from diffusing into the gate insulating layer.

[0081] Continuing with reference to FIG5 , in order to achieve a better anti-diffusion effect, the orthographic projection of the second sub-conductive layer 32 on the base substrate 1 is usually designed to fall within the orthographic projection of the first sub-conductive layer 31 on the base substrate 1. This design can block the channel for the metal in the second sub-conductive layer 32 to directly diffuse into the first passivation layer 2, reduce the probability of the metal in the second sub-conductive layer 32 diffusing into the semiconductor region, and better improve the stability of the display panel. The third sub-conductive layer 33 is located on the side of the second sub-conductive layer 32 away from the base substrate 1. Usually, the third sub-conductive layer 33 uses a metal or alloy with high thermal stability similar to that of the first sub-conductive layer 31, which can prevent the second sub-conductive layer 32 from diffusing into other film layers and can also play a certain protective role for the second sub-conductive layer 32 during processes such as etching. The orthographic projection of the third sub-conductive layer 33 on the base substrate 1 falls within the orthographic projection of the second sub-conductive layer 32 on the base substrate 1. When the second sub-conductive layer 32 needs to be directly electrically connected to other wirings in a local area to meet high-performance conductivity, the local area of ​​the third sub-conductive layer 33 can be opened to expose the local area of ​​the second sub-conductive layer to achieve direct electrical connection with other wirings.

[0082] FIG6 is a schematic structural diagram of a display panel according to some other embodiments of the present disclosure, in which the second conductive layer is shown.

[0083] With reference to FIG6 , in some other embodiments of the present disclosure, the display panel further includes a second conductive layer 7, which is located on a side of the first sub-passivation layer 21 closer to the base substrate 1. The thickness D4 of the second conductive layer 7 is less than the thickness D3 of the first conductive layer 3. By designing a double conductive layer, the spatial routing layout of the conductive layer can be more flexibly designed, increasing the aperture ratio of the display area and achieving a better display effect.

[0084] FIG7 shows a planar schematic diagram of a display panel according to some embodiments of the present disclosure, which illustrates the electrical connection relationship among the pins, terminals, pads, and conductive connection parts of the driving chip.

[0085] The display panel can be controlled by connecting an IC (integrated circuit) driver chip. Referring to FIG7 , the display panel further includes a plurality of terminals 8, which are located in the first conductive layer 3 and are used to electrically connect to the pins 9 of the driver chip. The display panel further includes a plurality of conductive connection portions 10, which are located in the first conductive layer 3, and at least one conductive connection portion 10 connects at least one terminal 8 and the first pad 61 of at least one pad pair. Through the electrical connection between at least one pad pair 6, at least one conductive connection portion 10, at least one terminal 8, and the pins 9 of at least one driver chip, and then through the electrical connection between at least one pad pair 6 and the pixel unit 5, such as a light-emitting diode, the driver chip can control the pixel unit to achieve different display effects.

[0086] FIG8 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among traces, conductive portions, and pads.

[0087] 8 , the display panel includes a plurality of traces 72 , and the plurality of traces 72 are located in the second conductive layer 7 ; the display panel also includes: a via 13 located in the first passivation layer 2 ; and a conductive portion 11 located in the first conductive layer 3 ; one end of the conductive portion 11 is electrically connected to at least one of the second pads 62 , and at least one of the traces 72 is electrically connected to the conductive portion 11 through the via 13 .

[0088] FIG9 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection between the traces and the conductive portion, and the electrical connection between the terminals and the driver chip. FIG9 also shows the electrical connection between the ground line and the first trace.

[0089] 9 , the display panel includes a plurality of terminals 8 , the plurality of terminals 8 including a first terminal 81 , the first terminal 81 being electrically connected to a ground signal pin 91 of the driver chip;

[0090] The display panel further includes a plurality of traces 72 and a plurality of vias 13. The plurality of traces 72 include a first trace 721 for transmitting a ground signal; the plurality of vias 13 include a plurality of first vias 131. The display panel further includes a conductive portion 11, the conductive portion 11 including a first conductive portion 111. The first trace 721 is electrically connected to the first conductive portion 111 via the plurality of first vias 131. The other end of the first conductive portion 111 is electrically connected to the first terminal 81. The orthographic projections of the plurality of first vias 131 on the base substrate 1 are arranged side by side along a first direction within the orthographic projection of the first conductive portion 3 on the base substrate 1.

[0091] Continuing with reference to Figure 9, the display panel also includes a grounding wire 14, which is located in the first conductive layer 3, and the grounding wire 14 extends along a first direction, and the first wiring 721 extends along a second direction, and the first direction and the second direction intersect; the multiple vias 13 include multiple second vias 132, and the first wiring 721 is electrically connected to the grounding wire 14 through the multiple second vias 132, and the orthographic projections of the multiple second vias 132 on the base substrate 1 are arranged side by side along the first direction within the orthographic projection of the grounding wire 14 on the base substrate.

[0092] FIG10 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among pixels, terminals, pads, and conductive connection parts.

[0093] 10 , the display panel includes a plurality of pixel units 5, a plurality of terminals 8, and a plurality of pad pairs 6. Among the plurality of pixel units 5, at least one pixel unit includes a first sub-pixel 52, a second sub-pixel 53, and a third sub-pixel 54. The first sub-pixel 52 includes a first light-emitting diode 521, the second sub-pixel 53 includes a second light-emitting diode 531, and the third sub-pixel 54 includes a third light-emitting diode 541. The plurality of terminals 8 further include a second terminal 82, a third terminal 83, and a fourth terminal 84. The plurality of pad pairs 6 include a first pad pair 601, a second pad pair 602, and a third pad pair 603. The first pad and the second pad of the first pad pair 601 are respectively electrically connected to the first electrode and the second electrode of the first light-emitting diode 521, the first pad and the second pad of the second pad pair 602 are respectively electrically connected to the first electrode and the second electrode of the second light-emitting diode, and the first pad and the second pad of the third pad pair 603 are respectively electrically connected to the first electrode and the second electrode of the third light-emitting diode. The display panel also includes a conductive connecting part 10, which includes a first conductive connecting part 101, a second conductive connecting part 102 and a third conductive connecting part 103. The second terminal 82 is electrically connected to the first pad of the first pad pair 601 through the first conductive connecting part 101, the third terminal 83 is electrically connected to the first pad of the second pad pair 602 through the second conductive connecting part 102, and the fourth terminal 84 is electrically connected to the first pad of the third pad pair 603 through the third conductive connecting part 103.

[0094] FIG11 is a plan view schematic diagram of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among traces, conductive portions, pads, and light-emitting diodes.

[0095] 11 , the display panel includes a plurality of traces 72 , the plurality of traces 72 including a second trace 722 and a third trace 723 , the second trace 722 being used to transmit a first voltage signal to the first light-emitting diode 521 , and the third trace 723 being used to transmit a second voltage signal to the second light-emitting diode 531 and the third light-emitting diode 541 . The display panel also includes multiple vias and conductive parts, the multiple vias include a third via 133 and multiple fourth vias 134, the conductive parts include a second conductive part 112 and a third conductive part 113, the second trace 722 is electrically connected to one end of the second conductive part 112 through the third via 133, and the other end of the second conductive part 112 is electrically connected to the second pad of the first pad pair 601, the third trace 723 is electrically connected to the third conductive part 113 through the multiple fourth vias 134, the third conductive part 113 is electrically connected to the second pad of the second pad pair 602 and the second pad of the third pad pair 603, and the orthographic projections of the multiple fourth vias 134 on the base substrate 1 are arranged side by side along the second direction within the orthographic projection of the third conductive part 113 on the base substrate 1.

[0096] The display panel can not only control the display effect through the IC driver chip, but also control the display effect through the low-temperature polysilicon technology LTPS (Low Temperature Poly-silicon) driver circuit to achieve control of different screens.

[0097] FIG12 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship between the first voltage signal line, the second voltage signal line, and the pad.

[0098] With reference to Figures 10 and 12, an exemplary embodiment of a display panel controlled by an LTPS driving circuit is given. Referring to Figure 10, the display panel has multiple pixel units and multiple pad pairs, at least one of which includes a first sub-pixel 52, a second sub-pixel 53, and a third sub-pixel 54, the first sub-pixel includes a first light-emitting diode 521, the second sub-pixel includes a second light-emitting diode 531, and the third sub-pixel includes a third light-emitting diode 541; the multiple pad pairs include a first pad pair 601, a second pad pair 602, and a third pad pair 603, the first pad and the second pad of the first pad pair 601 being used to electrically connect to the first electrode and the second electrode of the first light-emitting diode 521, respectively, the first pad and the second pad of the second pad pair 602 being used to electrically connect to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair 603 being used to electrically connect to the first electrode and the second electrode of the third light-emitting diode, respectively. Referring to Figure 12, the display panel includes a first voltage signal line V1 and a second voltage signal line V2 located in the first conductive layer 3, the first pad of the first pad pair 601 is electrically connected to the first voltage signal line, the first pad of the second pad pair 602 and the first pad of the third pad pair 603 are both electrically connected to the second voltage signal line, and the first pad pair 601, the second pad pair 602 and the third pad pair are located between the first voltage signal line V1 and the second voltage signal line V2 in the first direction.

[0099] On the other hand, the present disclosure further provides a display panel, with reference to FIG1 and FIG2, the display panel includes: a base substrate 1; a first passivation layer 2 provided on the base substrate; a first conductive layer 3 provided on a side of the first passivation layer 2 away from the base substrate 1; and a second passivation layer 4 provided on a side of the first conductive layer 3 away from the base substrate 1, wherein the display panel includes a plurality of pixel units 5, the plurality of pixel units 5 are distributed in an array on the base substrate 1, and at least one of the pixel units 5 It includes a light-emitting diode 51, which includes a first electrode 511 and a second electrode 512; the display panel includes a plurality of pad pairs 6, which are located in the first conductive layer 3, and at least one of the pad pairs 6 includes a first pad 61 and a second pad 62, the first pad 61 is used to be connected to the first electrode 511, and the second pad 62 is used to be connected to the second electrode 512; the first passivation layer 2 includes a first sub-passivation layer 21 and a second sub-passivation layer 22, the first sub-passivation layer 21 is located on the base substrate 1, and the second sub-passivation layer 22 is located on the side of the first sub-passivation layer 21 away from the base substrate 1, and at least a portion of the second sub-passivation layer 22 contacts at least a portion of the plurality of pad pairs 6 located on the first conductive layer 3; the thickness of the first conductive layer D3 is greater than the thickness D1 of the first sub-passivation layer, and the thickness D3 of the first conductive layer is greater than the thickness D2 of the second sub-passivation layer; the first conductive layer 3 is formed on the surface of the second sub-passivation layer 22 away from the base substrate 1 through an electroplating process.

[0100] Compared with the process of sputtering or evaporating the first conductive layer, the warping of the substrate is significantly improved when the first conductive layer is prepared by electroplating. For example, when the thickness of the first passivation layer is fixed at 2500 angstroms, when the first conductive layer is prepared by sputtering, the warping of the substrate is between 1.8 and 2.7 mm when the thickness of the first conductive layer increases to 2.7 microns, and subsequent processes cannot be carried out. When the first conductive layer is prepared by electroplating, the warping of the substrate is less than 0.5 mm when the thickness of the first conductive layer increases to 3 microns, and subsequent processes can be carried out. This shows that for the first conductive layer, choosing an appropriate process can reduce the warping of the substrate when obtaining a first conductive layer of greater thickness, which is conducive to the continuation of subsequent processes.

[0101] Illustratively, in some embodiments of the present disclosure, the thickness D3 of the first conductive layer 3 is greater than or equal to 3 micrometers.

[0102] For example, in some embodiments of the present disclosure, the surface roughness of the first conductive layer 3 is between 8-15.

[0103] LED light sources can not only be used as display pixels to make display panels, but can also be used as backlight light sources in display panels, and then combined with light guide plates, diffuser plates, prism plates and liquid crystal modules to make display devices.

[0104] FIG13 shows a schematic structural diagram of other embodiments of the present disclosure, in which a backlight module is shown as a backlight source in a display device.

[0105] 13 , the present disclosure further provides a backlight module for use as a backlight source in a display device. The display device includes a backlight module 30 , a light guide plate 31 , a diffuser plate 32 , a prism plate 33 , and a liquid crystal module 34 .

[0106] FIG14A shows a schematic structural diagram of a backlight module according to some other embodiments of the present disclosure, and FIG14B shows a planar schematic diagram of the backlight module, wherein FIG14B shows an electrical connection relationship between a light-emitting unit and a pair of pads in a backlight module.

[0107] 14A , the backlight module 30 includes multiple film layers disposed on a base substrate 1. For example, the multiple film layers include: a first passivation layer 2 disposed on the base substrate 1; a first conductive layer 3 disposed on a side of the first passivation layer 2 away from the base substrate; and a second passivation layer 4 disposed on a side of the first conductive layer 3 away from the base substrate. The base substrate 1 may be made of, but is not limited to, glass, quartz, plastic, silicon, polyimide, and the like.

[0108] Continuing with reference to Figure 14A, in the embodiment of the present disclosure, the first passivation layer 2 is a double-layer structure, including a first sub-passivation layer 21 located on one side of the base substrate, and a second sub-passivation layer 22 arranged on the side of the first sub-passivation layer 21 away from the base substrate 1. The thickness D3 of the first conductive layer 3 is greater than the thickness D1 of the first sub-passivation layer 21, and the thickness D3 of the first conductive layer 3 is greater than the thickness D2 of the second sub-passivation layer 22; the material of the first sub-passivation layer 21 is the same as the material of the second sub-passivation layer 22, and the refractive index of the first sub-passivation layer 21 is different from the refractive index 22 of the second sub-passivation layer.

[0109] With reference to FIG14B , in the embodiment of the present disclosure, the backlight module 30 further includes a plurality of light-emitting units 20, which are distributed in an array on the base substrate 1. At least one of the light-emitting units includes a light-emitting diode 51, and the light-emitting diode 51 includes a first electrode 511 and a second electrode 512. The backlight module further includes a plurality of pad pairs 6, which are located in the first conductive layer 3. At least one of the pad pairs 6 includes a first pad 61 and a second pad 62. The first pad 61 is used to electrically connect to the first electrode 511, and the second pad 62 is used to electrically connect to the second electrode 512. At least a portion of the second sub-passivation layer 22 contacts at least a portion of the plurality of pad pairs 6 located in the first conductive layer 3.

[0110] 15A and 15B are each a display device according to an exemplary embodiment of the present disclosure.

[0111] 15A , an embodiment of the present disclosure exemplarily provides a display device 200 , wherein the display device 200 includes any one of the aforementioned display panels 100 .

[0112] 15B , an embodiment of the present disclosure exemplarily provides another display device 200 , wherein the display device 200 includes any of the aforementioned backlight modules 30 .

[0113] FIG16 is a diagram illustrating a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. As shown in FIG16 , the method may include steps S01 to S05.

[0114] It should be noted that some steps of the above manufacturing method can be performed individually or in combination, and can be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figures.

[0115] In step S01, a base substrate 1 is provided;

[0116] In step S02, a first passivation layer 2 is formed on the base substrate 1;

[0117] In step S03, a first conductive layer 3 is formed on a side of the first passivation layer 2 away from the base substrate 1;

[0118] In step S04, a patterning process is performed on the first conductive material layer 3 to form a plurality of pad pairs, wherein at least one of the pad pairs includes a first pad and a second pad, the first pad being electrically connected to a first electrode of a light-emitting diode, and the second pad being electrically connected to a second electrode of the light-emitting diode;

[0119] In step S05 , a second passivation layer 4 is formed on a side of the plurality of pad pairs away from the base substrate.

[0120] FIG. 17 illustrates a method for performing a patterning process on a first passivation layer according to an exemplary embodiment of the present disclosure.

[0121] 17 , the forming of the first passivation layer 2 on the base substrate 1 includes:

[0122] In step S201, a first sub-passivation material layer is formed on the base substrate;

[0123] In step S202, a second sub-passivation material layer is formed on a side of the first sub-passivation material layer away from the base substrate;

[0124] In step S203, performing a first etching on the second sub-passivation material layer to form a second sub-passivation layer;

[0125] In step S204, the first sub-passivation material layer is subjected to a second etching process to form a first sub-passivation layer.

[0126] 1 , the thickness D3 of the first conductive layer 3 is greater than the thickness D1 of the first sub-passivation layer 21, and the thickness D3 of the first conductive layer is greater than the thickness D2 of the second sub-passivation layer 22; the material of the first sub-passivation layer is the same as the material of the second sub-passivation layer, and the refractive index of the first sub-passivation layer is different from the refractive index of the second sub-passivation layer.

[0127] The first passivation layer includes a first sub-passivation material layer and a second sub-passivation material layer. Due to the cumulative thickness of the two layers, if a one-step dry etching process is used to dry-etch the first passivation layer, the required dry etching time is correspondingly longer, resulting in a higher degree of ashing of the photoresist. However, in order to take into account the glue-resolving ability of the photoresist, the thickness of the photoresist cannot be increased indefinitely. The one-step dry etching method in the current process cannot retain a sufficient amount of photoresist remaining after dry etching, and it is difficult to avoid the occurrence of over-etching. In the embodiment of the present disclosure, by decomposing the dry etching process into two steps, different dry etching processes are adopted according to the different film properties of the first sub-passivation material layer and the second sub-passivation material layer. This not only ensures the accuracy of the composition process, but also ensures a larger amount of photoresist remaining after dry etching, and does not cause over-etching. In addition, the edge tilt angle of the first passivation layer can be better controlled, for example, ensuring that the edge tilt angle of the first passivation layer is less than 40°. This is more conducive to improving the film quality of the first conductive layer prepared subsequently and improving the reliability of the display panel.

[0128] Exemplarily, in some embodiments of the present disclosure, forming the first conductive material layer 3 on the side of the first passivation layer 2 away from the base substrate 1 includes: electroplating a copper layer on the surface of the second sub-passivation layer 2 away from the base substrate 1 to form the first conductive material layer 3.

[0129] By adopting the copper electroplating process, the warping degree of the first conductive material layer can be reduced, thereby reducing the warping degree of the base substrate, which is beneficial to the normal progress of subsequent processes.

[0130] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0131] Although the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate substrate; A first passivation layer disposed on the substrate; A first conductive layer disposed on a side of the first passivation layer away from the substrate; and A second passivation layer is disposed on a side of the first conductive layer away from the substrate. Wherein, the array substrate comprises a plurality of array units, the plurality of array units are distributed in an array on the base substrate, at least one of the array units comprises a light emitting diode, and the light emitting diode comprises a first electrode and a second electrode; The array substrate comprises a plurality of pad pairs, the plurality of pad pairs are located in the first conductive layer, at least one of the pad pairs comprises a first pad and a second pad, the first pad is used to be electrically connected to the first electrode, and the second pad is used to be electrically connected to the second electrode; The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first sub-passivation layer is located on the base substrate, the second sub-passivation layer is located on a side of the first sub-passivation layer away from the base substrate, and at least a portion of the second sub-passivation layer contacts at least a portion of a plurality of pad pairs located on the first conductive layer; The thickness of the first conductive layer is greater than the thickness of the first sub-passivation layer, and the thickness of the first conductive layer is greater than the thickness of the second sub-passivation layer; and A material of the first sub-passivation layer is the same as a material of the second sub-passivation layer, and a refractive index of the first sub-passivation layer is different from a refractive index of the second sub-passivation layer.

2. The array substrate according to claim 1, wherein: The refractive index of the second sub-passivation layer is greater than the refractive index of the first sub-passivation layer.

3. The array substrate according to claim 1 or 2, wherein: The ratio of the thickness of the first sub-passivation layer to the thickness of the second sub-passivation layer is between 0.8 and 1.2; and / or, The ratio of the sum of the thickness of the first sub-passivation layer and the second sub-passivation layer to the thickness of the first conductive layer is greater than 0.15; and / or, The sum of the thickness of the first sub-passivation layer and the second sub-passivation layer is greater than or equal to 4500 angstroms.

4. The array substrate according to any one of claims 1 to 3, wherein: The thickness of the first conductive layer is greater than or equal to 1.8 micrometers; or, The thickness of the first conductive layer is greater than or equal to 3 micrometers.

5. The array substrate according to any one of claims 1 to 4, wherein: The surface roughness of the first conductive layer is between 8-15.

6. The array substrate according to any one of claims 1 to 5, wherein: The first passivation layer includes a bottom surface close to the base substrate, a top surface away from the base substrate, and a side wall connecting the bottom surface and the top surface. The side wall of the first passivation layer is inclined at a first inclination angle relative to the bottom surface, and the first inclination angle is less than or equal to 40°.

7. The array substrate according to claim 4, wherein: The first conductive layer has a stacked structure, the stacked structure of the first conductive layer includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is located on a side of the first passivation layer away from the base substrate, the second sub-conductive layer is located on a side of the first sub-conductive layer away from the base substrate, and the third sub-conductive layer is located on a side of the second sub-conductive layer away from the base substrate; The first sub-conductive layer and the third sub-conductive layer are made of the same material, and the second sub-conductive layer and the third sub-conductive layer are made of different materials; as well as The orthographic projection of the third sub-conductive layer on the base substrate falls within the orthographic projection of the second sub-conductive layer on the base substrate; and / or the orthographic projection of the second sub-conductive layer on the base substrate falls within the orthographic projection of the first sub-conductive layer on the base substrate.

8. The array substrate according to any one of claims 1 to 7, wherein: The array substrate further includes a second conductive layer, and the second conductive layer is located on a side of the first passivation layer close to the base substrate; and The thickness of the second conductive layer is smaller than the thickness of the first conductive layer.

9. The array substrate according to any one of claims 1 to 8, wherein: The array substrate further comprises a plurality of terminals, the plurality of terminals are located in the first conductive layer, and the plurality of terminals are used to be electrically connected to the pins of the driving chip; and The array substrate further includes a plurality of conductive connection portions, wherein the plurality of conductive connection portions are located in the first conductive layer, and at least one of the conductive connection portions electrically connects at least one of the terminals with at least one of the first pads.

10. The array substrate according to claim 9, wherein: The array substrate further comprises a plurality of wirings, and the plurality of wirings are located in the second conductive layer; The array substrate further includes: a via hole located in the first passivation layer; and a conductive portion located in the first conductive layer; and One end of the conductive portion is electrically connected to at least one of the second pads, and at least one of the traces is electrically connected to the conductive portion through the via hole.

11. The array substrate according to claim 10, wherein: The plurality of terminals include a first terminal, the first terminal being used to be electrically connected to a ground signal pin of the driving chip; The plurality of routing lines include a first routing line, the first routing line being used to transmit a ground signal; and The via includes a plurality of first vias, the conductive portion includes a first conductive portion, the first trace is electrically connected to the first conductive portion through the plurality of first vias, the other end of the first conductive portion is electrically connected to the first terminal, and the orthographic projections of the plurality of first vias on the base substrate are arranged side by side along a first direction within the orthographic projection of the first conductive portion on the base substrate.

12. The array substrate according to claim 11, wherein: The array substrate further includes a grounding line, the grounding line is located in the first conductive layer, the grounding line extends along a first direction, the first routing line extends along a second direction, and the first direction and the second direction intersect; The vias include a plurality of second vias, the first trace is electrically connected to the ground line through the plurality of second vias, and the orthographic projections of the plurality of second vias on the base substrate are arranged side by side along a first direction within the orthographic projection of the ground line on the base substrate.

13. The array substrate according to any one of claims 9 to 12, wherein: The array unit is a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; The plurality of terminals further include a second terminal, a third terminal and a fourth terminal, the plurality of pad pairs include a first pad pair, a second pad pair and a third pad pair, the first pad and the second pad of the first pad pair being used to be electrically connected to the first electrode and the second electrode of the first light-emitting diode, respectively, the first pad and the second pad of the second pad pair being used to be electrically connected to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair being used to be electrically connected to the first electrode and the second electrode of the third light-emitting diode, respectively; and The conductive connection part includes a first conductive connection part, a second conductive connection part and a third conductive connection part. The second terminal is electrically connected to the first pad of the first pad pair through the first conductive connection part, the third terminal is electrically connected to the first pad of the second pad pair through the second conductive connection part, and the fourth terminal is electrically connected to the first pad of the third pad pair through the third conductive connection part.

14. The array substrate according to claim 13, wherein: The plurality of wirings further include a second wiring and a third wiring, the second wiring is used to transmit a first voltage signal to the first light emitting diode, and the third wiring is used to transmit a second voltage signal to the second light emitting diode and the third light emitting diode; The via includes a third via and a plurality of fourth vias, the conductive portion includes a second conductive portion and a third conductive portion, the second routing is electrically connected to one end of the second conductive portion through the third via, the other end of the second conductive portion is electrically connected to the second pad of the first pad pair, the third routing is electrically connected to the third conductive portion through the plurality of fourth vias, the third conductive portion is electrically connected to both the second pad of the second pad pair and the second pad of the third pad pair, and the orthographic projections of the plurality of fourth vias on the substrate are arranged side by side along the second direction within the orthographic projection of the third conductive portion on the substrate.

15. The array substrate according to any one of claims 9 to 12, wherein: The array unit is a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; The plurality of pad pairs include a first pad pair, a second pad pair, and a third pad pair, wherein the first pad and the second pad of the first pad pair are respectively electrically connected to the first electrode and the second electrode of the first light-emitting diode, the first pad and the second pad of the second pad pair are respectively electrically connected to the first electrode and the second electrode of the second light-emitting diode, and the first pad and the second pad of the third pad pair are respectively electrically connected to the first electrode and the second electrode of the third light-emitting diode; and The array substrate includes a first voltage signal line and a second voltage signal line located in the first conductive layer, the first pad of the first pad pair is electrically connected to the first voltage signal line, the first pad of the second pad pair and the first pad of the third pad pair are both electrically connected to the second voltage signal line, and the first pad pair, the second pad pair and the third pad pair are located between the first voltage signal line and the second voltage signal line in a first direction.

16. An array substrate, characterized in that: The array substrate comprises: substrate substrate; A first passivation layer disposed on the substrate; A first conductive layer disposed on a side of the first passivation layer away from the substrate; and A second passivation layer is disposed on a side of the first conductive layer away from the substrate. Wherein, the array substrate comprises a plurality of array units, the plurality of array units are distributed in an array on the base substrate, at least one of the array units comprises a light emitting diode, and the light emitting diode comprises a first electrode and a second electrode; The array substrate comprises a plurality of pad pairs, the plurality of pad pairs are located in the first conductive layer, at least one of the pad pairs comprises a first pad and a second pad, the first pad is used to be electrically connected to the first electrode, and the second pad is used to be electrically connected to the second electrode; The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first sub-passivation layer is located on the base substrate, the second sub-passivation layer is located on a side of the first sub-passivation layer away from the base substrate, and at least a portion of the second sub-passivation layer contacts at least a portion of a plurality of pad pairs located on the first conductive layer; The thickness of the first conductive layer is greater than the thickness of the first sub-passivation layer, and the thickness of the first conductive layer is greater than the thickness of the second sub-passivation layer; and The first conductive layer is formed on the surface of the second sub-passivation layer away from the base substrate by an electroplating process.

17. The array substrate according to claim 16, wherein: The thickness of the first conductive layer is greater than or equal to 3 micrometers.

18. The array substrate according to claim 16 or 17, wherein: The surface roughness of the first conductive layer is between 8-15.

19. A display device, wherein: The display device comprises the array substrate according to any one of claims 1 to 18.

20. A method for preparing an array substrate, characterized in that: The preparation method comprises: providing a substrate base plate; forming a first passivation layer on the base substrate; forming a first conductive material layer on a side of the first passivation layer away from the substrate; Performing a patterning process on the first conductive material layer to form a plurality of pad pairs, wherein at least one of the pad pairs includes a first pad and a second pad, the first pad being used to be electrically connected to a first electrode of a light-emitting diode, and the second pad being used to be electrically connected to a second electrode of the light-emitting diode; and forming a second passivation layer on a side of the plurality of pad pairs away from the substrate; Wherein, forming a first passivation layer on the base substrate comprises: forming a first sub-passivation material layer on the base substrate; forming a second sub-passivation material layer on a side of the first sub-passivation material layer away from the base substrate; performing a first etching on the second sub-passivation material layer to form a second sub-passivation layer; and performing a second etching on the first sub-passivation material layer to form a first sub-passivation layer, wherein the thickness of the first conductive layer is greater than the thickness of the first sub-passivation layer, and the thickness of the first conductive layer is greater than the thickness of the second sub-passivation layer; and A material of the first sub-passivation layer is the same as a material of the second sub-passivation layer, and a refractive index of the first sub-passivation layer is different from a refractive index of the second sub-passivation layer.

21. The method of claim 20, wherein: The forming of a first conductive material layer on a side of the first passivation layer away from the substrate comprises: A copper layer is electroplated on a surface of the second sub-passivation layer away from the base substrate to form the first conductive material layer.

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