Semiconductor device and method for producing semiconductor device

Abstract

Provided are a storage device that allows for high integration and a semiconductor device that includes the storage device. A semiconductor device according to the present invention comprises a capacitive element, a first transistor, and a second transistor. The capacitive element has a first conductive layer, a second conductive layer which is on the first conductive layer, and a first insulating layer which has a region positioned between the first conductive layer and the second conductive layer. Provided on the first insulating layer is a third conductive layer which functions as one of a source electrode and a drain electrode of the first transistor. The third conductive layer contains the same material as the second conductive layer. A fourth conductive layer, which functions as the other one of the source electrode and the drain electrode of the first transistor, is positioned above the third conductive layer. A fifth conductive layer, which functions as a gate electrode of the first transistor, has a region in contact with the second conductive layer. The third conductive layer has a region which functions as a source electrode or a drain electrode of the second transistor.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One aspect of the present invention relates to a memory device. 2. Description of the Related Art One aspect of the present invention relates to a semiconductor device including a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] Nonvolatile storage devices are incorporated into a variety of portable devices, including smartphones and tablet devices, wristwatch-type devices, and wearable devices for AR (Augmented Reality) or VR (Virtual Reality). While hard disk drives have been the primary nonvolatile storage devices up until now, flash memory is now widely used in the portable devices mentioned above because it is shock-resistant, can be made smaller, is lightweight, and does not require physical operation.

[0004] Meanwhile, a transistor having an oxide semiconductor or a metal oxide in a channel formation region (also referred to as an oxide semiconductor transistor or an OS (oxide semiconductor) transistor) is known. An OS transistor has a characteristic that its drain current when the transistor is in an off state (also referred to as an off-state current) is extremely small. Patent Document 1 discloses a NAND memory device using an OS transistor.

[0005] US Patent Application Publication No. 2022 / 0068967

[0006] For nonvolatile memory devices used as storage, the larger the storage capacity, the more desirable it is, and high integration is desirable. For memory elements used in nonvolatile memory devices, high rewrite durability and low-voltage operation are desirable.

[0007] An object of one embodiment of the present invention is to provide a memory device that can be highly integrated and a semiconductor device including the memory device.An object of one embodiment of the present invention is to provide a memory element that has high rewrite endurance and a semiconductor device including the memory element.An object of one embodiment of the present invention is to provide a memory element that can be driven at a low voltage and a semiconductor device including the memory element.

[0008] An object of one embodiment of the present invention is to provide a highly reliable memory device or semiconductor device.An object of one embodiment of the present invention is to provide a memory device or semiconductor device having a novel structure.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One aspect of the present invention is a semiconductor device comprising: a first conductive layer; a first insulating layer disposed on the first conductive layer and having a first opening with a region overlapping the first conductive layer; a second conductive layer in contact with a side surface of the first insulating layer and an upper surface of the first conductive layer in the first opening; a second insulating layer disposed on the second conductive layer and the first insulating layer; a third conductive layer disposed on the second insulating layer and having a region embedded in the first opening via the second insulating layer and the second conductive layer; a fourth conductive layer disposed on the second insulating layer and spaced apart from the third conductive layer; A semiconductor device includes: a third insulating layer having a second opening having a region overlapping with the third conductive layer and a third opening having a region overlapping with the fourth conductive layer; a fifth conductive layer on the third insulating layer and having a fourth opening overlapping with the third opening; an oxide semiconductor layer in contact with a top surface of the fifth conductive layer, a side surface of the fifth conductive layer in the fourth opening, a side surface of the third insulating layer in the third opening, and a top surface of the fourth conductive layer in the third opening; a fourth insulating layer disposed on the oxide semiconductor layer and the third insulating layer and having a fifth opening overlapping with the second opening; and a sixth conductive layer on the fourth insulating layer. The sixth conductive layer has a region embedded in the third opening and the fourth opening via the fourth insulating layer and the oxide semiconductor layer, and a region in contact with the third conductive layer in the fifth opening and the second opening. The fourth conductive layer is made of the same material as the third conductive layer.

[0011] It is preferable that the semiconductor device includes a seventh conductive layer on the second insulating layer and an eighth conductive layer on the fourth insulating layer, the third insulating layer has a sixth opening having a region overlapping with the seventh conductive layer, the fifth conductive layer has a seventh opening overlapping with the sixth opening, the oxide semiconductor layer has a region in contact with a side surface of the fifth conductive layer in the seventh opening, a side surface of the third insulating layer in the sixth opening, and an upper surface of the seventh conductive layer in the sixth opening, and the eighth conductive layer has a region embedded in the seventh opening and the sixth opening via the fourth insulating layer and the oxide semiconductor layer.

[0012] In the above semiconductor device, the seventh conductive layer preferably has the same material as the third conductive layer.

[0013] In the above semiconductor device, the eighth conductive layer preferably has the same material as the sixth conductive layer.

[0014] In the above semiconductor device, the second insulating layer preferably contains a ferroelectric material.

[0015] In the above semiconductor device, the second insulating layer preferably contains hafnium, zirconium, and oxygen.

[0016] In the above semiconductor device, the second insulating layer preferably further contains one or more elements selected from scandium, yttrium, and lanthanum.

[0017] In the above semiconductor device, the oxide semiconductor layer preferably contains indium and oxygen.

[0018] One embodiment of the present invention is a semiconductor device including a capacitor, a first transistor, and a second transistor. The capacitor includes a first conductive layer, a second conductive layer over the first conductive layer, and a first insulating layer having a region located between the first conductive layer and the second conductive layer. A third conductive layer functioning as one of a source electrode and a drain electrode of the first transistor is provided over the first insulating layer. The third conductive layer has the same material as the second conductive layer. A fourth conductive layer functioning as the other of the source electrode and drain electrode of the first transistor is located above the third conductive layer and has a region overlapping with the third conductive layer. A fifth conductive layer functioning as a gate electrode of the first transistor has a region in contact with the second conductive layer. The third conductive layer has a region functioning as one of the source electrode and drain electrode of the second transistor.

[0019] In the above semiconductor device, the second conductive layer preferably has a region facing a side surface of the first conductive layer with the first insulating layer interposed therebetween.

[0020] In the above semiconductor device, the first insulating layer preferably includes a ferroelectric material.

[0021] In the above semiconductor device, the first insulating layer preferably contains hafnium, zirconium, and oxygen.

[0022] In the above semiconductor device, the first insulating layer preferably further contains one or more elements selected from scandium, yttrium, and lanthanum.

[0023] In the above semiconductor device, it is preferable that the first transistor is arranged above the first insulating layer and has a semiconductor layer having a region in contact with the third conductive layer and the fourth conductive layer, and the semiconductor layer contains indium and oxygen.

[0024] One embodiment of the present invention includes forming a first conductive layer, forming a first insulating layer having a first opening that overlaps with the first conductive layer, forming a second conductive layer in contact with a side surface of the first insulating layer and an upper surface of the first conductive layer in the first opening, forming a second insulating layer on the second conductive layer and the first insulating layer, forming a first conductive film on the second insulating layer, processing the first conductive film to form a third conductive layer and a fourth conductive layer that are arranged to fill the first opening, and forming a third insulating layer on the third conductive layer, the fourth conductive layer, and the second insulating layer. a second conductive film over the third insulating layer; a second opening having a region overlapping with a fourth conductive layer in the second conductive film and the third insulating layer; an oxide semiconductor layer in contact with a side surface of the second conductive film, a side surface of the third insulating layer, and a top surface of the fourth conductive layer in the second opening; a fourth insulating layer over the oxide semiconductor layer; a third opening having a region overlapping with the third conductive layer in the fourth insulating layer and the third insulating layer; and a fifth conductive layer so as to fill the second opening and the third opening.

[0025] In the above-described method for manufacturing a semiconductor device, it is preferable that the second insulating layer be an oxide film containing hafnium and zirconium formed by atomic layer deposition.

[0026] In the above-described method for manufacturing a semiconductor device, an oxide film containing at least one element selected from scandium, yttrium, and lanthanum in addition to hafnium and zirconium is preferably formed as the second insulating layer by atomic layer deposition.

[0027] In the above method for manufacturing a semiconductor device, heat treatment is preferably performed at a temperature higher than or equal to 300° C. and lower than or equal to 750° C. using an RTA apparatus after the second insulating layer is formed and before the oxide semiconductor layer is formed.

[0028] In the above-described method for manufacturing a semiconductor device, the oxide semiconductor layer is preferably formed using an oxide film containing indium by an atomic layer deposition method.

[0029] According to one embodiment of the present invention, a memory device capable of high integration and a semiconductor device including the memory device can be provided. According to one embodiment of the present invention, a memory element having high rewrite endurance and a semiconductor device including the memory element can be provided. According to one embodiment of the present invention, a memory element that can be driven at a low voltage and a semiconductor device including the memory element can be provided.

[0030] According to one aspect of the present invention, a highly reliable memory device or semiconductor device can be provided. According to one aspect of the present invention, a memory device or semiconductor device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be at least alleviated.

[0031] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0032] FIGS. 1A to 1C are configuration examples of a memory device. FIGS. 2A to 2E are configuration examples of a memory device. FIGS. 3A to 3C are configuration examples of a memory device. FIGS. 4A to 4C are configuration examples of a memory device. FIGS. 5A to 5C are configuration examples of a memory device. FIG. 6 is a diagram showing characteristics of a ferroelectric material. FIGS. 7A to 7D are configuration examples of a memory device. FIGS. 8A to 8D are configuration examples of a memory device. FIGS. 9A to 9D are configuration examples of a memory device. FIGS. 10A to 10D are configuration examples of a memory device. FIGS. 11A to 11D are configuration examples of a memory device. FIGS. 12A to 12D are configuration examples of a memory device. FIGS. 13A to 13D are configuration examples of a memory device. FIGS. 14A to 14F are diagrams explaining a method for manufacturing a memory device. FIGS. 15A to 15F are diagrams explaining a method for manufacturing a memory device. FIGS. 16A to 16F are diagrams explaining a method for manufacturing a memory device. 17A to 17F are diagrams illustrating a manufacturing method of a memory device. FIG. 18 is a configuration example of a memory device. FIG. 19 is a configuration example of a memory device. FIGS. 20A to 20C are configuration examples of an arithmetic processing unit. FIGS. 21A to 21D are configuration examples of an arithmetic processing unit. FIGS. 22A and 22B are configuration examples of a semiconductor device. FIG. 23 is a configuration example of a semiconductor device. FIG. 24 is a configuration example of a semiconductor device. FIG. 25 is a configuration example of a semiconductor device. FIG. 26 is a configuration example of a semiconductor device. FIGS. 27A and 27B are diagrams showing various memory devices by layer. FIGS. 28A to 28J are configuration examples of electronic devices. FIGS. 29A to 29H are configuration examples of electronic devices.

[0033] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0034] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0035] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0036] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0037] Embodiment 1 In this embodiment, a semiconductor device and a memory device according to one embodiment of the present invention will be described.

[0038] A semiconductor device according to one embodiment of the present invention functions as a storage device and includes a nonvolatile memory element. For example, it is preferable to use a large-capacity memory device having a so-called three-dimensional structure in which memory elements are arranged not only in a plane direction but also stacked in a thickness direction. As a more specific example, a NAND memory device including memory strings extending in a direction parallel to a formation surface can be used.

[0039] Furthermore, a memory element using a ferroelectric substance can be used as a nonvolatile memory element. This makes it possible to realize a memory device that is more reliable and consumes less power than a so-called charge trap type memory element. Note that a memory element using an antiferroelectric substance may be used in addition to a ferroelectric substance.

[0040] A nonvolatile memory element included in a semiconductor device according to one embodiment of the present invention has a structure in which a ferroelectric capacitor is connected to a gate of a transistor. Furthermore, an oxide containing hafnium and zirconium is preferably used as a ferroelectric layer provided between a pair of electrodes of the ferroelectric capacitor. In particular, an oxide to which one or more elements selected from yttrium, lanthanum, and scandium are added is preferably used. Furthermore, in a manufacturing process of the memory element, heat treatment at a temperature of 300° C. to 750° C. is preferably performed while the ferroelectric layer is in contact with at least one electrode, preferably while the ferroelectric layer is in contact with a pair of electrodes. This allows for low-voltage operation (writing and reading) and a memory element with extremely high rewrite endurance.

[0041] When an oxide semiconductor is used for a semiconductor layer of a transistor, the oxide semiconductor may be polycrystallized by the heat treatment, which may reduce the reliability of the transistor. Therefore, in one embodiment of the present invention, a semiconductor layer is formed after a ferroelectric capacitor is formed. This prevents the oxide semiconductor from being polycrystallized, thereby achieving a highly reliable transistor. In other words, the range of materials available for each component (typically, the semiconductor layer) of a transistor can be expanded.

[0042] In one embodiment of the present invention, some of the components of the ferroelectric capacitor and some of the components of the transistor are formed through the same process. Specifically, one of a pair of electrodes of the ferroelectric capacitor and a source electrode or a drain electrode of the transistor are formed through the same process. This can reduce the number of processes, improve yield, and reduce costs.

[0043] In addition, in a transistor included in a semiconductor device according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flowing through a semiconductor layer flows in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor can also be called a vertical field effect transistor (VFET), a vertical transistor, a vertical channel transistor, or the like. Since a source electrode, a semiconductor layer, and a drain electrode of a vertical transistor can be provided so as to overlap with each other, the vertical transistor can occupy a significantly smaller area than a so-called planar transistor (which can also be called a lateral transistor, LFET (lateral FET), or the like) in which a semiconductor layer is arranged on a plane.

[0044] Another embodiment of the present invention is a semiconductor device in which the memory device is stacked over a substrate on which one or more driver circuits or control circuits are provided. With such a configuration, the wiring length between the memory device and the various circuits can be significantly shorter than when these circuits are arranged side by side or when these circuits are formed of different chips and mounted on a printed circuit board or the like. This allows for an increase in the amount of data exchanged between them per unit time.

[0045] Furthermore, in one embodiment of the present invention, two types of memory devices, that is, the memory device (also referred to as a first memory device) and a different memory device (also referred to as a second memory device), may be stacked. This significantly reduces the wiring length between the first memory device and the second memory device, thereby increasing the amount of data exchanged between them per unit time.

[0046] The second storage device is preferably a storage device with a higher access speed than the first storage device. The second storage device may be a volatile storage device that loses information when power supply is stopped. As a more specific example, a dynamic random access memory (DRAM) can be used. For example, when performing an operation such as reading data stored in a first storage device used as storage to a second storage device, which is a higher-level memory device, and then sending the data to a processor, the operating speed can be made extremely fast.

[0047] As the second memory device, it is more preferable to use a memory device using a transistor (OS transistor) in which an oxide semiconductor is used for a channel formation region as a memory cell. Because OS transistors have a significantly small leakage current in an off state, memory devices using such transistors can retain data for a longer period of time than DRAMs, thereby reducing power consumption. Furthermore, since oxide semiconductors can be formed as thin films, OS transistors can be manufactured regardless of the surface on which they are formed. For example, an advantage of such a memory device is that a circuit including an OS transistor can be directly stacked on a semiconductor circuit including single-crystal silicon.

[0048] A more specific example will be described below with reference to the drawings.

[0049] 1A is a schematic perspective view of a storage device 21. In the drawings exemplified below, the X direction, Y direction, and Z direction, which are orthogonal to each other, may be indicated by arrows.

[0050] The memory device 21 is provided on an insulating layer 50 and has a plurality of memory strings 60. The memory strings 60 have a plurality of memory cells arranged in the X direction. The memory device 21 further has a plurality of conductive layers 51, at least one conductive layer 52, and at least one conductive layer 53, as well as a plurality of plugs 54, a plurality of plugs 55, and a plurality of plugs 56, which function as various wirings.

[0051] The memory strings 60 are arranged at equal intervals in the Y direction. In Fig. 1A, three memory strings 60 are shown as an example. In practice, however, it is preferable that the number of memory strings 60 arranged in the Y direction be greater than this.

[0052] One memory string 60 is provided to connect between plugs 54 and 55. For example, plug 54 is electrically connected to a bit line, and plug 55 is electrically connected to a source line. Furthermore, a plurality of conductive layers 51 are provided between plugs 54 and 55 when viewed from the Z direction. The conductive layers 51 function as control gate lines. Furthermore, a conductive layer 52 functioning as a selection line is provided between the conductive layer 51 adjacent to plug 54 and plug 54, and a conductive layer 53 functioning as a selection line is provided between the conductive layer 53 adjacent to plug 55 and plug 55. Furthermore, each of the plurality of conductive layers 51 is connected to one of the plurality of plugs 56.

[0053] The plug 54 and the conductive layer 52 extend in directions that intersect with each other. The plug 55 and the conductive layer 53 extend in directions that intersect with each other. The conductive layer 51 extends in a direction that intersects with the direction in which the memory string 60 extends.

[0054] 1A shows an example in which one memory string 60 has four memory cells, but the number of memory cells is not limited to this. Increasing the number of memory cells increases the data capacity of the storage device 21. The more memory cells that make up one memory string 60, the more preferable it is, and can be, for example, 32 or more, 64 or more, 128 or more, 160 or more, 192 or more, 224 or more, or 256 or more.

[0055] 1B shows an extracted configuration of one memory string 60 and its vicinity. A memory cell 65 is provided in the portion of the memory string 60 that overlaps with the conductive layer 51.

[0056] 1C is a circuit diagram of the configuration shown in FIG. 1B. The plug 54 is electrically connected to the wiring BL, the plug 55 is electrically connected to the wiring CL, and the plurality of conductive layers 51 are electrically connected to the wirings WL (wirings WL_1 to WL_n (n is an integer of 2 or more)). The conductive layer 52 corresponds to the wiring BSL, and the conductive layer 53 corresponds to the wiring SSL.

[0057] 1C, a transistor BTr, a plurality of memory cells MC, and a transistor STr are provided between a wiring BL and a wiring CL. The transistors BTr and STr each function as a selection transistor. The memory cell MC functions as one storage element.

[0058] The memory cell MC can be a memory element using a ferroelectric, such as a configuration in which a ferroelectric capacitor is connected to the gate or a configuration in which a ferroelectric is applied to a gate insulating layer. For example, a charge trap type flash memory or a floating gate type flash memory can also be used. In this embodiment, a memory cell having a configuration in which a ferroelectric capacitor is connected to the gate will be mainly described.

[0059] [Configuration Example of Memory String] A specific configuration example of a memory string that can be used in a storage device of one embodiment of the present invention will be described below.

[0060] The memory string 100 of one embodiment of the present invention can be used in a NAND memory device.

[0061] FIG. 2A is a plan view of the memory string 100 as viewed from the Z direction. FIG. 2A shows one memory string 100 extending in the X direction. FIG. 2B is an equivalent circuit of the memory string 100. The memory string 100 has a configuration in which multiple transistors are connected in series. Note that, for ease of explanation, the select transistors exemplified above are omitted here. In addition, some elements are omitted in the plan views shown below for clarity.

[0062] 2C and 2D are cross-sectional views of the portions A1-A2 and A3-A4 indicated by the dashed dotted lines in Fig. 2A as viewed from the Y direction, respectively. Fig. 2E is a cross-sectional view of the portion A5-A6 indicated by the dashed dotted lines in Fig. 2A as viewed from the X direction.

[0063] An insulating layer 140 is provided above a substrate (not shown), the memory string 100 is provided on the insulating layer 140 , and an insulating layer 283 is provided to cover the memory string 100 .

[0064] The memory string 100 has n memory cells MC (n is an integer equal to or greater than 2). In Figures 2A and 2B, in the X direction (A1-A2 direction), the first memory cell MC is shown as memory cell MC_1, and the nth memory cell MC is shown as memory cell MC_n.

[0065] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m, n]" may be added to the symbol. In this specification, when it is not necessary to distinguish between multiple elements, an identification symbol may not be used. For example, when it is not necessary to distinguish between memory cells MC_1 to MC_n, they may simply be referred to as "memory cells MC". Furthermore, in this specification, when referring to an arbitrary element, an identification symbol may not be used. For example, when referring to an arbitrary memory cell MC, they may simply be referred to as "memory cells MC".

[0066] The memory cells MC constituting the memory string 100 each include a transistor and a ferroelectric capacitor. The memory cells MC each have a configuration in which the ferroelectric capacitor is connected to the gate of the transistor. This configuration functions as a ferroelectric transistor (FeFET: Ferroelectric Field Effect Transistor). Another configuration of a ferroelectric transistor is one in which a ferroelectric is used for the insulating layer that functions as the gate insulating layer. The threshold voltage of a ferroelectric transistor can be changed by applying a voltage above a certain level to the gate. By using such memory cells MC, a NAND-type ferroelectric memory can be realized.

[0067] 2E, the transistor and capacitor included in the memory cell MC_1 are denoted as a transistor Tr_1 and a capacitor C_1, respectively. Similarly, the transistor and capacitor included in the memory cell MC_n are denoted as a transistor Tr_n and a capacitor C_n, respectively.

[0068] The memory string 100 includes n conductive layers 110, j conductive layers 220 (j is an integer of 1 to n), and k conductive layers 240 (k is an integer of 1 to n). In Figures 2A and 2C, in the X direction, the first conductive layer 110 is indicated as conductive layer 110_1, and the nth conductive layer 110 is indicated as conductive layer 110_n. Similarly, the first conductive layer 220 is indicated as conductive layer 220_1, and the jth conductive layer 220 is indicated as conductive layer 220_j. Similarly, the first conductive layer 240 is indicated as conductive layer 240_1, and the kth conductive layer 240 is indicated as conductive layer 240_k.

[0069] The memory string 100 includes k semiconductor layers 230. In Fig. 2C, the first semiconductor layer 230 in the X direction is shown as a semiconductor layer 230_1, and the kth semiconductor layer 230 is shown as a semiconductor layer 230_k.

[0070] In the transistor Tr, the conductive layer 220 and the conductive layer 240 function as a source electrode and a drain electrode, respectively. A channel is formed in the semiconductor layer 230.

[0071] A plurality of conductive layers 110 are provided on the insulating layer 140, an insulating layer 180 is provided on the insulating layer 140 and the plurality of conductive layers 110, a plurality of conductive layers 220 are provided above the insulating layer 180, an insulating layer 280 is provided above the insulating layer 180 and the plurality of conductive layers 220, and a plurality of conductive layers 240 are provided on the insulating layer 280. In other words, the conductive layer 240 is located above the conductive layer 220, and the source electrode and the drain electrode are located at different heights, so the transistor Tr is a vertical transistor.

[0072] 2C , the semiconductor layer 230_1 has a region in contact with the conductive layer 240_1 and a region in contact with the conductive layer 220_1, the semiconductor layer 230_2 has a region in contact with the conductive layer 240_2, a region in contact with the conductive layer 220_1, and a region in contact with the conductive layer 220_2. The semiconductor layer 230_k-1 has a region in contact with the conductive layer 240_k-1, a region in contact with the conductive layer 220_j, and a region in contact with the conductive layer 220_j-1 (not shown), and the semiconductor layer 230_k has a region in contact with the conductive layer 240_k and a region in contact with the conductive layer 220_j.

[0073] The conductive layer 240_1 is electrically connected to the wiring BL, and the conductive layer 240_k is electrically connected to the wiring CL. In this manner, the memory string 100 has a configuration in which a plurality of transistors are connected in series. In this case, the plurality of conductive layers 110 correspond to a plurality of wirings CG, respectively.

[0074] 2A to 2C has an even number of memory cells MC, j is n / 2, and k is (n / 2)+1.

[0075] 2A has a configuration in which the conductive layer 240_1 is electrically connected to the wiring BL via a first select transistor (not shown) or the like, and the conductive layer 240_k is electrically connected to the wiring CL via a second select transistor (not shown) or the like. Here, the first select transistor corresponds to the above-described transistor BTr, and the second select transistor corresponds to the above-described transistor STr. Note that the present invention is not limited to this.

[0076] 3A to 3C, the memory string 100 may have a configuration in which the conductive layer 220_1 is electrically connected to the wiring BL via a first select transistor (not shown) or the like, and the conductive layer 220_j is electrically connected to the wiring CL via a second select transistor (not shown) or the like. Note that FIG. 3A is a plan view of the memory string 100 as viewed from the Z direction, FIG. 3B is an equivalent circuit of the memory string 100, and FIG. 3C is a cross-sectional view of the portion A1-A2 indicated by the dashed-dotted line in FIG. 3A as viewed from the Y direction. Also, FIGS. 2D and 2E can be referred to, respectively, for a cross-sectional view of the portion A3-A4 indicated by the dashed-dotted line in FIG. 3A as viewed from the Y direction, and a cross-sectional view of the portion A5-A6 indicated by the dashed-dotted line in FIG. 3A as viewed from the X direction.

[0077] 3C , the semiconductor layer 230_1 has a region in contact with the conductive layer 240_1, a region in contact with the conductive layer 220_1, and a region in contact with the conductive layer 220_2, the semiconductor layer 230_2 has a region in contact with the conductive layer 240_2, a region in contact with the conductive layer 220_2, and a region in contact with the conductive layer 220_3 (not shown), and the semiconductor layer 230_k has a region in contact with the conductive layer 240_k, a region in contact with the conductive layer 220_j-1, and a region in contact with the conductive layer 220_j.

[0078] 3A to 3C has an even number of memory cells MC, j is (n / 2)+1, and k is n / 2.

[0079] 4A to 4C, the memory string 100 may have a configuration in which the conductive layer 240_1 is electrically connected to the wiring BL via a first select transistor (not shown) or the like, and the conductive layer 220_j is electrically connected to the wiring CL via a second select transistor (not shown) or the like. Note that FIG. 4A is a plan view of the memory string 100 as viewed from the Z direction, FIG. 4B is an equivalent circuit of the memory string 100, and FIG. 4C is a cross-sectional view of the portion A1-A2 indicated by the dashed-dotted line in FIG. 4A as viewed from the Y direction. Also, FIGS. 2D and 2E can be referred to, respectively, for a cross-sectional view of the portion A3-A4 indicated by the dashed-dotted line in FIG. 4A as viewed from the Y direction, and a cross-sectional view of the portion A5-A6 indicated by the dashed-dotted line in FIG. 4A as viewed from the X direction.

[0080] 4A to 4C has an odd number of memory cells MC, and j and k are each (n+1) / 2.

[0081] As described above, the memory string 100 shown in FIG. 2A and the memory string 100 shown in FIG. 4A have a configuration in which the memory cell MC_1 and the memory cell MC_2 share the conductive layer 220_1, and the memory cell MC_2 and the memory cell MC_3 share the conductive layer 240_2. Also, the memory string 100 shown in FIG. 3A has a configuration in which the memory cell MC_1 and the memory cell MC_2 share the conductive layer 240_1, and the memory cell MC_2 and the memory cell MC_3 share the conductive layer 220_2. Thus, the memory string 100 has a configuration in which adjacent memory cells MC in the X direction share one of the conductive layer 220 and the conductive layer 240. In other words, adjacent memory cells MC in the X direction share a part of their structure. This configuration reduces the area occupied by the memory string 100, allowing the memory strings 100 to be arranged at a high density, thereby increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0082] In other words, the memory string has a first memory cell and a second memory cell adjacent to the first memory cell, the first memory cell and the second memory cell have a first transistor and a second transistor, respectively, and a conductive layer functioning as one of the source electrode and drain electrode of the first transistor has a region functioning as one of the source electrode and drain electrode of the second transistor.

[0083] Note that the memory string of one embodiment of the present invention can also have a structure in which the memory cells MC adjacent to each other in the X direction do not share the conductive layer 220 or the conductive layer 240 .

[0084] Another configuration example of a memory string according to one embodiment of the present invention will be described with reference to Figures 5A to 5C. Figure 5A is a plan view of a memory string 100A as viewed from the Z direction, Figure 5B is an equivalent circuit of the memory string 100A, and Figure 5C is a cross-sectional view of a portion A1-A2 indicated by a dashed-dotted line in Figure 5A as viewed from the Y direction. Also, Figures 2D and 2E can be referred to for a cross-sectional view of a portion A3-A4 indicated by a dashed-dotted line in Figure 5A as viewed from the Y direction, and a cross-sectional view of a portion A5-A6 indicated by a dashed-dotted line in Figure 5A as viewed from the X direction, respectively.

[0085] The memory string 100A shown in FIGS. 5A to 5C differs from the memory string 100 described above in that it has (n−1) conductive layers 267 .

[0086] The conductive layer 267 is provided so as to be embedded in the insulating layer 280. The conductive layer 267_1 is in contact with part of the top surface of the conductive layer 220_1 and part of the bottom surface of the conductive layer 240_2. The conductive layer 267_2 is in contact with part of the top surface of the conductive layer 220_2 and part of the bottom surface of the conductive layer 240_3. The conductive layer 267_n-1 is in contact with part of the top surface of the conductive layer 220_j-1 and part of the bottom surface of the conductive layer 240_k. With this configuration, the memory string 100A has a configuration in which a plurality of transistors are connected in series.

[0087] 5A to 5C may have an even number or an odd number of memory cells, and j and k are each equal to n.

[0088] This concludes the explanation of the memory string.

[0089] Although the above description is directed to one memory string, the storage capacity can be increased by periodically arranging multiple memory strings with a common control gate, as shown in FIG. 1A and other figures.

[0090] [Configuration Example of Memory Cell] Specific configuration examples of memory cells that can be used in a memory device of one embodiment of the present invention are described below. As described above, a memory string of one embodiment of the present invention includes n memory cells MC (memory cells MC_1 to MC_n). First, a configuration example of the memory cell MC_1 will be described with reference to FIG. 2A and FIGS. 2C to 2E.

[0091] The memory cell MC_1 includes a capacitor C_1 and a transistor Tr_1.

[0092] The capacitor C_1 includes a conductive layer 115_1, an insulating layer 130, and a conductive layer 120_1. The insulating layer 130 has a region located between the conductive layer 115_1 and the conductive layer 120_1.

[0093] The transistor Tr_1 includes a conductive layer 220_1, a conductive layer 240_1, a semiconductor layer 230_1, an insulating layer 250, and a conductive layer 260_1.

[0094] The insulating layer 180 has an opening 190_1 that reaches the conductive layer 110_1. At this time, the opening 190_1 has a region that overlaps with the conductive layer 110_1.

[0095] The conductive layer 115_1 has a region disposed in the opening 190_1. The conductive layer 115_1 has a region in contact with the side surface of the insulating layer 180 and the top surface of the conductive layer 110_1 in the opening 190_1. The conductive layer 115_1 has a recess in a region overlapping with the opening 190_1. Note that in FIG. 2E, the conductive layer 115_1 has a region in contact with the top surface of the insulating layer 180 outside the opening 190_1.

[0096] The insulating layer 130 is provided over the conductive layer 115_1 and the insulating layer 180. The insulating layer 130 has a region disposed in the opening 190_1. The insulating layer 130 has a region that is in contact with the top surface of the conductive layer 115_1 in the opening 190_1. That is, the insulating layer 130 has a region formed along the recessed portion of the conductive layer 115_1. The insulating layer 130 has a recessed portion in a region that overlaps with the recessed portion of the conductive layer 115_1.

[0097] The conductive layer 120_1 and the conductive layer 220_1 are provided over the insulating layer 130. The conductive layer 220_1 is spaced apart from the conductive layer 220_1.

[0098] The conductive layer 120_1 has a region disposed in the opening 190_1. The conductive layer 120_1 has a region in contact with the top surface of the insulating layer 130 in the opening 190_1. The conductive layer 120_1 is provided so as to fill a recessed portion of the insulating layer 130. That is, the conductive layer 120_1 has a region that is filled in the opening 190_1 via the insulating layer 130 and the conductive layer 115_1. The conductive layer 120_1 also has a region that faces a side surface of the conductive layer 115_1 with the insulating layer 130 interposed therebetween.

[0099] Although the details will be described later, the conductive layer 120_1 and the conductive layer 220_1 are formed in the same process. Therefore, the conductive layer 220_1 has the same conductive material as the conductive layer 120_1.

[0100] The insulating layer 280 is provided over the conductive layer 120_1, the conductive layer 220_1, and the insulating layer 130. The insulating layer 280 has an opening 292_1 that reaches the conductive layer 120_1 and an opening 290_1 that reaches the conductive layer 220_1. In this case, the opening 292_1 has a region overlapping with the conductive layer 120_1, and the opening 290_1 has a region overlapping with the conductive layer 220_1.

[0101] The conductive layer 240_1 is provided over the insulating layer 280. That is, the conductive layer 240_1 is located above the conductive layer 220_1. The conductive layer 240_1 has a region overlapping with the conductive layer 220_1. The conductive layer 240_1 has an opening 291_1 overlapping with the opening 290_1.

[0102] The semiconductor layer 230_1 is disposed above the insulating layer 130. The semiconductor layer 230_1 has a region disposed in the opening 291_1 and the opening 290_1. The semiconductor layer 230_1 has a region in contact with the side surface of the conductive layer 240_1 in the opening 291_1, the side surface of the insulating layer 280 in the opening 290_1, and the top surface of the conductive layer 220_1 in the opening 290_1. That is, the semiconductor layer 230_1 has a region in contact with the conductive layer 220_1 and the conductive layer 240_1. The semiconductor layer 230_1 has recesses in the openings 291_1 and the opening 290_1. Note that in FIGS. 2C and 2E, the semiconductor layer 230_1 has a region in contact with the top surface of the conductive layer 240_1 outside the opening 291_1.

[0103] The insulating layer 250 is provided over the semiconductor layer 230_1 and the insulating layer 280. The insulating layer 250 is provided to cover the semiconductor layer 230_1 and the conductive layer 240_1.

[0104] The insulating layer 250 has regions disposed in the opening 291_1 and the opening 290_1. The insulating layer 250 has regions in contact with the top surface of the semiconductor layer 230_1 in the opening 291_1 and the opening 290_1. That is, the insulating layer 250 has a region formed along a recessed portion of the semiconductor layer 230_1. The insulating layer 250 has a recessed portion in a region overlapping with the recessed portion of the semiconductor layer 230_1. Furthermore, the insulating layer 250 has regions in contact with the side surface of the semiconductor layer 230_1 and the side surface of the conductive layer 240_1 outside the opening 291_1.

[0105] The insulating layer 250 has an opening 293_1 that overlaps with the opening 292_1.

[0106] The conductive layer 260_1 is provided over the insulating layer 250.

[0107] The conductive layer 260_1 has a region disposed in the opening 291_1 and the opening 290_1. The conductive layer 260_1 has a region in contact with the top surface of the insulating layer 250 in the opening 291_1 and the opening 290_1. The conductive layer 260_1 is provided so as to fill a recessed portion of the insulating layer 250. That is, the conductive layer 260_1 has a region filled in the opening 291_1 and the opening 290_1 with the insulating layer 250 and the semiconductor layer 230_1 interposed therebetween.

[0108] The conductive layer 260_1 is provided to fill the openings 293_1 and 292_1. That is, the conductive layer 260_1 has regions filled in the openings 293_1 and 292_1. The conductive layer 260_1 has regions in contact with the conductive layer 120_1 in the openings 293_1 and 292_1. The conductive layer 260_1 has regions in contact with the side surface of the insulating layer 250 in the opening 293_1, the side surface of the insulating layer 280 in the opening 292_1, and the top surface of the conductive layer 120_1 in the opening 292_1.

[0109] In the capacitor C_1, the conductive layer 115_1 functions as one of a pair of electrodes (also referred to as a lower electrode), the conductive layer 120_1 functions as the other of the pair of electrodes (also referred to as an upper electrode), and the insulating layer 130 functions as a dielectric.

[0110] The capacitor C_1 has a configuration in which a pair of electrodes face each other with a dielectric sandwiched between them not only on the bottom surface but also on the side surface inside the opening 190_1, which allows for a larger capacitance per unit area. Therefore, the deeper the opening 190_1, the larger the capacitance of the capacitor C_1 can be. Increasing the capacitance per unit area of ​​the capacitor C_1 in this way allows for miniaturization or higher integration of semiconductor devices.

[0111] In the transistor Tr_1, the conductive layer 260_1 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating layer. The conductive layer 220_1 functions as one of a source electrode and a drain electrode, and the conductive layer 240_1 functions as the other of the source electrode and the drain electrode. At least a part of the semiconductor layer 230_1 functions as a channel formation region. As described above, the transistor Tr_1 is a vertical transistor.

[0112] The channel length of the transistor Tr_1 is determined by the thickness of the insulating layer 280 over the conductive layer 220_1. The channel length is the distance between the edge of the region where the semiconductor layer 230_1 and the conductive layer 220_1 contact each other and the edge of the region where the semiconductor layer 230_1 and the conductive layer 240_1 contact each other in a cross-sectional view. In other words, the channel length corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0113] The channel length of the transistor Tr_1 can be precisely controlled by the thickness of the insulating layer 280, and therefore, the variation in the channel length can be significantly reduced compared to planar transistors. Furthermore, by thinning the insulating layer 280, a transistor with an extremely short channel length can also be manufactured. For example, a transistor with a channel length of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Therefore, a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure tool used in cutting-edge LSI technology.

[0114] Furthermore, since transistors with short channel lengths can be fabricated with high precision, the variation in characteristics among multiple transistors can be reduced. This stabilizes the operation of a semiconductor device including the transistor, improving its reliability. Furthermore, the reduction in the variation in characteristics increases the degree of freedom in the circuit design of the semiconductor device, allowing the operating voltage to be reduced. This reduces the power consumption of the semiconductor device.

[0115] In the opening 290_1, the semiconductor layer 230_1, the insulating layer 250, and the conductive layer 260_1 are provided concentrically. Therefore, the side surface of the conductive layer 260_1 provided in the center faces the side surface of the semiconductor layer 230_1 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire periphery of the semiconductor layer 230_1 becomes a channel formation region. In this case, for example, the channel width of the transistor Tr_1 is determined by the length of the outer periphery of the semiconductor layer 230_1. That is, it can be said that the channel width of the transistor Tr_1 is determined by the maximum width of the opening 290_1 (the diameter when the opening 290_1 is circular in a plan view). By increasing the maximum width of the opening 290_1, the channel width per unit area can be increased, and the on-current can be increased.

[0116] When the opening 290_1 is formed using photolithography, the maximum width of the opening 290_1 is limited by the exposure limit of photolithography. The maximum width of the opening 290_1 is set by the film thickness of each of the semiconductor layer 230_1, the insulating layer 250, and the conductive layer 260_1 provided in the opening 290_1. The maximum width of the opening 290_1 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290_1 is circular in plan view, the maximum width of the opening 290_1 corresponds to the diameter of the opening 290_1, and the channel width can be calculated as "D × π."

[0117] Furthermore, by forming the opening 290_1 so as to have a circular shape in a plan view, the semiconductor layer 230_1, the insulating layer 250, and the conductive layer 260_1 are provided concentrically. This makes the distance between the conductive layer 260_1 and the semiconductor layer 230_1 approximately uniform, allowing a gate electric field to be applied to the semiconductor layer 230_1 approximately uniformly.

[0118] The above is a description of an example of the configuration of the memory cell MC_1. The configurations of the memory cells MC_2 to MC_n are the same as the configuration of the memory cell MC_1. The configurations of the memory cells MC_2 to MC_n can be described by referring to the description of the configuration of the memory cell MC_1 by appropriately replacing the identification symbols.

[0119] 2A , for example, a memory cell MC_p (p is an integer greater than or equal to 1 and less than or equal to n) includes a conductive layer 115_p, an insulating layer 130, a conductive layer 120_p, a conductive layer 220_q, a conductive layer 240_r, a semiconductor layer 230_r, an insulating layer 250, and a conductive layer 260_p. When p is an odd number, q and r are each (p+1) / 2. When p is an even number, q is p / 2 and r is (p / 2)+1.

[0120] Next, matters common to the memory cells MC_1 to MC_n will be described.

[0121] A ferroelectric material can be used for the insulating layer 130. As a result, a ferroelectric capacitor is formed by the conductive layer 115, the conductive layer 120, and the insulating layer 130 located therebetween. Furthermore, the conductive layer 260 is electrically connected to the conductive layer 120. In this way, the memory cell MC has a configuration in which a ferroelectric capacitor is connected to the gate of the transistor Tr.

[0122] The insulating layer 130 is made of a material exhibiting ferroelectricity. Examples of ferroelectric materials include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use a material in which a Group 3 (IIIA) element is added to the oxide. For example, the oxide preferably contains one or more elements selected from the group consisting of scandium, yttrium, and lanthanides. Yttrium, lanthanum, and scandium are particularly preferred due to their relatively easy handling and high compatibility with semiconductor manufacturing processes. Adding such elements not only stabilizes ferroelectricity but also suppresses degradation of characteristics during repeated rewriting, improving reliability. For example, these elements are preferably added at a ratio of 0.5 at% to 10 at%. Other additive elements include silicon, aluminum, gadolinium, and scandium. The insulating layer 130 can be made of not only ferroelectric materials but also antiferroelectric materials.

[0123] Oxides containing one or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films prepared using thin film deposition methods such as sputtering and atomic layer deposition (ALD). Therefore, they have high compatibility with semiconductor manufacturing processes and can reduce manufacturing costs.

[0124] Furthermore, the insulating layer 130 may be made of piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or bismuth ferrite (BFO).

[0125] Alternatively, the insulating layer 130 may be made of an organic ferroelectric material such as polyvinylidene fluoride (PVDF) or a copolymer of vinylidene fluoride (VDF) and trifluoroethylene (TrFE).

[0126] The ferroelectric material may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the insulating layer 130 may have a layered structure made of multiple materials selected from the materials listed above.

[0127] Among these, hafnium oxide, hafnium zirconium oxide (HZO), and HZO containing yttrium (HZYO) are preferred as ferroelectric materials because they exhibit ferroelectricity even in thin films of only a few nanometers. By using a film containing hafnium oxide, HZO, or HZYO, the thickness of the insulating layer 130 can be set to 3 nm to 100 nm, preferably 3 nm to 50 nm, more preferably 3 nm to 20 nm, and even more preferably 4 nm to 10 nm. In particular, by setting the thickness of the insulating layer 130 to 3 nm to 20 nm or 4 nm to 10 nm, low-voltage operation (writing and reading) is possible, and a memory cell with extremely high rewrite endurance can be obtained.

[0128] When hafnium zirconium oxide is used as the ferroelectric material, it is preferable to form the film by the ALD method, particularly the thermal ALD method, and it is also preferable to use the ALD method (including the thermal ALD method) in which reactivity is enhanced by using plasma (PEALD method: Plasma Enhanced ALD method).

[0129] Furthermore, when using the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also called Hydro Carbon, HC) as a precursor. Either or both of hydrogen and carbon contained in the film may inhibit crystallization. Therefore, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the film. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Note that when hafnium zirconium oxide is used, the precursor may be HfCl ４ , ZrCl ４ Chlorine-based precursors such as the above may be used.

[0130] When an oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used as the insulating layer 130, the remanent polarization may be increased by adding an appropriate amount of carbon. In this case, it is preferable to add carbon to these oxides in a ratio of 0.5 at % to 10 at %, for example.

[0131] When hafnium zirconium oxide is used for the insulating layer 130, it is preferable to alternately deposit hafnium and zirconium in a 1:1 ratio using a thermal ALD method or an ALD method using plasma.

[0132] The oxidizing agent used in the thermal ALD method or the plasma-based ALD method is H ２ O or O ３ However, the oxidizing agent is not limited to this, and O ２ , O ３ , N ２ O, NO ２ , H ２ O and H ２ O ２ It may include one or more selected from the following.

[0133] The crystalline structure of the film used for the insulating layer 130 is not particularly limited as long as it does not have centrosymmetrical structure and has polarity. For example, a crystalline system other than a cubic system may be used. The film used for the insulating layer 130 may have a single crystalline structure, a polycrystalline structure, or a composite structure having an amorphous structure and a crystalline structure.

[0134] It is preferable to use a conductive material having a function of absorbing oxygen for one or both of the conductive layers 115 and 120 sandwiching the insulating layer 130. This allows oxygen to be absorbed from the insulating layer 130, thereby increasing the oxygen vacancy concentration in the insulating layer 130. Therefore, the remanent polarization of the insulating layer 130 can be increased. It is preferable to use a metal or an alloy as the conductive material having a function of absorbing oxygen. In particular, it is preferable to use tungsten, molybdenum, titanium, tantalum, or the like. Furthermore, tungsten is particularly preferable because it is easy to increase the remanent polarization of the insulating layer 130 from the viewpoint of stress.

[0135] It is also preferable to use a conductive material that does not easily diffuse oxygen for one or both of the conductive layers 115 and 120 that sandwich the insulating layer 130. This improves the withstand voltage of the insulating layer 130, and improves the rewrite durability of the ferroelectric capacitor. In particular, it is preferable to use a metal nitride such as titanium nitride or tantalum nitride.

[0136] The conductive layer 115 and the conductive layer 120 may each have a stacked structure. In this case, it is preferable to use a low-resistance conductive material on the side not in contact with the insulating layer 130. For example, a metal or alloy containing one or more selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like can be used. In particular, using a high-melting-point material such as tungsten, molybdenum, tantalum, ruthenium, or hafnium is preferable because the temperature of a subsequent heat treatment can be increased. Note that, in addition to the above low-resistance conductive material, oxide materials such as indium tin oxide, indium tin oxide containing silicon, indium zinc oxide, and indium gallium zinc oxide may also be used.

[0137] The layer exhibiting ferroelectricity used in the insulating layer 130 is also called a "ferroelectric layer." One of the differences between ferroelectrics and paraelectrics is that ferroelectrics have hysteresis in their voltage-polarization characteristics. FIG. 6 is a graph showing an example of voltage-polarization characteristics. In FIG. 6, the horizontal axis represents the voltage applied to the ferroelectric layer, and the vertical axis represents the polarization of the ferroelectric layer. Note that the electric field strength can be calculated by dividing the voltage by the thickness of the ferroelectric layer.

[0138] The hysteresis characteristics of the ferroelectric layer can be represented by a curve 71 and a curve 72. The two voltages at the two intersections of the curve 71 and the curve 72 are called saturation polarization voltages (VSP, −VSP), respectively.

[0139] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 71. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 72. Note that VSP may be called a "positive saturation polarization voltage" or a "first saturation polarization voltage," and -VSP may be called a "negative saturation polarization voltage" or a "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0140] Here, when the polarization of the ferroelectric layer changes according to the curve 71, the voltage at which the polarization becomes 0 is called the coercive voltage Vc, and when the polarization changes according to the curve 72, the voltage at which the polarization becomes 0 is called the coercive voltage -Vc. The values ​​of Vc and -Vc are between -VSP and VSP. The absolute values ​​of the two coercive voltages may be the same or different.

[0141] When a voltage exceeding the coercive voltage is applied to the ferroelectric layer, the polarization of the ferroelectric layer is likely to be reversed. In an FeFET, if the polarization of the ferroelectric layer is not to be reversed, the voltage applied between the gate and source (also referred to as "gate voltage" or "Vg") is set to be greater than or equal to -Vc and less than or equal to Vc. In order to control the on and off states of the FeFET without reversing the polarization of the ferroelectric layer, it is preferable that the absolute value of the coercive voltage is large.

[0142] The two polarizations when no voltage is applied to the ferroelectric layer (when the voltage is 0 V) ​​are called remanent polarizations (Pr, −Pr). The larger the absolute value of the difference between Pr and −Pr (2Pr), the greater the fluctuation range of the threshold voltage in the FeFET due to polarization reversal, which is preferable.

[0143] The semiconductor layer 230 functions as a semiconductor layer in which a channel of the transistor Tr is formed. The semiconductor layer 230 can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0144] The semiconductor layer used in the transistor may be a single semiconductor layer or a stack of semiconductor layers. When the semiconductor layers are stacked, semiconductor materials having different crystal states may be used for each layer, or different semiconductor materials may be used for each layer.

[0145] The transistor Tr is particularly preferably a transistor (OS transistor) using a metal oxide (oxide semiconductor) functioning as a semiconductor for the semiconductor layer 230 in which a channel is formed. Because the band gap of an oxide semiconductor is 2 eV or more, the off-state current of an OS transistor is significantly small. Therefore, the power consumption of the memory string 100 can be reduced. Therefore, the power consumption of a semiconductor device including the memory string 100 can be reduced.

[0146] Furthermore, while polycrystalline silicon transistors exhibit variations in threshold voltage due to grain boundaries, OS transistors are less affected by grain boundaries and exhibit small variations in threshold voltage. Therefore, by using an OS transistor as the transistor Tr, malfunctions of the memory string 100 due to variations in threshold voltage can be suppressed.

[0147] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, the off-state current hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in ambient temperatures above room temperature and below 200° C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Therefore, the memory string 100 including the OS memory operates stably even in high-temperature environments and has high reliability. Furthermore, OS transistors have a high withstand voltage between the source and drain. By using OS transistors as the transistors constituting the memory string 100, the memory string 100 can be realized as one with stable operation and high reliability even in high-temperature environments. Therefore, the reliability of a semiconductor device including the memory string 100 can be improved.

[0148] Examples of metal oxides that can be used for the semiconductor layer 230 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred.

[0149] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of element M. Examples of atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and compositions in the vicinity thereof. Note that the term "nearby compositions" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of the transistor can be increased.

[0150] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of the element M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0151] The semiconductor layer 230 can be made of, for example, In oxide, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, etc. When these oxides are used as the semiconductor layer 230, the semiconductor layer 230 contains indium and oxygen. Ga—Zn oxide may also be used. Using a material that does not contain Zn, such as indium oxide, is preferable because it enhances compatibility with the LSI manufacturing process. On the other hand, using a material that contains Zn is preferable because it facilitates high crystallinity.

[0152] In particular, it is preferable to use an In-Zn oxide in which the atomic ratio of metal elements is In:Zn=4:1, In:Zn=2:1, or a similar ratio, or an In-Sn-Zn oxide in which the atomic ratio of metal elements is In:Sn:Zn=4:0.1:1, In:Sn:Zn=2:0.1:1, or a similar ratio, because the field-effect mobility of the transistor can be suitably increased.

[0153] Note that the metal oxide may contain one or more metal elements with a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0154] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0155] The metal oxide can be preferably formed by sputtering or ALD. It is particularly preferable to form the metal oxide film by ALD, which has excellent coverage. When forming the metal oxide by sputtering, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0156] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0157] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0158] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 230, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when a metal oxide containing Ga is used, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0159] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0160] Furthermore, by increasing the Zn content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability.

[0161] The semiconductor layer 230 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 230 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. Note that a stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, metal oxide layers whose compositions continuously vary in the thickness direction can also be formed. This not only broadens the range of design options compared to when a film with a fixed composition is used, but also makes it possible to prevent the generation of interface states or the like between two layers with different compositions, thereby improving electrical characteristics and reliability.

[0162] A crystalline metal oxide layer is preferably used for the semiconductor layer 230. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 230, the density of defect states in the semiconductor layer 230 can be reduced, and a highly reliable semiconductor device can be realized.

[0163] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 230, the more the density of defect states in the semiconductor layer 230 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0164] Silicon can be used as the semiconductor layer 230. In this case, examples of silicon that can be used include single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, and polycrystalline silicon. In addition to metal oxides and silicon, compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe can also be used as the semiconductor layer 230 in some cases.

[0165] When silicon is used for the semiconductor layer 230, the conductive layers 220 and 240 are preferably silicon doped with impurities. The impurities can be n-type impurities (donors). Examples of n-type impurities include phosphorus and arsenic. Alternatively, p-type impurities (acceptors) can be used. Examples of p-type impurities include boron, aluminum, and gallium. Examples of silicon that can be used include single-crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, and polycrystalline silicon. By using silicon containing such impurities, when the semiconductor layer 230 is crystallized using a catalytic element such as nickel, the conductive layers 220 and 240 can be used as gettering layers that absorb the catalytic element. In addition to silicon, metal oxides with high carrier concentrations can also be used for the conductive layers 220 and 240. Compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe can also be used.

[0166] The material applied to the conductive layer 220 and the conductive layer 240 is preferably the same as the material applied to the semiconductor layer 230. That is, when silicon is used for the semiconductor layer 230, silicon is preferably used for the conductive layer 220 and the conductive layer 240. When a metal oxide is used for the semiconductor layer 230, a conductive metal oxide is preferably used for the conductive layer 220 and the conductive layer 240. In this case, the carrier concentration of the conductive layer 220 and the conductive layer 240 is preferably higher than that of the semiconductor layer 230.

[0167] For the conductive layers (conductive layer 110, conductive layer 115, conductive layer 120, conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. A semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may also be used. A conductive material containing a metal element such as titanium or tantalum and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. For example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon, etc. may also be used. Alternatively, for example, nitrogen-containing indium gallium zinc oxide may be used, which may be able to capture hydrogen or water mixed in from surrounding insulators.

[0168] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 140, insulating layer 180, insulating layer 250, insulating layer 280, insulating layer 283, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0169] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0170] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0171] In this embodiment, an example has been shown in which the opening 290 is circular in plan view, but the present invention is not limited to this. For example, the opening 290 may be approximately circular in plan view, such as an ellipse, polygonal in plan view, such as a rectangle, or polygonal in plan view with rounded corners. In this case, the maximum width of the opening 290 can be calculated appropriately according to the shape of the top of the opening 290. For example, if the opening is rectangular in plan view, the maximum width of the opening 290 is the length of the diagonal line at the top of the opening 290. The same applies to the openings 190, 291, 292, and 293.

[0172] The above is a description of memory cells applicable to memory strings.

[0173] [Modification of Memory Cell] The following describes an example of the configuration of a memory cell that is partially different from the configuration described above. Note that in the following, the same parts as those described above will be referred to, and descriptions thereof will be omitted.

[0174] 7A to 12D, A in each figure shows a plan view of a memory cell, B in each figure shows a cross-sectional view of a portion A1-A2 shown by a dashed dotted line in A in each figure, as viewed from the Y direction, C in each figure shows a cross-sectional view of a portion A3-A4 shown by a dashed dotted line in A in each figure, as viewed from the Y direction, and D in each figure shows a cross-sectional view of a portion A5-A6 shown by a dashed dotted line in A in each figure, as viewed from the X direction.

[0175] 7A to 7D show a memory cell MCA. The memory cell MCA differs from the memory cell MC described above mainly in that it has insulating layers 130a and 130b instead of insulating layer 130.

[0176] The memory cell MCA includes a transistor Tr and a capacitance element CA.

[0177] The capacitance element CA includes a conductive layer 115 , an insulating layer 130 a , and a conductive layer 120 .

[0178] The end of the insulating layer 130a coincides or substantially coincides with the end of the conductive layer 120. With this configuration, it is not necessary to remove the insulating layer 130 when forming an opening common to the insulating layer 280 and the insulating layer 180, and therefore etching can be easily performed when forming the opening.

[0179] Furthermore, it is preferable that the insulating layer 130a has a structure that covers the side end portion of the conductive layer 115. This can prevent the conductive layer 115 and the conductive layer 120 from shorting out.

[0180] The insulating layer 130b is provided under the conductive layer 220. The edge of the insulating layer 130b coincides with or approximately coincides with the edge of the conductive layer 220.

[0181] The insulating layer 130a and the insulating layer 130b are formed in the same process, and therefore the insulating layer 130b has the same insulating material as the insulating layer 130a.

[0182] 8A to 8D show a memory cell MCB. The memory cell MCB includes a transistor Tr and a capacitance element CB. The shape of the conductive layer 115 of the capacitance element CB is different from the shape of the conductive layer 115 of the capacitance element C.

[0183] 8C and 8D, the conductive layer 115 does not contact the upper surface of the insulating layer 180. In other words, the height of the upper surface of the conductive layer 115 is the same as or approximately the same as the height of the upper surface of the insulating layer 180. By adopting such a configuration, the step at the end of the conductive layer 115 can be reduced. Therefore, the coverage of the insulating layer 130 and the like to be formed later can be improved. In addition, short-circuiting between the conductive layer 115 and the conductive layer 120 can be prevented.

[0184] Note that the memory cell MCB may be configured to have insulating layers 130a and 130b instead of insulating layer 130, as described in [Modification 1]. 9A to 9D show a memory cell MCC in which part of the configuration of memory cell MCA is applied to memory cell MCB.

[0185] The memory cell MCC includes a transistor Tr and a capacitance element CC.

[0186] The capacitance element CC includes a conductive layer 115 whose upper surface is at or approximately at the same height as the upper surface of the insulating layer 180, a conductive layer 120, and an insulating layer 130a whose end is at or approximately at the same height as the end of the conductive layer 120. The insulating layer 130b is provided below the conductive layer 220, and the end of the insulating layer 130b is at or approximately at the same height as the end of the conductive layer 220.

[0187] 10A to 10D show a memory cell MCD. The memory cell MCD has a transistor Tr and a capacitance element CD. The shapes of the conductive layer 120 and the insulating layer 130 of the capacitance element CD are different from the shapes of the conductive layer 120 and the insulating layer 130 of the capacitance element C.

[0188] The conductive layer 115 has a protruding portion above the insulating layer 180. In other words, the uppermost portion of the conductive layer 115 is located above the upper surface of the insulating layer 180. In other words, the upper surface of the insulating layer 180 is located below the uppermost portion of the conductive layer 115 (on the insulating layer 140 side).

[0189] The insulating layer 130 is provided so as to cover the protruding portion of the conductive layer 115. That is, the insulating layer 130 has a region in contact with the upper surface of the conductive layer 115 in the opening 190, the upper surface and side surfaces of the protruding portion of the conductive layer 115, and the upper surface of the insulating layer 180 outside the opening 190.

[0190] The conductive layer 120 is provided so as to fill the recessed portion of the conductive layer 115 via the insulating layer 130. Furthermore, the conductive layer 120 has a region facing a part of the outer side surface of the conductive layer 115 via the insulating layer 130. In other words, the end of the conductive layer 120 is located outside the conductive layer 115.

[0191] By adopting the above-described configuration, the capacitance per unit area can be increased.

[0192] Note that the memory cell MCD may be configured to have insulating layers 130a and 130b instead of the insulating layer 130, as described in [Modification 1]. Figures 11A to 11D show a memory cell MCE in which part of the configuration of the memory cell MCA is applied to the memory cell MCD.

[0193] The memory cell MCE includes a transistor Tr and a capacitance element CE.

[0194] The capacitance element CE includes a conductive layer 115 having the protruding portion, an insulating layer 130a provided so as to cover the protruding portion of the conductive layer 115, and a conductive layer 120 having an end coincident with or substantially coincident with an end of the insulating layer 130a. The insulating layer 130b is provided below the conductive layer 220, and an end of the insulating layer 130b coincides with or substantially coincides with an end of the conductive layer 220.

[0195] The above-described capacitor element can be said to have a cylindrical shape. Note that the capacitor element of the memory cell is not limited to the above-described capacitor element configuration, and a capacitor element having a parallel plate type, pillar type, or other shape can be used.

[0196] 12A to 12D show a memory cell MCF. The memory cell MCF differs from the above-described memory cell MC mainly in that it has a conductive layer 261 and a conductive layer 265.

[0197] 12B , the insulating layer 285 has an opening 294 overlapping with the opening 293 and the opening 292. The height of the upper surface of the insulating layer 285 is the same as or approximately the same as the height of the upper surface of the conductive layer 260.

[0198] The conductive layer 261 is provided so as to fill the openings 294, 293, and 292. The conductive layer 261 is in contact with at least a part of the upper surface of the conductive layer 120. The height of the upper surface of the conductive layer 261 is the same as or approximately the same as the height of the upper surface of the insulating layer 285.

[0199] The conductive layer 265 is provided over the conductive layer 260 and the insulating layer 285. The conductive layer 265 has a region in contact with the top surface of the conductive layer 260 and a region in contact with the top surface of the conductive layer 261.

[0200] As described above, the conductive layer 260 is electrically connected to the conductive layer 120 via the conductive layer 265 and the conductive layer 261. That is, the memory cell MCF has a configuration in which the capacitor C is connected to the gate of the transistor Tr. With this configuration, it is not necessary to extend the conductive layer 260 to a position where it overlaps with the capacitor C. Therefore, the area where the conductive layer 260 and the conductive layer 240 overlap can be reduced. Furthermore, the insulating layer 281 and the insulating layer 250 are located between the conductive layer 265 and the conductive layer 240. This allows the physical distance between the conductive layer 265 and the conductive layer 240 to be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240 to be reduced.

[0201] The above is a description of the modified memory cell.

[0202] [Modification of Memory String] Below, an example of the configuration of a memory string that is partially different from the above configuration will be described. Note that in the following, parts that overlap with the above configuration will be referred to and descriptions thereof will be omitted.

[0203] 13A to 13D show a memory string 100B having a second gate. FIG. 13A is a plan view of the memory string 100B as viewed from the Z direction. FIG. 13B is an equivalent circuit of the memory string 100B. FIG. 13C is a cross-sectional view of the portion A1-A2 indicated by the dashed dotted line in FIG. 13A as viewed from the Y direction. FIG. 13D is a cross-sectional view including the portion B1-B2 indicated by the dashed dotted line in FIG. 13A.

[0204] The memory string 100B differs from the memory string 100 in that the memory string 100B includes conductive layers 215_1 to 215_n and insulating layers 225_1 to 225_n.

[0205] Conductive layers 215_1 to 215_n are provided over the insulating layer 280. An insulating layer 281 is provided over the insulating layer 280 and the conductive layers 215_1 to 215_n. Conductive layers 240_1 to 240_k are provided over the insulating layer 281. The conductive layers 215_1 to 215_n correspond to the wirings BG_1 to BG_n, respectively.

[0206] The memory string 100B includes memory cells MCG_1 to MCG_n.

[0207] The memory cell MCG includes a transistor TrG and a capacitance element C.

[0208] The transistor TrG includes a conductive layer 260 , an insulating layer 250 , a conductive layer 215 , an insulating layer 225 , a conductive layer 220 , a conductive layer 240 , and a semiconductor layer 230 .

[0209] 13A, the conductive layer 215 extends in the Y direction. That is, the conductive layer 215 extends in a direction parallel to the direction in which the conductive layer 110 extends.

[0210] The conductive layer 215 has an opening overlapping the opening 290 and the opening 291. The insulating layer 281 has a first opening overlapping the opening 290 and the opening 291.

[0211] The insulating layer 225 has an opening 291, a first opening in the insulating layer 281, an opening in the conductive layer 215, and a region disposed in the opening 290. The insulating layer 225 has a region in contact with a side surface of the conductive layer 240 in the opening 291, a side surface of the insulating layer 281 in the first opening, a side surface of the conductive layer 215 in the opening that the conductive layer 215 has, a side surface of the insulating layer 280 in the opening 290, and a part of the upper surface of the conductive layer 220 in the opening 290. The insulating layer 225 has an opening that reaches the conductive layer 220 in a region overlapping with the opening 290.

[0212] The semiconductor layer 230 has a region in contact with the top surface of the conductive layer 240 , the side surface of the insulating layer 225 in the opening portion of the insulating layer 225 , and the top surface of the conductive layer 220 .

[0213] The insulating layer 281 has a second opening overlapping with the opening 292 and the opening 293. The conductive layer 260 has a region filled in the opening 293, the second opening of the insulating layer 281, and the opening 292. The conductive layer 260 has a region in contact with the conductive layer 120 through the opening 293, the second opening, and the opening 292.

[0214] In the transistor TrG, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 215 functions as a second gate electrode, and the insulating layer 225 functions as a second gate insulating layer.

[0215] By providing the second gate electrode, the on / off state of the transistor can be controlled independently of the polarization held in the ferroelectric layer, and the polarization of the ferroelectric layer can be maintained when switching the transistor between the on and off states.

[0216] The above is a description of the modified memory string.

[0217] [Manufacturing Method Example] An example of a method for manufacturing the memory string 100 shown in FIG. 2A will be described below as an example of a method for manufacturing a semiconductor device of one embodiment of the present invention.

[0218] 14A to 17F, A, C, and E in each figure are cross-sectional views of the semiconductor device viewed from the Y direction, and B, D, and F in each figure are cross-sectional views of the semiconductor device viewed from the X direction. Note that the cross-sectional views A, C, and E in each figure show a region including three memory cells, and the cross-sectional views B, D, and F in each figure show a region including one memory cell.

[0219] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, an ALD method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or the like.

[0220] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0221] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0222] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0223] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0224] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0225] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0226] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0227] 14A and 14B, an insulating layer 140 is formed over a substrate (not shown), a plurality of conductive layers 110 are formed over the insulating layer 140, and an insulating layer 180 is formed over the insulating layer 140 and the plurality of conductive layers 110. Note that in FIG. 14A, conductive layers 110_1 to 110_3 are shown as the plurality of conductive layers 110.

[0228] The insulating layer 180 functions as an interlayer insulating layer. It is preferable to use a material with a low relative dielectric constant for the insulating layer 180. This reduces the parasitic capacitance generated between the conductive layer 110 and the conductive layer 220, thereby improving the driving speed of the semiconductor device. The insulating layer 180 may also have a stacked structure of multiple insulating layers, such as a stack of silicon oxide and silicon nitride.

[0229] The insulating layer 180 is preferably subjected to chemical mechanical polishing (CMP) treatment after deposition to planarize the top surface thereof. By performing the planarization treatment on the insulating layer 180, a conductive film that will later become the plurality of conductive layers 115 can be suitably formed.

[0230] In some cases, the CMP process may not be necessary. In this case, the upper surface of the insulating layer 180 has an upwardly convex curved shape. By not performing the planarization process, the manufacturing cost can be reduced and the production yield can be increased.

[0231] 14C and 14D, a plurality of openings 190 are formed in the insulating layer 180. Each of the plurality of openings 190 has a region overlapping one of the plurality of conductive layers 110. Each of the plurality of openings 190 reaches one of the plurality of conductive layers 110. Note that FIG. 14D shows an opening 190_1 that reaches the conductive layer 110_1.

[0232] For example, the opening 190 can be formed by forming a resist mask on the insulating layer 180 and performing etching using the resist mask as a mask. Anisotropic dry etching is preferably used as the etching process, and the opening is preferably processed so that the sidewalls of the opening are as vertical as possible. In this case, the opening preferably has a cylindrical shape.

[0233] The resist mask can be formed by, for example, lithography, printing, inkjet printing, or the like, as appropriate. When the resist mask is formed by the inkjet printing, a photomask is not used, which may reduce the manufacturing cost. In addition, for the etching process, one or both of dry etching and wet etching can be used. Processing by the dry etching method is suitable for fine processing.

[0234] In forming a resist mask by lithography, a resist is first formed, and then the resist is exposed to light through a photomask. Next, the exposed or unexposed region is removed using a developer to form a resist mask.

[0235] By performing etching through the resist mask, a conductive layer, a semiconductor layer, an insulating layer, or the like can be processed into a desired shape. For example, KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like can be used for exposure. Immersion technology may also be used. Furthermore, using a beam such as an electron beam or an ion beam instead of the aforementioned light is preferable because it eliminates the need for a photomask. The resist mask can be removed by wet etching, dry etching, or both.

[0236] Alternatively, a hard mask made of an inorganic material may be used instead of the resist mask. In the case of using a hard mask, a film serving as a hard mask material is formed on the layer to be processed, a resist mask is formed thereon, and the film is etched to form a hard mask having a desired shape.

[0237] As the dry etching apparatus, for example, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes or an inductively coupled plasma (ICP) etching apparatus can be used.

[0238] 14E and 14F , a conductive film 115f, which will later become the plurality of conductive layers 115, is formed on the insulating layer 180. The conductive film 115f is preferably formed by a film formation method with high coverage, such as an ALD method or a thermal CVD method. At this time, the conductive film 115f can be formed so that a portion thereof covers the opening 190.

[0239] 15A and 15B, the conductive film 115f is processed by lithography to form a plurality of conductive layers 115. Note that FIG. 15B shows a conductive layer 115_1 among the plurality of conductive layers 115.

[0240] The conductive film 115f can be processed by dry etching or wet etching. Dry etching is suitable for microfabrication. By this processing, the conductive layer 115 is formed so as to contact the sidewall and bottom surface of the opening 190. The conductive layer 115 also has a recess in the region overlapping with the opening 190. Note that when processing the conductive film 115f, a part of the insulating layer 180 is processed, and the thickness of the insulating layer 180 in the region not overlapping with the conductive layer 115 may become thin.

[0241] The conductive film 115f may be processed by a method other than the above-described lithography method. For example, a sacrificial layer may be formed to fill the opening 190, a planarization process may be performed to expose the upper surface of the insulating layer 180, and then a process of removing the sacrificial layer may be performed. By this process, the conductive layer 115 shown in FIGS. 8C and 8D may be formed.

[0242] Subsequently, as shown in FIGS. 15C and 15D, an insulating layer 130 and a conductive film 120f are formed in this order on the insulating layer 180 and the plurality of conductive layers 115.

[0243] The insulating layer 130 is preferably formed using a film formation method with high coverage so as to be formed along the recesses of the conductive layer 115. Furthermore, the conductive film 120f is preferably formed so as to fill the recesses. For example, the insulating layer 130 can be formed by the ALD method, and the conductive film 120f can be formed by the CVD method.

[0244] When hafnium zirconium oxide is formed as the insulating layer 130 by the ALD method, a precursor containing hafnium, a precursor containing zirconium, and an oxidizing agent can be used. Examples of the precursor containing hafnium include tetrakis(ethylmethylamido)hafnium (TEMAHf), HfCl ４ Furthermore, as a precursor containing zirconium, tetrakis(ethylmethylamido)zirconium (TEMAZr), ZrCl ４ In addition, as an oxidizing agent, O ２ , O ３ , N ２ O, NO ２ , H ２ O and H ２ O ２ Any one or more selected from the above can be used.

[0245] Furthermore, it is preferable to use an oxide containing a Group 3 element such as scandium, yttrium, or lanthanum in addition to hafnium and zirconium for the insulating layer 130. Adding such an element to hafnium zirconium oxide is expected to improve the rewrite endurance of the ferroelectric capacitor.

[0246] As a precursor containing a Group 3 element such as scandium, yttrium, or lanthanum, an inorganic compound or an organic compound containing the target element can be used. The precursor may be liquid or solid at room temperature and pressure. For example, an example of a precursor containing yttrium is tris(methylcyclopentadienyl)yttrium(III) (Y(MeCp) ３ ), tris(isopropylcyclopentadienyl)yttrium(III) (Y(iPrCp) ３ ), tris[N,N-bis(trimethylsilyl)amido]yttrium(III) (Y(tmsa) ３ On the other hand, precursors containing lanthanum include tris(cyclopentadienyl)lanthanum(III) (La(Cp) ３ ), tris(methylcyclopentadienyl)lanthanum(III) (La(MeCp) ３ ), tris(isopropylcyclopentadienyl)lanthanum(III) (La(iPrCp) ３ ) and other lanthanum compounds.

[0247] Here, heat treatment is preferably performed after the formation of the insulating layer 130. The heat treatment crystallizes the insulating layer 130, causing the insulating layer 130 to exhibit ferroelectricity. Alternatively, the heat treatment can enhance the ferroelectricity of the insulating layer 130. A higher temperature for the heat treatment is preferable because it promotes crystallization and increases remanent polarization. Note that the heat treatment is preferably performed before forming a semiconductor film (semiconductor film 230f described later) that will later become multiple semiconductor layers, and more preferably before forming the insulating layer 280 described later. When an oxide semiconductor is used as the semiconductor layer 230, the semiconductor layer 230 is formed after the heat treatment, preventing polycrystallization of the oxide semiconductor and realizing a highly reliable transistor.

[0248] Heat treatment for crystallizing the insulating layer 130 is preferably performed in a state in which the insulating layer 130 is in contact with the conductive layer 115 or in contact with the conductive layer 115 and the conductive layer 120 (or the conductive film 120f). This makes it easier for the insulating layer 130 to have a crystalline structure exhibiting ferroelectricity compared to a case in which heat treatment is performed in a state in which the insulating layer 130 is not in contact with a conductive layer or a conductive film. In particular, heat treatment in a state in which the insulating layer 130 is sandwiched between a pair of conductive layers is preferable because it exhibits large remanent polarization.

[0249] For example, a rapid thermal annealing (RTA) apparatus, a resistance heating furnace, or a microwave heating apparatus can be used for the heat treatment. In particular, using an RTA apparatus is preferable because it allows high temperatures to be applied in a short time, thereby enhancing the ferroelectricity of the insulating layer 130, shortening the process time, and reducing thermal damage to layers other than the insulating layer 130. The heat treatment is preferably performed in an inert gas or reducing gas atmosphere, because oxidation of the electrodes can be suppressed. Examples of inert gases that can be used include noble gases such as helium, argon, and neon, and nitrogen gas. Examples of reducing gases that can be used include hydrogen gas, carbon monoxide gas, and hydrocarbon gas.

[0250] In particular, when an oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used for the insulating layer 130, the crystal structure exhibiting ferroelectricity is not a stable structure (stable phase) but is classified as a metastable phase that appears at relatively high temperatures. Therefore, by heating at high temperatures using the RTA method and then rapidly cooling, the metastable phase in the film is maintained, and an insulating layer 130 containing a large amount of crystal structure exhibiting ferroelectricity can be formed.

[0251] Examples of RTA apparatuses that can be used include LRTA (Lamp Rapid Thermal Anneal) apparatuses and GRTA (Gas Rapid Thermal Anneal) apparatuses. LRTA apparatuses are apparatuses that heat workpieces by radiating light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. GRTA apparatuses are apparatuses that perform heat treatment using high-temperature gases. The gases used are noble gases such as helium, neon, and argon, or inert gases such as nitrogen that do not react with the workpieces during heat treatment.

[0252] When the RTA method is used for the heat treatment, the treatment temperature can be 300°C to 750°C, preferably 400°C to 700°C, and more preferably 500°C to 650°C. The treatment time can be 1 second to 10 minutes, preferably 3 seconds to 5 minutes, and more preferably 5 seconds to 1 minute. For example, an RTA apparatus using a halogen lamp (LRTA apparatus) can be used for the heat treatment, and the treatment can be performed for 1 minute at a treatment temperature of 600°C in a nitrogen atmosphere. When the heat treatment is performed using an apparatus other than an RTA apparatus, such as a resistance heating furnace, the treatment time excluding the temperature rise period and the temperature fall period can be 1 minute to 5 hours, and preferably 1 minute to 2 hours.

[0253] 15E and 15F, the conductive film 120f is processed by lithography to form a plurality of conductive layers 120 and a plurality of conductive layers 220. Note that FIG. 15E shows conductive layer 220_1 and conductive layer 220_2 among the plurality of conductive layers 220. FIG. 15F shows conductive layer 120_1 among the plurality of conductive layers 120 and conductive layer 220_1 among the plurality of conductive layers 220. For a processing method of the conductive film 120f, refer to the above description of the processing of the conductive film 115f.

[0254] One conductive layer 220 is formed so as to overlap two conductive layers 110 adjacent in the A1-A2 direction. In Fig. 15E, the conductive layer 220_1 is formed so as to have a region overlapping with the conductive layer 110_1 and a region overlapping with the conductive layer 110_2.

[0255] As described above, the conductive layer 120 and the conductive layer 220 are formed in the same process. Therefore, the conductive layer 220 has the same conductive material as the conductive layer 120.

[0256] Through the steps up to this point, the capacitance element C is formed.

[0257] The insulating layer 130 may be processed after the conductive film 120f is processed. The conductive film 120f and the insulating layer 130 may be processed simultaneously, or the processing conditions may be different for the conductive film 120f and the insulating layer 130. This makes it possible to form the insulating layer 130a whose end coincides or substantially coincides with the end of the conductive layer 120, and the insulating layer 130b whose end coincides or substantially coincides with the end of the conductive layer 220, as shown in FIGS. 7B to 7D . Note that when the conductive film 120f and the insulating layer 130 are processed, a portion of the insulating layer 180 may be processed, resulting in a reduction in the thickness of the insulating layer 180 in the regions that do not overlap with the conductive layer 120 and the insulating layer 130a, and in the regions that do not overlap with the conductive layer 220 and the insulating layer 130b.

[0258] Furthermore, the insulating layer 130a and the insulating layer 130b are formed in the same process, and therefore the insulating layer 130b has the same insulating material as the insulating layer 130a.

[0259] 16A and 16B , an insulating layer 280 is formed on the insulating layer 130, the plurality of conductive layers 120, and the plurality of conductive layers 220. The insulating layer 280 functions as an interlayer insulating layer, and therefore, an insulating material applicable to the insulating layer 180 can be used.

[0260] The insulating layer 280 is preferably subjected to CMP treatment after deposition to planarize the top surface thereof. By performing the planarization treatment on the insulating layer 280, the conductive film 240f can be suitably formed.

[0261] In some cases, the CMP process may not be necessary. In this case, the upper surface of the insulating layer 280 has an upwardly convex curved shape. By not performing the planarization process, the manufacturing cost can be reduced and the production yield can be increased.

[0262] Subsequently, as shown in FIGS. 16A and 16B, a conductive film 240f, which will later become the plurality of conductive layers 240, is formed on the insulating layer 280.

[0263] 16C and 16D , a plurality of openings are formed in the conductive film 240f and the insulating layer 280. Each of the openings has a region overlapping with one of the conductive layers 220. Each of the openings reaches one of the conductive layers 220. Each of the openings includes an opening 291 and an opening 290. Note that FIG. 16C shows openings 291_1, 291_2, and 291_3 formed in the conductive film 240f, and openings 290_1, 290_2, and 290_3 formed in the insulating layer 280. Also, FIG. 16D shows opening 291_1 formed in the conductive film 240f and opening 290_1 formed in the insulating layer 280.

[0264] For the method of forming the openings 291 and 290, the above description of the formation of the openings 190 can be referred to.

[0265] 16E and 16F , a semiconductor film 230f, which will later become the plurality of semiconductor layers 230, is formed on the conductive film 240f. The semiconductor film 230f is preferably formed by a film formation method with high coverage, such as an ALD method. At this time, the semiconductor film 230f can be formed so that a portion of it covers the openings 291 and 290. For example, an oxide film containing indium can be formed by an ALD method as the semiconductor film 230f.

[0266] The method for forming the semiconductor film 230f is not limited to the above, and may be sputtering, CVD, PLD, MBE, or the like.

[0267] The crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0268] The semiconductor layer 230 preferably includes a crystalline metal oxide layer. Examples of the structure of a crystalline metal oxide include a CAAC structure, a polycrystalline structure, and a microcrystalline structure. By using a crystalline metal oxide layer for the semiconductor layer 230, the defect level density in the semiconductor layer 230 can be reduced, and a highly reliable semiconductor device can be realized. Note that the CAAC structure is a crystalline structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an OS film having a CAAC structure is observed using a high-resolution TEM image, it can be confirmed that metal atoms are arranged in a layered manner in the crystalline portion. Therefore, an OS film having a CAAC structure can also be said to have a structure having layered crystalline portions.

[0269] The polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystal portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. Since the CAAC structure does not have clear crystal grain boundaries (grain boundaries) in the a-b plane, a semiconductor device with higher reliability than a polycrystalline structure can be realized.

[0270] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 230, the more the density of defect states in the semiconductor layer 230 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0271] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during the formation (hereinafter also referred to as oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0272] The semiconductor layer 230 can have a stacked structure of two or more metal oxide layers with different crystallinity. In this case, the two or more metal oxide layers may have different compositions or may have the same or approximately the same composition. For example, when the semiconductor layer 230 has a two-layer structure, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, so the crystallinity of the second metal oxide layer can be increased in some cases. Furthermore, by performing heat treatment (also called crystallization treatment) after forming the second metal oxide layer, the crystallinity of the first metal oxide layer can be increased.

[0273] For example, a first metal oxide layer is formed using an ALD method, and a second metal oxide layer is formed using a sputtering method to have a higher crystallinity than the first metal oxide layer. Heat treatment can then be performed to improve the crystallinity of the first and second metal oxide layers. In this case, the crystals contained in the second metal oxide layer grow continuously in the vertical direction toward the first metal oxide layer, which may make the boundary between the first and second metal oxide layers unrecognizable by cross-sectional observation.

[0274] Alternatively, a three-layer structure may be formed by depositing a third metal oxide layer on the second metal oxide layer using an ALD method. After the deposition of the third metal oxide layer, heat treatment can be performed to improve the crystallinity of the first to third metal oxide layers. In this case, the crystals contained in the second metal oxide layer grow continuously vertically toward the first and third metal oxide layers and then laterally. This may result in the boundary between the first and second metal oxide layers and the boundary between the second and third metal oxide layers becoming indistinguishable from cross-sectional observation.

[0275] In this way, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the film thickness direction. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the film thickness direction. This makes it possible to realize a highly reliable transistor.

[0276] For example, in a three-layer structure in which a first metal oxide layer is formed by ALD, a second metal oxide layer is formed by sputtering to have a CAAC structure, and a third metal oxide layer is formed by ALD, the CAAC structure of the second metal oxide layer can be used as a nucleus or seed to enhance the crystallinity of the upper and lower metal oxide layers. A metal oxide layer with enhanced crystallinity can be called an axial growth CAAC (AG CAAC).

[0277] The heat treatment is preferably performed at a temperature lower than that of the heat treatment for crystallizing the insulating layer 130. When the heat treatment is performed at a temperature lower than that of the heat treatment for crystallizing the insulating layer 130, polycrystallization of the metal oxide can be prevented.

[0278] The heat treatment is preferably carried out at a temperature of 250° C. to 650° C., more preferably 350° C. to 550° C. The treatment time is preferably, for example, 1 minute to 1 hour, or 10 minutes to 30 minutes, at a temperature of 350° C. to 550° C.

[0279] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA device or a GRTA device can be used.

[0280] 17A and 17B , the semiconductor film 230f and the conductive film 240f are processed by lithography to form a plurality of semiconductor layers 230 and a plurality of conductive layers 240. Note that Fig. 17A shows the semiconductor layer 230_1 and the semiconductor layer 230_2 of the plurality of semiconductor layers 230, and the conductive layer 240_1 and the conductive layer 240_2 of the plurality of conductive layers 240. Fig. 17B shows the semiconductor layer 230_1 of the plurality of semiconductor layers 230 and the conductive layer 240_1 of the plurality of conductive layers 240.

[0281] The semiconductor film 230f and the conductive film 240f can be processed by dry etching or wet etching. Dry etching is suitable for microfabrication. By this processing, the semiconductor layer 230 is formed so as to contact the sidewalls of the opening 291 and the sidewalls and bottom surface of the opening 290. The semiconductor layer 230 has recesses in the regions overlapping with the openings 291 and 290. The semiconductor film 230f and the conductive film 240f may be processed under the same conditions or different conditions.

[0282] One conductive layer 240 is formed so as to overlap two conductive layers 220 adjacent in the A1-A2 direction. In Fig. 17A, the conductive layer 240_2 is formed so as to have a region overlapping with the conductive layer 220_1 and a region overlapping with the conductive layer 220_2.

[0283] By forming the plurality of conductive layers 220 and the plurality of conductive layers 240 as described above, it is possible to configure the first transistor and the second transistor adjacent in the A1-A2 direction to share one of the conductive layer 220 and the conductive layer 240, and the second transistor and the third transistor adjacent in the A1-A2 direction to share the other of the conductive layer 220 and the conductive layer 240. This allows the memory string 100 to have a configuration in which a plurality of transistors are connected in series.

[0284] Subsequently, the insulating layer 250 is formed on the insulating layer 280 and the plurality of semiconductor layers 230. The insulating layer 250 is preferably formed by a film formation method with high coverage. At this time, the insulating layer 250 can be formed so that a part of it covers the recessed portion.

[0285] The insulating layer 250 is preferably formed by, for example, a CVD method or an ALD method. In particular, it is preferable to form a plurality of different insulating films by stacking them using the ALD method.

[0286] For example, the insulating layer 250 is preferably an insulating film having a barrier property against oxygen. Furthermore, the insulating layer 250 is preferably an insulating film having a function of capturing or fixing hydrogen. By providing such an insulating film, oxidation of the conductive layer 260 in contact with the insulating layer 250 can be suppressed. Furthermore, the insulating layer 250 can capture or fix hydrogen contained in the semiconductor layer 230 and its vicinity. This can reduce the hydrogen concentration in the semiconductor layer 230, thereby improving the reliability of the transistor.

[0287] For example, a laminated film of aluminum oxide and hafnium oxide can be used for the insulating layer 250. Since aluminum oxide and hafnium oxide are high dielectric constant (high-k) materials, using these for the gate insulating layer makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. In other words, it becomes possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0288] A silicon oxide film, a silicon oxynitride film, or the like having a high withstand voltage is preferably used for the insulating layer 250. This can reduce leakage current of the transistor.

[0289] Furthermore, an insulating film having a barrier property against hydrogen may be provided on the side of the insulating layer 250 that is in contact with the conductive layer 260. This can suppress the diffusion of impurities such as hydrogen contained in the conductive layer 260 into the semiconductor layer 230. Examples of insulating films having a barrier property against hydrogen include a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. A silicon nitride film is particularly preferable because of its high barrier property against hydrogen. Furthermore, such an insulating film has a barrier property against oxygen in addition to hydrogen, and can therefore block oxygen diffusing from the semiconductor layer 230 to the conductive layer 260, thereby preventing the conductive layer 260 from being oxidized.

[0290] When the insulating layer 250 is a stacked film of multiple insulating films, the thickness of each film is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. For example, a stacked film of a 1-nm-thick aluminum oxide film, a 2-nm-thick silicon oxide film, and a 2-nm-thick hafnium oxide film can be used from the semiconductor layer 230 side. Alternatively, a stacked film in which a 1-nm-thick silicon nitride film is stacked on the conductive layer 260 side in addition to this may be used. However, the film thickness is not limited to the above, and for example, the thickness of any one or more of the films may be 15 nm or more.

[0291] 17C and 17D , a plurality of openings are formed in the insulating layer 250 and the insulating layer 280. Each of the plurality of openings has a region overlapping with one of the plurality of conductive layers 120. Each of the plurality of openings reaches one of the plurality of conductive layers 120. Each of the plurality of openings includes an opening 293 and an opening 292. Note that FIG. 17D shows an opening 292_1 that reaches the conductive layer 120_1 and an opening 293_1 that overlaps with the opening 292_1.

[0292] For the method of forming the openings 293 and 292, the above description of the formation of the openings 190 can be referred to.

[0293] Subsequently, a conductive film that will later become the plurality of conductive layers 260 is formed. The conductive film is preferably formed so as to fill the openings 291 and 290, and the openings 293 and 292. For example, the conductive film can be formed by a CVD method.

[0294] 17E and 17F, the conductive film is processed by lithography to form a plurality of conductive layers 260. Note that Fig. 17E shows conductive layers 260_1, 260_2, and 260_3 among the plurality of conductive layers 260. Fig. 17F shows conductive layer 260_1 among the plurality of conductive layers 260.

[0295] The conductive layer can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. By this processing, the conductive layer 260 is formed so as to fill the openings 293 and 292, and the openings 292 and 291.

[0296] Subsequently, an insulating layer 283 is formed on the insulating layer 250 and the plurality of conductive layers 260, thereby forming a memory string (FIGS. 2C and 2E).

[0297] This concludes the description of an example method for fabricating a memory string.

[0298] [Configuration Example of Storage Device] Next, a configuration example of a storage device that can use the above memory string will be described.

[0299] 18 is a block diagram showing an example of the configuration of the circuit OSC and the memory cell unit MCL. The memory cell unit MCL is a circuit including the above-mentioned memory cells and memory strings.

[0300] The memory cell unit MCL has a memory cell array MCAA. The memory cell array MCAA has a plurality of memory strings SRG. The memory strings SRG are electrically connected to wiring BL. The memory strings SRG have a plurality of memory cells MC electrically connected in series, and selection transistors BTr and STr.

[0301] The memory cell MC is a transistor that operates with normally-on characteristics and has a control gate and a functional layer. A ferroelectric layer can be used as the functional layer. A configuration using a ferroelectric layer as the functional layer can be the configuration in which a ferroelectric capacitor is connected to the gate, as exemplified above. For example, the functional layer corresponds to the insulating layer 130 described above.

[0302] The channel formation regions of the transistor BTr, memory cell MC, and transistor STr preferably contain, for example, one of silicon, germanium, gallium arsenide, silicon carbide, metal oxide, or a plurality of materials selected from the above.

[0303] In particular, it is preferable to use an oxide of one or more metals selected from indium, element M (element M is, for example, one or more elements selected from aluminum, gallium, yttrium, and tin), and zinc in the channel formation region. The metal oxide can be used as a wide-gap semiconductor, and can impart characteristics of extremely low off-state current to the transistor BTr, memory cell MC, and transistor STr whose channel formation region includes the metal oxide. In other words, the leakage current in the transistor BTr, memory cell MC, and transistor STr in the off state can be reduced, which may reduce the power consumption of the storage device.

[0304] Although FIG. 18 shows an example in which the transistors BTr and STr are formed in the memory cell unit MCL, the transistors BTr and STr may be formed in the circuit OSC.

[0305] The memory cell array MCAA has a plurality of memory cells MC in the memory string SRG. The plurality of memory cells MC are arranged in a matrix. The memory cell array MCAA has n memory cells MC in each column and m memory cells MC in each row, for a total of n x m memory cells MC (m and n are each independently an integer of 2 or greater). The memory cell MC located in the i-th row and j-th column (i is an integer of 1 or greater and n is an integer of 1 or greater and j is an integer of 1 or greater and m is an integer of 1 or greater) is represented as MC[i, j].

[0306] The wirings WL are a plurality of word lines, each electrically connected to a memory cell MC for each row. The wirings BL are a plurality of bit lines, each electrically connected to a memory cell MC for each column. The wirings CL are power supply lines.

[0307] Next, the connection configuration of the memory string SRG will be described. The transistor BTr, the memory cells MC, and the transistor STr are connected in series, and the transistor BTr is electrically connected to a wiring BSL, and the transistor STr is electrically connected to a wiring SSL.

[0308] The wirings BSL and SSL function as wirings for selecting a memory string when performing operations such as writing, reading, erasing, etc. The wiring BSL is electrically connected to the gate of the transistor BTr, and the wiring SSL is electrically connected to the gate of the transistor STr.

[0309] Although one memory string SRG is electrically connected to one wiring BL in this configuration, one embodiment of the present invention is not limited to this. For example, as shown in Figure 19, the memory cell portion MCL may have a configuration in which multiple memory strings SRG are electrically connected to one wiring BL. Note that the block diagram in Figure 19 illustrates only the memory cell portion MCL and a part of the circuit OSC.

[0310] The circuit OSC includes a control circuit CTR, a circuit PRPH, and an output circuit OUTP. The control circuit CTR receives control signals CS (such as a clock signal, a chip enable signal, a write enable signal, and an address signal) and a data signal WDATA from outside the memory device.

[0311] The control circuit CTR has a function of accessing the circuit PRPH to write data to the memory cell unit MCL and a function of reading data from the memory cell unit MCL. For example, when a write command based on a control signal CS and a data signal WDATA are input from outside the memory device, the control circuit CTR writes the data signal WDATA to the memory cell unit MCL. In addition, in response to a read command based on the control signal CS, the control circuit CTR reads data from the memory cell unit MCL and outputs it as a data signal RDATA. Note that the write command and read command include an address signal.

[0312] The control circuit CTR may also have a function of detecting and correcting errors (also called ECC: Error Check and Correct) when data is read from the memory cell unit MCL.

[0313] The circuit PRPH includes, for example, a circuit WLD, a circuit BLD, and a circuit CVC. The circuit WLD functions as a word line driver circuit and is electrically connected to a wiring WL. The circuit BLD functions as a bit line driver circuit and is electrically connected to a wiring BL. The circuit CVC functions as a power supply that generates a constant potential and outputs the constant potential and is electrically connected to a wiring CL. Note that the circuit CVC may not be included in the circuit PRPH and may be provided outside the memory device. In this case, the memory device is configured so that a constant potential is applied to the memory cell unit MCL from outside.

[0314] The above is a description of an example of the configuration of the storage device.

[0315] [Configuration Example of Arithmetic Device] Hereinafter, a configuration example of an arithmetic processing device to which the above-exemplified storage device can be applied will be described.

[0316] 20A is a block diagram of the arithmetic processing device 1100. In FIG. 20A, an example of the configuration of a CPU is shown as an example of the configuration that can be used for the arithmetic processing device 1100.

[0317] The arithmetic processing device 1100 shown in FIG. 20A has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189 on a substrate 1190. The substrate 1190 may be a semiconductor substrate, an SOI (Silicon On Insulator) substrate, a glass substrate, or the like. The arithmetic processing device 1100 may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may also be provided on separate chips.

[0318] The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding the data.

[0319] The arithmetic processing device 1100 shown in Figure 20A is merely an example of a simplified configuration, and actual arithmetic processing devices 1100 have a wide variety of configurations depending on their applications. For example, the arithmetic processing device 1100 shown in Figure 20 or a configuration including an arithmetic circuit may be used as one core, and a configuration may include multiple such cores, each of which operates in parallel, i.e., a GPU-like configuration. Furthermore, the number of bits that the arithmetic processing device 1100 can handle in its internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0320] An instruction input to the processor 1100 via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0321] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Furthermore, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask state while the arithmetic processing unit 1100 is executing a program. The register controller 1197 generates an address for the register 1196 and reads or writes data from the register 1196 depending on the state of the arithmetic processing unit 1100.

[0322] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0323] In the processor 1100 shown in FIG. 20A, a register 1196 and a cache 1199 are provided with storage devices.

[0324] 20A, the register controller 1197 selects the holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether the memory cells in the register 1196 will hold data using flip-flops or using capacitors. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 1196. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply voltage to the memory cells in the register 1196 can be stopped.

[0325] The arithmetic processing device 1100 is not limited to a CPU, but may be a GPU, a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), or the like.

[0326] The semiconductor device 1000 including the memory device exemplified above and the processing unit 1100 can be provided overlapping each other. Figures 20B and 20C show perspective views of a semiconductor device 1150A. The semiconductor device 1150A includes the semiconductor device 1000 functioning as a memory device on the processing unit 1100. The processing unit 1100 and the semiconductor device 1000 have overlapping regions. To make the configuration of the semiconductor device 1150A easier to understand, the processing unit 1100 and the semiconductor device 1000 are shown separated in Figure 20C.

[0327] By stacking the semiconductor device 1000 and the arithmetic processing unit 1100, the connection distance between them can be shortened, thereby increasing the communication speed between them. Furthermore, the short connection distance can reduce power consumption.

[0328] Furthermore, a plurality of semiconductor devices 1000 may be provided on top of the arithmetic processing device 1100. Perspective views of a semiconductor device 1150B are shown in FIGS. 21A and 21B. The semiconductor device 1150B includes a semiconductor device 1000a and a semiconductor device 1000b on the arithmetic processing device 1100. The arithmetic processing device 1100, the semiconductor device 1000a, and the semiconductor device 1000b have overlapping regions. To make the configuration of the semiconductor device 1150B easier to understand, the arithmetic processing device 1100, the semiconductor device 1000a, and the semiconductor device 1000b are shown separately in FIG. 21B.

[0329] The semiconductor device 1000a and the semiconductor device 1000b function as memory devices. For example, one of the semiconductor device 1000a and the semiconductor device 1000b may be used as a NOR memory device, and the other as a NAND memory device. Both the semiconductor device 1000a and the semiconductor device 1000b may be NAND memory devices. Examples of NOR memory devices include DRAM and SRAM. Since NOR memory devices can operate faster than NAND memory devices, for example, part of the semiconductor device 1000a can be used as a main memory and / or cache 1199. Note that the stacking order of the semiconductor device 1000a and the semiconductor device 1000b may be reversed.

[0330] 21C and 21D are perspective views of a semiconductor device 1150C. The semiconductor device 1150C has a configuration in which a processing unit 1100 is sandwiched between a semiconductor device 1000a and a semiconductor device 1000b.

[0331] The configuration of the semiconductor device 1150C can increase the communication speed between the semiconductor device 1000a and the processing unit 1100 and the communication speed between the semiconductor device 1000b and the processing unit 1100. In addition, the power consumption can be reduced compared to the semiconductor device 1150B.

[0332] Next, an example of the cross-sectional structure of the semiconductor device will be described.

[0333] 22A shows an example in which a layer 11 including a transistor 300 and a layer 12 including a plurality of memory strings are stacked. A circuit using a single crystal silicon substrate as the substrate can be applied to layer 11, and a memory device having a three-dimensional NAND memory can be applied to layer 12. For example, layer 11 is the arithmetic processing device 1100 exemplified above, and layer 12 is a semiconductor device 1000 that functions as a memory device.

[0334] The multiple memory strings included in layer 12 are arranged at equal intervals in the Y direction. Note that Fig. 22A illustrates one memory string. Fig. 22B shows a cross-sectional view of a region including transistor 142 as viewed from the X direction. Note that layer 11 is omitted from Fig. 22B.

[0335] Each memory string provided in layer 12 has a transistor 142, a transistor 141 included in each of the multiple memory cells, and a transistor 143. Note that detailed explanation of the configuration of layer 12 will be omitted for parts that can be referred to the memory string 100 illustrated in FIG. 2A and the like, and only differences will be explained.

[0336] The transistor 300 included in the layer 11 is provided over a substrate 311 and includes a conductive layer 316, an insulating layer 315, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314 a and 314 b functioning as source and drain regions. Figure 22A shows a cross section of the transistor 300 in the channel length direction.

[0337] The transistor 300 is preferably a so-called Fin-type transistor in which, in a cross section in the channel width direction, the top surface and the side surface in the channel width direction of the semiconductor region 313 are covered with the conductive layer 316 via the insulating layer 315. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0338] Note that the transistor 300 may be either a p-channel type or an n-channel type.

[0339] The region where the channel of the semiconductor region 313 is formed, the region nearby, and the low-resistance region 314a and low-resistance region 314b that serve as the source region or drain region preferably contain a semiconductor such as a silicon-based semiconductor, and preferably single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaN (gallium nitride), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0340] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0341] The conductive layer 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0342] Since the work function is determined by the material of the conductor, the threshold voltage (Vth) of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and tungsten is particularly preferable in terms of heat resistance.

[0343] Note that the transistor 300 illustrated in FIG. 22A is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0344] An insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order to cover the transistor 300.

[0345] The insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0346] The insulating layer 322 may function as a planarizing film that planarizes a step caused by the transistor 300 or the like provided thereunder. For example, the top surface of the insulating layer 322 may be planarized by planarization treatment using CMP treatment or the like to improve the planarity.

[0347] The insulating layer 324 is preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 300 to a region where the transistor 141 and the like are provided.

[0348] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 141, may degrade the characteristics of the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 141 or the like and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0349] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectrometry (TDS). For example, in an analysis using TDS, the amount of desorption of hydrogen from the insulating layer 324 is calculated as 10×10 per area of ​​the insulating layer 324 when the surface temperature of the film is in the range of 50° C. to 500° C. and the amount of desorption converted into hydrogen atoms is 10×10 １５ atoms / cm ２ Preferably, it is 5×10 or less. １５ atoms / cm ２More preferably, it is:

[0350] The insulating layer 326 preferably has a lower dielectric constant than the insulating layer 324. For example, the dielectric constant of the insulating layer 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the dielectric constant of the insulating layer 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the dielectric constant of the insulating layer 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0351] Furthermore, conductive layers 328 and 330 are embedded in the insulating layers 320, 322, 324, and 326. The conductive layers 328 and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be an integrated entity. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0352] As the material for each plug and wiring (the conductive layer 328, the conductive layer 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a stacked layer. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferred. Alternatively, it is preferred to form the plug and wiring using a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0353] 22A , a wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, it is preferable to provide an insulator having a barrier property against hydrogen, similar to the insulating layer 324, over the insulating layer 326 and the conductive layer 330, and to form a conductor having a barrier property against hydrogen in the insulator. By forming a conductor having a barrier property against hydrogen in an opening of the insulator having a barrier property against hydrogen, the transistor 300 and the transistor 141, etc. can be separated by the barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 141, etc. can be suppressed.

[0354] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which a tantalum nitride layer having a barrier property against hydrogen is in contact with an insulator having a barrier property against hydrogen is preferable. Note that in FIG. 22A , an insulating layer 350 having a barrier property against hydrogen is provided over the insulating layer 326 and the conductive layer 330.

[0355] <Layer 12> Layer 12 includes an insulating layer 140, a plurality of conductive layers 110, an insulating layer 180, an insulating layer 130, a plurality of conductive layers 220, an insulating layer 280, a plurality of conductive layers 240, a plurality of semiconductor layers 230, an insulating layer 250, a plurality of conductive layers 260, a conductive layer 262, a conductive layer 263, an insulating layer 283, an insulating layer 284, and the like.

[0356] The transistors 142 and 143 function as selection transistors. The conductive layer 262 has a region that functions as the gate electrode of the transistor 142, and the conductive layer 263 has a region that functions as the gate electrode of the transistor 143. The conductive layer 262 extends in the Y direction, and a capacitor element formed of the conductive layer 115, the insulating layer 130, and the conductive layer 120 is not provided in the insulating layer 180 in a region that overlaps with the conductive layer 262. Although not shown, similar to the conductive layer 262, the conductive layer 263 extends in the Y direction, and a capacitor element is not provided in the insulating layer 180 in a region that overlaps with the conductive layer 263.

[0357] An insulating layer 284 is provided over the insulating layer 283. A conductive layer 362 is provided in an opening formed in the insulating layer 284, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, and a conductive layer 363 is provided in another opening formed in the insulating layer 284, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230. The conductive layer 362 and the conductive layer 363 function as plugs.

[0358] A conductive layer 372 is provided over the conductive layer 362, and a conductive layer 373 is provided over the conductive layer 363. An insulating layer 382 is provided over the conductive layer 372 and the conductive layer 373. The conductive layers 372 and 373 function as wirings.

[0359] The memory strings may be stacked in the Z direction. Figure 23 illustrates a layer 12 in which the second memory string is stacked on the first memory string. Note that layer 11 is omitted from Figure 23.

[0360] 23 has a structure in which a first layer provided with a first memory string and a second layer provided with a second memory string are bonded together. With this structure, polycrystallization of the oxide semiconductor included in the semiconductor layer of the first memory string can be prevented by heat treatment performed on the insulating layer 130 when the second memory string is manufactured, and a highly reliable semiconductor layer device can be realized.

[0361] Here, an insulating layer 345 is preferably provided under the insulating layer 140. An insulating layer 346 is preferably provided over the insulating layer 382. The insulating layers 345 and 346 function as protective layers and can suppress impurity diffusion above the insulating layer 140 and below the insulating layer 382. The insulating layers 345 and 346 can be formed using inorganic insulating films.

[0362] In the second layer, a plug 343 is provided that penetrates the insulating layer 140, the insulating layer 345, etc. Furthermore, a conductive layer 342 is provided below the insulating layer 345. The conductive layer 342 is preferably provided so as to be embedded in the insulating layer 335. Furthermore, the lower surfaces of the conductive layer 342 and the insulating layer 335 are preferably flattened. Here, the conductive layer 342 is electrically connected to the plug 343.

[0363] On the other hand, in the first layer, a conductive layer 341 is provided over an insulating layer 346. The conductive layer 341 is preferably provided so as to be embedded in the insulating layer 336. In addition, the top surfaces of the conductive layer 341 and the insulating layer 336 are preferably flattened.

[0364] The first layer and the second layer are electrically connected by bonding the conductive layer 341 and the conductive layer 342. Here, by improving the flatness of the surface formed by the conductive layer 342 and the insulating layer 335 and the surface formed by the conductive layer 341 and the insulating layer 336, the conductive layer 341 and the conductive layer 342 can be favorably attached to each other.

[0365] It is preferable to use the same conductive material for the conductive layers 341 and 342. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc., can be used. In particular, it is preferable to use copper for the conductive layers 341 and 342. This allows the use of Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conductivity by connecting Cu (copper) pads together).

[0366] <Layer 13> The semiconductor device may have a structure in which two or more memory devices are stacked. Figure 24 shows an example in which a layer 13 is stacked on a layer 12 having a memory string. The layer 13 has a transistor 500 and a capacitor 550.

[0367] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has a pair of gates with a semiconductor in which a channel is formed sandwiched therebetween. A capacitor 550 is connected to one of the source and drain of the transistor 500. The transistor 500 has an extremely low off-state current; therefore, data (potential) written to the capacitor 550 through the transistor 500 can be held for a long period of time.

[0368] In the layer 13, insulating films such as an insulating layer 510, an insulating layer 512, an insulating layer 514, an insulating layer 516, an insulating layer 520, an insulating layer 522, an insulating layer 540, an insulating layer 544, an insulating layer 541, an insulating layer 542, an insulating layer 546, and an insulating layer 548 are stacked on the insulating layer 384. The insulating layer 512, the insulating layer 516, the insulating layer 540, the insulating layer 541, the insulating layer 546, and the insulating layer 548 function as interlayer insulating films. Furthermore, it is preferable to use an insulating film having a barrier property that prevents diffusion of hydrogen, impurities, and the like for the insulating layer 510, the insulating layer 514, the insulating layer 520, the insulating layer 522, the insulating layer 544, the insulating layer 542, and the like.

[0369] A conductive layer 518 is provided so as to be buried in the insulating layers 510, 512, 514, and 516. The conductive layer 518 functions as a plug. In FIG. 24, the conductive layer 518 is provided in contact with the conductive layer 386.

[0370] The transistor 500 includes a conductive layer 505 arranged so as to be embedded in the insulating layer 516, an insulating layer 520 and an insulating layer 522 on the insulating layer 516 and the conductive layer 505, an insulating layer 524 on the insulating layer 522, a semiconductor layer 501 on the insulating layer 524, a pair of conductive layers 504 on the semiconductor layer 501, an insulating layer 540 located on the conductive layer 504 and having a groove reaching the semiconductor layer 501, and an insulating layer 503 and a conductive layer 502 provided so as to be embedded in the insulating layer 540.

[0371] In the transistor 500, one of a pair of conductive layers 504 functions as a source electrode and the other functions as a drain electrode. The conductive layer 502 functions as a first gate electrode, and the insulating layer 503 functions as a first gate insulating layer. The conductive layer 505 functions as a second gate electrode, and the insulating layers 520, 522, and 524 function as a second gate insulating layer.

[0372] The insulating layer 524 and the insulating layer 503 in contact with the semiconductor layer 501 are preferably made of an oxide or oxynitride, such as silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide. Alternatively, nitrogen-containing compounds, such as silicon nitride, silicon nitride oxide, or aluminum nitride, may be used. Furthermore, it is preferable to use a single layer or a stack of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become more miniaturized and highly integrated, thinning of the gate insulating film can cause problems such as leakage current. Therefore, using a high-k material as an insulator that functions as a gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0373] A stacked film in which a plurality of insulating films are stacked is preferably used as the insulating layer 503. For example, a stacked film in which two, three, or four or more layers of films made of the above insulating materials are stacked is preferably used.

[0374] Alternatively, a thin film containing the above-described ferroelectric material may be used as the insulating layer 503. In this case, the transistor 500 can be used as a nonvolatile memory element. In this case, the capacitor 550 does not necessarily have to be used.

[0375] The insulating layer 534 is provided to cover the conductive layer 504 and has a function of suppressing oxidation of the conductive layer 504. In this case, the insulating layer 534 is provided to cover the side surfaces of the semiconductor layer 501 and the insulating layer 524 and to be in contact with the insulating layer 522. The insulating layer 534 is preferably an insulating film having a barrier property that prevents diffusion of hydrogen, impurities, and the like.

[0376] The capacitor 550 is provided on the insulating layer 546. The capacitor 550 has a conductive layer 551, a conductive layer 552, and an insulating layer 553 located therebetween. The capacitor 550 is a so-called MIM (Metal-Insulator-Metal) capacitor.

[0377] The insulating layer 553 is preferably a single layer or a stack of layers of an insulator containing the above-described high-k material. Alternatively, the above-described ferroelectric material can be used for the insulating layer 553. This allows the capacitor 550 to be a ferroelectric capacitor, and by combining it with the transistor 500, a nonvolatile memory cell can be realized.

[0378] A conductive layer 554 functioning as a wiring may be provided over the insulating layer 546. The conductive layer 554 can be formed by processing the same conductive film as the conductive layer 551.

[0379] The conductive layer 554 and the conductive layer 504 are connected through the conductive layer 536 and the conductive layer 538. The conductive layer 536 and the conductive layer 538 function as plugs. The conductive layer 536 and the conductive layer 538 can be formed using the same materials as the conductive layer 328 and the conductive layer 330.

[0380] Fig. 25 shows an example in which the configuration of the layer 13 is different from that of Fig. 24. In Fig. 25, a transistor 400a and a transistor 400b are provided in the layer 13. The transistors 400a and 400b are both vertical transistors.

[0381] The transistor 400a and the transistor 400b each include a semiconductor layer 401, a conductive layer 402 functioning as a gate electrode, an insulating layer 403 functioning as a gate insulating layer, a conductive layer 404 functioning as one of a source electrode and a drain electrode, and a conductive layer 406 functioning as the other.

[0382] The structure of the transistor 400b will be described. A conductive layer 407 is provided over an insulating layer 516, a conductive layer 406 is provided over the conductive layer 407, and an insulating layer 410 is provided to cover the conductive layer 406. A conductive layer 405 is provided over the insulating layer 410, and a conductive layer 404 is provided over the conductive layer 405. Openings reaching the conductive layer 406 are provided in the conductive layers 404, 405, and the insulating layer 410. A semiconductor layer 401 is in contact with the conductive layers 404 and 406 and is in contact with a side surface of the insulating layer 410 located at the opening. An insulating layer 403 is provided to cover the semiconductor layer 401, and a conductive layer 402 is provided to fill the opening.

[0383] In one or both of the transistors 400a and 400b, a thin film containing a material exhibiting ferroelectricity applicable to the insulating layer 130 can be used as the insulating layer 403 functioning as a gate insulating layer. In particular, it is preferable to use such a thin film for the insulating layer 403 of the transistor 400b. This allows the transistor 400b to be used as a nonvolatile memory element.

[0384] Although various semiconductor materials can be used for the semiconductor layer 401, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a large on-state current and an extremely small off-state current can be realized at low cost. Unless otherwise specified, a preferred structure example in which an oxide semiconductor is used for the semiconductor layer 401 will be described below.

[0385] The conductive layer 404 and the conductive layer 406 have a structure in which the semiconductor layer 401 is in contact with the upper surface thereof. Therefore, when an oxide semiconductor is used for the semiconductor layer 401, the exposed surfaces of the conductive layer 404 and the conductive layer 406 may be oxidized due to the influence of heat applied during or after the deposition process of the semiconductor film that becomes the semiconductor layer 401, and an insulating oxide film may be formed between the conductive layer 404 and the conductive layer 406 and the semiconductor layer 401, resulting in an increase in contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for at least the uppermost portions of the conductive layer 404 and the conductive layer 406. This can prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layer 404 and the conductive layer 406. The conductive layer 404 and the conductive layer 406 can also be called an oxide layer, a metal oxide layer, an oxide conductor layer, or the like.

[0386] The conductive layer 405 can be used as one of the source wiring and the drain wiring. Part of the conductive layer 407 can be used as the other of the source wiring and the drain wiring. By providing the conductive layer 405 and the conductive layer 407 in contact with the conductive layer 404 and the conductive layer 406, respectively, in this manner, the electrical resistance of the wiring can be reduced. For the conductive layer 405 and the conductive layer 407, a material having higher conductivity than an oxide conductor, such as a metal, an alloy, or a nitride thereof, is preferably used.

[0387] The semiconductor layer 401 is provided in contact with a sidewall of the opening of the insulating layer 410. It is preferable to use an oxide insulating film for the insulating layer 410. In particular, it is preferable to use an oxide insulating film that releases oxygen by heating. The insulating layer 410 preferably has a stacked structure of three or more layers in which an oxide insulating film is sandwiched between insulating films (for example, nitride insulating films) that have a barrier property against oxygen. This structure allows oxygen contained in the oxide insulating film to be confined in a region surrounded by the pair of nitride insulating films and the semiconductor layer 401, and oxygen in the oxide insulating film can be prevented from being released and reduced during the process; therefore, oxygen can be more efficiently supplied to the semiconductor layer 401.

[0388] The transistor 400a has a structure similar to that of the transistor 400b except that an insulating layer 414 is used instead of the insulating layer 410 and a conductive layer 402 is used instead of the conductive layer 406 of the transistor 400b.

[0389] The gate electrode of the transistor 400b also serves as one of the source electrode and drain electrode of the transistor 400a.

[0390] The insulating layers 410, 414, and 418 function as interlayer insulating films. For the insulating layers 412, 416, and the like, an insulating film having a barrier property against hydrogen, impurities, and the like is preferably used.

[0391] The transistors 400a and 400b are vertical transistors. Therefore, the configuration of the transistor Tr described above can be referred to for the configuration of the transistors 400a and 400b. Furthermore, the configuration of the transistors 400a and 400b may be applied to the transistor Tr described above.

[0392] Fig. 26 illustrates an example in which the configuration is partially different from that of Fig. 25. The layer 13 illustrated in Fig. 26 includes a transistor 400 having a similar configuration to the transistor 400a and a capacitor 420 instead of the transistor 400b.

[0393] The capacitor 420 includes a conductive layer 421, a conductive layer 422, and an insulating layer 423 sandwiched between them. The insulating layer 423 functions as a dielectric layer of the capacitor 420. The conductive layer 407 is provided in contact with the conductive layer 421 and functions as a wiring.

[0394] An opening reaching the conductive layer 407 is provided in the insulating layer 410. A conductive layer 421 is provided in contact with the top surface of the insulating layer 410, the side surface located in the opening, and the top surface of the conductive layer 407 located at the bottom of the opening. An insulating layer 423 is provided to cover the conductive layer 421. A conductive layer 422 is provided to cover the insulating layer 423.

[0395] The insulating layer 423 is preferably formed using a single layer or a stack of layers of an insulator containing the above-described high-k material. Alternatively, the above-described material exhibiting ferroelectricity can be used for the insulating layer 423. In this way, the capacitor 420 can be a ferroelectric capacitor, and a nonvolatile memory cell can be realized by combining the capacitor 420 with the transistor 400.

[0396] By stacking a vertical transistor and a vertical capacitor in this manner, the area occupied by the memory cell can be made extremely small, which facilitates high integration and enables the realization of a memory device with a large capacity.

[0397] The above is a description of an example of the cross-sectional structure of a semiconductor device.

[0398] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0399] Embodiment 2 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0400] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. FIG. 27A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and recording density are required. In FIG. 27A , from the top layer, there are memories embedded as registers in a processing unit such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, and storage. Note that while an example having up to an L3 cache is shown here, lower-level caches may also be included.

[0401] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0402] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate faster than main memory. In addition, data rewritten in the cache is duplicated and supplied to main memory.

[0403] The main memory has a function of holding programs, data, etc. read from the storage.

[0404] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.

[0405] A storage device according to one aspect of the present invention has a storage device with a large storage capacity, and therefore can be applied to the tier where the storage is located in Fig. 27A. Furthermore, a storage device according to one aspect of the present invention that includes both a storage device with a large storage capacity and a storage device with a high operating speed can be applied to both the tier where the storage is located and the tier where the main memory is located.

[0406] Furthermore, a storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 27A , the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where a cache is located and the hierarchy where a main memory is located.

[0407] FIG. 27B also shows an example in which an SRAM is used as part of a cache and an OS memory of one embodiment of the present invention is used as the other part of the cache.

[0408] The lowest level cache can be called a last level cache (LLC). While an LLC does not require faster operation speed than higher level caches, it is desirable for the LLC to have a large storage capacity. The OS memory of one embodiment of the present invention has a high operation speed and can retain data for a long period of time, and therefore can be suitably used for an LLC. The OS memory of one embodiment of the present invention can also be applied to a final level cache (FLC).

[0409] For example, as shown in Fig. 27B, a configuration can be adopted in which SRAM is used for the higher-level caches (L1 cache, L2 cache, etc.) and the OS memory according to one aspect of the present invention is used for the LLC. Also, as shown in Fig. 27B, not only the OS memory but also DRAM can be applied to the main memory.

[0410] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0411] Embodiment 3 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0412] The storage device of one embodiment of the present invention can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, and game consoles). The storage device can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0413] 28A to 28J and 29A to 29E illustrate examples of electronic devices including a memory device according to one embodiment of the present invention.

[0414] 28A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0415] By applying a storage device of one embodiment of the present invention, the information terminal 5500 can store data used by an application or store temporary files generated when an application is executed (e.g., a cache when using a web browser).

[0416] 28B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0417] Like the information terminal 5500 described above, a wearable device can store data used in an application or temporary files generated when an application is executed by applying a storage device of one embodiment of the present invention.

[0418] 28C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0419] Like the information terminal 5500 described above, the desktop information terminal 5300 can store data used by an application or temporary files generated when an application is executed by applying a storage device of one embodiment of the present invention.

[0420] In Figures 28A to 28C, smartphones, wearable terminals, and desktop information terminals have been described as electronic devices, but other information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0421] 28D shows an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, and a freezer compartment door 5803. For example, the electric refrigerator-freezer 5800 is an IoT-compatible electric refrigerator-freezer.

[0422] The storage device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to and from an information terminal via the Internet, for example. The electric refrigerator-freezer 5800 can store programs and data used by the programs, or temporary files generated when transmitting the information, in the storage device of one embodiment of the present invention.

[0423] In Figure 28D, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0424] 28E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0425] FIG. 28F also shows a stationary game console 7500, which is an example of a game console. The stationary game console 7500 is a home-use stationary game console. The stationary game console 7500 includes a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or via a wired connection. The shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, the shape may be modeled after a gun, a musical instrument, or a musical device. Alternatively, the controller may be equipped with one or more of a camera, a depth sensor, a motion sensor, and a microphone instead of a controller, and may be operated by the game player's gestures or voice.

[0426] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a computer display, a game display, or a head-mounted display.

[0427] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500. Furthermore, the reduced power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0428] Furthermore, by applying a storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500, it is possible to store programs or data used by the programs, or temporary files and the like required for calculations that occur during game execution.

[0429] Other examples of game machines to which the storage device of one embodiment of the present invention can be applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0430] [Mobile Body] A storage device according to one embodiment of the present invention can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0431] FIG. 28G illustrates an automobile 5700 as an example of a moving object.

[0432] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows such information may also be provided around the driver's seat.

[0433] In particular, the display device can compensate for, for example, a view blocked by a pillar or a blind spot of the driver's seat, thereby improving safety, by displaying an image from an imaging device (not shown) provided on the automobile 5700. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0434] The storage device of one embodiment of the present invention can store a program for performing hazard prediction, data used for the program, etc. The storage device of one embodiment of the present invention can store temporary information necessary for a system for performing autonomous driving, road guidance, hazard prediction, etc. of the automobile 5700. The storage device of one embodiment of the present invention may also store video images from a driving recorder installed in the automobile 5700.

[0435] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0436] [Camera] The storage device according to one embodiment of the present invention can be applied to a camera.

[0437] 28H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0438] The storage device of one embodiment of the present invention can be applied to the digital camera 6240. In this case, captured image data can be stored. Furthermore, temporary data used in the system of the digital camera 6240 can also be stored.

[0439] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the digital camera 6240. Furthermore, the reduced power consumption can reduce heat generation from a circuit, and the influence of heat on the circuit itself, peripheral circuits, and modules can be reduced.

[0440] [Video Camera] The storage device of one embodiment of the present invention can be applied to a video camera.

[0441] 28I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0442] By using the storage device of one embodiment of the present invention, a large amount of captured video data can be stored. Furthermore, when recording video captured by the video camera 6300, encoding needs to be performed according to the data recording format. By using the storage device of one embodiment of the present invention, the video camera 6300 can store temporary files generated during encoding.

[0443] [ICD] The storage device according to one aspect of the present invention can be applied to an implantable cardioverter defibrillator (ICD).

[0444] 28J is a cross-sectional schematic diagram showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0445] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0446] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0447] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store, in the electronic component 700, data on the heart rate acquired by the sensor, the number of times pacing therapy has been performed, or the duration of the therapy, for example.

[0448] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0449] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0450] Furthermore, by applying the storage device of one embodiment of the present invention to the ICD main body 5400, acquired physiological signal data can be stored as digital data. The ICD main body 5400 can output the stored data in response to a request from an external monitor device. For example, various types of biological information can be managed by a portable information terminal device such as a smartphone.

[0451] [Expansion Device for PC] A storage device according to one aspect of the present invention can be applied to an expansion device for a computer such as a PC (Personal Computer) and an information terminal.

[0452] 29A shows an expansion device 6100 that can be connected to a PC via USB (Universal Serial Bus). The expansion device 6100 can be used as a USB memory stick. The expansion device 6100 is not limited to a compact form, and may also be a relatively large expansion device equipped with a cooling fan.

[0453] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with, for example, a circuit that drives the storage device of one embodiment of the present invention. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0454] [SD Card] A storage device according to one embodiment of the present invention can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.

[0455] FIG. 29B is a schematic diagram of the external appearance of an SD card, and FIG. 29C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 700.

[0456] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 700.

[0457] [SSD] A storage device according to one embodiment of the present invention can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0458] FIG. 29D is a schematic diagram of the external appearance of an SSD, and FIG. 29E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a memory device and a circuit for driving the memory device. For example, the circuit board 5153 is equipped with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC (Error-Correcting Code) circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0459] 29F is an example of a large-scale computer. The computer 5600 has a rack 5610 in which a plurality of rack-mounted computers 5620 are stored.

[0460] The computer 5620 can have the configuration shown in the perspective view in Fig. 29G, for example. In Fig. 29G, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0461] A PC card 5621 shown in Figure 29H is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 29H illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.

[0462] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0463] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621 or inputting signals. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). When a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0464] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0465] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU.

[0466] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0467] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0468] By using the storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be miniaturized and consume less power. Furthermore, the storage device of one embodiment of the present invention consumes less power, which can reduce heat generation from a circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the storage device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0469] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0470] BG: wiring, BL: wiring, BLD: circuit, BSL: wiring, BTr: transistor, C_1: capacitor, C_n: capacitor, CA: capacitor, CB: capacitor, CC: capacitor, CD: capacitor, CE: capacitor, CG: wiring, CL: wiring, CS: control signal, CTR: control circuit, CVC: circuit, MC_1: memory cell, MC_2: memory cell, MC_3: memory cell, MC_n: memory cell, MC_p: memory cell, MC: memory cell, MCA: memory cell, MCAA: memory cell array, MCB: memory cell, MCC: memory cell, MCD: memory cell ,MCE: memory cell, MCF: memory cell, MCG_1: memory cell, MCG_n: memory cell, MCG: memory cell, MCL: memory cell unit, OSC: circuit, OUTP: output circuit, PRPH: circuit, RDATA: data signal, SRG: memory string, SSL: wiring, STr: transistor, Tr_1: transistor, Tr_n: transistor, Tr: transistor, TrG: transistor, Vc: coercive voltage, WDATA: data signal, WL_1: wiring, WL_n: wiring, WL: wiring, WLD: circuit, 11: layer, 12: layer, 13: layer, 21: memory device , 50: insulating layer, 51: conductive layer, 52: conductive layer, 53: conductive layer, 54: plug, 55: plug, 56: plug, 60: memory string, 65: memory cell, 71: curve, 72: curve, 100A: memory string, 100B: memory string, 100: memory string, 110_1: conductive layer, 110_2: conductive layer, 110_3: conductive layer, 110_n: conductive layer, 110: conductive layer, 115_1: conductive layer, 115_p: conductive layer, 115f: conductive film, 115: conductive layer, 120_1: conductive layer, 120_p: conductive layer, 120f: conductive film, 120: conductive layer, 13 0a: insulating layer, 130b: insulating layer, 130: insulating layer, 140: insulating layer, 141: transistor, 142: transistor, 143: transistor, 180: insulating layer, 190_1: opening, 190: opening, 215_1: conductive layer, 215_n: conductive layer, 215: conductive layer, 220_1: conductive layer, 220_2: conductive layer, 220_j: conductive layer, 220_q: conductive layer, 220: conductive layer, 225_1: insulating layer, 225_n: insulating layer, 225: insulating layer, 230_1: semiconductor layer, 230_2: semiconductor layer, 230_k: semiconductor layer, 230_r: semiconductor layer, 230f: semiconductor film,230: semiconductor layer, 240_1: conductive layer, 240_2: conductive layer, 240_3: conductive layer, 240_k: conductive layer, 240_r: conductive layer, 240f: conductive film, 240: conductive layer, 250: insulating layer, 260_1: conductive layer, 260_2: conductive layer, 260_3: ​​conductive layer, 260_p: conductive layer, 260: conductive layer, 261: conductive layer, 262: conductive layer, 263: conductive layer, 265: conductive layer, 267_1: conductive layer, 267_2: conductive layer, 267: conductive layer, 280: insulating layer, 281: insulating layer, 283: insulating layer, 284: insulating layer, 285: insulating layer, 290_1: opening, 290_2: opening portion, 290_3: opening, 290: opening, 291_1: opening, 291_2: opening, 291_3: opening, 291: opening, 292_1: opening, 292: opening, 293_1: opening, 293: opening, 294: opening, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 335: insulating layer, 336: insulating layer, 341: conductive layer, 342: conductive layer, 34 3: plug, 345: insulating layer, 346: insulating layer, 350: insulating layer, 362: conductive layer, 363: conductive layer, 372: conductive layer, 373: conductive layer, 382: insulating layer, 384: insulating layer, 386: conductive layer, 400a: transistor, 400b: transistor, 400: transistor, 401: semiconductor layer, 402: conductive layer, 403: insulating layer, 404: conductive layer, 405: conductive layer, 406: conductive layer, 407: conductive layer, 410: insulating layer, 412: insulating layer, 414: insulating layer, 416: insulating layer, 418: insulating layer, 420: capacitor, 421: conductive layer, 422: conductive layer, 423: insulating layer , 500: transistor, 501: semiconductor layer, 502: conductive layer, 503: insulating layer, 504: conductive layer, 505: conductive layer, 510: insulating layer, 512: insulating layer, 514: insulating layer, 516: insulating layer, 518: conductive layer, 520: insulating layer, 522: insulating layer, 524: insulating layer, 534: insulating layer, 536: conductive layer, 538: conductive layer, 540: insulating layer, 541: insulating layer, 542: insulating layer, 544: insulating layer, 546: insulating layer, 548: insulating layer, 550: capacitor element, 551: conductive layer, 552: conductive layer, 553: insulating layer, 554: conductive layer, 700: electronic component, 1000a: semiconductor device,1000b: semiconductor device, 1000: semiconductor device, 1100: arithmetic processing unit, 1150A: semiconductor device, 1150B: semiconductor device, 1150C: semiconductor device, 1189: cache interface, 1190: substrate, 1191: ALU, 1192: ALU controller, 1193: instruction decoder, 1194: interrupt controller, 1195: timing controller, 1196: register, 1197: register controller, 1198: bus interface, 1199: cache, 5110: SD card, 5111: housing, 5112: Connector, 5113: Board, 5115: Controller chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Board, 5155: Memory chip, 5156: Controller chip, 5200: Portable game console, 5201: Housing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display unit, 5303: Keyboard, 5400: ICD main unit, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: information terminal, 5510: housing, 5511: display unit, 5600: computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 5700: automobile, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator door, 5803: freezer door, 5900: information terminal, 5901: housing, 5902: display unit, 5 903: operation switch, 5904: operation switch, 5905: band, 6100: expansion device, 6101: housing, 6102: cap, 6103: USB connector, 6104: board, 6106: controller chip, 6240: digital camera, 6241: housing, 6242: display unit, 6243: operation switch, 6244: shutter button, 6246: lens, 6300: video camera, 6301: first housing, 6302: second housing, 6303: display unit, 6304: operation switch, 6305: lens, 6306: connection unit, 7500: stationary game console,7520: Main body, 7522: Controller,

Claims

A first conductive layer; and a first insulating layer disposed on the first conductive layer and having a first opening with a region overlapping the first conductive layer; a second conductive layer in contact with a side surface of the first insulating layer and an upper surface of the first conductive layer in the first opening; a second insulating layer on the second conductive layer and on the first insulating layer; a third conductive layer disposed on the second insulating layer and having a region embedded in the first opening via the second insulating layer and the second conductive layer; a fourth conductive layer disposed on the second insulating layer and spaced apart from the third conductive layer; a third insulating layer disposed on the third conductive layer, the fourth conductive layer, and the second insulating layer, the third insulating layer having a second opening having a region overlapping the third conductive layer, and a third opening having a region overlapping the fourth conductive layer; a fifth conductive layer on the third insulating layer, the fifth conductive layer having a fourth opening overlapping the third opening; an oxide semiconductor layer in contact with an upper surface of the fifth conductive layer, a side surface of the fifth conductive layer in the fourth opening, a side surface of the third insulating layer in the third opening, and an upper surface of the fourth conductive layer in the third opening; a fourth insulating layer disposed on the oxide semiconductor layer and the third insulating layer and having a fifth opening overlapping the second opening; a sixth conductive layer on the fourth insulating layer; the sixth conductive layer has a region embedded in the third opening and the fourth opening via the fourth insulating layer and the oxide semiconductor layer, and a region in contact with the third conductive layer in the fifth opening and the second opening; The fourth conductive layer has the same material as the third conductive layer. 　 In claim 1, a seventh conductive layer on the second insulating layer and an eighth conductive layer on the fourth insulating layer; the third insulating layer has a sixth opening having a region overlapping with the seventh conductive layer; the fifth conductive layer has a seventh opening overlapping the sixth opening; the oxide semiconductor layer has a region in contact with a side surface of the fifth conductive layer in the seventh opening, a side surface of the third insulating layer in the sixth opening, and an upper surface of the seventh conductive layer in the sixth opening; the eighth conductive layer has a region embedded in the seventh opening and the sixth opening via the fourth insulating layer and the oxide semiconductor layer. 　 In claim 2, The seventh conductive layer has the same material as the third conductive layer. 　 In claim 2, The eighth conductive layer has the same material as the sixth conductive layer. 　 In any one of claims 1 to 4, The second insulating layer comprises a ferroelectric material. 　 In claim 5, The second insulating layer comprises hafnium, zirconium, and oxygen. 　 In claim 6, The second insulating layer further contains one or more elements selected from the group consisting of scandium, yttrium, and lanthanum. 　 In claim 5, The semiconductor device, wherein the oxide semiconductor layer contains indium and oxygen. 　 a capacitance element, a first transistor, and a second transistor; the capacitive element includes a first conductive layer, a second conductive layer on the first conductive layer, and a first insulating layer having a region located between the first conductive layer and the second conductive layer; a third conductive layer functioning as one of a source electrode and a drain electrode of the first transistor is provided over the first insulating layer; the third conductive layer has the same material as the second conductive layer; a fourth conductive layer functioning as the other of the source electrode and the drain electrode of the first transistor is located above the third conductive layer and has a region overlapping with the third conductive layer; a fifth conductive layer functioning as a gate electrode of the first transistor has a region in contact with the second conductive layer, the third conductive layer has a region functioning as one of a source electrode and a drain electrode of the second transistor. In claim 9, The second conductive layer has a region facing a side surface of the first conductive layer with the first insulating layer interposed therebetween. 　 In claim 9 or 10, The first insulating layer comprises a ferroelectric material. 　 In claim 11, The first insulating layer comprises hafnium, zirconium, and oxygen. 　 In claim 12, The semiconductor device, wherein the first insulating layer further contains one or more elements selected from the group consisting of scandium, yttrium, and lanthanum. 　 In claim 11, the first transistor is disposed above the first insulating layer and includes a semiconductor layer having a region in contact with the third conductive layer and the fourth conductive layer; The semiconductor device, wherein the semiconductor layer contains indium and oxygen. 　 forming a first conductive layer; forming a first insulating layer having a first opening with a region overlapping the first conductive layer; forming a second conductive layer in contact with a side surface of the first insulating layer and an upper surface of the first conductive layer in the first opening; forming a second insulating layer on the second conductive layer and on the first insulating layer; forming a first conductive film on the second insulating layer; processing the first conductive film to form a third conductive layer and a fourth conductive layer disposed so as to fill the first opening; forming a third insulating layer on the third conductive layer, on the fourth conductive layer, and on the second insulating layer; forming a second conductive film on the third insulating layer; forming a second opening portion having a region overlapping with the fourth conductive layer in the second conductive film and the third insulating layer; forming an oxide semiconductor layer so as to be in contact with a side surface of the second conductive film, a side surface of the third insulating layer, and an upper surface of the fourth conductive layer in the second opening; forming a fourth insulating layer on the oxide semiconductor layer; forming a third opening in the fourth insulating layer and the third insulating layer, the third opening having a region overlapping with the third conductive layer; a fifth conductive layer is formed so as to fill the second opening and the third opening. 　 In claim 15, forming an oxide film containing hafnium and zirconium by atomic layer deposition as the second insulating layer. 　 In claim 15, a second insulating layer formed by atomic layer deposition of an oxide film containing at least one element selected from the group consisting of scandium, yttrium, and lanthanum in addition to hafnium and zirconium; 　 In claim 16 or 17, the method for manufacturing a semiconductor device further comprising the steps of: performing heat treatment at a temperature of 300° C. or higher and 750° C. or lower using an RTA apparatus after the second insulating layer is formed and before the oxide semiconductor layer is formed. 　 In claim 15, The method for manufacturing a semiconductor device further comprises forming an oxide film containing indium by an atomic layer deposition method as the oxide semiconductor layer.

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