Power supply device

Abstract

According to the present invention, first to fourth switching elements (M1 to M4) are connected in series toward a power supply node that receives an input voltage (VIN) from a reference node. Each switching element comprises an N channel-type MOSFET. In order to turn on the second to fourth switching elements, first to third boot voltages (VBOOT1 to VBOOT3) supplied to the gates of the second to fourth switching elements are generated in first to third boot wirings (WBOOT1 to WBOOT3). The respective boot voltages are generated using first to third boot capacitors (CBOOT1 to CBOOT3) and first to third boot switches (Ma to Mc), the first to third boot capacitors and the first to third boot switches being provided to correspond to the first to third boot wirings, respectively.

Description

power supply

[0001] The present disclosure relates to a power supply device.

[0002] 2. Description of the Related Art Power supply devices that use multiple switching techniques to step down an input voltage to generate a desired output voltage are widely used.

[0003] Japanese Patent Application Laid-Open No. 2020-89043

[0004] [Summary] Improving efficiency is important in power supply devices.

[0005] The power supply device according to the present disclosure includes a first switching element provided between a first node and a reference node having a potential lower than an input voltage, a second switching element provided between the first node and a second node, a third switching element provided between the second node and a third node, a fourth switching element provided between the third node and a fourth node receiving the input voltage, a boost circuit configured to generate a first boot voltage on a first boot wiring to be supplied to a gate of the second switching element to turn on the second switching element, generate a second boot voltage on a second boot wiring to be supplied to the gate of the third switching element to turn on the third switching element, and generate a third boot voltage on a third boot wiring to be supplied to the gate of the fourth switching element to turn on the fourth switching element, a control circuit configured to generate a control signal for specifying a state of each switching element, and a control circuit configured to control the first switching element in response to the control signal using a predetermined drive voltage and the first to third boot voltages. a drive circuit configured to individually turn on or off the first to fourth switching elements, and generates an output voltage lower than the input voltage by controlling the states of the first to fourth switching elements, the first to fourth switching elements being each composed of an N-channel field effect transistor, the boost circuit comprising: a first boot capacitor provided between the first node and the first boot wiring, a second boot capacitor provided between the second node and the second boot wiring, a third boot capacitor provided between the third node and the third boot wiring, a first boot switch provided between the drive wiring to which the drive voltage is applied and the first boot wiring, a second boot switch provided between the first boot wiring and the second boot wiring, and a third boot switch provided between the second boot wiring and the third boot wiring, and the first to third boot voltages are generated by the control circuit controlling the states of each switching element and each boot switch.

[0006] FIG. 1 is an overall configuration diagram of a power supply device according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating the relationship between control signals, gate signals, and the states of switching elements according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating the flow of current when switching control is performed in the power supply device according to the first embodiment of the present disclosure. FIG. 4 is a configuration diagram of a power supply device according to the first embodiment of the present disclosure, illustrating the internal configuration of a control circuit. FIG. 5 is a timing chart of the power supply device according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating the internal configuration of a drive circuit according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating the internal configuration of a boost circuit according to the first embodiment of the present disclosure. FIG. 8 is a diagram illustrating the internal configurations of a drive circuit and a boost circuit according to the first embodiment of the present disclosure. FIG. 9 is a diagram illustrating the state of each switching element and each boot switch in state ST_A1 according to the first embodiment of the present disclosure. FIG. 10 is a diagram illustrating the state of each switching element and each boot switch in state ST_A2 according to the first embodiment of the present disclosure. FIG. 11 is an external perspective view of a power supply control device according to the first embodiment of the present disclosure. FIG. 12 is a diagram illustrating the relationship between a power supply control device and a group of discrete components according to the first embodiment of the present disclosure. FIG. 13 is an overall configuration diagram of a power supply device according to a second embodiment of the present disclosure. FIG. 14 is a diagram illustrating the state and generated current of each switching element in state ST_B1 according to the second embodiment of the present disclosure. FIG. 15 is a diagram illustrating the state and generated current of each switching element in state ST_B2 according to the second embodiment of the present disclosure. FIG. 16 is a diagram illustrating the state and generated current of each switching element in state ST_B3 according to the second embodiment of the present disclosure. FIG. 17 is a diagram illustrating the state and generated current of each switching element in state ST_B4 according to the second embodiment of the present disclosure. FIG. 18 is an overall configuration diagram of a power supply device according to a third embodiment of the present disclosure. FIG. 19 is a diagram illustrating the state and generated current of each switching element in state ST_C1 according to the third embodiment of the present disclosure. FIG. 20 is a diagram illustrating the state and generated current of each switching element in state ST_C2 according to the third embodiment of the present disclosure. FIG. 21 is a diagram showing the states of the switching elements and the generated currents in the state ST_C3 according to the third embodiment of the present disclosure.Fig. 22 is a diagram showing the states of each switching element and generated current in state ST_C4 according to the third embodiment of the present disclosure. Fig. 23 is a diagram showing the internal configuration of a control circuit according to the third embodiment of the present disclosure. Fig. 24 is a timing chart of the power supply device according to the third embodiment of the present disclosure. Fig. 25 is a diagram showing a modified example of the power supply device according to the third embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0 V (zero volts) or the 0 V reference potential itself. When a component, electrode, or node is connected to ground, it means that the component, electrode, or node is connected to a reference node having a reference potential of 0 V. The reference node and ground can be read interchangeably.

[0009] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a high level signal or voltage strictly means that the signal or voltage level is high, and a low level signal or voltage strictly means that the signal or voltage level is low. For any given signal or voltage, a transition from a low level to a high level is called a rising edge, and a transition from a high level to a low level is called a falling edge.

[0010] Any switching element can be configured with a transistor. For any transistor configured as a FET (field effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Furthermore, unless otherwise specified, the back gate of any MOSFET can be considered to be short-circuited to the source.

[0011] Hereinafter, the on and off states of any switching element (transistor) may be simply referred to as on and off. For any switching element, switching from the off state to the on state is referred to as turning on, and switching from the on state to the off state is referred to as turning off. Furthermore, for any switching element, the period during which the switching element is in the on state is referred to as the on period, and the period during which the switching element is in the off state is referred to as the off period.

[0012] For any signal that takes a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. The same applies to any voltage that takes a high or low voltage level.

[0013] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0014] If two arbitrary voltages to be compared are voltages v1 and v2, then "v1>v2" indicates that voltage v1 is higher than voltage v2, and "v1<v2" indicates that voltage v1 is lower than voltage v2. The same applies to other equations that include physical quantities other than voltage.

[0015] <<First Embodiment>> A first embodiment of the present disclosure will be described. Fig. 1 is an overall configuration diagram of a power supply device 1A according to a first embodiment of the present disclosure. The power supply device 1A receives a positive input voltage V from a voltage source (not shown). IN is supplied, and the input voltage V IN By stepping down the voltage, a positive output voltage V OUT Generates an output voltage V OUT is the input voltage V IN The power supply device 1A has an output voltage V OUT That is, in a steady state, the output voltage V OUT The target voltage is substantially equal to the target voltage. Hereinafter, the target voltage is referred to as "V TG In the power supply device 1A, the intermediate voltage V MID is generated. The output voltage V OUT is the intermediate voltage V MID Also, in the steady state, the intermediate voltage V MID is essentially the input voltage V IN Therefore, "V IN >2 x V OUT " is true. "V IN >2 x V OUT As long as " is true, the input voltage V IN and output voltage V OUT The value of "V" is arbitrary. IN >2 x V TG As long as " is true, the input voltage V IN and target voltage V TG The value of is arbitrary. For example, the input voltage V IN is 48V, and the target voltage V TG (i.e., the output voltage V OUT ) is 12V or 5V.

[0016] Regarding the power supply device 1A, the steady state is when the output voltage V OUT rises from 0V to the target voltage V TG After reaching OUT is the target voltage V TG In the following, unless otherwise specified, it is assumed that the power supply device 1A is in a steady state.

[0017] The power supply device 1A mainly comprises switching elements M1 to M4 and a capacitor C FLY , C MID and C OUT The power supply circuit includes an inductor L1, a control circuit 30A, a drive circuit 40A, and a boost circuit 50A. FLY can be called a flying capacitor. MID can be referred to as the intermediate capacitor. OUT can be referred to as the output capacitor.

[0018] The power supply device 1A includes a buck converter and a stacked converter. The buck converter in the power supply device 1A includes switching elements M1 and M2 and an inductor L1, and outputs an intermediate voltage V MID By lowering the voltage at the output node ND OUT Output voltage V OUT The capacitor C OUT The switching elements M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter. The stacked converter in the power supply device 1A includes the switching elements M3 and M4 and the capacitor C FLY and an input voltage V IN to intermediate voltage V MID The capacitor C MID can be understood to be included in the components of the stacked converter.

[0019] In this embodiment, the switching elements M1 to M4 are each configured by an N-channel MOSFET, and therefore hereinafter may be referred to as transistors M1 to M4.

[0020] The transistors M1 to M4 are connected in series between the ground and a node ND4. The transistor M1 is provided between the ground and the node ND1, the transistor M2 is provided between the nodes ND1 and ND2, the transistor M3 is provided between the nodes ND2 and ND3, and the transistor M4 is provided between the nodes ND3 and ND4. More specifically, the source of the transistor M1 is connected to the ground. The drain of the transistor M1 and the source of the transistor M2 are connected to the node ND1. The drain of the transistor M2 and the source of the transistor M3 are connected to the node ND2. The drain of the transistor M3 and the source of the transistor M4 are connected to the node ND3. The drain of the transistor M4 is connected to the node ND4. The node ND4 is connected to the input voltage V IN That is, the node ND4 is a power supply node that receives the input voltage V IN The signals supplied to the gates of the transistors M1 to M4 are referred to as gate signals G1 to G4, respectively.

[0021] Capacitor C FLY is provided between the nodes ND3 and ND1. That is, the capacitor C FLY The first end of the capacitor C is connected to the node ND3. FLY The second end of the transistor ND1 is connected to the node ND1.

[0022] Capacitor C MID is provided between the node ND2 and the ground. That is, the capacitor C MID The first end of the capacitor C is connected to the node ND2. MID The second end of the capacitor C is connected to ground. MID The first end of the capacitor C MID The voltage at node ND2 corresponds to the positive electrode of the intermediate voltage V MID That is, the capacitor C MID An intermediate voltage V MID The voltage at the node ND1 is V LX and the voltage at node ND3 is referred to as voltage V FLY It is called.

[0023] The inductor L1 is connected between the node ND1 and the output node ND OUTThat is, a first end of the inductor L1 is connected to the node ND1, and a second end of the inductor L1 is connected to the output node ND OUT is connected to.

[0024] Capacitor C OUT is the output node ND OUT and ground. That is, the capacitor C OUT The first end of the output node ND OUT and a capacitor C OUT The second end of the capacitor C is connected to ground. OUT The first end of the capacitor C OUT This corresponds to the positive electrode of the output node ND. OUT The voltage at is the output voltage V OUT That is, the capacitor C OUT An output voltage V OUT occurs.

[0025] The control circuit 30A generates and outputs control signals that specify the states (on or off) of the transistors M1 to M4. The control signals generated by the control circuit 30A include control signals CNT1 to CNT4. The control signals CNT1 to CNT4 are binary signals. Any binary signal has a low level or a high level. The control circuit 30A can individually set the levels of the control signals CNT1 to CNT4 to a high level or a low level. The drive circuit 40A is connected to each gate of the transistors M1 to M4 and supplies gate signals G1 to G4 to the transistors M1 to M4 in accordance with the control signals CNT1 to CNT4, thereby individually setting the states of the transistors M1 to M4 to on or off. The boost circuit 50A generates the voltage required to turn on the transistors M2 to M4 and supplies the generated voltage to the drive circuit 40A. Details of the boost circuit 50A will be described later.

[0026] The control circuit 30A cooperates with the drive circuit 40A and the boost circuit 50A to control the states of the transistors M1 to M4, thereby controlling the input voltage V IN The lower desired output voltage V OUT output node ND OUT to generate.

[0027] FIG. 2 shows the relationship between the control signals CNT1 to CNT4, the gate signals G1 to G4, and the states of the transistors M1 to M4. High-level control signals CNT1, CNT2, CNT3, and CNT4 are signals that specify turning on the transistors M1, M2, M3, and M4, respectively. Low-level control signals CNT1, CNT2, CNT3, and CNT4 are signals that specify turning off the transistors M1, M2, M3, and M4, respectively. Therefore, during the high-level period of the control signal CNT1, the gate signal G1 is also high, and the transistor M1 is turned on. During the low-level period of the control signal CNT1, the gate signal G1 is also low, and the transistor M1 is turned off. Similarly, during the high-level period of the control signal CNT2, the gate signal G2 is also high, and the transistor M2 is turned on. During the low-level period of the control signal CNT2, the gate signal G2 is also low, and the transistor M2 is turned off. Similarly, during the high level period of the control signal CNT3, the gate signal G3 also has a high level, and the transistor M3 is turned on. During the low level period of the control signal CNT3, the gate signal G3 also has a low level, and the transistor M3 is turned off. Similarly, during the high level period of the control signal CNT4, the gate signal G4 also has a high level, and the transistor M4 is turned on. During the low level period of the control signal CNT4, the gate signal G4 also has a low level, and the transistor M4 is turned off.

[0028] Output node ND OUT is connected to a load (not shown). The load is connected to an output voltage V OUT The output node ND is an arbitrary load that drives the OUT The current supplied to the load from LD The load current I LD corresponds to the output current of the power supply device 1A. The current flowing through the inductor L1 is the inductor current I L The node ND1 to the output node ND OUT The inductor current I L has a positive polarity, and the output node ND OUT An inductor current I flows from the node L is assumed to have negative polarity.

[0029] The control circuit 30A can use the drive circuit 40A to set the states of the transistors M1 to M4 to one of a plurality of states and switch between the plurality of states. The plurality of states includes states ST_A1 and ST_A2 shown in FIG. 3. In state ST_A1, the transistors M2 and M4 are on and the transistors M1 and M3 are off. In state ST_A2, the transistors M2 and M4 are off and the transistors M1 and M3 are on. A state in which the transistors M1 to M4 are all off may be included in the plurality of states, but in the following description of the present embodiment, the situation in which the transistors M1 to M4 are all off will be ignored.

[0030] The control circuit 30A can use the drive circuit 40A to perform switching control that alternately switches the states of the transistors M1 to M4 between states ST_A1 and ST_A2. Referring to FIG. 3, the current generated when the switching control is performed will be described. FLY (i.e., the potential at the node ND1) as a reference. FLY The current that increases the potential at the first end of the capacitor C FLY The reverse current is the charging current of the capacitor C FLY is the discharge current of the capacitor C MID Regarding the intermediate voltage V MID The current that increases the intermediate voltage V MID The current that decreases the capacitance is the discharge current.

[0031] In state ST_A1, currents 811 and 813 are generated. The current 811 flows through the capacitor C MID from the output node ND through the transistor M2 and the inductor L1. OUT is the current going to the capacitor C MID The current 813 is generated by the discharge of the input voltage V IN The voltage is applied from node ND4 to capacitor C FLY The current 813 flows into the capacitor C FLYis charged.

[0032] In state ST_A2, currents 812 and 814 are generated. The current 812 flows from ground through transistor M1 and inductor L1 to output node ND OUT The current 814 flows into the capacitor C FLY through the transistor M3 to the capacitor C MID The current 814 flows through the capacitor C FLY is generated by the discharge of the capacitor C MID contributes to charging.

[0033] In state ST_A1, transistors M2 and M4 are on, so that capacitor C FLY and C MID For state ST_A1, the capacitor C FLY and C MID In the state ST_A2, the capacitor C FLY and C MID As a result, the transistors M1 to M4 and the capacitor C FLY and C MID Therefore, in the steady state, the capacitor C MID The intermediate voltage V MID is approximately the voltage (V IN / 2) That is, the input voltage V IN The intermediate voltage V corresponds to the divided voltage of MID In this way, the control circuit 30A controls the transistors M1 to M4 and the capacitor C MID and C FLY The circuit having the intermediate voltage V MID Generates.

[0034] Meanwhile, the intermediate voltage V MIDTherefore, the power supply device 1A can be called a hybrid buck converter that combines a switched capacitor circuit and a synchronous buck converter.

[0035] The switched capacitor circuit generates an input voltage V IN is reduced to half, and the resulting intermediate voltage V MID High efficiency can be achieved by further stepping down the voltage using a synchronous buck converter.

[0036] For example, if the input voltage V is 48V, IN to 12V output voltage V OUT Consider the case where a 48V input voltage V is generated. As a reference method, a simple synchronous buck converter is used to directly step down 48V to 12V. In the reference method, IN By switching between these, a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 48 V) is generated, and the square wave voltage is rectified and smoothed to obtain an output voltage of 12 V. In contrast, in the power supply device 1A, the voltage (V IN / 2) to generate a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 24 V), and then the square wave voltage is rectified and smoothed to obtain an output voltage of 12 V. Therefore, compared to power supply devices related to the reference method, power supply device 1A can keep switching losses low.

[0037] There are several factors that contribute to the reduction of switching loss, some of which are listed below. In the reference method, the switching duty is relatively small. When the switching duty is relatively small, the effects of loss during periods when the instantaneous value of the square wave voltage rises and falls become relatively large. In contrast, when the power supply device 1A is used, the input voltage to the synchronous buck converter is a voltage (V IN / 2), the switching duty is relatively large compared to the reference method, which leads to an improvement in switching loss. Also, during the switching process, various parasitic capacitances are charged and discharged. In the power supply device 1A, the input voltage to the synchronous buck converter is a voltage (V IN / 2), the loss due to charging and discharging of the parasitic capacitance can be kept relatively low compared to the reference method.

[0038] FIG. 4 shows a configuration diagram of the power supply device 1A showing an example of the internal configuration of the control circuit 30A. L 5, it is assumed that the power supply device 1A operates in a continuous current mode where V is greater than 0 and V is greater than 1.0, and unless otherwise specified, only the configuration related to the continuous current mode will be described. LX , inductor current I L , error voltage V ERR , slope voltage V SLP , the waveforms of signals CLK, CMPOUT, CNT1, CNT2, CNT3, and CNT4 are shown.

[0039] The control circuit 30A includes an error amplifier 31, a ramp circuit 32, a current information acquisition circuit 33, an adder 34, a PWM comparator 35, an oscillator circuit (clock generation circuit) 36, and a controller 37. The power supply device 1A also includes resistors R1 and R2. A first end of the resistor R1 is connected to an output node ND. OUT The second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to ground. An output voltage V OUT Feedback voltage V according to FB The feedback voltage V FB is the output voltage V OUT Therefore, the output voltage V OUT The resistors R1 and R2 are proportional to the feedback voltage V FB A feedback voltage generating circuit is formed to generate the feedback voltage V FB is supplied to the control circuit 30A. However, it may be understood that the feedback voltage generating circuit is included in the components of the control circuit 30A. OUT It is the feedback voltage V FB In any case, the feedback voltage V FB is the output voltage V OUT Information on the output voltage V OUT It contains information indicating the value of

[0040] The error amplifier 31 is a current output type transconductance amplifier. The error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal. A feedback voltage V FB A predetermined reference voltage V REF The reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the control circuit 30A. The output terminal of the error amplifier 31 is connected to the wiring WR ERR When the power supply device 1A is started, the reference voltage V REF Although a soft start control may be performed to gradually increase the value of from 0 V to a predetermined positive voltage value, the existence of the soft start control will be ignored below.

[0041] The error amplifier 31 outputs a feedback voltage V FB and the reference voltage V REF By outputting a current signal corresponding to the difference between the feedback voltage V FB and the reference voltage V REF Error voltage V according to the difference between ERR Wiring WR ERR Specifically, the error amplifier 31 generates a feedback voltage V FB is the reference voltage V REF When the error voltage V ERR Wiring WR from its own output terminal so that ERR and outputs a current to the feedback voltage V FB is the reference voltage V REF When the error voltage V ERR Wiring WR to reduce ERR The current is drawn from the wiring WR ERR A phase compensation circuit including a capacitor may be connected between the input and ground.

[0042] The ramp circuit 32 generates a predetermined initial voltage V INT The ramp voltage V monotonically increases at a predetermined rate of change from RAMP In the ramp circuit 32, an initial voltage V INTis, for example, 0 V, but may be different from 0 V. During the off period of the transistor M2, the ramp voltage V RAMP is the initial voltage V INT It is fixed in place.

[0043] The current information acquisition circuit 33 acquires current information of the inductor L1 and outputs a sense voltage V IL The current information of the inductor L1 is the inductor current I L This is information indicating the value of the sense voltage V IL is a positive proportional coefficient and the inductor current I L Therefore, the inductor current I L As the sense voltage V IL rises, and the inductor current I L With the decrease in the sense voltage V IL For example, "V IL = k IV ×I L " may be. IV is a predetermined positive coefficient.

[0044] Sense voltage V IL indicates the current information of the inductor L1, the sense voltage V IL The method for generating the inductor current I L By directly detecting the current with a current sensor, the sense voltage V IL The current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L1 and the node ND1. Alternatively, for example, the current flowing through the transistor M2 during the ON period of the transistor M2 (therefore, the inductor current I L ) or by detecting the current flowing through the transistor M1 during the ON period of the transistor M1 (thus the inductor current I L ) is detected, the sense voltage V IL Alternatively, the inductor current I L By detecting the voltage at any point where a voltage corresponding to IL may be generated.

[0045] The adder 34 calculates the lamp voltage VRAMP With respect to the sense voltage V IL By adding these, the slope voltage V SLP That is, "V SLP =V RAMP +V IL "

[0046] The PWM comparator 35 outputs the error voltage V ERR and the slope voltage V SLP The PWM comparator 35 compares the error voltage V ERR is input, and the slope voltage V SLP is input to the PWM comparator 35. SLP <V ERR " is established, a low level signal CMPOUT is output, and "V SLP >V ERR " is established, a high level signal CMPOUT is output. SLP =V ERR When "is established," the signal CMPOUT has a low level or a high level.

[0047] The oscillator circuit 36 ​​generates and outputs a clock signal CLK by oscillating. The clock signal CLK has a predetermined frequency f PWM The clock signal CLK is a rectangular wave signal having a frequency f and alternates between high and low levels. The duty of the clock signal CLK is arbitrary. In this example, the clock signal CLK has a low level in principle and a frequency f PWM The signal is set to have a high level for a short time at intervals equal to the reciprocal of the value of the reference signal (see FIG. 5).

[0048] A signal CMPOUT and a clock signal CLK are input to the controller 37. In response to a predetermined level change in the clock signal CLK, the controller 37 generates a rising edge in the control signals CNT2 and CNT4 (i.e., switches the levels of the control signals CNT2 and CNT4 from low to high) and generates a falling edge in the control signals CNT1 and CNT3 (i.e., switches the levels of the control signals CNT1 and CNT3 from high to low). Here, the predetermined level change in the clock signal CLK is a change from low to high, but it may also be a change from high to low. The control signals CNT1 to CNT4 from the controller 37 are supplied to the drive circuit 40A. The drive circuit 40A turns on transistors M2 and M4 by generating a rising edge in gate signals G2 and G4 in response to the rising edge of control signals CNT2 and CNT4, and turns off transistors M1 and M3 by generating a falling edge in gate signals G1 and G3 in response to the falling edge of control signals CNT1 and CNT3.

[0049] After transistors M2 and M4 are turned on and transistors M1 and M3 are turned off, the slope voltage V SLP After a monotonous rise in SLP <V ERR "From the established state of "V SLP >V ERR " transitions to an established state, causing a rising edge to occur in the signal CMPOUT. In switching control, when a rising edge occurs in the signal CMPOUT, the controller 37 causes a falling edge to occur in the control signals CNT2 and CNT4 and also causes a rising edge to occur in the control signals CNT1 and CNT3. The drive circuit 40A turns off the transistors M2 and M4 by causing a falling edge to occur in the gate signals G2 and G4 in response to the falling edge of the control signals CNT2 and CNT4, and turns on the transistors M1 and M3 by causing a rising edge to occur in the gate signals G1 and G3 in response to the rising edge of the control signals CNT1 and CNT3.

[0050] As the transistor M2 turns off, the lamp voltage V RAMP is a sufficiently low initial voltage V INT Since it decreases to "V SLP <V ERR ” is established, and a falling edge is quickly generated in the signal CMPOUT. In the switching control, the time from when the transistors M2 and M4 are turned on and the transistors M1 and M3 are turned off to when the transistors M2 and M4 are turned off and the transistors M1 and M3 are turned on is defined as time t ON It is called.

[0051] "V OUT =V TG "When "V FB =V REF "V OUT =V TG Starting from the state where " LD Through the increase of "V OUT <V TG "So, "V FB <V REF " so the error voltage V ERR The error voltage V ERR The increase in the ON period of the transistor M2 causes the inductor current I L increases, resulting in an output voltage V OUT is the target voltage V TG On the other hand, "V OUT =V TG Starting from the state where " LD Through the decrease of "V OUT >V TG "So, "V FB >V REF " so the error voltage V ERR The error voltage V ERR The decrease in the ON period of the transistor M2 reduces the inductor current I L decreases, resulting in the output voltage V OUT is the target voltage V TGIn this way, in switching control, the output voltage V OUT and target voltage V TG Control is performed to reduce the difference between the

[0052] The above-mentioned time t ON is the error voltage V ERR (and hence the output voltage V OUT ) and the sense voltage V IL (and therefore depends on the current information of the inductor L1). In other words, the controller 37 controls the output voltage V OUT Based on the information on the current of the inductor L1 and the information on the current of the inductor L1, the controller 37 controls the switching of the transistors M1 to M4 in synchronization with the clock signal CLK. In the switching control, the controller 37 uses the drive circuit 40A to turn on the transistors M2 and M4 and turn off the transistors M1 and M3 in response to a predetermined level change in the clock signal CLK, and then controls the output voltage V OUT and the time t ON After this time has elapsed, transistors M2 and M4 are turned off and transistors M1 and M3 are turned on.

[0053] The controller 37 controls the capacitor C MID An intermediate voltage V MID and generates an intermediate voltage V in a buck converter including transistors M1 and M2 and inductor L1. MID By lowering the voltage at the output node ND OUT Output voltage V OUT Generates.

[0054] 6 shows the internal configuration of the drive circuit 40A. The drive circuit 40A includes level shifters 41_1 to 41_4 and gate drivers 42_1 to 42_4. FIG. 7 shows the internal configuration of the boost circuit 50A. The boost circuit 50A includes boot switches Ma, Mb, and Mc, and a boot capacitor C BOOT1 , C BOOT2 and C BOOT3However, the level shifters 41_2 to 41_4 and the gate drivers 42_2 to 42_4 may function as the level shifters 51_2 to 51_4 and the gate drivers 52_2 to 52_4.

[0055] Each component in the control circuit 30A (and therefore the controller 37) operates using a voltage VDD as a positive power supply voltage and a voltage VSS as a negative power supply voltage. The voltage VSS corresponds to the ground voltage here. The voltage VDD and a voltage V (described later) DRV is the input voltage V IN is a positive DC voltage lower than the input voltage V IN The voltages VDD and V DRV may have different voltage values. DRV The driving voltage V DRV is the drive wiring W DRV is the voltage at

[0056] Boot wiring W BOOT1 , W BOOT2 and W BOOT3 and drive wiring W DRV It can be understood that the boot wiring W is also included in the components of the boost circuit 50A. BOOT1 The voltage at BOOT1 This is called the boot wiring W. BOOT2 The voltage at BOOT2 This is called the boot wiring W. BOOT3 The voltage at BOOT3 The boot voltage V BOOT1 , V BOOT2 , V BOOT3 are the voltages supplied to the gates of transistors M2, M3, and M4 to turn them on, respectively.

[0057] 6, the controller 37 outputs control signals CNT1 to CNT4 to the level shifters 41_1 to 41_4, respectively. For each of the control signals CNT1 to CNT4, a high-level control signal output from the controller 37 has the level of voltage VDD, and a low-level control signal output from the controller 37 has the level of voltage VSS.

[0058] The level shifter 41_1 supplies voltages VDD, VSS, and V DRV The level shifter 41_1 is connected to wiring to which the voltages VDD, VSS, and V DRV The level shifter 41_1 shifts the level of the control signal CNT1 from the controller 37 using the driving voltage V, and outputs the level-shifted control signal CNT1. The output signal of the level shifter 41_1 is supplied to the gate driver 42_1. The output signal of the level shifter 41_1 has a high level when the controller 37 outputs a high-level control signal CNT1, and has a low level when the controller 37 outputs a low-level control signal CNT1. The high level of the output signal of the level shifter 41_1 is DRV The low level of the output signal of the level shifter 41_1 has the level of the voltage VSS.

[0059] The gate driver 42_1 is connected to the gate of the transistor M1. The gate driver 42_1 supplies a voltage V DRV and VSS, the gate of the transistor M1 is driven in response to a control signal CNT1 (specifically, in response to the control signal CNT1 after level shifting from the level shifter 41_1), thereby turning the transistor M1 on or off. When the output signal of the level shifter 41_1 has a high level, the gate driver 42_1 supplies a high-level gate signal G1 to the gate of the transistor M1, thereby setting the state of the transistor M1 on. When the output signal of the level shifter 41_1 has a low level, the gate driver 42_1 supplies a low-level gate signal G1 to the gate of the transistor M1, thereby setting the state of the transistor M1 off. The high-level gate signal G1 is supplied to the gate of the transistor M1 by the driving voltage V DRVThe gate signal G1 at a low level has a level of the voltage VSS. DRV is higher than the gate threshold voltage of transistor M1.

[0060] The level shifter 41_2 outputs voltages VDD, VSS, and V BOOT1 and V LX The level shifter 41_2 is connected to wiring to which the voltages VDD, VSS, and V BOOT1 and V LX The level shifter 41_2 uses the voltage V to shift the level of the control signal CNT2 from the controller 37, and outputs the level-shifted control signal CNT2. The output signal of the level shifter 41_2 is supplied to the gate driver 42_2. The output signal of the level shifter 41_2 has a high level when the controller 37 outputs a high-level control signal CNT2, and has a low level when the controller 37 outputs a low-level control signal CNT2. The high level of the output signal of the level shifter 41_2 is equal to the boot voltage V BOOT1 The low level of the output signal of the level shifter 41_2 is a voltage V LX It has a level of.

[0061] The gate driver 42_2 is connected to the gate of the transistor M2. The gate driver 42_2 supplies a voltage V BOOT1 and V LX , and drives the gate of the transistor M2 in response to the control signal CNT2 (specifically, in response to the level-shifted control signal CNT2 from the level shifter 41_2), thereby turning the transistor M2 on or off. When the output signal of the level shifter 41_2 has a high level, the gate driver 42_2 supplies a high-level gate signal G2 to the gate of the transistor M2, thereby setting the state of the transistor M2 to on. When the output signal of the level shifter 41_2 has a low level, the gate driver 42_2 supplies a low-level gate signal G2 to the gate of the transistor M2, thereby setting the state of the transistor M2 to off. The high-level gate signal G2 is BOOT1 and the low-level gate signal G2 has a voltage V LXThe differential voltage (V BOOT1 -V LX ) is higher than the gate threshold voltage of transistor M2.

[0062] The level shifter 41_3 outputs voltages VDD, VSS, and V BOOT2 and V MID The level shifter 41_3 is connected to wiring to which the voltages VDD, VSS, and V BOOT2 and V MID The level shifter 41_3 uses the voltage V to shift the level of the control signal CNT3 from the controller 37, and outputs the level-shifted control signal CNT3. The output signal of the level shifter 41_3 is supplied to the gate driver 42_3. The output signal of the level shifter 41_3 has a high level when the controller 37 outputs a high-level control signal CNT3, and has a low level when the controller 37 outputs a low-level control signal CNT3. The high level of the output signal of the level shifter 41_3 is equal to the boot voltage V BOOT2 The low level of the output signal of the level shifter 41_3 is the intermediate voltage V MID It has a level of.

[0063] The gate driver 42_3 is connected to the gate of the transistor M3. The gate driver 42_3 supplies a voltage V BOOT2 and V MID , and drives the gate of the transistor M3 in response to the control signal CNT3 (specifically, in response to the level-shifted control signal CNT3 from the level shifter 41_3), thereby turning the transistor M3 on or off. When the output signal of the level shifter 41_3 has a high level, the gate driver 42_3 supplies a high-level gate signal G3 to the gate of the transistor M3, thereby setting the state of the transistor M3 on. When the output signal of the level shifter 41_3 has a low level, the gate driver 42_3 supplies a low-level gate signal G3 to the gate of the transistor M3, thereby setting the state of the transistor M3 off. The high-level gate signal G3 is supplied to the gate of the transistor M3 in response to the boot voltage V BOOT2 The low-level gate signal G3 has an intermediate voltage V MID The differential voltage (VBOOT2 -V MID ) is higher than the gate threshold voltage of transistor M3.

[0064] The level shifter 41_4 outputs voltages VDD, VSS, and V BOOT3 and V FLY The level shifter 41_4 is connected to wiring to which the voltages VDD, VSS, and V BOOT3 and V FLY The level shifter 41_4 uses the voltage V to shift the level of the control signal CNT4 from the controller 37, and outputs the level-shifted control signal CNT4. The output signal of the level shifter 41_4 is supplied to the gate driver 42_4. The output signal of the level shifter 41_4 has a high level when the controller 37 outputs a high-level control signal CNT4, and has a low level when the controller 37 outputs a low-level control signal CNT4. The high level of the output signal of the level shifter 41_4 is equal to the boot voltage V BOOT3 The low level of the output signal of the level shifter 41_4 is a voltage V FLY It has a level of.

[0065] The gate driver 42_4 is connected to the gate of the transistor M4. The gate driver 42_4 supplies a voltage V BOOT3 and V FLY , and drives the gate of the transistor M4 in response to the control signal CNT4 (specifically, in response to the level-shifted control signal CNT4 from the level shifter 41_4), thereby turning the transistor M4 on or off. When the output signal of the level shifter 41_4 has a high level, the gate driver 42_4 supplies a high-level gate signal G4 to the gate of the transistor M4, thereby setting the state of the transistor M4 on. When the output signal of the level shifter 41_4 has a low level, the gate driver 42_4 supplies a low-level gate signal G4 to the gate of the transistor M4, thereby setting the state of the transistor M4 off. The high-level gate signal G4 is supplied to the gate of the transistor M4 in response to the boot voltage V BOOT3 The low level gate signal G4 has a voltage V FLY The differential voltage (V BOOT3 -VFLY ) is higher than the gate threshold voltage of transistor M4.

[0066] Referring to Figure 7, the boot switches Ma to Mc are each composed of a P-channel MOSFET. For this reason, hereinafter, the boot switches Ma to Mc may be referred to as transistors Ma to Mc. Figure 7 also shows parasitic diodes added to the transistors Ma to Mc (the same applies to several drawings described below that show the transistors Ma to Mc). In each of the transistors Ma to Mc, the parasitic diode has a forward direction that points from the drain to the source.

[0067] Boot capacitor C BOOT1 is the node ND1 and the boot wiring W BOOT1 That is, the boot capacitor C BOOT1 The first end and the second end of the BOOT1 The boot wiring W BOOT1 From the boot capacitor C BOOT1 The current flowing to node ND1 through boot capacitor C BOOT1 is charged, and the reverse current charges the boot capacitor C BOOT1 is discharged. The boot capacitor C BOOT1 Charging the boot voltage V BOOT1 rises.

[0068] Boot capacitor C BOOT2 is the node ND2 and the boot wiring W BOOT2 That is, the boot capacitor C BOOT2 The first end and the second end of the BOOT2 The boot wiring W BOOT2 From the boot capacitor C BOOT2 The current flowing to node ND2 via boot capacitor C BOOT2 is charged, and the reverse current charges the boot capacitor C BOOT2 is discharged. The boot capacitor C BOOT2 Charging the boot voltage V BOOT2 rises.

[0069] Boot capacitor CBOOT3 is the node ND3 and the boot wiring W BOOT3 That is, the boot capacitor C BOOT3 The first end and the second end of the BOOT3 The boot wiring W BOOT3 From the boot capacitor C BOOT3 The current flowing to node ND3 via boot capacitor C BOOT3 is charged, and the reverse current charges the boot capacitor C BOOT3 is discharged. The boot capacitor C BOOT3 Charging the boot voltage V BOOT3 rises.

[0070] The transistor Ma is driven by a voltage V DRV The drive wiring W DRV and boot wiring W BOOT1 Specifically, the drain of the transistor Ma is connected to the drive wiring W DRV The source of the transistor Ma is connected to the boot wiring W BOOT1 The transistor Mb is connected to the boot wiring W BOOT1 and boot wiring W BOOT2 Specifically, the drain of the transistor Mb is connected to the boot wiring W BOOT1 The source of the transistor Mb is connected to the boot wiring W BOOT2 The transistor Mc is connected to the boot wiring W BOOT2 and boot wiring W BOOT3 Specifically, the drain of the transistor Mc is connected to the boot wiring W BOOT2 The source of the transistor Mc is connected to the boot wiring W BOOT3 is connected to.

[0071] The controller 37 outputs control signals CNT1 to CNT4 to the level shifters 51_2 to 51_4, respectively.

[0072] The level shifter 51_2 outputs voltages VDD, VSS, and V BOOT1 and V LX The level shifter 51_2 is connected to the wiring to which the voltages VDD, VSS, and V BOOT1 and VLX The level shifter 51_2 uses the voltage V to shift the level of the control signal CNT2 from the controller 37, and outputs the level-shifted control signal CNT2. The output signal of the level shifter 51_2 is supplied to the switch driver 52_2. The output signal of the level shifter 51_2 has a high level when the controller 37 outputs a high-level control signal CNT2, and has a low level when the controller 37 outputs a low-level control signal CNT2. The high level of the output signal of the level shifter 51_2 is equal to the boot voltage V BOOT1 The low level of the output signal of the level shifter 51_2 is a voltage V LX It has a level of.

[0073] The switch driver 52_2 is connected to the gate of the transistor Ma. The switch driver 52_2 supplies a voltage V BOOT1 and V LX The switch driver 52_2 turns on or off the transistor Ma by driving the gate of the transistor Ma in accordance with the control signal CNT2 (specifically, in accordance with the control signal CNT2 after level shifting from the level shifter 51_2) based on the boot voltage V. When the output signal of the level shifter 51_2 has a high level, the switch driver 52_2 supplies a high-level gate signal to the gate of the transistor Ma to set the state of the transistor Ma to off. When the output signal of the level shifter 51_2 has a low level, the switch driver 52_2 supplies a low-level gate signal to the gate of the transistor Ma to set the state of the transistor Ma to on. The high-level gate signal for the transistor Ma is a boot voltage V BOOT1 and the low level gate signal for transistor Ma has a voltage V LX The differential voltage (V BOOT1 -V LX ) is greater than the absolute value of the gate threshold voltage of transistor Ma.

[0074] The level shifter 51_3 outputs voltages VDD, VSS, and V BOOT2 and V MID The level shifter 51_3 is connected to the wiring to which the voltages VDD, VSS, and V BOOT2and V MID is used to shift the level of the control signal CNT3 from the controller 37, and output the level-shifted control signal CNT3. The output signal of the level shifter 51_3 is supplied to the switch driver 52_3. The output signal of the level shifter 51_3 has a high level when the controller 37 outputs a high-level control signal CNT3, and has a low level when the controller 37 outputs a low-level control signal CNT3. The high level of the output signal of the level shifter 51_3 is equal to the boot voltage V BOOT2 The low level of the output signal of the level shifter 51_3 is a voltage V MID It has a level of.

[0075] The switch driver 52_3 is connected to the gate of the transistor Mb. The switch driver 52_3 supplies a voltage V BOOT2 and V MID The switch driver 52_3 turns on or off the transistor Mb by driving the gate of the transistor Mb in response to the control signal CNT3 (specifically, in response to the level-shifted control signal CNT3 from the level shifter 51_3) based on the boot voltage V. When the output signal of the level shifter 51_3 has a high level, the switch driver 52_3 sets the state of the transistor Mb to off by supplying a high-level gate signal to the gate of the transistor Mb. When the output signal of the level shifter 51_3 has a low level, the switch driver 52_3 sets the state of the transistor Mb to on by supplying a low-level gate signal to the gate of the transistor Mb. The high-level gate signal for the transistor Mb is BOOT2 and the low level gate signal for transistor Mb has a voltage V MID The differential voltage (V BOOT2 -V MID ) is greater than the absolute value of the gate threshold voltage of transistor Mb.

[0076] The level shifter 51_4 outputs voltages VDD, VSS, and V BOOT3 and V FLY The level shifter 51_4 is connected to the wiring to which the voltages VDD, VSS, and VBOOT3 and V FLY The level shifter 51_4 uses the voltage V to shift the level of the control signal CNT4 from the controller 37, and outputs the level-shifted control signal CNT4. The output signal of the level shifter 51_4 is supplied to the switch driver 52_4. The output signal of the level shifter 51_4 has a high level when the controller 37 outputs a high-level control signal CNT4, and has a low level when the controller 37 outputs a low-level control signal CNT4. The high level of the output signal of the level shifter 51_4 is equal to the boot voltage V BOOT3 The low level of the output signal of the level shifter 51_4 is a voltage V FLY It has a level of.

[0077] The switch driver 52_4 is connected to the gate of the transistor Mc. The switch driver 52_4 supplies a voltage V BOOT3 and V FLY , and drives the gate of the transistor Mc in response to the control signal CNT4 (specifically, in response to the level-shifted control signal CNT4 from the level shifter 51_4), thereby turning the transistor Mc on or off. When the output signal of the level shifter 51_4 has a high level, the switch driver 52_4 sets the state of the transistor Mc to off by supplying a high-level gate signal to the gate of the transistor Mc. When the output signal of the level shifter 51_4 has a low level, the switch driver 52_4 sets the state of the transistor Mc to on by supplying a low-level gate signal to the gate of the transistor Mc. The high-level gate signal for the transistor Mc is BOOT3 and a low level gate signal for transistor Mc has a voltage V FLY The differential voltage (V BOOT3 -V FLY ) is greater than the absolute value of the gate threshold voltage of transistor Mc.

[0078] As described above, the level shifters 41_2 to 41_4 and the gate drivers 42_2 to 42_4 may function as the level shifters 51_2 to 51_4 and the gate drivers 52_2 to 52_4. In this case, the boost circuit 50A does not include dedicated level shifters and switch drivers for driving the transistors Ma to Mc (i.e., the level shifters 51_2 to 51_4 and the gate drivers 52_2 to 52_4 are omitted from the boost circuit 50A). The gate signal G2 output from the driver 42_2 may be supplied to the gate of the transistor Ma, the gate signal G3 output from the driver 42_3 may be supplied to the gate of the transistor Mb, and the gate signal G4 output from the driver 42_4 may be supplied to the gate of the transistor Mc.

[0079] 8 shows the internal configuration of the drive circuit 40A and the internal configuration of the boost circuit 50A. However, the reference numerals "40A" and "50A" are omitted from the illustration in FIG. 8 and in FIGS. 9 and 10 described later.

[0080] The operation of charging or discharging each boot capacitor will be described with reference to FIGS.

[0081] 9, in state ST_A1, the controller 37 outputs low-level control signals CNT1 and CNT3 and high-level control signals CNT2 and CNT4. Therefore, in state ST_A1, the drive circuit 40A turns off the transistors G1 and G3 and turns on the transistors G2 and G4 based on the control signals CNT1 to CNT4. Also, in state ST_A1, the boost circuit 50A turns off the transistors Ma and Mc and turns on the transistor Mb based on the control signals CNT2 to CNT4.

[0082] As a result, in state ST_A1, a current 821 is generated. The current 821 flows through the boot capacitor C BOOT2 The current that charges the boot capacitor C BOOT1 The current 821 flows through the boot wiring W BOOT1 From transistor Mb, boot wiring W BOOT2 , boot capacitor C BOOT2, node ND2, transistor M2, node ND1 and boot capacitor C BOOT1 Through the boot wiring W BOOT1 Also, in state ST_A1, the current flows through the boot capacitor C BOOT1 The gate signal G2 is pulled up to a high level using a discharge current of BOOT3 The gate signal G4 is raised to a high level using a discharge current of .

[0083] 10, in state ST_A2, the controller 37 outputs high-level control signals CNT1 and CNT3 and low-level control signals CNT2 and CNT4. Therefore, in state ST_A2, the drive circuit 40A turns on the transistors G1 and G3 and turns off the transistors G2 and G4 based on the control signals CNT1 to CNT4. Also, in state ST_A2, the boost circuit 50A turns on the transistors Ma and Mc and turns off the transistor Mb based on the control signals CNT2 to CNT4.

[0084] As a result, in state ST_A2, currents 822 and 823 are generated. The current 822 flows through the boot capacitor C BOOT1 is a current that charges the drive voltage V DRV The voltage source is provided in the power supply device 1A (power supply control device 10A, described later; see FIG. 11 ) and generates an input voltage V IN Based on this, the driving voltage V DRV The current 822 flows from the voltage source to the drive wiring W DRV , transistor Ma, boot wiring W BOOT1 , boot capacitor C BOOT1 , through node ND1, transistor M1, and ground, and back to the voltage source. BOOT3 The current that charges the boot capacitor C BOOT2 The current 823 flows through the boot wiring W BOOT2 From the transistor Mc, the boot wiring W BOOT3 , boot capacitor C BOOT3, node ND3, transistor M3, node ND2 and boot capacitor C BOOT2 Through the boot wiring W BOOT2 In state ST_A2, the current flows through the boot capacitor C BOOT2 The gate signal G3 is raised to a high level using a discharge current of .

[0085] When the switching control (see FIG. 3) is performed to alternately switch the states of the transistors M1 to M4 between the states ST_A1 and ST_A2, the states of the transistors Ma to Mc are also switched as shown in FIGS. 9 and 10. As a result, at least in the steady state, the differential voltage (V BOOT1 -V LX ) is higher than the gate threshold voltage of transistor M2, and the difference voltage (V BOOT2 -V MID ) is higher than the gate threshold voltage of transistor M3, and the difference voltage (V BOOT3 -V FLY ) remains higher than the gate threshold voltage of transistor M4.

[0086] Figure 11 is an external perspective view of the power supply control device 10A included in the power supply device 1A. The power supply control device 10A is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed to the outside of the power supply control device 10A from the housing. The power supply control device 10A is formed by sealing the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply control device 10A and the type of housing for the power supply control device 10A shown in Figure 2 are merely examples, and they can be designed as desired.

[0087] The power supply 1A comprises a power supply control device 10A and a group of discrete components externally connected to the power supply control device 10A. Some of the components of the power supply 1A are provided in the power supply control device 10A, and the remaining parts are composed of the group of discrete components.

[0088] Referring to FIG. 12, the inductor L1 and the capacitor C OUT , C MID , C FLY , C BOOT1, C BOOT2 and C BOOT3 , and resistors R1 and R2 are provided in the group of discrete components. However, the resistors R1 and R2 may be built into the power supply control device 10A. The transistors M1 to M4 are also provided in the group of discrete components. However, the transistors M1 to M4 may be built into the power supply control device 10A. The control circuit 30A and the drive circuit 40A are provided in the power supply control device 10A. Of the components of the boost circuit 50A, the boot capacitor C BOOT1 ~C BOOT3 The rest are provided in the power supply control device 10A.

[0089] A reference power supply (not shown) that does not include the boost circuit 50A of this embodiment is also being considered. In the reference power supply, three bootstrap diodes are externally connected to the power supply control device. The number of components in the reference power supply is greater than that of the power supply control device 1A due to the presence of these diodes. The power supply control device 1A uses P-channel MOSFETs (Ma to Mb) instead of diodes as the bootstrap rectifier elements, allowing the bootstrap rectifier elements to be built into the power supply control device 10. This reduces the number of components and allows for a more compact power supply. Furthermore, in the reference power supply, the level of the gate signal for turning on transistors M2 to M4 is lowered by the forward voltage of the diodes. In contrast, the power supply control device 1A is not affected by the forward voltage of the diodes, which reduces the switching loss of transistors M2 to M4 and makes it easier to ensure a driving margin when the voltages of each component are relatively low.

[0090] <<Second Embodiment>> A second embodiment of the present disclosure will be described. The second embodiment and the third and fourth embodiments described below are embodiments based on the first embodiment, and for matters not specifically mentioned in the second to fourth embodiments, the description of the first embodiment also applies to the second to fourth embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third and fourth embodiments described below). As long as there is no contradiction, any two or more of the first to fourth embodiments may be combined.

[0091] FIG. 13 is an overall configuration diagram of a power supply device 1B according to a second embodiment of the present disclosure. The power supply device 1B is a type of multi-phase converter. The power supply device 1B is configured by adding a switching element M5 and an inductor L2 to the power supply device 1A according to the first embodiment. When applying the description of the first embodiment to the second embodiment, the description of "power supply device 1A" in the first embodiment can be read as "power supply device 1B" in this embodiment. With the above addition, in the power supply device 1B, a capacitor C FLY The first end of the capacitor C is connected to the node ND3. FLY The second end of the inductor L2 is connected to the node ND5. The switching element M5 is configured by an N-channel MOSFET, similar to the switching elements M1 to M4. For this reason, the switching element M5 may be referred to as the transistor M5 hereinafter. In the power supply device 1B, the drain of the transistor M5 and the first end of the inductor L2 are connected to the node ND5, and the second end of the inductor L2 is connected to the output node ND OUT and the source of transistor M5 is connected to ground.

[0092] The power supply device 1B includes a buck converter CNVa and a stacked converter CNVb. The buck converter CNVa includes transistors M1 and M2, an inductor L1, and a capacitor C OUT and an intermediate voltage V MID By stepping down the voltage, the desired output voltage V OUT The transistors M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter CNVa.

[0093] The stacked converter CNVb includes transistors M3 to M5 and a capacitor C FLY and inductor L2, and the input voltage V IN to intermediate voltage V MID The capacitor C MIDIt can be understood that the stacked converter CNVb also includes the capacitor C. The stacked converter CNVb also functions as a converter for one phase in a multi-phase converter. MID The transistor M4 functions as a control switching element for charging the intermediate voltage V MID The transistor M5 functions as a switching element for generating a voltage Vout and also functions as a high-side switching element for multiphase. The transistor M6 functions as a low-side switching element for multiphase.

[0094] In the power supply device 1B, a control circuit 30B, a drive circuit 40B and a boost circuit 50B are provided instead of the control circuit 30A, the drive circuit 40A and the boost circuit 50A of FIG.

[0095] The control circuit 30B controls the output voltage V OUT and the current information of the inductor L1, the output voltage V OUT is the target voltage V TG The driving circuit 40B controls the switching of the transistors M1 to M5 so that the output voltage V OUT The information is output voltage V OUT For example, the feedback voltage V FB The current information of the inductor L1 may be the inductor current I L For example, the inductor current I L A voltage signal proportional to the value of the sense voltage V in FIG. IL The control circuit 30B controls the transistors M1 to M5 to be turned on or off individually in the switching control. The control circuit 30B controls the output voltage V OUTThe drive circuit 40B generates the above-mentioned control signals CNT1 to CNT4 based on the information on the inductor L1 and the current information of the inductor L1, and also generates a control signal CNT5 that specifies the state (on or off) of the transistor M5. The drive circuit 40B has the same configuration as the drive circuit 40A of the first embodiment, and generates a gate signal G5 in response to the control signal CNT5. The boost circuit 50B has the same configuration as the boost circuit 50A of the first embodiment. The drive circuit 40B supplies gate signals G1 to G5 to the gates of the transistors M1 to M5, respectively, thereby individually setting the states of the transistors M1 to M5 to on or off.

[0096] The states of the transistors M1 to M5 are switched between states ST_B1 to ST_B4 shown in Figures 14 to 17 by the switching control of the control circuit 30B. In Figures 14 to 17, the current flow occurring in each state is indicated by multiple broken lines with arrows. Here, it is assumed that the power supply device 1B is operating in the continuous current mode. Note that the capacitor C FLY (i.e., the potential at the node ND5) as a reference. FLY The current that increases the potential at the first end of the capacitor C FLY The reverse current is the charging current of the capacitor C FLY is the discharge current of the capacitor C MID Regarding the intermediate voltage V MID The current that increases the intermediate voltage V MID The current that decreases the capacitance is the discharge current.

[0097] 14, in state ST_B1, transistors M1 and M4 are on, and transistors M2, M3, and M5 are off. In state ST_B1, currents 841 and 842 are generated. The current 841 flows through the input voltage V IN From the application terminal of the transistor M4, the capacitor C FLY and the output node ND through the inductor L2 OUT The current 841 flows into the capacitor C FLY This corresponds to the charging current to the capacitor C FLYA current 842 flows from ground through transistor M1 and inductor L1 to output node ND OUT In state ST_B1, the capacitor C MID No charging or discharging occurs for the capacitor C MID The stored charge remains unchanged.

[0098] 15, in the state ST_B2, the transistors M2 and M4 are in an on state, and the transistors M1, M3, and M5 are in an off state. In the state ST_B2, a current 843 is generated together with the current 841. The current 843 flows through the capacitor C MID from the output node ND through the transistor M2 and the inductor L1. OUT is the current going to the capacitor C MID It is generated by the discharge of

[0099] 16, in state ST_B3, transistors M2, M3, and M5 are in an on state, and transistors M1 and M4 are in an off state. In state ST_B3, currents 844 and 845 are generated along with the current 843. The current 844 flows from the ground through transistor M5 and capacitor C FLY and through transistor M3, capacitor C MID and the positive electrode of the capacitor C MID Current 844 flows through capacitor C FLY is discharged while the capacitor C MID A current 845 flows from ground through transistor M5 and inductor L2 to output node ND OUT Heading towards.

[0100] 17, in state ST_B4, the transistors M1, M3 and M5 are in the on state, and the transistors M2 and M4 are in the off state. In state ST_B4, the above-mentioned currents 842, 844 and 845 are generated.

[0101] In state ST_B1, the magnitudes of the currents 841 and 842 are approximately the same. In state ST_B2, the magnitudes of the currents 841 and 843 are approximately the same. In state ST_B2, the transistors M2 and M4 are on, so the capacitor CFLY and C MID For state ST_B2, the capacitor C FLY and C MID In states ST_B3 and ST_B4, the capacitor C FLY and C MID As a result, similar to the power supply device 1A, the power supply device 1B has transistors M1 to M5 and capacitors C FLY and C MID The control circuit 40B operates the circuit as a switched capacitor circuit, thereby controlling the capacitor C MID The positive terminal of the input voltage V IN The intermediate voltage V corresponds to the divided voltage of MID Generates an intermediate voltage V MID is essentially the voltage (V IN / 2). Strictly speaking, the intermediate voltage V MID is the voltage (V IN / 2) and fluctuates slightly.

[0102] Output node ND by buck converter CNVa OUT The output current (842, 843) to the output node ND OUT The output currents (841, 845) to the power supply 1B are pulsating currents, and the former output current and the latter output current have different phases. That is, the power supply 1B is a multi-phase converter (a multi-phase DC / DC converter) with two phases.

[0103] The configuration and operation of the boost circuit 50B are the same as those of the boost circuit 50A of the first embodiment (see FIG. 7). Therefore, transistor Ma is off during the on period of transistor M2 and on during the off period of transistor M2. Transistor Mb is off during the on period of transistor M3 and on during the off period of transistor M3. Transistor Mc is off during the on period of transistor M4 and on during the off period of transistor M4. When only the states of transistors M1 to M4 and Ma to Mc are considered, state ST_B2 in FIG. 15 is equivalent to state ST_A1 in FIG. 9, and state ST_B4 in FIG. 17 is equivalent to state ST_A2 in FIG. 10.

[0104] <<Third Embodiment>> A third embodiment of the present disclosure will be described. Fig. 18 is an overall configuration diagram of a power supply device 1C according to the third embodiment of the present disclosure. Note that the description of the first embodiment can be applied to the third embodiment, and in this application, the description "power supply device 1A" in the first embodiment can be read as "power supply device 1C" in this embodiment.

[0105] Like the power supply devices 1A and 1B, the power supply device 1C receives a positive input voltage V IN is supplied, and the input voltage V IN By stepping down the voltage, a positive output voltage V OUT The power supply device 1C includes converters CNV1 and CNV2, a control circuit 30C, a drive circuit 40C, and a boost circuit 50C. The components of the converters CNV1 and CNV2 include switching elements M1 to M8 and a capacitor C FLY1 , C FLY2 , C MID1 , C MID2 and C OUT and inductors L1 to L4. FLY1 and C FLY2 can be called a flying capacitor. MID1 and C MID2 can be referred to as the intermediate capacitor. OUT can be referred to as the output capacitor.

[0106] The converter CNV1 is a converter of the first channel. The components of the converter CNV1 include switching elements M1 to M4 and a capacitor C FLY1 and C MID1 The converter CNV2 is a second-channel converter. The components of the converter CNV2 include switching elements M5 to M8 and a capacitor C FLY2 and C MID2 and inductors L2 and L4. Capacitor C OUT is used for both the converters CNV1 and CNV2. OUT are components of the converters CNV1 and CNV2, and are shared by the converters CNV1 and CNV2.

[0107] Capacitor C OUT In addition, some components in the power supply device 1C are shared by the converters CNV1 and CNV2, as will be described in detail below.

[0108] The converter CNV1 includes a first channel buck converter and a first channel stacked converter. The first channel buck converter includes switching elements M1 and M2, an inductor L1, and a capacitor C OUT In cooperation with the intermediate voltage V MID1 By lowering the voltage at the output node ND OUT Output voltage V OUT When attention is paid to the operation of the converter CNV1, the switching elements M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter of the first channel.

[0109] The stacked converter of the first channel includes switching elements M3 to M5 and a capacitor C FLY1 and inductor L3, and the input voltage V IN to intermediate voltage V MID1 The capacitor C MID1It can be understood that the switching element M3 is also included in the components of the stacked converter of the first channel. The converter CNV1 itself is a two-phase multiphase converter. The stacked converter of the first channel also functions as a converter for one phase in the converter CNV1. MID1 The switching element M4 functions as a control switching element for charging the intermediate voltage V MID1 When attention is paid to the operation of the converter CNV1, the switching element M5 functions as a multiphase low-side switching element.

[0110] The converter CNV2 includes a second channel buck converter and a second channel stacked converter. The second channel buck converter includes switching elements M5 and M6, an inductor L2, and a capacitor C OUT In cooperation with the intermediate voltage V MID2 By lowering the voltage at the output node ND OUT Output voltage V OUT When attention is paid to the operation of the converter CNV2, the switching elements M5 and M6 function as a low-side switching element and a high-side switching element in the buck converter of the second channel.

[0111] The second channel of the stacked converter includes switching elements M7, M8, and M1, and a capacitor C FLY2 and an inductor L4, and an input voltage V IN to intermediate voltage V MID2 The capacitor C MID2 It can be understood that the switching element M7 is also included in the components of the stacked converter of the second channel. The converter CNV2 itself is a two-phase multiphase converter. The stacked converter of the second channel also functions as a converter for one phase in the converter CNV2. MID2 The switching element M8 functions as a control switching element for charging the intermediate voltage VMID2 When attention is paid to the operation of the converter CNV2, the switching element M1 functions as a multiphase low-side switching element.

[0112] In the power supply device 1C, the first channel buck converter, the first channel stacked converter, the second channel buck converter, and the second channel stacked converter each output a current to an output node ND. OUT , which supplies the output node ND OUT output voltage V having a desired voltage value OUT Generates.

[0113] As can be understood from the above description, the switching device M1 serves as both a low-side switching device in the Buck converter of the first channel and a low-side switching device for multi-phases in the stacked converter of the second channel. Similarly, the switching device M5 serves as both a low-side switching device in the Buck converter of the second channel and a low-side switching device for multi-phases in the stacked converter of the first channel.

[0114] As described above, converters CNV1 and CNV2 are each two-phase multi-phase converters. In power supply unit 1C, converters CNV1 and CNV2 operate in parallel. Whereas providing two power supply units 1B of FIG. 13 requires a total of 10 switching elements, power supply unit 1C achieves the same effect as two power supply units 1B operating in parallel with a total of eight switching elements, thereby achieving the effect of reducing the number of parts.

[0115] The configuration of the power supply device 1C in Fig. 18 will be described in further detail. In this embodiment, the switching elements M1 to M8 are each configured by an N-channel MOSFET. For this reason, hereinafter, the switching elements M1 to M8 may be referred to as transistors M1 to M8.

[0116] The transistors M1 to M4 are connected in series between the ground and a node ND4. The transistor M1 is provided between the ground and the node ND1, the transistor M2 is provided between the nodes ND1 and ND2, the transistor M3 is provided between the nodes ND2 and ND3, and the transistor M4 is provided between the nodes ND3 and ND4. More specifically, the source of the transistor M1 is connected to the ground. The drain of the transistor M1 and the source of the transistor M2 are connected to the node ND1. The drain of the transistor M2 and the source of the transistor M3 are connected to the node ND2. The drain of the transistor M3 and the source of the transistor M4 are connected to the node ND3. The drain of the transistor M4 is connected to the node ND4. The signals supplied to the gates of the transistors M1 to M4 are referred to as gate signals G1 to G4, respectively.

[0117] The transistors M5 to M8 are connected in series between the ground and a node ND8. The transistor M5 is provided between the ground and the node ND5, the transistor M6 is provided between the nodes ND5 and ND6, the transistor M7 is provided between the nodes ND6 and ND7, and the transistor M8 is provided between the nodes ND7 and ND8. More specifically, the source of the transistor M5 is connected to the ground. The drain of the transistor M5 and the source of the transistor M6 are connected to the node ND5. The drain of the transistor M6 and the source of the transistor M7 are connected to the node ND6. The drain of the transistor M7 and the source of the transistor M8 are connected to the node ND7. The drain of the transistor M8 is connected to the node ND8. The signals supplied to the gates of the transistors M5 to M8 are referred to as gate signals G5 to G8, respectively.

[0118] Nodes ND4 and ND8 are connected to the input voltage V IN That is, the nodes ND4 and ND8 are power supply nodes that receive the input voltage V INHere, different reference symbols (ND4, ND8) are assigned to the power supply node to which the drain of the transistor M4 is connected and the power supply node to which the drain of the transistor M8 is connected, but the nodes ND4 and ND8 may be a single node, or the input voltage V IN Alternatively, the nodes may be two separate nodes that receive the same power supply.

[0119] Capacitor C MID1 is provided between the node ND2 and the ground. That is, the capacitor C MID1 The first end of the capacitor C is connected to the node ND2. MID1 The second end of the capacitor C is connected to ground. MID1 The first end of the capacitor C MID1 The voltage at node ND2 corresponds to the positive electrode of the intermediate voltage V MID1 That is, the capacitor C MID1 At the intermediate voltage V MID1 A charge of 1000kJ / s is accumulated.

[0120] Capacitor C MID2 is provided between the node ND6 and the ground. That is, the capacitor C MID2 The first end of the capacitor C is connected to the node ND6. MID2 The second end of the capacitor C is connected to ground. MID2 The first end of the capacitor C MID2 The voltage at node ND6 corresponds to the positive electrode of the intermediate voltage V MID2 That is, the capacitor C MID2 At the intermediate voltage V MID2 A charge of 1000 volts is accumulated.

[0121] The inductor L1 is connected between the node ND1 and the output node ND OUT That is, a first end of the inductor L1 is connected to the node ND1, and a second end of the inductor L1 is connected to the output node ND OUT is connected to the capacitor C FLY1 is provided between the nodes ND3 and ND5. That is, the capacitor C FLY1 The first end of the capacitor C is connected to the node ND3. FLY1The second end of the inductor L3 is connected to the node ND5. OUT That is, the first end of the inductor L3 is connected to the node ND5 (and therefore the capacitor C FLY1 , and the second end of inductor L3 is connected to output node ND OUT is connected to.

[0122] The inductor L2 is connected between the node ND5 and the output node ND OUT That is, a first end of the inductor L2 is connected to the node ND5, and a second end of the inductor L2 is connected to the output node ND OUT is connected to the capacitor C FLY2 is provided between the nodes ND7 and ND1. That is, the capacitor C FLY2 The first end of the capacitor C is connected to the node ND7. FLY2 The second end of the inductor L4 is connected to the node ND1. OUT That is, the first end of the inductor L4 is connected to the node ND1 (and therefore the capacitor C FLY2 , and the second end of inductor L4 is connected to output node ND OUT is connected to.

[0123] Capacitor C OUT is the output node ND OUT and ground. That is, the capacitor C OUT The first end of the output node ND OUT and a capacitor C OUT The second end of the capacitor C is connected to ground. OUT The first end of the capacitor C OUT This corresponds to the positive electrode of the output node ND. OUT The voltage at is the output voltage V OUT That is, the capacitor C OUT At the output voltage V OUT A charge of 1000 volts is accumulated.

[0124] The control circuit 30C controls the output voltage V OUT , the current information of inductor L1, and the current information of inductor L2, the output voltage V OUT is the target voltage VTG The control circuit 30C controls the switching of the transistors M1 to M8 and the on / off control of the transistors M1 to M8 using a drive circuit 40C, but the description of the drive circuit 40C may be omitted. OUT The information is the output voltage V OUT For example, the feedback voltage V FB The current information of the inductor L1 is information according to the current flowing through the inductor L1, for example, a voltage signal proportional to the current flowing through the inductor L1. The current information of the inductor L2 is information according to the current flowing through the inductor L2, for example, a voltage signal proportional to the current flowing through the inductor L2. The control circuit 30C controls the transistors M1 to M8 individually to turn on or off in the switching control. The control circuit 30C controls the output voltage V OUT and the current information of the inductors L1 and L2, control signals CNT1 to CNT8 that specify the state (on or off state) of the transistors M1 to M8 are generated.

[0125] The drive circuit 40C generates gate signals G1 to G4 in response to the control signals CNT1 to CNT4, similar to the drive circuit 40A of the first embodiment, and further generates gate signals G5 to G8 in response to the control signals CNT5 to CNT8. The gate signals G1 to G8 from the drive circuit 40C are supplied to the gates of the transistors M1 to M8, respectively, thereby individually setting the states of the transistors M1 to M8 to on or off. The boost circuit 50C will be described later.

[0126] Gate signals G1 to G8 correspond to the control signals CNT1 to CNT8, respectively. Any of the control signals CNT1 to CNT8 is referred to as the control signal CNTx, and the gate signal corresponding to the control signal CNTx is referred to as the gate signal Gx. Of the transistors M1 to M8, the transistor that receives the gate signal Gx at its gate is referred to as the transistor Mx. The drive circuit 40C keeps the gate signal Gx at a high level during the high-level period of the control signal CNTx, and keeps the gate signal Gx at a low level during the low-level period of the control signal CNTx. When the gate signal Gx is at a high level, the transistor Mx is in an on state, and when the gate signal Gx is at a low level, the transistor Mx is in an off state. Therefore, for example, during the high-level period of the gate signal G1, the transistor M1 is in an on state, and during the low-level period of the gate signal G1, the transistor M1 is in an off state. Similarly, transistor M2 is on when gate signal G2 is at a high level, and off when gate signal G2 is at a low level. The same applies to transistors M3 to M8. A high-level gate signal Gx has a potential higher than the potential that is higher than the source potential of transistor Mx by the gate threshold voltage of transistor Mx. A low-level gate signal Gx may have a potential equivalent to the source potential of transistor Mx.

[0127] The control circuit 30C controls the states of the transistors M1 to M8, thereby controlling the input voltage V IN The lower desired output voltage V OUT is the output node ND OUT The control circuit 30C sequentially switches the states of the transistors M1 to M8 between states ST_C1 to ST_C4. The states ST_C1 to ST_C4 will be described with reference to FIGS.

[0128] In addition, the capacitor C FLY1 (i.e., the potential at the node ND5) as a reference. FLY1 The current that increases the potential at the first end of the capacitor C FLY1 The reverse current is the charging current of the capacitor C FLY1 Similarly, the discharge current of the capacitor CFLY2 (i.e., the potential at the node ND1) as a reference. FLY2 The current that increases the potential at the first end of the capacitor C FLY2 The reverse current is the charging current of the capacitor C FLY2 is the discharge current of the capacitor C MID1 Regarding the intermediate voltage V MID1 The current that increases the intermediate voltage V MID1 Similarly, the current that decreases the capacitor C MID2 Regarding the intermediate voltage V MID2 The current that increases the intermediate voltage V MID2 The current that decreases the capacitance is the discharge current.

[0129] In this case, it is assumed that the power supply device 1C is operating in the continuous current mode. In the continuous current mode, current always flows from the first terminal to the second terminal of each of the inductors L1 to L4. That is, the capacitor C OUT A current always flows through inductors L1 to L4 in the direction in which the inductor is charged. The current flowing through inductor L1 is called the inductor current I L1 Similarly, the currents flowing through the inductors L2, L3, and L4 are respectively referred to as inductor currents I L2 , I L3 , I L4 The output node ND OUT is connected to a load (not shown). The load is connected to an output voltage V OUT The output node ND is an arbitrary load that drives the OUT The current supplied to the load from LD The load current I LD corresponds to the output current of the power supply device 1C.

[0130] 19 shows the on / off states of transistors M1 to M8 in state ST_C1 and the current flow that occurs in state ST_C1. In state ST_C1, the control circuit 30C uses the drive circuit 40C to control transistors M2, M3, M5, and M8 to an on state, while controlling transistors M1, M4, M6, and M7 to an off state. The state in state ST_C1 corresponds to state ST_B3 in FIG. 16 for converter CNV1 and to state ST_B1 in FIG. 14 for converter CNV2.

[0131] In the state ST_C1, currents 911 to 913 are generated in the converter CNV1. MID1 from the output node ND through the switching element M2 and the inductor L1. OUT is the current going to the capacitor C MID1 The current 912 flows from the ground through the switching element M5 and the capacitor C FLY1 , through the switching element M3, the capacitor C MID1 Towards the first end of the capacitor C MID1 The current 912 returns to ground through the capacitor C FLY1 is discharged while the capacitor C MID1 The current 913 flows from the ground through the switching element M5 and the inductor L3 to the output node ND OUT Heading towards.

[0132] In the state ST_C1, currents 914 and 915 are generated in the converter CNV2. The current 914 flows from the node ND8 through the switching element M8 and the capacitor C FLY2 and the output node ND through the inductor L4 OUT The current 914 flows to the capacitor C FLY2 The current 915 flows from the ground through the switching element M5 and the inductor L2 to the output node ND OUT In state ST_C1, the capacitor C MID2 No charging or discharging occurs for the capacitor C MID2 The stored charge remains unchanged.

[0133] 20 shows the on / off states of the transistors M1 to M8 in state ST_C2 and the current flow that occurs in state ST_C2. In state ST_C2, the control circuit 30C uses the drive circuit 40C to control the transistors M2, M4, M6, and M8 to an on state, while controlling the transistors M1, M3, M5, and M7 to an off state. The state in state ST_C2 corresponds to state ST_B2 in FIG. 15 for the converter CNV1, and also corresponds to state ST_B2 in FIG. 15 for the converter CNV2.

[0134] In the state ST_C2, the converter CNV1 generates a current 916 together with the current 911. As described above, the current 911 flows through the capacitor C MID1 The current 916 flows from the node ND4 through the switching element M4 and the capacitor C FLY1 and the output node ND through the inductor L3 OUT The current 916 flows to the capacitor C FLY1 is charged.

[0135] In the state ST_C2, a current 917 is generated in the converter CNV2 together with the current 914. As described above, the current 914 causes a current to flow through the capacitor C FLY2 The current 917 charges the capacitor C MID1 from the output node ND through the switching element M6 and the inductor L2. OUT is the current going to the capacitor C MID2 It is generated by the discharge of

[0136] 21 shows the on / off states of the transistors M1 to M8 in state ST_C3 and the current flow that occurs in state ST_C3. In state ST_C3, the control circuit 30C uses the drive circuit 40C to control the transistors M1, M4, M6, and M7 to an on state, while controlling the transistors M2, M3, M5, and M8 to an off state. The state in state ST_C3 corresponds to state ST_B1 in FIG. 14 for the converter CNV1 and to state ST_B3 in FIG. 16 for the converter CNV2.

[0137] In state ST_C3, a current 918 is generated in converter CNV1 together with the current 916. As described above, the current 916 causes a current to flow through capacitor C FLY1 A current 918 flows from the ground through the switching element M1 and the inductor L1 to the output node ND OUT In state ST_C3, the capacitor C MID1 No charging or discharging occurs for the capacitor C MID1 The stored charge remains unchanged.

[0138] In state ST_C3, currents 919 and 920 are generated in converter CNV2 along with the current 917. As described above, current 917 flows through capacitor C MID2 The current 919 flows from the ground through the switching element M1 and the capacitor C FLY2 , through the switching element M7, the capacitor C MID2 Towards the first end of the capacitor C MID2 The current 919 flows through the capacitor C FLY2 is discharged while the capacitor C MID2 The current 920 flows from the ground through the switching element M1 and the inductor L4 to the output node ND OUT Heading towards.

[0139] 22 shows the on / off states of the transistors M1 to M8 in state ST_C4 and the current flow that occurs in state ST_C4. In state ST_C4, the control circuit 30C uses the drive circuit 40C to control the transistors M1, M3, M5, and M7 to an on state, while controlling the transistors M2, M4, M6, and M8 to an off state. The state in state ST_C4 corresponds to state ST_B4 in FIG. 17 for the converter CNV1, and also corresponds to state ST_B4 in FIG. 17 for the converter CNV2.

[0140] In state ST_C4, the above currents 912, 913, and 918 are generated in converter CNV1. As described above, current 912 causes capacitor C FLY1 is discharged while the capacitor C MID1 is charged.

[0141] In state ST_C4, the above currents 919, 920, and 915 are generated in converter CNV2. As described above, current 919 causes a current to flow through capacitor C FLY2 is discharged while the capacitor C MID2 is charged.

[0142] Attention is now focused on converter CNV1. In state ST_C3, the magnitudes of currents 918 and 916 (i.e., inductor current I L1 and I L3 In addition, in state ST_C2, the magnitudes of the currents 911 and 916 (i.e., the inductor current I L1 and I L3 In the state ST_C2, the transistors M2 and M4 are on, so the magnitude of the capacitor C FLY1 and C MID1 For state ST_C2, the state of the capacitor C FLY1 and C MID1 In states ST_C1 and ST_C4, the capacitor C FLY1 and C MID1 As a result, the transistors M1 to M5 and the capacitor C FLY1 and C MID1 The control circuit 40C operates the circuit as a switched capacitor circuit, thereby controlling the capacitor C MID1 The positive terminal of the input voltage V IN The intermediate voltage V corresponds to the divided voltage of MID1 Generates an intermediate voltage V MID1 is essentially the voltage (V IN / 2). Strictly speaking, the intermediate voltage V MID1 is the voltage (V IN / 2) and fluctuates slightly.

[0143] Attention is now focused on converter CNV2. In state ST_C1, the magnitudes of currents 915 and 914 (i.e., inductor current I L2 and I L4 In addition, in state ST_C2, the magnitudes of currents 917 and 914 (i.e., the inductor current IL2 and I L4 In the state ST_C2, the transistors M6 and M8 are on, so the magnitude of the capacitor C FLY2 and C MID2 For state ST_C2, the state of the capacitor C FLY2 and C MID2 In states ST_C3 and ST_C4, the capacitor C FLY2 and C MID2 As a result, the transistors M5 to M8 and M1 and the capacitor C FLY2 and C MID2 The control circuit 40C operates the circuit as a switched capacitor circuit, thereby controlling the capacitor C MID2 The positive terminal of the input voltage V IN The intermediate voltage V corresponds to the divided voltage of MID2 Generates an intermediate voltage V MID2 is essentially the voltage (V IN / 2). Strictly speaking, the intermediate voltage V MID2 is the voltage (V IN / 2) and fluctuates slightly.

[0144] Boost circuit 50C has a boost circuit for converter CNV1 and a boost circuit for converter CNV2.

[0145] The boost circuit for converter CNV1 is the same as the boost circuit 50A of the first embodiment (see FIG. 7). Therefore, transistor Ma in the boost circuit for converter CNV1 is off when transistor M2 is on and on when transistor M2 is off. Transistor Mb in the boost circuit for converter CNV1 is off when transistor M3 is on and on when transistor M3 is off. Transistor Mc in the boost circuit for converter CNV1 is off when transistor M4 is on and on when transistor M4 is off. When only the states of transistors M1 to M4 and Ma to Mc are considered, state ST_C2 in FIG. 20 is equivalent to state ST_A1 in FIG. 9, and state ST_C4 in FIG. 22 is equivalent to state ST_A2 in FIG. 10.

[0146] The boost circuit for converter CNV1 generates a boot voltage for turning on transistors M2 to M4, while the boost circuit for converter CNV2 generates a boot voltage for turning on transistors M6 to M8. Except for this, the configuration and operation of the boost circuit for converter CNV2 may be the same as the configuration and operation of the boost circuit for converter CNV1.

[0147] Fig. 23 shows the internal configuration of the control circuit 30C. Fig. 24 shows a timing chart relating to the operation of the control circuit 30C. Fig. 24 shows, from top to bottom, the waveforms of the signals CLK1, CMPOUT1, CLK2, CMPOUT2, and CNT1 to CNT8.

[0148] The control circuit 30C includes an error amplifier 31, ramp circuits 32_1 and 32_2, current information acquisition circuits 33_1 and 33_2, adders 34_1 and 34_2, PWM comparators 35_1 and 35_2, a clock generation circuit 36C, and controllers 37_1 and 37_2. The power supply device 1C is provided with resistors R1 and R2. A first end of the resistor R1 is connected to an output node ND. OUT The second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to ground. An output voltage V OUT Feedback voltage V according toFB The feedback voltage V FB is the output voltage V OUT Therefore, the output voltage V OUT The resistors R1 and R2 are proportional to the feedback voltage V FB A feedback voltage generating circuit is formed to generate the feedback voltage V FB is supplied to the control circuit 30C. However, it may be understood that the feedback voltage generating circuit is included in the components of the control circuit 30C. OUT It is the feedback voltage V FB In any case, the feedback voltage V FB is the output voltage V OUT Information on the output voltage V OUT (information indicating the value of

[0149] The error amplifier 31 is a current output type transconductance amplifier. The error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal. A feedback voltage V FB A predetermined reference voltage V REF The reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the control circuit 30C. The output terminal of the error amplifier 31 is connected to the wiring WR ERR When the power supply device 1C is started, the reference voltage V REF Although a soft start control may be performed to gradually increase the value of from 0 V to a predetermined positive voltage value, the existence of the soft start control will be ignored below.

[0150] The error amplifier 31 outputs a feedback voltage V FB and the reference voltage V REF By outputting a current signal corresponding to the difference between the feedback voltage V FB and the reference voltage V REF Error voltage V according to the difference between ERR Wiring WR ERR Specifically, the error amplifier 31 generates a feedback voltage V FB is the reference voltage V REF When the error voltage VERR Wiring WR from its own output terminal so that ERR and outputs a current to the feedback voltage V FB is the reference voltage V REF When the error voltage V ERR Wiring WR to reduce ERR The current is drawn from the wiring WR ERR A phase compensation circuit including a capacitor may be connected between the input and ground.

[0151] The ramp circuit 32_1 generates a predetermined initial voltage V INT The ramp voltage V monotonically increases at a predetermined rate of change from RAMP1 In the ramp circuit 32_1, an initial voltage V INT is, for example, 0 V, but may be different from 0 V. During the off period of the transistor M2, the ramp voltage V RAMP1 is the initial voltage V INT It is fixed in place.

[0152] The current information acquisition circuit 33_1 acquires current information of the inductor L1 and outputs a sense voltage V IL1 The current information of the inductor L1 is the inductor current I L1 This is information indicating the value of the sense voltage V IL1 is a positive proportional coefficient and the inductor current I L1 Therefore, the inductor current I L1 As the sense voltage V IL1 rises, and the inductor current I L1 With the decrease in the sense voltage V IL1 Here, "V IL1 = k IV ×I L1 ". k IV is a predetermined positive coefficient.

[0153] Sense voltage V IL1 indicates the current information of the inductor L1, the sense voltage V IL1 The method for generating the inductor current I L1 By directly detecting the current with a current sensor, the sense voltage VIL1 The current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L1 and the node ND1. Alternatively, for example, the current flowing through the transistor M2 during the ON period of the transistor M2 (therefore, the inductor current I L1 ) or by detecting the current flowing through the transistor M1 during the ON period of the transistor M1 (thus the inductor current I L1 ) is detected, the sense voltage V IL1 Alternatively, the inductor current I L1 By detecting the voltage at any point where a voltage corresponding to IL1 may be generated.

[0154] The adder 34_1 calculates the lamp voltage V RAMP1 With respect to the sense voltage V IL1 By adding these, the slope voltage V SLP1 That is, "V SLP1 =V RAMP1 +V IL1 "

[0155] The PWM comparator 35_1 outputs an error voltage V ERR and the slope voltage V SLP1 and generates and outputs a signal CMPOUT1 indicating the comparison result. ERR is input, and the slope voltage V SLP1 is input to the PWM comparator 35_1. SLP1 <V ERR " is established, a low level signal CMPOUT1 is output, and "V SLP1 >V ERR " is established, a high level signal CMPOUT1 is output. SLP1 =V ERR When "is established," the signal CMPOUT1 has a low level or a high level.

[0156] A signal CMPOUT1 and a reference clock signal CLK1 are input to the controller 37_1. The reference clock signal CLK1 is generated by a clock generation circuit 36C. The reference clock signal CLK1 has a predetermined frequency f PWM The reference clock signal CLK1 is a rectangular wave signal having a frequency f PWM The signal is set to have a high level for a short time at intervals equal to the reciprocal of the value of the reference signal (see FIG. 24).

[0157] When a predetermined level change occurs in the reference clock signal CLK1, the controller 37_1 generates a falling edge in the control signals CNT1 and CNT7 to turn off the transistors M1 and M7, and generates a rising edge in the control signals CNT2 and CNT8 to turn on the transistors M2 and M8. The predetermined level change (first predetermined level change) in the reference clock signal CLK1 here is a change from low to high in the reference clock signal CLK1, but it may also be a change from high to low in the reference clock signal CLK1.

[0158] After transistors M1 and M7 are turned off and transistors M2 and M8 are turned on, the slope voltage V SLP1 After a monotonous rise in SLP1 <V ERR "From the established state of "V SLP1 >V ERR When the rising edge occurs in the signal CMPOUT1, the controller 37_1 generates rising edges in the control signals CNT1 and CNT7 to turn on the transistors M1 and M7, and generates falling edges in the control signals CNT2 and CNT8 to turn off the transistors M2 and M8. As the transistor M2 turns off, the ramp voltage V RAMP1 is a sufficiently low initial voltage V INT Since it decreases to "V SLP1 <V ERR” is established again, and a falling edge is generated in the signal CMPOUT1 immediately. The time from when the transistors M1 and M7 are turned off and the transistors M2 and M8 are turned on to when the transistors M1 and M7 are turned on and the transistors M2 and M8 are turned off is defined as time t ON1 It is called.

[0159] The ramp circuit 32_2 generates a predetermined initial voltage V INT The ramp voltage V monotonically increases at a predetermined rate of change from RAMP2 In the ramp circuit 32_2, an initial voltage V INT is, for example, 0 V, but may be different from 0 V. During the off period of the transistor M6, the ramp voltage V RAMP2 is the initial voltage V INT The ramp circuit 32_2 has the same configuration as the ramp circuit 32_1. Therefore, the ramp voltage V RAMP2 The rate of change of the ramp voltage V during the on-period of the transistor M2 is RAMP1 is equal to the rate of change of

[0160] The current information acquisition circuit 33_2 acquires current information of the inductor L2 and outputs a sense voltage V IL2 The current information of the inductor L2 is the inductor current I L2 This is information indicating the value of the sense voltage V IL2 is a positive proportional coefficient and the inductor current I L2 Therefore, the inductor current I L2 As the sense voltage V IL2 rises, and the inductor current I L2 With the decrease in the sense voltage V IL2 Here, "V IL2 = k IV ×I L2 "Let us assume that

[0161] Sense voltage V IL2 indicates the current information of the inductor L2, the sense voltage V IL2 The method for generating the inductor current IL2 By directly detecting the current with a current sensor, the sense voltage V IL2 The current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L2 and the node ND5. Alternatively, for example, the current flowing through the transistor M6 during the on-period of the transistor M6 (hence the inductor current I L2 ) or by detecting the current flowing through the transistor M5 during the ON period of the transistor M5 (thus the inductor current I L2 ) is detected, the sense voltage V IL2 Alternatively, the inductor current I L2 By detecting the voltage at any point where a voltage corresponding to IL2 may be generated.

[0162] The adder 34_2 calculates the lamp voltage V RAMP2 With respect to the sense voltage V IL2 By adding these, the slope voltage V SLP2 That is, "V SLP2 =V RAMP2 +V IL2 "

[0163] The PWM comparator 35_2 outputs the error voltage V ERR and the slope voltage V SLP2 and generates and outputs a signal CMPOUT2 indicating the comparison result. ERR is input, and the slope voltage V SLP2 is input to the PWM comparator 35_2. SLP2 <V ERR " is established, a low level signal CMPOUT2 is output, and "V SLP2 >V ERR " is established, a high level signal CMPOUT2 is output. SLP2 =V ERR When "is established," the signal CMPOUT2 has a low level or a high level.

[0164] A signal CMPOUT2 and a shift clock signal CLK2 are input to the controller 37_2. The shift clock signal CLK2 is generated by the clock generation circuit 36C based on the reference clock CLK1. The shift clock signal CLK2 is a signal obtained by shifting the phase of the reference clock CLK1. Therefore, the reference clock signal CLK1 and the shift clock signal CLK2 have the same frequency f PWM and have different phases. As with the reference clock CLK1, the shift clock signal CLK2 has a low level in principle and a frequency f PWM (See FIG. 24). Here, the shift clock signal CLK2 is assumed to be a signal whose phase is delayed by 180° from the reference clock signal CLK1. Therefore, the phase difference between the clock signals CLK1 and CLK2 is 180°. Setting the delay amount to 180° results in the output voltage V OUT However, the amount of delay in phase of the shift clock signal CLK2 from the phase of the reference clock signal CLK1 may be other than 180° (for example, it may be 170° or 190°).

[0165] When a predetermined level change occurs in the shift clock signal CLK2, the controller 37_2 generates a falling edge in the control signals CNT3 and CNT5 to turn off the transistors M3 and M5, and generates a rising edge in the control signals CNT4 and CNT6 to turn on the transistors M4 and M6. The predetermined level change (second predetermined level change) in the shift clock signal CLK2 here is a change from low level to high level in the shift clock signal CLK2, but it may also be a change from high level to low level in the shift clock signal CLK2.

[0166] After transistors M3 and M5 are turned off and transistors M4 and M6 are turned on, the slope voltage V SLP2 After a monotonous rise in SLP2 <V ERR "From the established state of "V SLP2 >V ERRWhen the rising edge occurs in the signal CMPOUT2, the controller 37_2 generates rising edges in the control signals CNT3 and CNT5 to turn on the transistors M3 and M5, and generates falling edges in the control signals CNT4 and CNT6 to turn off the transistors M4 and M6. As the transistor M6 turns off, the ramp voltage V RAMP2 is a sufficiently low initial voltage V INT Since it decreases to "V SLP2 <V ERR ” is established again, and a falling edge is generated in the signal CMPOUT2 immediately. The time from when the transistors M3 and M5 are turned off and the transistors M4 and M6 are turned on to when the transistors M3 and M5 are turned on and the transistors M4 and M6 are turned off is defined as time t ON2 It is called.

[0167] 24 (see also FIGS. 19 to 22), the states of the transistors M1 to M8 are sequentially switched between states ST_C1 to ST_C4. In other words, starting from state ST_C3 in the timing chart of FIG. 24, the states of the transistors M1 to M8 are switched from state ST_C3 to state ST_C2 at the rising edge of the reference clock signal CLK1, then switched from state ST_C2 to state ST_C1 at the rising edge of the signal CMPOUT2, then switched from state ST_C1 to state ST_C4 at the rising edge of the signal CMPOUT1, and then returned from state ST_C4 to state ST_C3 at the rising edge of the shift clock signal CLK2. Thereafter, the same operation is repeated. The length between the transition timing from state ST_C3 to state ST_C2 and the next transition timing from state ST_C3 to state ST_C2 is the frequency f of the reference clock signal CLK1. PWM is equal to the inverse of

[0168] "V OUT =V TG "When "V FB =VREF "V OUT =V TG Starting from the state where " LD Through the increase of "V OUT <V TG "So, "V FB <V REF " so the error voltage V ERR The error voltage V ERR The increase in the ON period of the transistors M2 and M6 results in an increase in the ON period of the transistor M2. L1 As the on-period of the transistor M6 increases, the inductor current I L2 increases, resulting in an output voltage V OUT is the target voltage V TG On the other hand, "V OUT =V TG Starting from the state where " LD Through the decrease of "V OUT >V TG "So, "V FB >V REF " so the error voltage V ERR The error voltage V ERR The decrease in the ON period of the transistors M2 and M6 results in a decrease in the inductor current I L1 As the on-period of the transistor M6 decreases, the inductor current I L2 decreases, resulting in the output voltage V OUT is the target voltage V TG In this way, the output voltage V OUT and target voltage V TG Control is performed to reduce the difference between the

[0169] The above-mentioned time t ON1 is the error voltage V ERR (and hence the output voltage V OUT ) and the sense voltage V IL1 (and therefore depends on the current information of the inductor L1). In other words, the controller 37_1 controls the output voltage V OUTBased on the information on the current of the inductor L1 and the information on the current of the inductor L1, the controller 37_1 controls the switching of the transistors M1, M2, M7, and M8 in synchronization with the reference clock signal CLK1. The controller 37_1 turns off the transistors M1 and M7 and turns on the transistors M2 and M8 in response to a predetermined level change in the reference clock signal CLK1, and then controls the output voltage V OUT and the time t ON1 lapses, causing transistors M1 and M7 to turn on and transistors M2 and M8 to turn off.

[0170] The above-mentioned time t ON2 is the error voltage V ERR (and hence the output voltage V OUT ) and the sense voltage V IL2 (and therefore depends on the current information of the inductor L2). In other words, the controller 37_2 controls the output voltage V OUT The controller 37_2 controls the switching of the transistors M3 to M6 in synchronization with the shift clock signal CLK2 based on the information on the current of the inductor L2 and the information on the current of the inductor L2. The controller 37_2 turns off the transistors M3 and M5 and turns on the transistors M4 and M6 in response to a predetermined level change in the shift clock signal CLK2, and then controls the output voltage V OUT and the time t ON2 lapses, causing transistors M3 and M5 to turn on and transistors M4 and M6 to turn off.

[0171] Converters CNV1 and CNV2 have the same configuration. In addition, the switching control of transistors M1, M2, M7, and M8 based on the current information of inductor L1 is equivalent to the switching control of transistors M3, M4, M5, and M6 based on the current information of inductor L2. Therefore, multiphase operation is achieved with the output current of converter CNV1 and the output current of converter CNV2 balanced.

[0172] In the power supply device 1C, the output current of the converter CNV1 is the inductor current I L1 and IL3 The output current of the converter CNV2 is the inductor current I L2 and I L4 The output current of the buck converter of the first channel (i.e., the inductor current I L1 ) and the output current of the stacked converter of the first channel (i.e., the inductor current I L3 ) will be approximately the same. Similarly, the output current of the buck converter of the second channel (i.e., the inductor current I L2 ) and the output current of the stacked converter of the second channel (i.e., the inductor current I L4 As a result, the average of the inductor current I L1 ~I L4 Although the instantaneous values ​​of the inductor current I L1 and the average inductor current I L2 and the average inductor current I L3 and the average inductor current I L4 is essentially equal to the average of

[0173] The output current of the first channel buck converter (i.e., the inductor current I L1 ), the output current of the second channel buck converter (i.e., the inductor current I L2 ), the output current of the stacked converter of the first channel (i.e., the inductor current I L3 ), and the output current of the stacked converter of the second channel (i.e., the inductor current I L4 ) are pulsating currents. Among these, the output current of the buck converter of the first channel (i.e., the inductor current I L1 ) and the output current of the stacked converter of the first channel (i.e., the inductor current I L3 ) have different phases from each other, while the output current of the buck converter of the second channel (i.e., the inductor current I L2 ) and the output current of the second channel stacked converter (i.e., the inductor current I L4 ) have different phases from each other.

[0174] Note that by deleting inductors L3 and L4 from power supply device 1C of Fig. 18, power supply device 1C may be modified into power supply device 1C' of Fig. 25. In power supply device 1C', the only difference is that no current is generated passing through inductors L3 and L4 as seen from power supply device 1C, and in other respects the configuration and operation of power supply device 1C' are the same as those of power supply device 1C.

[0175] Although not specifically shown, in the power supply device 1C or 1C′, the capacitor C MID2 In this case, the nodes ND2 and ND6 are short-circuited. MID2 After omitting the capacitor C MID1 may be inserted between the nodes ND2 and ND6 (i.e., the capacitor C MID1 a first end of the capacitor C MID1 The second end of the resistor 11 may be connected to the node ND6.

[0176] <<Fourth Embodiment>> A fourth embodiment of the present disclosure will be described. In the fourth embodiment, modified techniques, applied techniques, supplementary matters, etc. to the first to third embodiments will be described.

[0177] The power supply device according to the present disclosure will be referred to as power supply device 1. The power supply device 1 may be any of the power supply devices described in the first to third embodiments, and therefore may be any of power supply devices 1A, 1B, 1C, and 1C'. The power supply device 1 can be applied to any device or system that requires a stable DC voltage. For example, the power supply device 1 may be applied to a power supply system for a data center. In this case, for example, the output voltage V OUT may be 48V, and the power supply device 1 outputs an output voltage V OUT In recent years, reducing power consumption in data centers has become an important issue, and as part of this effort, there has been a shift from 12V power buses to 48V power buses. It is necessary to supply power from the 48V power bus with high efficiency to server systems or storage devices consisting of semiconductor memories, magnetic disks, etc. Use of the power supply unit 1 enables high-efficiency power supply.

[0178] Alternatively, the power supply device 1 may be applied to a primary power supply in a vehicle such as an automobile. In this case, the power supply device 1 receives an input voltage V IN Directly receives the output voltage V OUT and an output voltage V OUT The power supply device 1 may function as a driving voltage for any system (e.g., a level 3 or higher autonomous driving system) installed in the vehicle. Alternatively, for example, the power supply device 1 may be applied to a power source for a charging system. The charging system may charge the battery of an electric vehicle. Alternatively, for example, the power supply device 1 may be applied to a power source for a base station.

[0179] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0180] The channel types of the FETs (field effect transistors) shown in each embodiment are merely examples. The channel type of any FET can be changed between P-channel and N-channel types without departing from the spirit of the above.

[0181] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0182] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0183] <<Supplementary Notes>> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0184] A power supply device according to one aspect of the present disclosure (for example, 1A; see FIGS. 1 and 6 to 8) receives an input voltage (V IN ) and a first node (ND1); a second switching element (M2) provided between the first node and a second node (ND2); a third switching element (M3) provided between the second node and a third node (ND3); a fourth switching element (M4) provided between the third node and a fourth node (ND4) receiving the input voltage; and a first boot voltage (V) provided to a gate of the second switching element to turn on the second switching element. BOOT1 ) to the first boot wiring (W BOOT1 ) and supplied to the gate of the third switching element to turn on the third switching element. BOOT2 ) to the second boot wiring (W BOOT2 ) and a third boot voltage (V) supplied to the gate of the fourth switching element to turn on the fourth switching element. BOOT3 ) to the third boot wiring (W BOOT3 ), a boost circuit (50A) configured to generate a predetermined drive voltage (V DRV) and the first boot voltage to the third boot voltage, and a drive circuit (40A) configured to turn on or off the first switching element to the fourth switching element individually in accordance with the control signal, and an output voltage (V OUT ), the first switching element to the fourth switching element are each configured by an N-channel field effect transistor, and the boost circuit generates a first boot capacitor (C BOOT1 ) and a second boot capacitor (C BOOT2 ) and a third boot capacitor (C BOOT3 ) and a drive wiring (W DRV ) and the first boot wiring, a second boot switch (Mb) provided between the first boot wiring and the second boot wiring, and a third boot switch (Mc) provided between the second boot wiring and the third boot wiring, and the first boot voltage to the third boot voltage are generated by the control circuit controlling the states of each switching element and each boot switch (first configuration).

[0185] This makes it possible to form a highly efficient power supply device in which the switching loss of each switching element is kept low.

[0186] In the power supply device according to the first configuration (see FIGS. 9 and 10), the control circuit may be configured (second configuration) to switch the states of the first to fourth switching elements between a plurality of states including a first state (ST_A1) and a second state (ST_A2), in which in the first state the second switching element and the fourth switching element are on and the first switching element and the third switching element are off, and in the second state the second switching element and the fourth switching element are off and the first switching element and the third switching element are on.

[0187] In the power supply device according to the second configuration (see Figures 9 and 10), the boost circuit may be configured (third configuration) such that in the first state, the first boot switch and the third boot switch are set to off and the second boot switch is set to on, and in the second state, the first boot switch and the third boot switch are set to on and the second boot switch is set to off.

[0188] In the power supply device according to any of the first to third configurations, the first to third boot switches may each be configured by a P-channel field effect transistor (fourth configuration).

[0189] By configuring each boot switch with a P-channel field effect transistor, it is possible to obtain a high boot voltage. As a result, the switching loss of each switching element can be kept low. Furthermore, when configuring a power supply unit using a semiconductor device having a semiconductor integrated circuit and a group of disc lead components, it is possible to provide a control circuit and the like in the semiconductor integrated circuit, and in this case, it is easy to provide each boot switch in the semiconductor integrated circuit as well. This makes it possible to reduce the number of components in the power supply unit, thereby making it possible to miniaturize the power supply unit.

[0190] In the power supply device according to the fourth configuration (see FIGS. 9 and 10), the booster circuit LX) and the first boot voltage, and sets the first boot switch on or off based on the voltage of the second node (V MID ) and the second boot voltage, and sets the second boot switch on or off based on the voltage of the third node (V FLY ) and the third boot voltage, the third boot switch may be set to ON or OFF (fifth configuration).

[0191] In the power supply device according to any one of the first to fifth configurations, the control circuit performs switching control to switch the states of the first to fourth switching elements between the plurality of states based on information about the output voltage and current information about an inductor (L1) provided between the first node and an output node to which the output voltage is applied, thereby dividing the input voltage and generating an intermediate voltage (V MID ) to generate the output voltage, and the control circuit, in the switching control, controls an intermediate capacitor (C MID ) and a flying capacitor (C FLY ) may be operated as a switched capacitor circuit, thereby generating the intermediate voltage at the second node (sixth configuration).

[0192] In the power supply device according to any of the first to sixth configurations, the control signals generated by the control circuit include first to fourth control signals (CNT1 to CNT4), and the drive circuit includes a first gate driver (42_1) configured to turn on or off the first switching element by driving a gate of the first switching element in response to the first control signal based on the drive voltage and a voltage (VSS) of the reference node, and a second gate driver (42_2) configured to turn on or off the first switching element by driving a gate of the first switching element in response to the first control signal based on the drive voltage and a voltage (VSS) of the reference node. LX a second gate driver (42_2) configured to drive a gate of the second switching element in response to the second control signal based on the second boot voltage and the voltage (VMID a third gate driver (42_3) configured to drive a gate of the third switching element in response to the third control signal based on the third boot voltage and the voltage (V FLY and a fourth gate driver (42_4) configured to drive the gate of the fourth switching element in response to the fourth control signal based on the fourth control signal, thereby turning on or off the fourth switching element (seventh configuration).

[0193] 1A, 1B, 1C, 1C' Power supply device 10A Power supply control device 30A, 30B, 30C Control circuit 40A, 40B, 40C Drive circuit 50A, 50B, 50C Boost circuit M1 to M8 Switching elements (transistors) G1 to G8 Gate signal C FLY , C FLY1 , C FLY2 Capacitor (Flying Capacitor) C MID , C MID1 , C MID2 Capacitor (intermediate capacitor) C OUT Capacitor (output capacitor) L1 to L4 Inductor V IN Input voltage V OUT Output voltage V MID , V MID1 , V MID2 Intermediate voltage V LX , V FLY Voltage ND1 to ND8 Node ND OUT Output node I L , I L1 ~I L4 Inductor current I LD Load current CNT1 to CNT8 Control signal G1 to G8 Gate signal 31 Error amplifier 32, 32_1, 32_2 Ramp circuit 33, 33_1, 33_2 Current information acquisition circuit 34, 34_1, 34_2 Adder 35, 35_1, 35_2 PWM comparator 36 Oscillator circuit 36C Clock generation circuit 37, 37_1, 37_2 Controller R1, R2 Resistor V FB Feedback voltage V REF Reference voltage VERR Error voltage WR ERR Wiring V RAMP , V RAMP1 , V RAMP2 Lamp voltage V IL , V IL1 , V IL2 Sense voltage V SLP , V SLP1 , V SLP2 Slope voltage CLK Reference clock signal CLK1 Reference clock signal CLK2 Shift clock signal 41_1 to 41_4, 51_2 to 51_4 Level shifter 42_1 to 42_4 Gate driver 52_2 to 52_4 Switch driver V DRV Driving voltage V BOOT1 ~V BOOT3 Boot voltage W BOOT1 ~W BOOT3 Boot wiring Ma to Ma Boot switch (transistor) CNVa Buck converter CNVb Stacked converter CNV1, CNV2 Converter

Claims

1. A first switching element provided between a first node and a reference node having a potential lower than an input voltage, a second switching element provided between the first node and a second node, a third switching element provided between the second node and a third node, and a fourth switching element provided between the third node and a fourth node receiving the input voltage, a boost circuit configured to generate a first boot voltage on a first boot wiring to be supplied to a gate of the second switching element to turn on the second switching element, generate a second boot voltage on a second boot wiring to be supplied to a gate of the third switching element to turn on the third switching element, and generate a third boot voltage on a third boot wiring to be supplied to the gate of the fourth switching element to turn on the fourth switching element, and a control circuit configured to generate a control signal specifying a state of each switching element, a drive circuit configured to use a predetermined drive voltage and the first boot voltage to the third boot voltage and turn on or off the first switching element to the fourth switching element individually in response to the control signal, and generating an output voltage lower than the input voltage by controlling the states of the first switching element to the fourth switching element, the first switching element to the fourth switching element being each constituted by an N-channel type field effect transistor, and the boost circuit comprises: a first boot capacitor provided between the first node and the first boot wiring, a second boot capacitor provided between the second node and the second boot wiring, a third boot capacitor provided between the third node and the third boot wiring, a first boot switch provided between the drive wiring to which the drive voltage is applied and the first boot wiring, a second boot switch provided between the first boot wiring and the second boot wiring, and a third boot switch provided between the second boot wiring and the third boot wiring, and the first boot voltage to the third boot voltage are generated by the control circuit controlling the states of each switching element and each boot switch.

2. The power supply device of claim 1, wherein the control circuit switches the states of the first switching element to the fourth switching element between a plurality of states including a first state and a second state, and in the first state, the second switching element and the fourth switching element are on and the first switching element and the third switching element are off, and in the second state, the second switching element and the fourth switching element are off and the first switching element and the third switching element are on.

3. The power supply device of claim 2, wherein the boost circuit sets the first boot switch and the third boot switch to off and sets the second boot switch to on in the first state, and sets the first boot switch and the third boot switch to on and sets the second boot switch to off in the second state.

4. A power supply device according to any one of claims 1 to 3, wherein the first boot switch to the third boot switch are each constituted by a P-channel type field effect transistor.

5. The power supply device of claim 4, wherein the boost circuit sets the first boot switch on or off based on the voltage of the first node and the first boot voltage, sets the second boot switch on or off based on the voltage of the second node and the second boot voltage, and sets the third boot switch on or off based on the voltage of the third node and the third boot voltage.

6. The power supply device according to any one of claims 1 to 5, wherein the control circuit performs switching control to switch states of the first switching element to the fourth switching element between the plurality of states based on information about the output voltage and information about a current through an inductor provided between the first node and an output node to which the output voltage is applied, thereby dividing the input voltage and stepping down an intermediate voltage obtained by voltage division to generate the output voltage, and the control circuit, in the switching control, operates a circuit having the first switching element to the fourth switching element, an intermediate capacitor connected to the second node, and a flying capacitor connected to the third node as a switched capacitor circuit, thereby generating the intermediate voltage at the second node.

7. A power supply device as claimed in any one of claims 1 to 6, wherein the control signals generated by the control circuit include first control signal to fourth control signal, and the drive circuit comprises: a first gate driver configured to turn on or off the first switching element by driving the gate of the first switching element in response to the first control signal based on the drive voltage and the voltage of the reference node; a second gate driver configured to turn on or off the second switching element by driving the gate of the second switching element in response to the second control signal based on the first boot voltage and the voltage of the first node; a third gate driver configured to turn on or off the third switching element by driving the gate of the third switching element in response to the third control signal based on the second boot voltage and the voltage of the second node; and a fourth gate driver configured to turn on or off the fourth switching element by driving the gate of the fourth switching element in response to the fourth control signal based on the third boot voltage and the voltage of the third node.

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