Display panel

Abstract

Disclosed is a display panel (100), comprising N GOA units (310) arranged in a first direction, each GOA unit (310) comprising a first output module (20), a signal generation module (10) and a second output module (30) that are arranged in a second direction (Y), wherein the first output module (20) is used for outputting a first gate drive signal; the second output module (30) is used for outputting a second gate drive signal; the first gate drive signal and the second gate drive signal are different; and the length of the first output module (20) and the length of the second output module (30) are different.

Description

Display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new display technology that has gradually attracted people's attention for its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the related art, the pixel driving circuit of an OLED display panel is usually an 8T2C circuit. For this pixel driving circuit, a complementary metal oxide semiconductor (CMOS) gate driving circuit (Gate On Array, GOA) has been proposed to solve the technical problem of high power consumption of conventional gate driving circuits.

[0004] Since the CMOS GOA circuit needs to generate two gate drive signals, Nout and Pout, the gate drive circuit is provided with two buffer parts corresponding to Nout and Pout respectively. The existing signal generation part is usually set close to the frame, and the buffer part is usually set close to the display area. The two buffer parts may overlap in the vertical direction. When the longitudinal size of each level of GOA unit is limited, the size of the two buffer parts in the vertical direction will become smaller. In order to ensure the performance of the transistors in Nout and Pout, the size of the buffer part in the horizontal direction needs to be increased. It is necessary to reserve a wider area on the frame of the product to set the gate drive circuit, which is contrary to the narrow frame design of the product. SUMMARY OF THE INVENTION

[0005] The present application provides a display panel to improve the technical problem of excessively large borders in existing display devices.

[0006] To solve the above problem, the technical solution provided by this application is as follows:

[0007] The present application provides a display panel, comprising a display portion and a gate driving circuit located on one side of the display portion, wherein the gate driving circuit comprises N cascaded GOA units, and the N GOA units are arranged along a first direction; wherein each of the GOA units comprises a signal generating module, a first output module, and a second output module arranged along a second direction;

[0008] The first output module is provided on a side of the signal generating module close to the display portion, and the first output module is used to output a first gate driving signal;

[0009] The second output module is provided at a side of the signal generating module away from the display unit, and the second output module is used to output a second gate driving signal, wherein the first gate driving signal and the second gate driving signal are different;

[0010] In which, in the second direction, the lengths of the first output module and the second output module are different, the second direction is parallel to the scan line of the display panel, the angle between the first direction and the second direction is greater than 0° and less than or equal to 90, and N is a positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a simplified structural diagram of the display panel of the present application;

[0012] FIG2 is a simplified structural diagram of a gate drive circuit in a display panel of the present application;

[0013] FIG3 is a first equivalent circuit diagram of a gate driving circuit in a display panel of the present application;

[0014] FIG4 is a timing control diagram of a gate drive circuit in a display panel of the present application;

[0015] FIG5 is a second equivalent circuit diagram of the gate driving circuit in the display panel of the present application;

[0016] FIG6 is a schematic diagram of a film layer in a display panel of the present application;

[0017] FIG7 is a film layer diagram of the first gate layer in the display panel of the present application;

[0018] FIG8 is a film layer diagram of the second gate layer in the display panel of the present application;

[0019] FIG9 is a diagram showing the superposition of the first gate layer and the second gate layer in the display panel of the present application;

[0020] FIG10 is a film layer diagram of the third gate layer in the display panel of the present application;

[0021] FIG11 is a diagram showing the superimposed film layers of the second gate layer and the third gate layer in the display panel of the present application;

[0022] FIG12 is a film diagram of the first active layer in the display panel of the present application;

[0023] FIG13 is a diagram of the stacked film layers of the first gate layer, the second gate layer, the third gate layer, the first active layer, and the second active layer in the display panel of the present application;

[0024] FIG14 is a film diagram of the second active layer in the display panel of the present application;

[0025] FIG15 is a film diagram of the first source and drain electrode layer in the display panel of the present application;

[0026] FIG16 is a diagram showing the superimposed film layers of the first active layer, the second active layer, and the first source and drain electrode layer of the display panel of the present application;

[0027] FIG17 is a diagram showing the superimposed film layers of the first gate layer, the second gate layer, and the first source and drain layer of the present application;

[0028] FIG18 is a film diagram of the second source and drain electrode layer in the display panel of the present application;

[0029] FIG19 is a film diagram of the first source-drain layer and the second source-drain layer in the display panel of the present application;

[0030] FIG20 is a diagram showing the superimposed film layers of the first active layer, the second active layer, and the second source and drain electrode layer in the display panel of the present application;

[0031] FIG21 is a diagram of the superimposed film layers of the first gate layer, the first source-drain layer, and the second source-drain layer in the display panel of the present application. Modes for Carrying Out the Invention

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0033] Related OLED display panels typically use a complementary metal oxide semiconductor (CMOS) gate drive circuit to address the high power consumption of conventional gate drive circuits. However, because the CMOS GOA circuit needs to generate two gate drive signals, Nout and Pout, the gate drive circuit is equipped with two buffer sections corresponding to Nout and Pout, respectively. Conventional signal generation is typically located near the bezel, while the buffer section is typically located near the display area. This results in a wider area being reserved on the product's bezel for the buffer section, which conflicts with the product's narrow bezel design. This application proposes the following solution based on the aforementioned technical issues.

[0034] 1 to 21 , the present application provides a display panel 100 . The display panel 100 may include a display portion 200 and a gate driver circuit 300 located on one side of the display portion 200 . The gate driver circuit 300 includes N cascaded GOA units 310 . The N GOA units 310 are arranged along a first direction X.

[0035] In this embodiment, each GOA unit 310 includes a signal generating module 10, a first output module 20, and a second output module 30 arranged along the second direction Y; the first output module 20 is arranged on a side of the signal generating module 10 close to the display unit 200, and the first output module 20 is used to output a first gate driving signal; the second output module 30 is arranged on a side of the signal generating module 10 away from the display unit 200, and the second output module 30 is used to output a second gate driving signal, and the first gate driving signal and the second gate driving signal are different.

[0036] In this embodiment, in the second direction Y, the lengths of the first output module 20 and the second output module 30 are different. The second direction Y is parallel to the scan line of the display panel 100 . The first direction X and the second direction Y are perpendicular. N is a positive integer.

[0037] In this embodiment, the included angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°. Referring to FIG. 2 , the second direction Y may be perpendicular to the first direction X.

[0038] The present application arranges two output modules that output different gate drive signals and have different lengths on both sides of the signal generating module 10, so that the two output modules have sufficient width in the first direction X, thereby ensuring the performance of the transistors in the two output modules, avoiding the technical problem of increased borders due to stacking the two output modules on the same side, and realizing a narrow border design.

[0039] It should be noted that the first gate drive signal is a positive pulse signal, and the second gate drive signal is a negative pulse signal; and, within a frame time interval, the first signal output terminal Nout outputs two positive pulse signals, and the second signal output terminal Pout outputs one negative pulse signal; at the same time, the pulse width of a positive pulse signal is greater than the pulse width of a negative pulse signal.

[0040] Since the CMOS GOA circuit of the present application needs to output a first gate drive signal and a second gate drive signal, and the pulse width of the first gate drive signal is larger than the pulse width of the second gate drive signal, that is, the output load of the first output module 20 is larger than the output load of the second output module 30; therefore, the width of the first output module 20 can be larger than the width of the second output module 30 in the present application, so that the first output module 20 has a larger buffer space and a greater output load capacity.

[0041] It should be noted that since low-temperature polysilicon semiconductors have a large leakage current and metal oxide transistors have a small leakage current, in order to reduce the leakage current of the first output module 20, the present application can set the transistors in the first output module 20 to a combination of low-temperature polysilicon transistors and metal oxide transistors.

[0042] Please refer to Figure 2. The first output module 20 may include a first buffer unit 210 and a second buffer unit 220 arranged along the second direction Y. The first buffer unit 210 is arranged close to the signal generating module 10, and the second buffer unit 220 is arranged away from the signal generating module 10. The first buffer unit 210 includes a first output transistor T10, and the first output transistor T10 includes a first active portion T10A. The second buffer unit 220 includes a second output transistor T9, and the second output transistor T9 includes a second active portion T9A. The first active portion T10A is a metal oxide semiconductor, and the second active portion T9A is a low-temperature polysilicon semiconductor.

[0043] The present application configures the first output module 20 to be a combination of low-temperature polysilicon transistors and metal oxide transistors, utilizing the high mobility of low-temperature polysilicon transistors and the low leakage current of metal oxide transistors to improve the device effect of the first output module 20 .

[0044] In this embodiment, since the display area AA is also provided with a metal oxide semiconductor, that is, the metal oxide semiconductors in the non-display area NA and the display area AA can be formed in the same photomask process. However, since the patterning densities of the metal oxide semiconductors in the non-display area NA and the display area AA are different, if the first output transistor T10 is disposed adjacent to the display area AA, the patterning density of the metal oxide semiconductor in the first output transistor T10 may deviate from the designed value.

[0045] In the present application, the first output transistor T10 having a metal oxide semiconductor is arranged away from the display area AA, and the second output transistor T9 having a low-temperature polysilicon semiconductor is arranged close to the display area AA, so that the pattern of the metal oxide semiconductor of the first output transistor T10 is away from the pattern of the metal oxide semiconductor in the display area AA, thereby avoiding the deviation of the spacing of the metal oxide semiconductor pattern in the non-display area NA from the design value due to the adjacent arrangement of the patterned metal oxide semiconductors in the display area AA and the non-display area NA.

[0046] Referring to FIG. 2 , in the second direction Y, the length of the first output transistor T10 may be greater than the length of the second output transistor T9 .

[0047] In this embodiment, the first output transistor T10 is a metal oxide transistor. Although the metal oxide transistor has a small leakage current, the mobility of the metal oxide transistor is low. Therefore, in order to improve the driving capability of the first output transistor T10, the present application increases the length of the first output transistor T10 in the second direction Y as much as possible within a limited space to improve the driving capability of the first output transistor T10.

[0048] In the display panel 100 of the present application, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7. The third output transistor T6 includes a third active portion T6A, and the fourth output transistor T7 includes a fourth active portion T7A. The third active portion T6A and the fourth active portion T7A are low-temperature polysilicon semiconductors. The third output transistor T6 and the fourth output transistor T7 are arranged in parallel along the first direction X.

[0049] In this embodiment, since the third output transistor T6 and the fourth output transistor T7 in the second output module 30 are both low-temperature polycrystalline silicon semiconductors with relatively high mobility, the transistors in the second output module 30 do not need to increase their length in the second direction Y to improve the driving capability of the third output transistor T6 and the fourth output transistor; at the same time, the second gate drive signal output by the second output module 30 is a negative pulse signal, and the pulse width of the negative pulse signal is smaller than the pulse width of the positive pulse signal output by the first output module 20, so the output load of the second output module 30 is lower than the output load of the first output module 20, so the length of the first output module 20 in the second direction Y of this application is smaller than the length of the second output module 30 in the second direction Y.

[0050] The technical solution of this application is now described in conjunction with specific embodiments.

[0051] Referring to Figure 1 , the display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA includes a display portion 200. Optionally, the non-display area NA surrounds the display area AA, enclosing the display area AA. The display area AA is the region within the display panel 100 dedicated to display functions, and includes multiple display units therein for implementing these functions. The non-display area NA may be a border region of the display panel 100, and may include functional components that assist the display units within the display area AA in performing their display functions.

[0052] Referring to Figure 1 , the lower side of the display area AA is provided with a bonding terminal 400. The bonding terminal 400 can be connected to an external circuit and transmits signals input from the external circuit to the data traces, thereby driving the display panel 100 to display an image. For example, the bonding terminal 400 can be bonded to a chip or a chip-on-film to provide power and drive signals to the display panel 100.

[0053] In this embodiment, a plurality of light-emitting devices LED and sub-pixel circuits for driving the light-emitting devices LED may be arranged in an array in the display area AA. The sub-pixel circuits may be pixel driving circuits such as 7T1C, 7T2C, and 8T2C, and this application does not impose any specific restrictions.

[0054] In this embodiment, the gate driving circuit 300 is arranged in the non-display area NA, and the gate driving circuit 300 can be arranged on both sides of the display area AA; the gate driving circuit 300 may include N cascaded GOA units 310, and the N GOA units 310 may be arranged along the first direction X. The structure of the GOA unit 310 can be various, such as the circuit structure in Figure 3, and Figure 4 is a timing control diagram of Figure 3.

[0055] Taking the structure of FIG3 as an example, each GOA unit 310 may include:

[0056] The stage transmission signal selection module 301 is electrically connected between the start signal line STV and the fourth node O.

[0057] The pull-up control module 302 controls the potential of the first node K according to the potential of the fourth node O and the potential of the second clock signal line XCK.

[0058] The first filter module 303 is electrically connected between the fifth node W and the first node K. The control end of the first filter module 303 is electrically connected to the reset signal line RST.

[0059] The second filtering module 304 is electrically connected between the fifth node W and the second node Q. The control terminal of the second filtering module 304 receives the first gate driving signal of the N-2th stage.

[0060] The first inverting module 305 is connected between the first node K and the third node P.

[0061] The feedback module 306 is connected between the first node K and the third node P.

[0062] The first output module 20 is connected between the first node K and the first signal output terminal Nout, and is configured to output a first gate driving signal.

[0063] The second output module 30 outputs a second gate driving signal according to the potential of the second node Q and the potential of the third node P.

[0064] The first storage capacitor C1 , a first plate C1 a of the first storage capacitor C1 is connected to the second node Q, and a second plate C1 b of the first storage capacitor C1 is connected to the second signal output terminal Pout.

[0065] The voltage regulating module 307 has a first terminal electrically connected to the first low potential line Nvgl1 , a second terminal electrically connected to the gate of the first output transistor T10 , and a control terminal electrically connected to the third node P.

[0066] In this embodiment, in one frame, the gate drive circuit 300 includes a stage S100 and a stage S200. In the stage S100, the pulses of each first gate drive signal and the pulses of each second gate drive signal are output, while in the stage S200, the pulses of each first gate drive signal and the pulses of each second gate drive signal are not required.

[0067] In this embodiment, the level transfer signal selection module 301 includes a first-level transfer transistor T13 and a second-level transfer transistor T12, and the first-level transfer transistor T13 is a dual-gate transistor; the two gates of the first-level transfer transistor T13 and the gate of the second-level transfer transistor T12 are connected to the start signal line STV, the source of the first-level transfer transistor T13 is connected to the second low-potential line Pvgl, the drain of the first-level transfer transistor T13 and the source of the second-level transfer transistor T12 are connected to the fourth node O, and the drain of the second-level transfer transistor T12 is connected to the third high-potential line Pvgh2.

[0068] In this embodiment, the pull-up control module 302 includes a pull-up transistor T2 , a gate of the pull-up transistor T2 connected to the second clock signal line XCK, a source of the pull-up transistor T2 connected to the fourth node O, and a drain of the pull-up transistor T2 connected to the first node K.

[0069] In this embodiment, the first filtering module 303 includes a first filtering transistor T11 and a second storage capacitor C2, the gate of the first filtering transistor T11 and the third plate C2a of the second storage capacitor C2 are connected to the reset signal line RST, the source of the first filtering transistor T11 is connected to the first node K, and the drain of the first filtering transistor T11 and the fourth plate C2b of the second storage capacitor C2 are connected to the fifth node W.

[0070] In this embodiment, the second filtering module 304 includes a second filtering transistor T8, the gate of the second filtering transistor T8 is connected to the first signal output terminal Nout of the N-2th stage GOA unit 310, the source of the second filtering transistor T8 is connected to the fifth node W, and the drain of the second filtering transistor T8 is connected to the second node Q.

[0071] In this embodiment, the first inverting module 305 includes a first inverting transistor T3 and a second inverting transistor T1, and the second inverting transistor T1 is a dual-gate transistor; the gate of the first inverting transistor T3 and the two gates of the second inverting transistor T1 are connected to the first node K, the source of the first inverting transistor T3 is connected to the third high potential line Pvgh2, the drain of the first inverting transistor T3 and the source of the second inverting transistor T1 are connected to the third node P, and the drain of the second inverting transistor T1 is connected to the second low potential line Pvgl.

[0072] In this embodiment, the feedback module 306 includes a first feedback transistor T4 and a second feedback transistor T5; wherein, the gate of the first feedback transistor T4 is connected to the first clock signal line CK, the source of the first feedback transistor T4 is connected to the first node K, the drain of the first feedback transistor T4 is connected to the source of the second feedback transistor T5, the gate of the second feedback transistor T5 is connected to the third node P, and the drain of the second feedback transistor T5 is connected to the second high potential line Pvgh1.

[0073] In this embodiment, the voltage regulation module 307 includes a regulation transistor T14, which is a dual-gate transistor; the two gates of the regulation transistor T14 are connected to the third node P, the source of the regulation transistor T14 is connected to the first node K, and the drain of the regulation transistor T14 is connected to the first low potential line Nvgl1.

[0074] In this embodiment, the first output module 20 includes a first output transistor T10 and a second output transistor T9, and the second output transistor T9 is a dual-gate transistor; the first gate T10G of the first output transistor T10 and the second gate T9G of the second output transistor T9 are connected to the first node K of the signal generating module 10, the first source T10S of the first output transistor T10 is connected to the first high potential line Nvgh, the first drain T10D of the first output transistor T10 and the second source T9S of the second output transistor T9 are connected to the first signal output terminal Nout, and the second drain T9D of the second output transistor T9 is connected to the first low potential line Nvgl1.

[0075] In this embodiment, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7; the third gate T6G of the third output transistor T6 is connected to the second node Q of the signal generating module 10, the third source T6S of the third output transistor T6 is connected to the first clock signal line CK, the third drain T6D of the third output transistor T6 and the fourth source T7S of the fourth output transistor T7 are connected to the second signal output terminal Pout, the fourth gate T7G of the fourth output transistor T7 is connected to the third node P of the signal generating module 10, and the fourth drain T7D of the fourth output transistor T7 is connected to the second high potential line Pvgh1.

[0076] In this embodiment, the first-stage pass transistor T13, the second inverting transistor T1, the first output transistor T10, and the regulating transistor T14 are N-type transistors, and the second-stage pass transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverting transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are P-type transistors.

[0077] In the gate drive circuit 300 provided in this embodiment, under the control of the third node P, the voltage regulation module 307 can stabilize or reduce the gate potential of the first output transistor T10 through the first low potential line Nvgl1, so that the first output transistor T10 is stabilized or better in the cut-off state to reduce leakage current, and the potential of the first gate drive signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0078] In this embodiment, the voltage regulating module 307 is used to stabilize or reduce the low potential of the first node K. Alternatively, in another embodiment, the voltage regulating module 307 is further used to stabilize or reduce the gate potential of the first output transistor T10 during the positive pulse of the first gate driving signal.

[0079] It should be noted that the regulating transistor T14 can stabilize or reduce the gate potential of the first output transistor T10 during the positive pulse of the first gate drive signal, so that the first output transistor T10 is stable or better in the cut-off state to reduce leakage current, and thus can maintain the potential of the first gate drive signal at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0080] In this embodiment, the internal node is the third node P, the second low potential line Pvgl and the first low potential line Nvgl1 are low potential lines with the same potential, and the channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10.

[0081] It should be noted that in this embodiment, the first output transistor T10 and the regulating transistor T14 can share the same low-potential line, which can reduce the number of wiring required for the gate drive circuit 300. The regulating transistor T14 has the same channel type as the first output transistor T10. When the first output transistor T10 is in the off state, the regulating transistor T14 can be turned on to further reduce the gate potential of the first output transistor T10.

[0082] In one embodiment, referring to FIG. 5 , the internal node may be a third node P, the channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10, the first low-potential line Nvgl1 transmits a first low-potential signal, and the third low-potential line Nvgl2 transmits a second low-potential signal, where the potential of the second low-potential signal is lower than the potential of the first low-potential signal.

[0083] It should be noted that the channel type of the regulating transistor T14 is the same as that of the first output transistor T10. When the first output transistor T10 is in the off state, the regulating transistor T14 can transmit the second low-potential signal to the gate of the first output transistor T10, thereby further reducing the gate potential of the first output transistor T10 and thus reducing the leakage current of the first output transistor T10. In this way, the stability of the low potential of the second node QK and the low potential of the intermediate node W can be improved.

[0084] In one embodiment, the difference between the potential of the first low-potential signal and the potential of the second low-potential signal is greater than or equal to 2V.

[0085] It should be noted that this embodiment can not only reduce the leakage current of the first output transistor T10 , but also adjust the threshold voltage of the first output transistor T10 to shift toward the positive direction, thereby increasing the threshold voltage range of the first output transistor T10 .

[0086] The following describes the film layers of the display panel 100 of the present application with reference to the structure of FIG. 3 .

[0087] Referring to FIG. 6 , the display area AA and non-display area NA of the display panel 100 may include a base substrate 110 and an array drive layer 120 disposed on the base substrate 110. Within the display area AA, the display panel 100 may further include a pixel definition layer disposed on the array drive layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer, and an encapsulation layer disposed on the pixel definition layer. The following primarily describes the film layer structure within the non-display area NA.

[0088] In this embodiment, the base substrate 110 supports various layers provided on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate can be used.

[0089] In this embodiment, the base substrate 110 is used to support the various film layers provided thereon. The base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0090] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0091] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material on a supporting substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the same material as the first flexible substrate 111 and curing the material. The second flexible substrate 113 is formed by the same method as the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 can be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby eliminating such defects.

[0092] Please refer to Figure 6. The array drive layer 120 may include multiple thin film transistors. The thin film transistors may be of etch barrier type, back channel etch type, or divided into bottom gate thin film transistors, top gate thin film transistors, etc. according to the position of the gate electrode and the active layer, or divided into N-type thin film transistors and P-type thin film transistors according to the performance of the thin film transistors. Among them, the thin film transistor in Figure 6 does not represent the structural diagram of any transistor in Figure 2, but is only a schematic diagram of the various film layers of the display panel 100 of the present application.

[0093] 6 , the array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, and a third gate insulating layer 125 disposed on the second gate layer 127. 8. A second active layer 129 arranged on the third gate insulation layer 128, a fourth gate insulation layer 130 arranged on the second active layer 129, a third gate layer 131 arranged on the fourth gate insulation layer 130, a first interlayer insulation layer 132 arranged on the third gate layer 131, a first source-drain layer 133 arranged on the first interlayer insulation layer 132, a second interlayer insulation layer 134 arranged on the first source-drain layer 133, a second source-drain layer 135 arranged on the second interlayer insulation layer 134, and a planarization layer 136 arranged on the second source-drain layer 135.

[0094] 6 , a light shielding layer 121 is provided on the second barrier layer 114 . The light shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The light shielding layer 121 may be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0095] Please refer to Figure 6. The buffer layer 122 is arranged on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen elements, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0096] Please refer to Figure 6. The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low-temperature polycrystalline silicon. For example, in the present application, the material of the first active layer 123 can be low-temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0097] Please refer to Figure 6. The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132, and the second interlayer insulating layer 134 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers. The material of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, and the second interlayer insulating layer 134 can be an inorganic substance composed of nitride oxide silicon or an organic material with flatness.

[0098] 6 , the first gate layer 125 , the second gate layer 127 and the third gate layer 131 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 , the second gate layer 127 and the third gate layer 131 may be copper, molybdenum or molybdenum-titanium alloy.

[0099] 6 , the first source-drain layer 133 is disposed on the first interlayer insulating layer 132 , and the second source-drain layer 135 is disposed on the second interlayer insulating layer 134 . The materials of the first source-drain layer 133 and the second source-drain layer 135 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0100] 6 , the planarization layer 136 is laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120 . The material of the planarization layer 136 can be an inorganic material composed of nitride oxide and silicon, or an organic material with flatness.

[0101] Please refer to FIG. 7 , which is a film diagram of the first gate layer 125 in the display panel 100 of the present application.

[0102] In this embodiment, the first gate layer 125 may include a second gate T9G and a third gate T6G; in the second direction Y, the length of the second gate T9G is greater than that of the third gate T6G, and the area of ​​the second gate T9G is greater than that of the third gate T6G.

[0103] In this embodiment, since the second output transistor T9 is used to output the first gate drive signal and the third output transistor T6 is used to output the second gate drive signal, and since the load of the first gate drive signal is greater than the load of the second gate drive signal, in order to increase the output load of the first output module 20, this application makes the area of ​​the second gate T9G greater than the area of ​​the third gate T6G.

[0104] Please refer to Figure 7. The second gate T9G may include a second main gate T9Ga and a plurality of second branch gates T9Gb arranged at intervals. The second main gate T9Ga extends along the first direction X, and the second branch gates T9Gb extend along the second direction Y. The plurality of second branch gates T9Gb are electrically connected to the second main gate T9Ga at one end facing the signal generating module 10. For example, the second gate T9G may include one second main gate T9Ga and four second branch gates T9Gb.

[0105] Referring to Figure 7, the third gate T6G may include a third trunk gate T6Ga and a plurality of third branch gates T6Gb arranged at intervals, the third trunk gate T6Ga extends along the first direction X, the third branch gates T6Gb extend along the second direction Y, and the plurality of third branch gates T6Gb are electrically connected to the third trunk gate T6Ga at one end facing the signal generating module 10; for example, the third gate T6G includes one third trunk gate T6Ga and three third branch gates T6Gb.

[0106] In this embodiment, the length and number of the strip branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the second gate T9G and the third gate T6G, the present application sets the second gate T9G and the third gate T6G as a plurality of separately arranged strip branch gates, each strip branch gate bears the load of the corresponding transistor, the strip branch electrode corresponds to the channel of the active part of the corresponding transistor, and the space between two adjacent strip branch gates corresponds to the source and drain of the upper layer. The composite electric field formed by the plurality of separately arranged strip branch gates can improve the driving capability of the transistor.

[0107] In this embodiment, in the first direction X, a distance between two adjacent second branch gates T9Gb and a distance between two adjacent third branch gates T6Gb may be equal.

[0108] 7 , the first gate layer 125 further includes a fourth gate T7G. The fourth gate T7G extends along the second direction Y. The fourth gate T7G and a plurality of third branch gates T6Gb in the third gate T6G are parallel and spaced apart.

[0109] In this embodiment, since the third output transistor T6 is connected to the first clock signal line CK, the load it needs to bear is relatively large. Therefore, the present application provides the third gate T6G with three strip-shaped branch gates, while the fourth gate T7G is not connected to the corresponding clock signal line. The load that the fourth output transistor T7 needs to bear is relatively small, so the fourth gate T7G is only provided with one strip-shaped branch gate.

[0110] In this embodiment, in the first direction X, the spacing between the fourth gate T7G and the adjacent third branch gate T6Gb may be equal to the spacing between two adjacent third branch gates T6Gb; that is, the spacing between two adjacent second branch gates T9Gb, the spacing between two adjacent third branch gates T6Gb, and the spacing between the fourth gate T7G and the adjacent third branch gate T6Gb are all equal, that is, the spacing between the strip-shaped branch electrodes is equal, which reduces the difficulty of patterning.

[0111] Referring to FIG. 7 , the first gate layer 125 further includes a first plate C1a. Multiple third branch gates T6Gb are connected to the first plate C1a at ends distal from the signal generating module 10. For example, the first plate C1a is connected to three third branch gates T6Gb. The three third branch gates T6Gb transmit voltage signals to different locations on the first plate C1a, allowing any region of the first plate C1a to simultaneously receive voltage signals transmitted by the three third branch gates T6Gb.

[0112] Referring to Figure 7 , the width of the first plate C1a is greater than the width of the third main gate T6Ga in the second direction Y. Since the capacitance of the storage capacitor is positively correlated with the facing surface of the plate in the storage capacitor, the present application can, within a limited space, increase the width of the first plate C1a relative to the width of the third main gate T6Ga. This increases the area of ​​the first plate C1a, thereby increasing the facing area between the two plates and thereby increasing the capacitance of the first storage capacitor C1.

[0113] 7 , the first gate layer 125 further includes a gate T2G of the pull-up transistor T2, a gate T3G of the first inverting transistor T3, a gate T4G of the first feedback transistor T4, a gate T5G of the second feedback transistor T5, a gate T8G of the second filter transistor T8, a gate T11G of the first filter transistor T11, a gate T12G of the second stage pass transistor T12, and a third plate C2a of the second storage capacitor C2.

[0114] In this embodiment, the gate T2G of the pull-up transistor T2, the gate T3G of the first inverter transistor T3, the gate T11G of the first filter transistor T11, the gate T12G of the second-stage pass transistor T12, and the third plate C2a of the second storage capacitor C2 extend along the second direction Y. The gate T12G of the second-stage pass transistor T12 is disposed near the first output module 20. The gate T3G of the first inverter transistor T3, the gate T2G of the pull-up transistor T2, and the gate T11G of the first filter transistor T11 are sequentially arranged along the first direction X in a central region of the signal generation module 10. The gate T12G of the second-stage pass transistor T12 and the third plate C2a of the second storage capacitor C2 are aligned on the same straight line, and the gate T11G of the first filter transistor T11 is directly connected to the third plate C2a of the second storage capacitor C2.

[0115] In this embodiment, the gate T4G of the first feedback transistor T4, the gate T5G of the second feedback transistor T5, and the gate T8G of the second filtering transistor T8 extend along the first direction X and are disposed proximate to the second output module 30. The gate T4G of the first feedback transistor T4 and the gate T5G of the second feedback transistor T5 are disposed in parallel along the second direction Y, and the gate T4G of the first feedback transistor T4 is disposed away from the fourth gate T7G. The gate T5G of the second feedback transistor T5 is disposed proximate to the fourth gate T7G. The gate T5G of the second feedback transistor T5 and the gate T8G of the second filtering transistor T8 are arranged along the first direction X, and the gate T5G of the second feedback transistor T5 is directly connected to the extension of the fourth gate T7G of the fourth output transistor T7 in the second direction Y.

[0116] Please refer to FIG. 8 , which is a film layer diagram of the second gate layer 127 in the display panel 100 of the present application.

[0117] The second gate layer 127 may include a first gate T10G, which includes two first main gates T10Ga and a plurality of first branch gates T10Gb disposed between the two first main gates T10Ga. The two first main gates T10Ga are disposed opposite and parallel to each other. The two first main gates T10Ga extend along a first direction X, and the plurality of first branch gates T10Gb extend along a second direction Y. The ends of the plurality of first branch gates T10Gb are respectively connected to the two first main gates T10Ga. For example, the first gate T10G includes two first main gates T10Ga and four first branch gates T10Gb. The ends of the four first branch gates T10Gb are respectively connected to the two first main gates T10Ga.

[0118] In this embodiment, the length of the first branch gate T10Gb is greater than the length of the second branch gate T9Gb in the second direction Y. Since the first output transistor T10 is a metal oxide semiconductor transistor and has low mobility, in order to improve the driving capability of the first output transistor T10, the present application increases the length of the first branch gate T10Gb, which is equivalent to increasing the width of the channel in the first active portion T10A, thereby improving the electron mobility in the first output transistor T10 and ensuring the driving capability of the first output transistor T10.

[0119] Referring to FIG8 , the second gate layer 127 further includes a second plate C1b of the first storage capacitor C1. The first plate C1a and the second plate C1b are disposed opposite and parallel to each other, with the orthogonal projection of the first plate C1a on the second plate C1b located within the second plate C1b. Since the capacitance of a storage capacitor is positively correlated with the facing surface of the plates in the storage capacitor, the present application can, within a limited space, ensure that the orthogonal projection of the first plate C1a on the second plate C1b is located within the second plate C1b, i.e., the area of ​​the first plate C1a is less than or equal to the area of ​​the second plate C1b. In this embodiment, the area of ​​the first plate C1a is smaller than the area of ​​the second plate C1b, i.e., the area of ​​the second plate C1b is increased as much as possible to increase the facing area between the two plates, thereby increasing the capacitance of the first storage capacitor C1 and improving the output stability of the first signal output terminal Nout.

[0120] In this embodiment, the second gate layer 127 also includes a first gate T1G of the second inverting transistor T1, a first gate T131G of the first-stage pass transistor T13, a first gate T14G of the regulating transistor T14, and a fourth plate C2b of the second storage capacitor C2; the first gate T1G of the second inverting transistor T1, the first gate T13G of the first-stage pass transistor T13, and the fourth plate C2b of the second storage capacitor C2 extend along the second direction Y, and the first gate T14G of the regulating transistor T14 extends along the first direction X.

[0121] Please refer to FIG. 9 , which is a film diagram of the first gate layer 125 and the second gate layer 127 stacked in the display panel 100 of the present application.

[0122] In this embodiment, the orthographic projection of the third plate C2a on the fourth plate C2b is located within the fourth plate C2b, that is, the area of ​​the third plate C2a is less than or equal to the area of ​​the fourth plate C2b. In this embodiment, the area of ​​the third plate C2a is smaller than the area of ​​the fourth plate C2b, that is, the area of ​​the fourth plate C2b is increased as much as possible to increase the facing area between the two plates, increase the capacitance of the second storage capacitor C2, and improve the stability of the voltage at the fifth node W.

[0123] In this embodiment, the capacitance of the second storage capacitor C2 needs to be greater than 50F.

[0124] In this embodiment, the area of ​​the first plate C1a is greater than the area of ​​the third plate C2a, and the area of ​​the third plate C2b is greater than the area of ​​the fourth plate C2b. The ratio of the capacitance of the first storage capacitor C1 to the capacitance of the second storage capacitor C2 is greater than 2. Since the first plate C1a in the first storage capacitor C1 is connected to the third gate T6G of the third output transistor T6, the second plate C1b in the first storage capacitor C1 is connected to the third drain T6D of the third output transistor T6, and the third source T6S of the third output transistor T6 is connected to the first clock signal line CK, the output signal of the clock signal line at different times will flip, which will affect the stability of the output signal of the second signal output terminal Pout connected to the third drain T6D of the third output transistor T6. Therefore, the present application ensures the output stability of the first signal output terminal Nout by increasing the capacitance of the first storage capacitor C1.

[0125] In the structure of Figure 9, the gate T1G of the second inverting transistor T1 and the gate T3G of the first inverting transistor T3 are arranged adjacent to each other, and the gate T12G of the second-stage pass transistor T12 is arranged between the gate T13G of the first-stage pass transistor T13 and the first gate T10G, the gate T13G of the first-stage pass transistor T13 and the gate T12G of the second-stage pass transistor T12 are arranged adjacent to each other, the gate T14G of the regulating transistor T14 is arranged between the gate T2G of the pull-up transistor T2 and the first gate T10G, and the gate T13G of the first-stage pass transistor T13 is arranged on the side of the gate T12G of the second-stage pass transistor T12 away from the first gate T10G.

[0126] Please refer to FIG. 10 , which is a film layer diagram of the third gate layer 131 in the display panel 100 of the present application.

[0127] The array drive layer 120 further includes a third gate layer 131 disposed on a side of the second gate layer 127 away from the base substrate 110. The third gate layer 131 includes a fifth gate T10H. The fifth gate T10H includes two fifth main gates T10Ha and a plurality of fifth branch gates T10Hb disposed between the two fifth main gates T10Ha. The two fifth main gates T10Ha are disposed opposite and parallel to each other. The two fifth main gates T10Ha extend along a first direction X, and the plurality of fifth branch gates T10Hb extend along a second direction Y. The ends of the plurality of fifth branch gates T10Hb are respectively connected to the two first main gates T10Ga. For example, the fifth gate T10H may include two fifth main gates T10Ha and four fifth branch gates T10Hb. The ends of the four fifth branch gates T10Hb are connected to the two fifth main gates T10Ha.

[0128] In this embodiment, the first output transistor T10 is a dual-gate transistor. The first gate T10G and the fifth gate T10H of the first output transistor T10 are arranged on the upper and lower sides of the first active portion T10A. The first gate T10G and the fifth gate T10H are electrically connected to simultaneously drive the migration of carriers in the first active portion T10A, thereby improving the conduction rate of the first output transistor T10.

[0129] In this embodiment, in the second direction Y, the length of the first branch gate T10Gb is equal to the length of the fifth branch gate T10Hb, and both the first branch gate T10Gb and the fifth branch gate T10Hb bear the output load of the first output transistor T10; at the same time, since the fifth branch gate T10Hb is required to serve as a shielding layer to perform ion doping on the first active portion T10A, the length of the channel in the first active portion T10A in the first direction X is equal to the length of the fifth branch gate T10Hb in the fifth gate T10H in the first direction X, and In order to ensure that external light enters the first active portion T10A, the present application makes the orthographic projection of the fifth branch gate T10Hb on the corresponding first branch gate T10Gb located within the corresponding first branch gate T10Gb, that is, the area of ​​the first branch gate T10Gb is greater than or equal to the area of ​​the fifth branch gate T10Hb. In this embodiment, the area of ​​the first branch gate T10Gb can be greater than the area of ​​the fifth branch gate T10Hb, or the distance between two adjacent first branch gates T10Gb can be less than the distance between two adjacent fifth branch gates T10Hb.

[0130] In this embodiment, the distance between two adjacent first branch gates T10Gb may be smaller than the distance between two adjacent second branch gates T9Gb in the second output transistor T9, and the distance between two adjacent second branch gates T9Gb may be smaller than the distance between two adjacent fifth branch gates T10Hb.

[0131] Please refer to FIG. 11 , which is a diagram showing the superimposed film layers of the second gate layer 127 and the third gate layer 131 in the display panel 100 of the present application.

[0132] Since the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are all metal oxide semiconductor transistors, to improve the driving capabilities of the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14, the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 can all be dual-gate transistors. That is, the third gate layer 131 can further include a second gate T1H of the second inverter transistor T1, a second gate T13H of the first-stage pass transistor T13, and a second gate T14H of the regulating transistor T14. The second gate T1H of the second inverter transistor T1 and the second gate T13H of the first-stage pass transistor T13 extend along the second direction Y, and the second gate T14H of the regulating transistor T14 extends along the first direction X.

[0133] In this embodiment, to prevent external light from entering the active portions of the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14, the second gate T1H of the second inverter transistor T1 is orthogonally projected onto and within the corresponding first gate T1G, the second gate T13H of the first-stage pass transistor T13 is orthogonally projected onto and within the corresponding first gate T13G, and the second gate T14H of the regulating transistor T14 is orthogonally projected onto and within the corresponding first gate T14G. The area of ​​the second gate T1H of the second inverter transistor T1 is smaller than the area of ​​the corresponding first gate T1G, the area of ​​the second gate T13H of the first-stage pass transistor T13 is smaller than the area of ​​the corresponding first gate T13G, and the area of ​​the second gate T14H of the regulating transistor T14 is smaller than the area of ​​the corresponding first gate T14G.

[0134] Please refer to Figures 12 and 13. Figure 12 is a film layer diagram of the first active layer 123 in the display panel 100 of the present application. Figure 13 is a film layer diagram of the first gate layer 125, the second gate layer 127, the third gate layer 131, the first active layer 123 and the second active layer 129 superimposed in the display panel 100 of the present application.

[0135] The array driving layer 120 also includes a first active layer 123 arranged between the first gate layer 125 and the base substrate 110, and the first active layer 123 includes a low-temperature polycrystalline silicon semiconductor; the first active layer 123 includes a second active portion T9A and a third active portion T6A, the second active portion T9A and a plurality of second branch gates T9Gb overlap, and the third active portion T6A and a plurality of third branch gates T6Gb overlap.

[0136] In this embodiment, the second output transistor T9 and the third output transistor T6 are top-gate transistors, the second gate T9G can serve as a shielding layer for the second active portion T9A to perform ion doping on the second active portion T9A, and the third gate T6G can serve as a shielding layer for the third active portion T6A to perform ion doping on the third active portion T6A; therefore, the portion of the active portion that overlaps with the corresponding branch gate is the channel portion, and the non-overlapping portion of the active portion is the source connection portion and the drain connection portion on both sides of the channel portion; for example, in the structure of Figure 14, the second active portion T9A overlaps with four second branch gates T9Gb, and the third active portion T6A overlaps with three third branch gates T6Gb. The second active portion T9A has four channel portions, and the third active portion T6A has three channel portions.

[0137] In this embodiment, since the second branch gate T9Gb and the third branch gate T6Gb are sufficiently long in the second direction Y, the dimensions of the second active portion T9A and the third active portion T6A in the second direction Y are increased as much as possible to increase the width of the channel in the active portion. However, when the low-temperature polysilicon semiconductor is too large in the second direction Y, static electricity will concentrate in the active portion, potentially damaging the active portion. Therefore, in this application, the second active portion T9A and the third active portion T6A may be configured as two separate sub-active portions.

[0138] 12 and 13 , the second active portion T9A may include two spaced-apart second sub-active portions T9Aa, and the third active portion T6A may include two spaced-apart third sub-active portions T6Aa, with the second sub-active portion T9Aa and the third sub-active portion T6Aa extending along the first direction X. The two spaced-apart second sub-active portions T9Aa and the two spaced-apart third sub-active portions T6Aa reduce the dimensions of the second active portion T9A and the third active portion T6Aa in the third direction, thereby avoiding the technical problem of static electricity concentration in the active portions.

[0139] In this embodiment, the width of the second sub-active portion T9Aa is greater than the width of the third sub-active portion T6Aa in the second direction Y. Since the output load of the second output transistor T9 is greater than the output load of the third output transistor T6, the present application increases the width of the second sub-active portion T9Aa to increase the second output load.

[0140] It should be noted that the width of the second sub-active portion T9Aa and the width of the third sub-active portion T6Aa are the width dimensions of the corresponding sub-active portions in the second direction Y.

[0141] 12 and 13 , the first active layer 123 further includes a fourth active portion T7A. The fourth active portion T7A includes two fourth sub-active portions T7Aa spaced apart from each other. The two fourth sub-active portions T7Aa overlap with the fourth gate electrode T7G. The fourth sub-active portion T7Aa is connected to the corresponding third sub-active portion T6Aa. For example, one fourth active portion T7A overlaps with one fourth gate electrode T7G, and the fourth active portion T7A has one channel.

[0142] In this embodiment, in the second direction Y, the width of the fourth sub-active portion T7Aa may be equal to the width of the third sub-active portion T6Aa.

[0143] In this embodiment, in order to simplify the process, the pattern of the third active part T6A can be connected to the pattern of the fourth active part T7A, which increases the pattern area of ​​the active part in the second output module 30, reduces the film forming accuracy of the active part in this area, and simplifies the film forming process.

[0144] In the structure of Figure 13, the first active layer 123 also includes an active portion T2A of the pull-up transistor T2, an active portion T3A of the first inverting transistor T3, an active portion T4A of the first feedback transistor T4, an active portion T5A of the second feedback transistor T5, an active portion T8A of the second filter transistor T8, an active portion T11A of the first filter transistor T11, and an active portion T12A of the second-stage pass transistor T12. The active portions of the pull-up transistor T2, the first inverting transistor T3, the first feedback transistor T4, the second feedback transistor T5, the second filter transistor T8, the first filter transistor T11, and the second-stage pass transistor T12 are arranged vertically to the gates of the corresponding transistors and have overlapping portions with the gates of the corresponding transistors. The overlapping portions are the channel portions of the corresponding active portions.

[0145] Please refer to FIG. 14 , which is a film diagram of the second active layer 129 in the display panel 100 of the present application.

[0146] In this embodiment, the array driving layer 120 further includes a second active layer 129 disposed between the third gate layer 131 and the second gate layer 127. The second active layer 129 includes a metal oxide semiconductor. The second active layer 129 includes a first active portion T10A. The first active portion T10A includes two first sub-active portions T10Aa spaced apart from each other. The first sub-active portion T10Aa extends along the first direction X. The two first sub-active portions T10Aa overlap with a plurality of first branch gates T10Gb.

[0147] In this embodiment, since the first output transistor T10 is a dual-gate transistor, the first gate T10G and the fifth gate T10H of the first output transistor T10 can both serve as switches of the first output transistor T10. At the same time, the fifth gate T10H can serve as a shielding layer for the first active portion T10A to perform ion doping on the first active portion T10A. Therefore, the portion of the first active portion T10A that overlaps with the multiple first branch gates T10Gb is the channel portion of the first active portion T10A, and the portion of the first active portion T10A that does not overlap with the multiple first branch gates T10Gb is the source connection portion and the drain connection portion on both sides of the channel portion. For example, in the structures of Figures 13 and 14, the first active portion T10A overlaps with four first branch gates T10Gb, and the first active portion T10A has four channel portions.

[0148] In this embodiment, since the first output transistor T10 is a metal oxide semiconductor transistor, this type of transistor has the advantage of low leakage current, but its mobility is relatively small. Therefore, in order to improve the mobility of the first output transistor T10, it is necessary to increase the width of the channel portion in the first active portion T10A, which is equivalent to the width of the first sub-active portion T10Aa in the second direction Y. Therefore, in the second direction Y, the width of the first sub-active portion T10Aa is greater than the width of the second sub-active portion T9Aa.

[0149] In addition, when the width of the first active portion T10A in the second direction Y is too large, static electricity concentration will occur in the first active portion T10A, which may cause the first active portion T10A to be damaged by static electricity. Therefore, the present application can set the first active portion T10A into two separately set first sub-active portions T10Aa.

[0150] Referring to Figures 13 and 14, the second active layer 129 further includes an active portion T1A of the second inverting transistor T1, an active portion T13A of the first-stage pass transistor T13, and an active portion T14A of the regulating transistor T14. The active portions of the second inverting transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are perpendicularly arranged to the gates of the corresponding transistors and have overlapping portions with the gates of the corresponding transistors. The overlapping portions are channel portions of the corresponding active portions. At the same time, in order to improve the mobility of the metal oxide semiconductor transistors, in the signal generating module 10, the channel widths of the active portions of the second inverting transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are all greater than the channel widths of the active portions of the pull-up transistor T2, the first inverting transistor T3, the first feedback transistor T4, the second feedback transistor T5, the second filter transistor T8, the first filter transistor T11, and the second-stage pass transistor T12.

[0151] In the structures of Figures 13 and 14, since the first output transistor T10 is a metal oxide semiconductor transistor, and the second output transistor T9 and the third output transistor T6 are low-temperature polysilicon semiconductor transistors, and since the mobility of metal oxide semiconductor transistors is relatively low, in order to improve the mobility of the first output transistor T10, the first gate T10G and the fifth gate T10H of the first output transistor T10 are provided with two main gates to connect the two ends of the multiple branch gates together, so that the electric field formed by the newly added main gates further drives the migration of electrons in the active portion.

[0152] In this embodiment, the spacing between the first trunk gate T10Ga and the fifth trunk gate T10Ha and the first active portion T10A in the second direction Y is a first spacing, the spacing between the end of the second branch gate T9Gb away from the second trunk gate T9Ga and the second active portion T9A in the second direction Y is a second spacing, and the spacing between the end of the third branch gate T6Gb away from the third trunk gate T6Ga and the third active portion T6A in the second direction Y is a third spacing. The first spacing is greater than the second spacing, and the second spacing is greater than or equal to the third spacing.

[0153] In this embodiment, the first spacing may be greater than 5 micrometers, the second spacing may be greater than 2.5 micrometers, and the third spacing may be greater than 2.5 micrometers.

[0154] Please refer to FIG. 15 , which is a film diagram of the first source-drain electrode layer 133 in the display panel 100 of the present application.

[0155] In this embodiment, the array driving layer 120 further includes a first source-drain layer 133 disposed on a side of the third gate layer 131 away from the second gate layer 127 . The first source-drain layer 133 includes a first source T10S, a first drain T10D, a second source T9S, and a second drain T9D.

[0156] In this embodiment, the first source T10S includes a first main source T10Sa and a plurality of first branch sources T10Sb spaced apart and arranged in parallel. The first drain T10D includes a plurality of first branch drains T10Db. The first main source T10Sa extends along a first direction X, the first branch sources T10Sb extend along a second direction Y, the plurality of first branch sources T10Sb are connected to the first main source T10Sa on a side away from the signal generating module 10, the plurality of first branch drains T10Db extend along the second direction Y, and the plurality of first branch drains T10Db are arranged between the plurality of first branch sources T10Sb.

[0157] In this embodiment, in the top view direction of the display panel 100, two first branch source electrodes T10Sb on both sides of the plurality of first branch source electrodes T10Sb are arranged on both sides of the first gate electrode T10G, and at least one first branch source electrode T10Sb on the inner side of the plurality of first branch source electrodes T10Sb and the plurality of first branch drain electrodes T10Db are arranged between the plurality of first branch gate electrodes T10Gb; for example, in the structure of FIG15 , the first source electrode T10S includes one first main source electrode T10Sa and three first branch source electrodes T10Sb, and the first drain electrode T10Sb includes one first main source electrode T10Sa and three first branch source electrodes T10Sb. 0D includes two first branch drains T10Db, three first branch sources T10Sb and two first branch drains T10Db arranged alternately in the first direction X, that is, the two first branch drains T10Db can be arranged between two adjacent first branch sources T10Sb; at the same time, the outermost two first branch sources T10Sb of the three first branch sources T10Sb are arranged on both sides of the first gate T10G, and one first branch source T10Sb and the two first branch drains T10Db are arranged between multiple first branch gates T10Gb.

[0158] In this embodiment, the second drain T9D includes a second main drain T9Da and a plurality of second branch drains T9Db spaced apart and arranged in parallel. The second source T9S includes a plurality of second branch sources T9Sb. The second main drain T9Da extends along the first direction X, the second branch drains T9Db extend along the second direction Y, the plurality of second branch drains T9Db are connected to the second main drain T9Da near the signal generating module 10, the plurality of second branch sources T9Sb extend along the second direction Y, and the plurality of second branch sources T9Sb are arranged between the plurality of second branch drains T9Db. The first main source T10Sa is connected to the second main drain T9Da.

[0159] In this embodiment, in the top view direction of the display panel 100, two second branch drains T9Db on both sides of the plurality of second branch drains T9Db are arranged on both sides of the second gate T9G, and at least one second branch drain T9Db on the inner side of the plurality of second branch drains T9Db and the plurality of second branch sources T9Sb are arranged between the plurality of second branch gates T9Gb; for example, in the structure of FIG15 , the second source T9S includes two second branch sources T9Sb, and the second drain T9D includes one second main drain T9Gb. 9Da and three second branch drains T9Db, two second branch sources T9Sb and three second branch drains T9Db are arranged at intervals in the first direction X, that is, two second branch sources T9Sb can be arranged between two adjacent second branch drains T9Db; at the same time, the two outermost second branch drains T9Db among the three second branch drains T9Db are arranged on both sides of the second gate T9G, and one second branch drain T9Db and two second branch sources T9Sb are arranged between multiple second branch gates T9Gb.

[0160] In this embodiment, the first trunk source T10Sa and the second trunk drain T9Da both overlap with the first trunk gate T10Ga on the side away from the signal generating module 10 , that is, the first trunk source T10Sa and the second trunk drain T9Da can share a trunk electrode.

[0161] In this embodiment, since the mobility of the first output transistor T10 is relatively low, in order to improve the driving capability of the first output transistor T10, the present application increases the width of the channel in the first active portion T10A to improve the electron mobility in the first output transistor T10. In order to enable the data signal to be transmitted from the source of the transistor to the drain of the transistor as quickly as possible, the present application provides spaced-apart first branch source electrodes T10Sb and first branch drain electrodes T10Db on both sides of the plurality of first branch gate electrodes T10Gb. At the same time, the first branch source electrodes T10Sb are electrically connected to the source connection portion of the first sub-active portion T10Aa through a plurality of source contact holes, and the first branch drain electrodes T10Db are electrically connected to the drain connection portion of the first sub-active portion T10Aa through a plurality of drain contact holes. Therefore, in the second direction Y, the length of the first branch source electrodes T10Sb is greater than the length of the second branch drain electrodes T9Db.

[0162] Please refer to FIG. 16 , which is a diagram illustrating the superimposed film layers of the first active layer 123 , the second active layer 129 , and the first source and drain layer 133 of the display panel 100 of the present application.

[0163] In this embodiment, each first branch source T10Sb is electrically connected to the source connection portion in the first sub-active portion T10Aa through four first source T10S contact holes, and each first branch drain T10Db is electrically connected to the drain connection portion in the first sub-active portion T10Aa through four first drain T10D contact holes; each second branch drain T9Db is electrically connected to the drain connection portion in the first sub-active portion T10Aa through three second drain T9D contact holes, and each first branch source T10Sb is electrically connected to the source connection portion in the first sub-active portion T10Aa through three second source T9S contact holes.

[0164] In this embodiment, the first source T10S contact hole and the first drain T10D contact hole penetrate the first interinsulating layer 132 and the fourth gate insulating layer 130, and the second source T9S contact hole and the second drain T9D contact hole penetrate the first interinsulating layer 132, the fourth gate insulating layer 130, the third gate insulating layer 128, the second gate insulating layer 126, and the first gate insulating layer 124.

[0165] Since the first gate T10G in the first output transistor T10 is electrically connected to the second gate T9G of the second output transistor T9, but the first gate T10G is on the first gate layer 125 and the second gate T9G is on the second gate layer 127, in order to electrically connect the first gate T10G and the second gate T9G, a certain distance needs to be left between the end of the second branch source T9Sb close to the signal generating module 10 and the second trunk drain T9Da to set a first connecting segment 151 connecting the first gate T10G and the second gate T9G.

[0166] 15 , the distance between the first branch drain T10Db away from the signal generating module 10 and the first main source T10Sa is smaller than the distance between the second branch source T9Sb close to the signal generating module 10 and the second main drain T9Da.

[0167] In this embodiment, referring to Figure 15, the first source-drain layer 133 further includes a first connecting segment 151, which is arranged between an end of the second branch source T9Sb close to the signal generating module 10 and the second main drain T9Da; at the same time, referring to Figure 10, the third gate layer 131 further includes a first protrusion 141 arranged on the fifth main gate T10Ha on the side away from the signal generating module 10, the first protrusion 141 is connected to the fifth main gate T10Ha, and the first protrusion 141 extends toward the side away from the signal generating module 10.

[0168] In this embodiment, the first end of the first connecting segment 151 overlaps with the first protrusion 141 and the second main gate T9Ga, the second end of the first connecting segment 151 overlaps with the second main gate T9Ga, and the first end of the first connecting segment 151 is electrically connected to the first protrusion 141 through the first via HL1, and the second end of the first connecting segment 151 is electrically connected to the second main gate T9Ga through the second via HL2; that is, the first end of the first connecting segment 151 is electrically connected to the fifth gate T10H, and the second end of the first connecting segment 151 is electrically connected to the second gate T9G. Since the first gate T10G is electrically connected to the fifth gate T10H, the second gate T9G is electrically connected to the first gate T10G through the fifth gate T10H.

[0169] In the structures of Figures 10 and 15, the third gate layer 131 includes two first protrusions 141, and the first source and drain layer 133 may include two first connecting segments 151. In order to avoid disconnection of the second gate T9G and the fifth gate T10H, the two first protrusions 141 are electrically connected to the corresponding first connecting segments 151.

[0170] In this embodiment, the first via hole HL1 passes through the first inter-insulating layer 132 , and the second via hole HL2 passes through the first inter-insulating layer 132 , the fourth gate insulating layer 130 , the third gate insulating layer 128 , and the second gate insulating layer 126 .

[0171] Since the first gate T10G and the fifth gate T10H in the first output transistor T10 are electrically connected, but the first gate T10G is on the first gate layer 125 and the fifth gate T10H is on the third gate layer 131, in order to electrically connect the first gate T10G and the fifth gate T10H, the present application can provide a connecting segment connecting the first gate T10G and the fifth gate T10H on the side of the first branch drain T10Db close to the signal generating module 10.

[0172] Please refer to Figure 15, the first source and drain layer 133 also includes a second connecting segment 152, which is arranged on the side of the first branch drain T10Db close to the signal generating module 10; please refer to Figures 8 and 9, the second gate layer 127 also includes a second protrusion 142 arranged on the side close to the signal generating module 10, the second protrusion 142 is connected to the first trunk gate T10Ga, and the second protrusion 142 extends toward the side close to the signal generating module 10; please refer to Figure 10, the third gate layer 131 may also include a third protrusion 143 arranged on the side close to the signal generating module 10, the third protrusion 143 is connected to the fifth trunk gate T10Ha, and the third protrusion 143 extends toward the side close to the signal generating module 10.

[0173] In this embodiment, the first end of the second connecting segment 152 overlaps with the second protrusion 142, the second end of the second connecting segment 152 overlaps with the third protrusion 143, and the first end of the second connecting segment 152 is electrically connected to the third protrusion 143 through the third via HL3, and the second end of the second connecting segment 152 is electrically connected to the second protrusion 142 through the fourth via HL4; that is, the first end of the second connecting segment 152 is electrically connected to the fifth gate T10H, and the second end of the second connecting segment 152 is electrically connected to the first gate T10G. The arrangement of the first connecting segment 151 and the second connecting segment 152 electrically connects the first gate T10G, the second gate T9G, and the fifth gate T10H.

[0174] In the display panel 100 of the present application, multiple first branch sources T10Sb include a first bottom electrode T10Sc close to the next-level GOA unit 310, and multiple second branch drains T9Db include a second bottom electrode T9Dc close to the next-level GOA unit 310. The first bottom electrode T10Sc and the second bottom electrode T9Dc are both electrically connected to the first signal output terminal Nout.

[0175] Please refer to Figure 15. The first source T10S includes three first branch sources T10Sb, and the first branch source T10Sb among the three first branch sources T10Sb close to the next-level GOA unit 310 is the first bottom electrode T10Sc. The second drain T9D includes three second branch drains T9Db, and the second branch drain T9Db among the three second branch drains T9Db close to the next-level GOA unit 310 is the second bottom electrode T9Dc. The first bottom electrode T10Sc and the second bottom electrode T9Dc are electrically connected; secondly, the end of the second bottom electrode T9Dc away from the signal generating module 10 is electrically connected to the first signal output terminal Nout to transmit the first gate driving signal to the display unit 200.

[0176] 15 , the first source-drain layer 133 may further include a third source electrode T6S, a third drain electrode T6D, a fourth source electrode T7S, and a fourth drain electrode T7D.

[0177] In this embodiment, the third source T6S may include a third main source T6Sa and two third branch sources T6Sb arranged in parallel and spaced apart, the two third branch sources T6Sb are connected to the third main source T6Sa at one end close to the signal generating module 10, and the third drain T6D includes a third main drain T6Da and two third branch drains T6Db arranged in parallel and spaced apart, the two third branch drains T6Db are connected to the third main drain T6Da at one end close to the signal generating module 10, and the two third branch sources T6Sb and the two third branch drains T6Db are arranged alternately in the first direction X.

[0178] In this embodiment, the fourth source T7S and the fourth drain T7D extend along the second direction Y, the fourth drain T7D is arranged adjacent to the third branch drain T6Db, the fourth source T7S is arranged on a side of the fourth drain T7D away from the third branch drain T6Db, and the first end of the fourth source T7S is connected to the third main drain T6Da.

[0179] Please refer to Figure 15, the fourth source T7S also includes a second extension segment 162 extending along the second direction Y, part of the second extension segment 162 is located in the GOA unit 310 of the current level, and part of the second extension segment 162 is located in the GOA unit 310 of the next level; at the same time, please refer to Figure 7, the first gate layer 125 also includes an output wire 170 extending along the second direction Y, the output wire 170 is arranged on the side of the first bottom electrode T10Sc in the first source T10S away from the first branch drain T10Db, the second end of the fourth source T7S is electrically connected to the first end of the second extension segment 162, the second end of the second extension segment 162 is connected to the first end of the output wire 170 through the tenth via HL10, and the second end of the output wire 170 is connected to the second signal output terminal Pout.

[0180] In this embodiment, the tenth via hole HL10 passes through the first inter-insulating layer 132 , the fourth gate insulating layer 130 , the third gate insulating layer 128 , and the second gate insulating layer 126 . The second signal output terminal Pout is used to output a second gate driving signal.

[0181] Please refer to FIG. 17 , which is a diagram illustrating the stacked film layers of the first gate layer 125 , the second gate layer 127 , and the first source and drain layer 133 of the present application.

[0182] 8 and 17 , the second plate C1b of the first storage capacitor C1 and the third main drain electrode T6Da have an overlapping portion, and the second plate C1b is electrically connected to the third main drain electrode T6Da via a third via HL3. The third via HL3 penetrates the first interlayer insulating layer 132, the fourth gate insulating layer 130, and the third gate insulating layer 128.

[0183] 15 and 16 , the first source-drain layer 133 further includes a source T2S and a drain T2D of the pull-up transistor T2, a source T3S and a drain T3D of the first inverting transistor T3, a source T4S and a drain of the first feedback transistor T4, a source and a drain T5D of the second feedback transistor T5, a source T8S and a drain T8D of the second filter transistor T8, a source T11S and a drain T11D of the first filter transistor T11, a source T12S and a drain T12D of the second-stage pass transistor T12, a source T1S and a drain T1D of the second inverting transistor T1, a source T13S and a drain T13D of the first-stage pass transistor T13, and a source T14S and a drain T14D of the regulating transistor T14, and the sources and drains of the above transistors are all arranged on both sides of the corresponding active portions.

[0184] In this embodiment, the drain T3D of the first inverting transistor T3 and the source T1S of the second inverting transistor T1 extend along the second direction Y and are connected, and the drain T2D of the pull-up transistor T2, the source T11S of the first filtering transistor T11, the source T4S of the first feedback transistor T4, and the second connecting section 152 are connected to each other.

[0185] In this embodiment, referring to FIG. 15 , the first source-drain layer 133 further includes a start signal line STV, a first end of the start signal line STV being connected to the first bottom electrode T10Sc in the previous-level GOA unit 310, and a second end of the start signal line STV being electrically connected to the gate of the first-level pass transistor T13 and the gate of the second-level pass transistor T12 in this level.

[0186] Please refer to FIG. 18 , which is a film diagram of the second source-drain electrode layer 135 in the display panel 100 of the present application.

[0187] In this embodiment, the array driving layer 120 further includes a second source-drain layer 135 disposed on a side of the first source-drain layer 133 away from the base substrate 110. The second source-drain layer 135 includes a first high potential line Nvgh, which extends along the first direction X. The first high potential line Nvgh overlaps with the plurality of second branch source electrodes T9Sb and the plurality of second branch drain electrodes T9Db in each GOA unit 310, and the first high potential line Nvgh is electrically connected to the plurality of second branch source electrodes T9Sb in each GOA unit 310 through a fifth via HL5.

[0188] Please refer to Figure 19, which shows a film layer diagram of the first source-drain layer 133 and the second source-drain layer 135 in the display panel 100 of the present application. The first high potential line Nvgh is electrically connected to the two second branch source electrodes T9Sb in each stage of the GOA unit 310. The first high potential line Nvgh is electrically connected to the one second branch source electrode T9Sb via two fifth vias HL5, which penetrate the second interlayer insulating layer 134.

[0189] Please refer to Figures 18 and 19. The second source and drain layer 135 also includes a first low potential line Nvgl1. The first low potential line Nvgl1 and the first high potential line Nvgh are arranged opposite and parallel to each other. The first low potential line Nvgl1 overlaps with multiple first branch source electrodes T10Sb and multiple first branch drain electrodes T10Db in each GOA unit 310, and the first low potential line Nvgl1 is electrically connected to multiple first branch drain electrodes T10Db in each GOA unit 310 through the sixth via HL6. For example, the first low potential line Nvgl1 is electrically connected to two first branch drain electrodes T10Db in each level of GOA unit 310, and the first low potential line Nvgl1 is electrically connected to one first branch drain electrode T10Db through two sixth vias HL6, and the sixth via HL6 passes through the second interlayer insulating layer 134.

[0190] Please refer to FIG. 20 , which is a diagram illustrating the superimposed film layers of the first active layer 123 , the second active layer 129 , and the second source-drain electrode layer 135 in the display panel 100 of the present application.

[0191] In this embodiment, in order to avoid interference of the voltage of the first high potential line Nvgh on the voltage of the signal line in the display unit 200, the present application can overlap the first high potential line Nvgh with the second sub-active portion T9Aa on the side close to the signal generating module 10; at the same time, in order to leave enough space for arranging the reset signal line RST, the first low potential line Nvgl1 can overlap with the first sub-active portion T10Aa on the side away from the signal generating module 10.

[0192] Referring to Figures 18 to 20, the second source-drain layer 135 further includes a second high potential line Pvgh1, which is arranged opposite and parallel to the first high potential line Nvgh. The second high potential line Pvgh1 overlaps with the third sub-active portion T6Aa and the fourth sub-active portion T7Aa on the side close to the signal generating module 10, and the second high potential line Pvgh1 is electrically connected to the fourth drain T7D through the seventh via HL7. The first via HL1 penetrates the second interlayer insulating layer 134.

[0193] In Figures 18 to 20 , in the second direction Y, the width of the first high potential line Nvgh is equal to the width of the first low potential line Nvgl1, and the width of the first high potential line Nvgh is greater than the width of the second high potential line Pvgh1. Since the first high potential line Nvgh and the first low potential line Nvgl1 are primarily used to provide high-level signals and low-level signals, respectively, to the first output module 20, and the first output module 20, in addition to outputting gate drive signals to the display unit 200, also needs to output stage transfer signals to the next-stage GOA unit 310, the output load of the first output module 20 is higher than the output load of the second output module 30. Therefore, the output loads of the first high potential line Nvgh and the first low potential line Nvgl1 are both greater than the output loads of the second high potential line Pvgh1 and the second low potential line Pvgl. Therefore, in the present application, the widths of the first high potential line Nvgh and the first low potential line Nvgl1 are both greater than the widths of the second high potential line Pvgh1 and the second low potential line Pvgl.

[0194] Please refer to Figures 18 to 20. The second source and drain layer 135 may also include a second low potential line Pvgl and a third high potential line Pvgh2 overlapping with the signal generating module 10. The second low potential line Pvgl, the third high potential line Pvgh2, and the second high potential line Pvgh1 are parallel and spaced apart. The second low potential line Pvgl is arranged between the second high potential line Pvgh1 and the third high potential line Pvgh2. The widths of the third high potential line Pvgh2, the second high potential line Pvgh1, and the second low potential line Pvgl are all equal.

[0195] Please refer to Figures 18 to 20. The second source and drain layer 135 also includes a first clock signal line CK and a second clock signal line XCK that overlap with the signal generating module 10. The first clock signal line CK and the second clock signal line XCK are parallel to and spaced apart from the second high potential line Pvgh1. The first clock signal line CK and the second clock signal line XCK are arranged between the second high potential line Pvgh1 and the second low potential line Pvgl.

[0196] In this embodiment, in the display panel 100 of the present application, the gate driving circuit 300 includes a plurality of repeating units, each repeating unit includes at least four GOA units 310. Hereinafter, four GOA units 310 are taken as one repeating unit as an example, and the plurality of repeating units are arranged in the first direction X.

[0197] Please refer to FIG. 21 , which is a diagram illustrating the superimposed film layers of the first gate layer 125 , the first source / drain electrode layer 133 , and the second source / drain electrode layer 135 in the display panel 100 of the present application.

[0198] In this embodiment, the repeating unit may include a first GOA unit 311, a second GOA unit 312, a third GOA unit 313 and a fourth GOA unit 314 arranged in sequence along the first direction X, and the display panel 100 may include a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4 arranged along the second direction Y, and every two clock signal lines are connected to one GOA unit 310.

[0199] In this embodiment, the first clock signal line PCK1, the second clock signal line PCK2 and the first GOA unit 311 are connected, the first clock signal line PCK1 is the first clock signal line CK of the first GOA unit 311, and the second clock signal line PCK2 is the second clock signal line XCK of the first GOA unit 311, that is, the first clock signal line PCK1 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the second clock signal line PCK2 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0200] In this embodiment, the second clock signal line PCK2, the third clock signal line PCK3 and the second GOA unit 312 are connected, the second clock signal line PCK2 is the first clock signal line CK of the first GOA unit 311, and the third clock signal line PCK3 is the second clock signal line XCK of the first GOA unit 311, that is, the second clock signal line PCK2 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the third clock signal line PCK3 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0201] In this embodiment, the third clock signal line PCK3, the fourth clock signal line PCK4 and the third GOA unit 313 are connected, the third clock signal line PCK3 is the first clock signal line CK of the first GOA unit 311, and the fourth clock signal line PCK4 is the second clock signal line XCK of the first GOA unit 311, that is, the third clock signal line PCK3 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0202] In this embodiment, the fourth clock signal line PCK4, the first clock signal line PCK1 and the fourth GOA unit 314 are connected, the fourth clock signal line PCK4 is the first clock signal line CK of the first GOA unit 311, and the first clock signal line PCK1 is the second clock signal line XCK of the first GOA unit 311, that is, the fourth clock signal line PCK4 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0203] Referring to Figures 15 and 21, the first source-drain layer 133 in each level of the GOA unit 310 further includes a first extension segment 161 connected to the third source T6S. The first extension segment 161 extends along the second direction Y, and the first extension segment 161 is located in the area where the signal generating module 10 is located. The first clock signal line CK in each level of the GOA unit 310 is electrically connected to the first extension segment 161 through the fourth via HL4; wherein the fourth via HL4 passes through the second interlayer insulating layer 134.

[0204] In this embodiment, since the third output transistor T6 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 is connected to different clock signal lines, in the repeating unit, the lengths of the first extension segments 161 in some GOA units 310 in the first direction X are different, that is, the lengths of the first extension segments 161 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 are different; for example, the lengths of the first extension segments 161 in the first GOA unit 311 and the second GOA unit 312 are equal, and the lengths of the first extension segments 161 in the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 gradually increase.

[0205] In this embodiment, in the second GOA unit 312, since the gate of the first feedback transistor T4 and the third output transistor T6 are both connected to the second clock signal line PCK2, and the connection positions of the two are close, in order to avoid interference between the two, the first source and drain layer 133 in the second GOA unit 312 also includes a third extension segment 163, and the third extension segment 163 extends along the first direction X. The second clock signal line PCK2 is electrically connected to the first extension segment 161 through the third extension segment 163.

[0206] In this embodiment, referring to FIG7 , the first gate layer 125 in each stage of the GOA unit 310 further includes a fourth extension segment 164 connected to the gate of the pull-up transistor T2, and the fourth extension segment 164 extends along the second direction Y, that is, the fourth extension segment 164 mainly extends toward a side away from the first output module 20; at the same time, referring to FIG15 and FIG21 , the first source-drain layer 133 in each stage of the GOA unit 310 further includes a fifth extension segment 165, and the fifth extension segment 165 extends along the second direction Y. The first end of the fifth extension segment 165 is connected to the second clock signal line XCK in the corresponding GOA unit 310, and the second end of the fifth extension segment 165 is electrically connected to the fourth extension segment 164.

[0207] In Figures 7, 15 and 21, the length of the fifth extension segment 165 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit 313 gradually decreases, and the length of the fifth extension segment 165 in the fourth GOA unit 314 increases compared with the length of the fifth extension segment 165 in the third GOA unit 313; at the same time, the lengths of the fourth extension segment 164 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit 313 are equal, and the length of the fourth extension segment 164 in the fourth GOA unit 314 is longer than the length of the fourth extension segment 164 in the third GOA unit 313.

[0208] In Figures 7, 15 and 21, since the pull-up transistors T2 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 are connected to different clock signal lines, in one repeating unit, the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in different GOA units 310 is different; for example, the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit gradually decreases, and the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in the fourth GOA unit 314 is greater than the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in the first GOA unit.

[0209] Please refer to Figures 7 and 15. The first gate layer 125 also includes a sixth extension segment 166 and a seventh extension segment 167. The sixth extension segment 166 and the seventh extension segment 167 extend along the second direction Y. The first end of the sixth extension segment 166 is connected to the fourth gate T7G, the second end of the sixth extension segment 166 is connected to the source T1S of the second inverting transistor T1 through a via, the first end of the seventh extension segment 167 is connected to the drain T3D of the first inverting transistor T3 through a via, and the second end of the seventh extension segment 167 is connected to the gate T14G of the regulating transistor T14.

[0210] Please refer to Figures 18 and 19. The second source and drain layer 135 includes a plurality of reset signal lines RST arranged at intervals, the plurality of reset signal lines RST overlap with the first buffer unit 210, and the plurality of reset signal lines RST are arranged between the first low potential line Nvgl1 and the third high potential line Pvgh2. The first end of the reset signal line RST is connected to the second branch source T9Sb in the N-10th level GOA unit 310 through the eighth via HL8, and the second end of the reset signal line RST is connected to the gate of the first filter transistor T11 through the ninth via HL9.

[0211] In this embodiment, the eighth transistor passes through the second inter-insulating layer 134 , and the ninth transistor passes through the third via hole HL3 that passes through the second inter-insulating layer 134 , the first inter-insulating layer 132 , the fourth gate insulating layer 130 , the third gate insulating layer 128 and the second gate insulating layer 126 .

[0212] Please refer to Figure 10, the third gate layer 131 includes a third connecting segment 153, and the third connecting segment 153 extends from the N-th level GOA unit 310 to the N-1-th level GOA unit 310; please refer to Figure 15, the first source and drain layer 133 also includes a fourth connecting segment 154, the first end of the fourth connecting segment 154 is connected to the gate of the second filter transistor T8, the second end of the fourth connecting segment 154 is connected to the first end of the third connecting segment 153, and the second end of the third connecting segment 153 is electrically connected to the start signal line STV in the N-1-th level GOA unit 310. Since the signal of the start signal line STV in the N-1-th level GOA unit 310 comes from the first signal transmission segment of the N-2-th level GOA unit 310, the signal of the gate of the second filter transistor T8 of the present application comes from the first signal output end Nout of the N-2-th level.

[0213] It should be noted that the source and drain in the above-mentioned transistors of the present application are only distinguished in name, as long as one of them is an input terminal and the other is an output terminal.

[0214] It should be noted that the film layer structure diagram provided in this application is not only applicable to the circuit structures in Figures 3 and 5, but is also applicable to this application as long as it has the same module structure as this application, that is, a module structure that outputs two gate drive signals, Nout and Pout.

[0215] The present application also provides a display terminal including the above-mentioned display panel. The display terminal can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0216] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0217] The above is a detailed introduction to a display panel and a display terminal provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising a display unit and a gate driving circuit located at one side of the display unit, wherein the gate driving circuit comprises N cascaded GOA units, and the N GOA units are arranged along a first direction; wherein, Each of the GOA units includes a signal generating module, a first output module and a second output module arranged along the second direction; The first output module is disposed on a side of the signal generating module close to the display unit, and the first output module is used to output a first gate driving signal; The second output module is arranged at a side of the signal generating module away from the display unit, and the second output module is used to output a second gate driving signal, and the first gate driving signal and the second gate driving signal are different; Among them, in the second direction, the lengths of the first output module and the second output module are different, the second direction is parallel to the scan line of the display panel, the angle between the first direction and the second direction is greater than 0° and less than or equal to 90, and N is a positive integer.

2. The display panel according to claim 1, wherein: The first output module comprises a first buffer unit and a second buffer unit arranged along the second direction, the first buffer unit is arranged close to the signal generating module, and the second buffer unit is arranged far away from the signal generating module; The first buffer unit includes a first active portion, the second buffer unit includes a second active portion, the first active portion is a metal oxide semiconductor, and the second active portion is a low temperature polysilicon semiconductor.

3. The display panel according to claim 2, wherein: The first buffer unit includes a first output transistor having the first active portion, and the second buffer unit includes a second output transistor having the second active portion; Wherein, in the second direction, the length of the first output transistor is greater than the length of the second output transistor.

4. The display panel according to claim 3, wherein: The second output module includes a third output transistor and a fourth output transistor, the third output transistor includes a third active portion, the fourth output transistor includes a fourth active portion, the third active portion and the fourth active portion are low temperature polysilicon semiconductors, and the third output transistor and the fourth output transistor are arranged in parallel along the first direction Wherein, the first gate of the first output transistor and the second gate of the second output transistor are connected to the first node of the signal generating module, the first source of the first output transistor is connected to the first high potential line, the first drain of the first output transistor and the second source of the second output transistor are connected to the first signal output terminal, and the second drain of the second output transistor is connected to the first low potential line; In addition, the third gate of the third output transistor is connected to the second node of the signal generating module, the third source of the third output transistor is connected to the first clock signal line, the third drain of the third output transistor and the fourth source of the fourth output transistor are connected to the second signal output terminal, the fourth gate of the fourth output transistor is connected to the third node of the signal generating module, and the fourth drain of the fourth output transistor is connected to the second high potential line.

5. The display panel according to claim 4, wherein: The first output transistor further includes a fifth gate disposed opposite to the first gate, and the fifth gate is connected to the first node.

6. The display panel according to claim 5, wherein: The display panel includes a base substrate and an array driving layer arranged on the base substrate, and the array driving layer includes: A first gate layer, comprising the second gate, the third gate and the fourth gate; In the second direction, the length of the second gate is greater than the length of the third gate, and the area of ​​the second gate is greater than the area of ​​the third gate.

7. The display panel according to claim 6, wherein: The second gate includes a second main gate and a plurality of second branch gates arranged at intervals, the third gate includes a third main gate and a plurality of third branch gates arranged at intervals, the second main gate and the third main gate extend along the first direction, the second branch gate and the third branch gate extend along the second direction, the fourth gate extends along the second direction, and the fourth gate and a plurality of the third branch gates in the third gate are parallel and arranged at intervals; Among them, one end of the plurality of second branch gates facing the signal generating module is electrically connected to the second trunk gate, and one end of the plurality of third branch gates facing the signal generating module is electrically connected to the third trunk gate.

8. The display panel according to claim 7, wherein: The display panel further comprises a first storage capacitor, a first plate of the first storage capacitor is connected to the second node, and a second plate of the storage capacitor is connected to the second signal output terminal; The first gate layer further includes the first electrode plate, and one end of the plurality of third branch gates away from the signal generating module is connected to the first electrode plate. In the second direction, the width of the first electrode plate is greater than the width of the third main gate.

9. The display panel according to claim 7, wherein: The array driving layer further comprises a second gate layer arranged on a side of the first gate layer away from the base substrate, and the second gate layer comprises the first gate; Among them, the first gate includes two first main gates and multiple first branch gates arranged between the two first main gates, the two first main gates are arranged opposite to each other and in parallel, the two first main gates extend along the first direction, the multiple first branch gates extend along the second direction, and the two ends of the multiple first branch gates are respectively connected to the two first main gates.

10. The display panel according to claim 9, wherein: The array driving layer further comprises a third gate layer arranged on a side of the second gate layer away from the base substrate, and the third gate layer comprises the fifth gate; Among them, the fifth gate includes two fifth main gates and multiple fifth branch gates arranged between the two fifth main gates, the two fifth main gates are arranged oppositely and in parallel, the two fifth main gates extend along the first direction, and the multiple fifth branch gates extend along the second direction, and the two ends of the multiple fifth branch gates are respectively connected to the two first main gates.

11. The display panel according to claim 10, wherein: The array driving layer further comprises a first active layer disposed between the first gate layer and the base substrate, wherein the first active layer comprises a low temperature polysilicon semiconductor; The first active layer includes the second active portion, the third active portion and the fourth active portion, the second active portion overlaps with a plurality of the second branch gates, and the third active portion overlaps with a plurality of the third branch gates; the second active portion includes two second sub-active portions arranged at intervals, the third active portion includes two third sub-active portions arranged at intervals, the second sub-active portion and the third sub-active portion extend along the first direction, the fourth active portion includes two fourth sub-active portions arranged at intervals, and the two fourth sub-active portions overlap with the fourth gate; Among them, in the second direction, the width of the second sub-active portion is greater than the width of the third sub-active portion, the width of the fourth sub-active portion is equal to the width of the third sub-active portion, and the fourth sub-active portion is connected to the corresponding third sub-active portion.

12. The display panel according to claim 11, wherein: The array driving layer further comprises a second active layer disposed between the third gate layer and the second gate layer, wherein the second active layer comprises a metal oxide semiconductor; The second active layer includes the first active portion, the first active portion includes two first sub-active portions that are spaced apart, the first sub-active portions extend along the first direction, and the two first sub-active portions and a plurality of the first branch gates overlap.

13. The display panel according to claim 12, wherein: The array driving layer further comprises a first source-drain electrode layer disposed on a side of the third gate layer away from the second gate layer, wherein the first source-drain electrode layer comprises the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; Wherein, the first source includes a first main source and a plurality of first branch sources arranged in parallel and at intervals, the first drain includes a plurality of first branch drains, the first main source extends along the first direction, the first branch source extends along the second direction, a side of the plurality of first branch sources away from the signal generating module is connected to the first main source, the plurality of first branch drains extends along the second direction, and the plurality of first branch drains are arranged between the plurality of first branch sources; Furthermore, the second drain includes a second main drain and a plurality of second branch drains that are spaced apart and arranged in parallel, the second source includes a plurality of second branch sources, the second main drain extends along the first direction, the second branch drain extends along the second direction, a plurality of second branch drains are connected to the second main drain near the signal generating module, a plurality of second branch sources extend along the second direction, and a plurality of second branch sources are arranged between a plurality of second branch drains, and the first main source and the second main drain are connected.

14. The display panel according to claim 13, wherein: The first source-drain electrode layer further includes a first connecting segment, and the first connecting segment is arranged between an end of the second branch source electrode close to the signal generating module and the second trunk drain electrode; The third gate layer further includes a first protrusion disposed on the fifth trunk gate at a side away from the signal generating module, the first protrusion is connected to the fifth trunk gate, and the first protrusion extends toward a side away from the signal generating module; The first end of the first connecting segment overlaps with the first protrusion and the second main gate, the second end of the first connecting segment overlaps with the second main gate, and the first connecting segment is electrically connected to the first protrusion, and the second end of the first connecting segment is electrically connected to the second main gate.

15. The display panel according to claim 14, wherein: The first source-drain electrode layer further includes a second connecting segment, and the second connecting segment is arranged on a side of the first branch drain electrode close to the signal generating module; Wherein, the second gate layer further includes a second protrusion disposed on a side close to the signal generating module, the second protrusion is connected to the first trunk gate, and the second protrusion extends toward a side close to the signal generating module; The third gate layer further includes a third protrusion disposed on a side close to the signal generating module, the third protrusion is connected to the fifth trunk gate, and the third protrusion extends toward a side close to the signal generating module; The first end of the second connecting segment overlaps with the second protrusion, the second end of the second connecting segment overlaps with the third protrusion, and the first end of the second connecting segment is electrically connected to the third protrusion, and the second end of the second connecting segment is electrically connected to the fourth protrusion.

16. The display panel according to claim 14, wherein: The first source-drain electrode layer further includes a third source electrode, a third drain electrode, a fourth source electrode and a fourth drain electrode; Wherein, the third source includes a third main source and two third branch sources arranged in parallel and at intervals, one end of the two third branch sources close to the signal generating module is connected to the third main source, the third drain includes a third main drain and two third branch drains arranged in parallel and at intervals, one end of the two third branch drains close to the signal generating module is connected to the third main drain, and the two third branch sources and the two third branch drains are alternately arranged in the first direction; The fourth source and the fourth drain extend along the second direction, the fourth drain is arranged adjacent to the third branch drain, the fourth source is arranged on a side of the fourth drain away from the third branch drain, and the first end of the fourth source is connected to the third main drain.

17. The display panel according to claim 16, wherein: The first source-drain electrode layer further includes a first extension segment connected to the third source electrode, the first extension segment extends along the second direction, and the first extension segment is located in the area where the signal generating module is located; The gate driving circuit includes a plurality of repeating units, each of the repeating units includes at least four GOA units, and in the repeating units, the first extension segments in some of the GOA units have different lengths in the first direction.

18. The display panel according to claim 16, wherein: The array driving layer further comprises a second source-drain layer arranged on a side of the first source-drain layer away from the base substrate, the second source-drain layer comprises the first high potential line, the first low potential line and the second high potential line, the first high potential line, the first low potential line and the second high potential line are arranged in parallel and extend along the first direction; Wherein, the first high potential line overlaps with a plurality of the second branch sources and a plurality of the second branch drains in each of the GOA units, and the first high potential line is electrically connected to a plurality of the second branch sources in each of the GOA units; The first low potential line overlaps with a plurality of the first branch sources and a plurality of the first branch drains in each of the GOA units, and the first low potential line is electrically connected to a plurality of the first branch drains in each of the GOA units; The second high potential line overlaps with the third sub-active portion and the fourth sub-active portion close to the signal generating module. In the second direction, the width of the first high potential line is equal to the width of the first low potential line, and the width of the first high potential line is greater than the width of the second high potential line.

19. The display panel according to claim 4, wherein: The signal generating module comprises: A level transmission signal selection module is electrically connected between the start signal line and the fourth node; A pull-up control module, controlling the potential of the first node K according to the potential of the fourth node and the potential of the second clock signal line; A first filtering module is electrically connected between the fifth node and the first node, and a control end of the first filtering module is electrically connected to a reset signal line; A second filtering module, electrically connected between the fifth node and the second node, wherein a control end of the second filtering module receives the first gate driving signal of the N-2th stage; A first inverting module, connected between the first node and the third node; a feedback module connected between the first node and the third node; and A voltage regulating module, wherein a first end of the voltage regulating module is electrically connected to the first low potential line, a second end of the voltage regulating module is connected to the gate of the first output transistor, and a control end of the voltage regulating module is electrically connected to the third node.

20. The display panel according to claim 1, wherein: The first gate driving signal is a positive pulse signal, and the second gate driving signal is a negative pulse signal; Wherein, within a time interval of one frame, the first signal output terminal outputs two positive pulse signals, and the second signal output terminal outputs one negative pulse signal.

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