Scanning driving circuit and display panel

Abstract

A scanning driving circuit (30) and a display panel (10). The scanning driving circuit (30) comprises a plurality of stages of shift register units and a timing controller (20), wherein each stage of shift register unit comprises 13 transistors and three capacitors, and the timing controller (20) comprises two timing control signal lines. By providing a new 13T3C shift register unit, the mutual restriction and effect between transistors are solved, such that the scanning driving circuit (30) is more stable, thereby preventing abnormal display caused by length-to-width ratio fluctuations of the transistors due to threshold voltage shifts or manufacturing process errors, and prolonging the service life of the display panel (10); and the problem in respect of electric floating of nodes in a circuit is solved, thereby improving the reliability of the display panel (10).

Description

Scan driving circuit and display panel Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a scan drive circuit and a display panel. Background Art

[0002] The display panel includes a pixel array and a scanning drive circuit and a light-emitting drive circuit that control the pixel array. The display panel adopts a row-by-row scanning display mode, wherein the scanning drive circuit is used to generate a scanning signal to turn on each row of pixels in sequence.

[0003] The scan driving circuit includes a plurality of cascaded shift register units, wherein the circuit of each shift register unit is usually mainly composed of several transistors. By inputting a clock signal CKV and a start pulse signal IN into the circuit, a scan signal Gout is output at the output end.

[0004] Chinese patent CN105989797A provides a scanning circuit, as shown in Figures 1 and 2, Figure 1 shows a circuit diagram of a shift register unit in the prior art; Figure 2 shows a waveform diagram of the shift register unit in the prior art when it is working. Among them, "H" represents a high-level signal and "L" represents a low-level signal. In this circuit, the T5 transistor and the T6 transistor will restrain each other. When the display panel is used for a long time, the threshold voltage vth of the transistor shifts, or the display panel manufacturing process error causes the aspect ratio of the transistor to change, which may cause the scanning circuit output of the display panel to be abnormal. As shown in Figure 2, Gout is an ideal output signal, and Abnormal Gout is an abnormal output signal, which causes the display panel to display an abnormal picture. In addition, the second node N2 in the circuit of the shift register unit has an electrical floating problem at certain moments during operation, causing the display panel to display abnormally and reduce reliability.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field.

[0006] Summary of the Invention

[0007] In view of this, the present invention provides a scan driving circuit and a display panel.

[0008] One aspect of the present invention provides a scan driving circuit, comprising a multi-stage shift register unit, wherein the shift register unit comprises:

[0009] a first transistor, wherein a first electrode of the first transistor is connected to the signal input terminal, a second electrode is connected to the second node, and a gate is connected to the second timing control terminal;

[0010] a second transistor, wherein a second electrode of the second transistor is connected to the second node, and a gate of the second transistor is connected to the first node;

[0011] a third transistor, wherein a first electrode of the third transistor is connected to the first power supply, a second electrode of the third transistor is connected to the first electrode of the second transistor, and a gate of the third transistor is connected to the first timing control terminal;

[0012] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the second power supply, a second electrode of the fourth transistor is connected to the fourth node, and a gate of the fourth transistor is connected to the second timing control terminal;

[0013] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the second timing control terminal, a second electrode of the fifth transistor is connected to the first node, and a gate of the fifth transistor is connected to the second node;

[0014] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second node, a second electrode of the sixth transistor is connected to the fifth node, and a gate of the sixth transistor is connected to the second power supply;

[0015] a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node;

[0016] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the first timing control terminal, and a gate of the eighth transistor is connected to the fifth node;

[0017] a ninth transistor, wherein a first electrode of the ninth transistor is connected to the fourth node, a second electrode of the ninth transistor is connected to the first node, and a gate of the ninth transistor is connected to the third node;

[0018] a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first timing control terminal, a second electrode of the tenth transistor is connected to the third node, and a gate of the tenth transistor is connected to the signal input terminal;

[0019] an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the third node, a second electrode is connected to the second power supply, and a gate is connected to the first timing control terminal;

[0020] a twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the first node, and a gate of the twelfth transistor is connected to the fourth node;

[0021] a thirteenth transistor, wherein a first electrode of the thirteenth transistor is connected to the second electrode of the twelfth transistor, a second electrode of the thirteenth transistor is connected to the second power supply, and a gate of the thirteenth transistor is connected to the first timing control terminal;

[0022] a first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node;

[0023] a second capacitor, wherein a first electrode of the second capacitor is connected to the fifth node, and a second electrode of the second capacitor is connected to the signal output terminal;

[0024] A third capacitor has a first electrode connected to the fourth node and a second electrode connected to the third node.

[0025] In some embodiments, a timing controller is further included, and the timing controller includes a first timing control signal line and a second timing control signal line.

[0026] In some embodiments, the first timing control signal line is used to output a first timing control signal; and the second timing control signal line is used to output a second timing control signal.

[0027] In some embodiments, the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0028] In some embodiments, the shift register unit is used to perform delay processing on the signal received from the signal input end under the control of the first timing control signal and the second timing control signal, and the processed signal is output from the signal output end.

[0029] In some embodiments, the shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

[0030] In some embodiments, in the odd-numbered shift register units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

[0031] In some embodiments, in the even-numbered shift register units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

[0032] In some embodiments, the first to thirteenth transistors are all P-type MOS transistors.

[0033] Another aspect of the present invention further provides a display panel, characterized by comprising any one of the above-mentioned scan driving circuits.

[0034] The beneficial effects of the present invention compared with the prior art include at least:

[0035] The scan drive circuit and display panel of the present invention provide a new 13T3C shift register unit to resolve the mutual restraint between transistors, making the scan circuit more stable, avoiding display anomalies caused by fluctuations in transistor aspect ratio due to threshold voltage offset or manufacturing process errors, and improving the service life of the display panel. In addition, the shift register unit solves the problem of electrical floating of nodes in the circuit, thereby improving the reliability of the display panel.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0038] FIG1 shows a circuit diagram of a shift register unit in the prior art;

[0039] FIG2 shows a waveform diagram of a shift register unit in the prior art when it is working;

[0040] FIG3 is a schematic diagram showing a display panel according to an embodiment of the present invention;

[0041] FIG4 shows a schematic diagram of a cascade connection of a scan driving circuit according to an embodiment of the present invention;

[0042] FIG5 shows a circuit diagram of a shift register unit according to an embodiment of the present invention;

[0043] FIG6 shows a waveform diagram of the shift register unit shown in FIG5 when it is working;

[0044] FIG7 is a schematic diagram showing the conduction state of the shift register unit at stage t1 in FIG6 ;

[0045] FIG8 is a schematic diagram showing the conduction state of the shift register unit at stage t2 in FIG6 ;

[0046] FIG9 is a schematic diagram showing the conduction state of the shift register unit at stage t3 in FIG6 ;

[0047] FIG. 10 is a schematic diagram showing the conduction state of the shift register unit at stage t4 in FIG. 6 .

[0048] Reference Signs: 10 display panel 11 display area 20 timing controller 30 scan driving circuit CKV1 first timing control signal line CKV2 second timing control signal line c1 first timing control terminal c2 second timing control terminal IN signal input terminal Gout signal output terminal T1 first transistor T2 second transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor T8 eighth transistor T9 ninth transistor T10 tenth transistor T11 eleventh transistor T12 twelfth transistor T13 thirteenth transistor C1 first capacitor C2 second capacitor C3 third capacitor VDD first power supply VEE second power supply n1 first node n2 second node n3 third node n4 fourth node n5 fifth node DETAILED DESCRIPTION

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the figures represent identical or similar structures, and thus a repeated description thereof will be omitted.

[0050] The terms "first," "second," and similar terms used in the specific description do not denote any order, quantity, or importance, but are simply used to distinguish different components. Furthermore, in the description of the present invention, the terms "upper," "lower," and similar terms indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely for ease of description and do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0051] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0052] Through meticulous and in-depth research, the inventors of this case have provided a solution to the problems existing in the prior art. As shown in Figures 3 to 5, Figure 3 shows a schematic diagram of a display panel according to an embodiment of the present invention; Figure 4 shows a cascade diagram of a scan drive circuit according to an embodiment of the present invention; and Figure 5 shows a circuit diagram of a shift register unit according to an embodiment of the present invention. The present embodiment discloses a scan drive circuit 30 and a display panel 10. The scan drive circuit 30 includes multiple shift register units and a timing controller 20. Each shift register unit includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, and three timing control terminals. The timing controller 20 includes three timing control signal lines. The scan drive circuit and display panel of the present invention, by providing a new 13T3C shift register unit, address the mutual restraint between transistors, making the scan circuit more stable, avoiding display anomalies caused by fluctuations in transistor aspect ratio due to threshold voltage offset or manufacturing process errors, and improving the service life of the display panel. Furthermore, the shift register unit solves the problem of electrical floating nodes in the circuit, improving the reliability of the display panel.

[0053] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0054] As shown in FIG3 , the present invention provides a display panel 10 comprising a display area 11 and a non-display area. A scan driver circuit 30, a data driver, and a light-emitting driver circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the scan driver circuit 30, the data driver, the light-emitting driver circuit, and the pixel circuits.

[0055] As shown in FIG. 3 and FIG. 4 , the present invention further provides a scan driving circuit 30 , which includes a multi-stage shift register unit and a timing controller 20 .

[0056] In some embodiments, the shift register unit includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2, and a third timing control terminal c3. Each shift register unit outputs a scan signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive the pixels in that row to emit light. The previous shift register unit also outputs the scan signal to the signal input terminal IN of the next shift register unit as a start signal. Because the last shift register unit does not have a next stage, the scan signal it outputs is only input to the pixel circuits in that row.

[0057] Specifically, FIG4 shows four cascaded shift register units as an example. The signal input terminal IN1 of the first-stage shift register unit S1 receives a start pulse signal STV as an input signal. The signal output terminal Gout1 of the first-stage shift register unit S1 outputs a scan signal as an input signal for the second-stage shift register unit S2. The signal output terminal Gout1 of the first-stage shift register unit S1 is connected to the signal input terminal IN2 of the second-stage shift register unit S2. The signal output terminal Gout2 of the second-stage shift register unit S2 outputs a scan signal as an input signal for the third-stage shift register unit S3. The signal output terminal Gout2 of the second-stage shift register unit S2 is connected to the signal input terminal IN3 of the third-stage shift register unit S3. The signal output terminal Gout3 of the third-stage shift register unit S3 outputs a scan signal as an input signal for the fourth-stage shift register unit S4. The signal output terminal Gout3 of the third-stage shift register unit S3 is connected to the signal input terminal IN4 of the fourth-stage shift register unit S4. This process is repeated for subsequent stages of shift register units, forming a scan drive circuit 30.

[0058] In some embodiments, as shown in FIG4 , the timing controller 20 includes a first timing control signal line CKV1 and a second timing control signal line CKV2. The first timing control signal line CKV1 is used to output a first timing control signal. The second timing control signal line CKV2 is used to output a second timing control signal. The first timing control signal and the second timing control signal are square wave signals having the same output frequency and a phase difference of 180°.

[0059] In some preferred embodiments, with continued reference to FIG4 , further, the first timing control terminal c1 of the odd-numbered shift register unit is connected to the first timing control signal line CKV1 for receiving the first timing control signal, and the second timing control terminal c2 thereof is connected to the second timing control signal line CKV2 for receiving the second timing control signal. The first timing control terminal c1 of the even-numbered shift register unit is connected to the second timing control signal line CKV2 for receiving the second timing control signal, and the second timing control terminal c2 thereof is connected to the first timing control signal line CKV1 for receiving the first timing control signal.

[0060] In some embodiments, the shift register unit is used to delay the signal received from the signal input terminal IN under the control of the first timing control signal and the second timing control signal. The processed signal is output by the signal output terminal Gout, and the signal is output as a scanning signal to the display area 11 or input to the signal input terminal IN of the next-level shift register unit.

[0061] In some embodiments, referring to Figures 5 to 10, Figure 6 shows a waveform diagram of the shift register unit shown in Figure 5 when it is working; Figure 7 shows a schematic diagram of the on-state of the shift register unit in stage t1 in Figure 6; Figure 8 shows a schematic diagram of the on-state of the shift register unit in stage t2 in Figure 6; Figure 9 shows a schematic diagram of the on-state of the shift register unit in stage t3 in Figure 6; and Figure 10 shows a schematic diagram of the on-state of the shift register unit in stage t4 in Figure 6.

[0062] As shown in FIG5 , the shift register unit according to an embodiment of the present invention includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, and a second timing control terminal c2. The first transistor T1 has a first electrode connected to the signal input terminal IN, a second electrode connected to the second node n2, and a gate connected to the second timing control terminal c2. The second transistor T2 has a second electrode connected to the second node n2, and a gate connected to the first node n1. The third transistor T3 has a first electrode connected to the first power supply VDD, a second electrode connected to the first electrode of the second transistor T2, and a gate connected to the first timing control terminal c1. The fourth transistor T4 has a first electrode connected to the second power supply VEE, a second electrode connected to the fourth node n4, and a gate connected to the second timing control terminal c2. The fifth transistor T5 has a first electrode connected to the second timing control terminal c2, a second electrode connected to the first node n1, and a gate connected to the second node n2. The sixth transistor T6 has a first electrode connected to the second node n2, a second electrode connected to the fifth node n5, and a gate connected to the second power supply VEE. The seventh transistor T7 has a first electrode connected to the first power supply VDD, a second electrode connected to the signal output terminal Gout, and a gate connected to the first node n1. The eighth transistor T8 has a first electrode connected to the signal output terminal Gout, a second electrode connected to the first timing control terminal c1, and a gate connected to the fifth node n5. The ninth transistor T9 has a first electrode connected to the fourth node n4, a second electrode connected to the first node n1, and a gate connected to the third node n3. The tenth transistor T10 has a first electrode connected to the first timing control terminal c1, a second electrode connected to the third node n3, and a gate connected to the signal input terminal IN. The eleventh transistor T11 has a first electrode connected to the third node n3, a second electrode connected to the second power supply VEE, and a gate connected to the first timing control terminal c1. The twelfth transistor T12 has a first electrode connected to the first node n1, and a gate connected to the fourth node n4. The thirteenth transistor T13 has a first electrode connected to the second electrode of the twelfth transistor T12, a second electrode connected to the second power supply VEE, and a gate connected to the first timing control terminal c1. The first electrode of the first capacitor C1 is connected to the first power supply VDD, and the second electrode is connected to the first node n1. The first electrode of the second capacitor C2 is connected to the fifth node n5, and the second electrode is connected to the signal output terminal Gout. The first electrode of the third capacitor C3 is connected to the fourth node n4, and the second electrode is connected to the third node n3. The first power supply VDD provides a positive voltage signal, and the second power supply VEE provides a negative voltage signal.

[0063] In this embodiment, the first transistor T1 to the thirteenth transistor T13 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source. The on-level of the PMOS transistor is a low level, and the off-level is a high level. In other embodiments, those skilled in the art will readily appreciate that the shift register unit provided by the present invention can be easily modified to include all N-type MOS transistors. Alternatively, the shift register unit provided by the present invention can be easily modified to include CMOS transistors, etc.

[0064] In this embodiment, referring to FIG6 , the waveform diagram shown in FIG6 includes four processes: t1, t2, t3, and t4. In these four processes, the output signal of the signal output terminal Gout of the shift register unit completes a process from set to reset. It should be noted that, for ease of understanding, the high-level signal is represented by "H" and the low-level signal is represented by "L". The relationship between the input and output of the shift register unit in the above four processes is analyzed below in conjunction with the waveform diagram of FIG6 and the circuit diagram of FIG5 :

[0065] In this embodiment, referring to Figures 6 and 7, during process t1, a low level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, and a low level is input to the second timing control signal line CKV2. At this time, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 are turned on, while the third transistor T3, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned off. Specifically, due to the low levels of the signal input terminal IN, the second timing control signal line CKV2, and the second power supply VEE, the first transistor T1, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are turned on. A low level is written to the second node n2 by the signal input terminal IN through the first transistor T1, the fifth transistor T5 is turned on, the second timing control signal line CKV2 is written to the first node n1 by the fifth transistor T5, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned on through the sixth transistor T6. Finally, the signal output terminal Gout outputs the high potential of the first power source VDD and the first timing control signal line CKV1.

[0066] In this embodiment, referring to Figures 6 and 8, during process t2, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKV1, and a high level is input to the second timing control signal line CKV2. At this time, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the tenth transistor T10, and the twelfth transistor T12 are turned off. Specifically, the eleventh transistor T11 is turned on by the low level of the first timing control signal line CKV1, and the ninth transistor T9 is turned on through the eleventh transistor T11. The high level of the second timing control signal line CKV2 is transmitted through the fifth transistor T5, causing the first node n1 to be refreshed to a high level. The seventh transistor T7 is turned off, the second node n2 maintains the low level at the previous moment, and the eighth transistor T8 is turned on. Ultimately, the signal output terminal Gout outputs the low level of the second timing control signal line CKV2.

[0067] In this embodiment, referring to Figures 6 and 9, during process t3, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, and a low level is input to the second timing control signal line CKV2. At this time, the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the twelfth transistor T12 are turned on, while the third transistor T3, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the thirteenth transistor T13 are turned off. Specifically, the first transistor T1 and the fourth transistor T4 are turned on by the second timing control signal line CKV2, the first node n1 is refreshed to a low level by the second power supply VEE through the ninth transistor T9 and the fourth transistor T4, the seventh transistor T7 is turned on, the second node n2 is refreshed to a high level by the signal input terminal IN through the first transistor T1, the fifth transistor T5 is turned off, and the eighth transistor T8 is also turned off through the sixth transistor T6. Ultimately, the signal output terminal Gout outputs a high level of the first power supply VDD through the seventh transistor T7.

[0068] In this embodiment, referring to Figures 6 and 10, during process t4, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKV1, and a high level is input to the second timing control signal line CKV2. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are turned off. Specifically, the third transistor T3, the eleventh transistor T11, and the thirteenth transistor T13 are turned on by the first timing control signal line CKV1, the first transistor T1 and the fourth transistor T4 are turned off by the second timing control signal line CKV2, the ninth transistor T9 and the twelfth transistor T12 maintain their previous on state via the third capacitor C3, the first node n1 is continuously written to a low level by the second power supply VEE via the twelfth transistor T12 and the thirteenth transistor T13, the second transistor T2 and the seventh transistor T7 are turned on, the second node n2 is continuously written to a high level by the first power supply VDD via the third transistor T3 and the second transistor T2, and the eighth transistor T8 is turned off. Ultimately, the signal output terminal Gout outputs a high level of the first power supply VDD via the seventh transistor T7.

[0069] The shift register unit repeats the working steps from t3 to t4 after t4 until the next frame begins to be displayed, and the start pulse signal STV or the signal input terminal IN inputs a low potential, and re-enters the next round t1 process.

[0070] In this embodiment, the relationship between the input and output of the shift register unit is as follows: if the start pulse signal STV or the signal input terminal IN is at a low level in a certain process, then under the action of the first timing control signal line CKV1 and the second timing control signal line CKV2, the signal output terminal Gout also outputs a low level in the next process. In other processes, the start pulse signal STV or the signal input terminal IN and the signal output terminal Gout both maintain a high level until the start pulse signal STV or the signal input terminal IN inputs a low level again, at which point the signal output terminal Gout outputs a low level again. This is equivalent to the shift register unit delaying the low-level signal from the start pulse signal STV or the signal input terminal IN and outputting it from the signal output terminal Gout.

[0071] In this embodiment, the 13T3C circuit of the shift register unit adds a thirteenth transistor T13 and changes some wiring arrangements, thereby resolving the mutual restraint between the fifth transistor T5 and the sixth transistor T6, ensuring the correctness of the output waveform, making the scanning circuit more stable, and avoiding display anomalies caused by fluctuations in the aspect ratio of transistors due to threshold voltage offset or manufacturing process errors, thereby improving the service life of the display panel. It also ensures that the second node n2 is electrically floating, thereby improving the reliability of the display panel.

[0072] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel 10 described above. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The implementation of the display device can be referenced to the embodiments of the display panel 10 described above, and any repetitive details will not be repeated here.

[0073] The scan drive circuit and display panel of the present invention provide a new 13T3C shift register unit to resolve the mutual restraint between transistors, making the scan circuit more stable, avoiding display anomalies caused by fluctuations in transistor aspect ratio due to threshold voltage offset or manufacturing process errors, and improving the service life of the display panel. In addition, the shift register unit solves the problem of electrical floating of nodes in the circuit, thereby improving the reliability of the display panel.

[0074] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A scanning driving circuit, characterized in that: A multi-stage shift register unit is included, wherein the shift register unit includes: A first transistor, wherein a first electrode of the first transistor is connected to the signal input terminal, a second electrode is connected to the second node, and a gate is connected to the second timing control terminal; a second transistor, wherein a second electrode of the second transistor is connected to the second node, and a gate of the second transistor is connected to the first node; a third transistor, wherein a first electrode of the third transistor is connected to the first power supply, a second electrode of the third transistor is connected to the first electrode of the second transistor, and a gate of the third transistor is connected to the first timing control terminal; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the second power supply, a second electrode of the fourth transistor is connected to the fourth node, and a gate of the fourth transistor is connected to the second timing control terminal; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the second timing control terminal, a second electrode of the fifth transistor is connected to the first node, and a gate of the fifth transistor is connected to the second node; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second node, a second electrode of the sixth transistor is connected to the fifth node, and a gate of the sixth transistor is connected to the second power supply; a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node; an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the first timing control terminal, and a gate of the eighth transistor is connected to the fifth node; a ninth transistor, wherein a first electrode of the ninth transistor is connected to the fourth node, a second electrode of the ninth transistor is connected to the first node, and a gate of the ninth transistor is connected to the third node; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first timing control terminal, a second electrode of the tenth transistor is connected to the third node, and a gate of the tenth transistor is connected to the signal input terminal; an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the third node, a second electrode of the eleventh transistor is connected to the second power supply, and a gate of the eleventh transistor is connected to the first timing control terminal; a twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the first node, and a gate of the twelfth transistor is connected to the fourth node; a thirteenth transistor, wherein a first electrode of the thirteenth transistor is connected to the second electrode of the twelfth transistor, a second electrode of the thirteenth transistor is connected to the second power supply, and a gate of the thirteenth transistor is connected to the first timing control terminal; A first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node; a second capacitor, wherein a first electrode of the second capacitor is connected to the fifth node, and a second electrode of the second capacitor is connected to the signal output terminal; A third capacitor, wherein a first electrode of the third capacitor is connected to the fourth node, and a second electrode of the third capacitor is connected to the third node.

2. The scanning driving circuit according to claim 1, characterized in that: The invention also includes a timing controller, wherein the timing controller includes a first timing control signal line and a second timing control signal line.

3. The scanning driving circuit according to claim 2, characterized in that: The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

4. The scanning driving circuit according to claim 3, characterized in that: The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

5. The scanning driving circuit according to claim 3, characterized in that: The shift register unit is used for delaying the signal received from the signal input end under the control of the first timing control signal and the second timing control signal, and the processed signal is output from the signal output end.

6. The scanning driving circuit according to claim 2, characterized in that: The shift register unit of the previous stage outputs a scan signal to the shift register unit of the next stage, and the shift register unit of the last stage outputs a scan signal.

7. The scanning driving circuit according to claim 6, characterized in that: In the odd-numbered shift register units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

8. The scanning driving circuit according to claim 7, characterized in that: In the even-numbered shift register units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

9. The scanning driving circuit according to claim 1, characterized in that: The first transistor to the thirteenth transistor are all P-type MOS transistors.

10. A display panel, characterized in that: The invention comprises a scanning driving circuit according to any one of claims 1 to 9.

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