Large-scale linear circuit simulation method and system, circuit simulator and storage medium

Abstract

The present invention particularly relates to the technical field of analog circuit numerical simulation. Provided are a large-scale linear circuit simulation method and system, a circuit simulator and a storage medium. The present solution comprises: constructing an ordinary differential equation of a linear circuit, and on the basis of an Euler iteration method, converting same into a large-scale sparse linear equation system; using a graph partitioning algorithm to rearrange rows and columns of a coefficient matrix of the equation system, so as to obtain a doubly bordered diagonal matrix; using a plurality of computing nodes to constitute distributed nodes, solving local Schur complements of the distributed nodes by means of parallel computation, and summing same to obtain a global Schur complement; and on the basis of the global Schur complement and the state of each distributed node at a previous moment, obtaining the state of each distributed node at a current moment, so as to obtain a large-scale linear circuit simulation result. The present solution can control the number and size of blocks of circuit matrixes, and can remarkably improve the circuit simulation efficiency while ensuring smooth execution of simulation processes.

Description

Large-scale linear circuit simulation method, system, circuit simulator and storage medium Technical Field

[0001] The present invention relates to the technical field of analog circuit numerical simulation, and in particular to a large-scale linear circuit simulation method, system, circuit simulator and storage medium. Background Art

[0002] Large-scale circuits have reached tens to hundreds of millions of circuits at advanced nodes, posing significant challenges for circuit simulators. For example, the multifunctionality and emerging mixed-domain design demands of modern electronic products are driving ever-higher performance requirements for various analog, digital, electromagnetic, RF, and thermal modules at the chip, package, and system levels in VLSI design. Furthermore, the continued increase in operating frequency introduces significant effects, such as delay, distortion, reflection, and crosstalk.

[0003] In the existing technology, the core step for large-scale circuit simulation is sparse matrix decomposition. Currently, most methods use the method of rearranging the sparse matrix to decompose the sparse matrix, but it is impossible to obtain and control the number of divided matrix blocks and the size of each matrix block, resulting in low circuit simulation efficiency.

[0004] Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a large-scale linear circuit simulation method, system, circuit simulator and storage medium, aiming to solve the problem of low efficiency of large-scale linear circuit simulation in the prior art.

[0006] In order to achieve the above object, the first aspect of the present invention provides a large-scale linear circuit simulation method, comprising the following steps:

[0007] Constructing an ordinary differential equation of the linear circuit according to the scale of the linear circuit, and converting the ordinary differential equation of the linear circuit into a large-scale sparse linear equation system according to the Euler iteration method;

[0008] Rearranging the coefficient matrix of the large-scale sparse linear equation system so that all diagonal elements of the coefficient matrix are non-zero, thereby obtaining a pre-rearranged matrix;

[0009] Using a graph partitioning algorithm, the pre-rearranged matrix is ​​rearranged in rows and columns so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix;

[0010] Using a plurality of computing nodes to form distributed nodes, solving the local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and summing each of the local Schur complements to obtain a global Schur complement;

[0011] Based on the global Schur complement and the solution results of each distributed node at the previous moment, the state of each distributed node at the current moment is solved in parallel; based on the column rearrangement and row-column rearrangement, the solution results of each distributed node at all moments are converted into the large-scale linear circuit simulation results.

[0012] Optionally, the step of using a graph partitioning algorithm to rearrange the rows and columns of the pre-rearranged matrix so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries to obtain a double-boundary diagonal matrix includes:

[0013] Creating an original image stack for storing an original image and a sub-image stack for storing a sub-image obtained by binary division, wherein the original image refers to an undirected graph corresponding to the pre-rearrangement matrix;

[0014] After removing the original images from the original image stack one by one, the images are divided into two sub-images to obtain two sub-images; and the two sub-images are added to the sub-image stack until the original image stack is empty, and the original image stack and the sub-image stack are exchanged;

[0015] Repeating the process of dividing each original image into two sub-images and exchanging the original image stack and the sub-image stack until the number of the two sub-images in the sub-image stack or the number of times the original image stack and the sub-image stack are exchanged reaches a preset number;

[0016] The pre-rearranged matrix is ​​rearranged in rows and columns using all the bipartite subgraphs so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix.

[0017] Optionally, the step of taking the original images out of the original image stack one by one and dividing them into two sub-images to obtain two sub-images includes:

[0018] Obtaining the sizes of all original images popped from the original image stack;

[0019] A bipartite graph size threshold is preset based on the global information of all the bipartite subgraphs obtained by the previous bisection. If the size of the original image exceeds the preset bipartite graph size threshold, the original image is divided into subgraphs to obtain a bipartite subgraph; otherwise, the original image is set to the bipartite subgraph.

[0020] Optionally, the step of rearranging the pre-rearranged matrix using all the bipartite subgraphs so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries to obtain a double-boundary diagonal matrix includes:

[0021] Based on the dimension of the coefficient matrix, a column rearrangement matrix, a double-boundary diagonal rearrangement matrix, a row expansion matrix, and a column expansion matrix are preset;

[0022] Obtaining a pre-rearrangement matrix based on the column reordering matrix, the row scaling matrix, and the column scaling matrix, so that the coefficient matrix has elements on the diagonal with an absolute value of 1 and the absolute values ​​of elements other than the diagonal elements do not exceed 1;

[0023] A double-boundary diagonal rearrangement form is constructed based on the graph partitioning algorithm, and columns and rows of the pre-rearranged matrix are rearranged based on the double-boundary diagonal rearrangement form to obtain a double-boundary diagonal matrix.

[0024] Optionally, the step of using a plurality of computing nodes to form a distributed node, solving a local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and summing each of the local Schur complements to obtain a global Schur complement includes:

[0025] Using a plurality of computing nodes to form a distributed node, storing the data of the double-boundary diagonal matrix on a target node, and recording the target node as a master node, and recording nodes other than the master node as child nodes;

[0026] Broadcasting the data on the master node to each of the child nodes through a first message passing interface function, and solving the local Schur complement of all the distributed nodes;

[0027] The local Schur complements are summed up through a second message passing interface function to obtain a global Schur complement.

[0028] Optionally, broadcasting the data on the master node to each of the child nodes through the first message passing interface function to solve the local Schur complement of all the distributed nodes includes:

[0029] Based on the data on the master node, elements in the double-boundary diagonal matrix corresponding to each of the distributed nodes are screened out, and a block matrix is ​​constructed using the elements corresponding to each of the distributed nodes;

[0030] Each of the block matrices is solved in a parallel computing manner to obtain the local Schur complement of each of the distributed nodes.

[0031] Optionally, converting the solution results of each of the distributed nodes at all times into the large-scale linear circuit simulation results includes:

[0032] Solving the status of each of the distributed nodes at the current moment in parallel based on the global Schur complement and the solution results of each of the distributed nodes at the previous moment;

[0033] Finding rows of the large-scale linear circuit simulation results corresponding to the solution results of each distributed node at all times according to the column rearrangement matrix and the double-boundary diagonal rearrangement matrix;

[0034] All elements on the row are scaled according to the column scaling matrix to obtain the large-scale linear circuit simulation result.

[0035] A second aspect of the present invention provides a large-scale linear circuit simulation system, the system comprising:

[0036] an initialization module, configured to construct an ordinary differential equation of the linear circuit according to the scale of the linear circuit, and convert the ordinary differential equation of the linear circuit into a large-scale sparse linear equation system according to the Euler iteration method;

[0037] a matrix rearrangement module for rearranging the coefficient matrix of the large-scale sparse linear equation system by columns so that all diagonal elements of the coefficient matrix are non-zero, thereby obtaining a pre-rearranged matrix; and using a graph partitioning algorithm to rearrange the pre-rearranged matrix by rows and columns so that the non-zero elements of the double-boundary diagonal matrix are distributed on the diagonal and on the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix;

[0038] a Schur complement calculation module, configured to employ a plurality of computing nodes to constitute a distributed node, solve a local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and sum each of the local Schur complements to obtain a global Schur complement;

[0039] The circuit simulation module is used to solve the current state of each distributed node in parallel based on the global Schur complement and the solution results of each distributed node at the previous moment; and convert the solution results of each distributed node at all times into the large-scale linear circuit simulation results based on the column rearrangement and row-column rearrangement.

[0040] A third aspect of the present invention provides a circuit simulator, which includes a simulation chip, a memory, and a large-scale linear circuit simulation program stored in the memory and capable of running on the simulation chip. When the large-scale linear circuit simulation program is executed by the simulation chip, any one of the steps of the above-mentioned large-scale linear circuit simulation method is implemented.

[0041] A fourth aspect of the present invention provides a computer-readable storage medium storing a large-scale linear circuit simulation program. When the large-scale linear circuit simulation program is executed by a processor, the large-scale linear circuit simulation program implements any one of the steps of the above-mentioned large-scale linear circuit simulation method.

[0042] Compared with the prior art, the beneficial effects of the solution of the present invention are as follows:

[0043] The present invention first constructs the ordinary differential equations of the linear circuit according to the scale of the linear circuit, and converts the ordinary differential equations of the linear circuit into a large-scale sparse linear equation group according to the Euler iteration method, so that the coefficient matrix is ​​first rearranged in columns and then converted into a diagonal matrix with all non-zero elements, and then further rearranged in rows and columns using a graph partitioning algorithm to obtain a double-boundary diagonal matrix of expected dimension, which can effectively control the number and size of blocks of the large-scale linear circuit, thereby ensuring the normal progress of the subsequent simulation process; then, multiple computing nodes are used to form distributed nodes, and based on the double-boundary diagonal matrix data, the local Schur complement of each distributed node is solved, and the global Schur complement is obtained by simply summing the local Schur complements, thereby improving the simulation efficiency; then, the state of each distributed node at the current moment is solved in parallel through the solution results of each distributed node at the previous moment and the global Schur complement, thereby accelerating the circuit simulation efficiency; finally, the solution results of each distributed node at all moments are converted into circuit simulation results.

[0044] It can be seen that the present invention converts the ordinary differential equations of the linear circuit into a large-scale sparse linear equation system of appropriate dimension based on the scale of the large-scale linear circuit to control the number and size of blocks of the circuit matrix. Under the premise of ensuring the smooth progress of the simulation process, circuit simulation can be performed by parallel processing of each sub-node, which can significantly improve the efficiency of circuit simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] FIG1 is a flow chart of a large-scale linear circuit simulation method according to the present invention;

[0047] FIG2 is a flow chart of a specific process of a large-scale linear circuit simulation method according to the present invention;

[0048] FIG3 is a schematic diagram showing the principle of rearranging a matrix into a BBD form in the prior art;

[0049] FIG4 is a schematic diagram of the system structure of the present invention;

[0050] FIG5 is a schematic diagram of the structure of a circuit simulator of the present invention. DETAILED DESCRIPTION

[0051] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0052] It will be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0053] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0054] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0055] The following is a clear and complete description of the technical solutions in the embodiments of the present invention, in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0056] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0057] The present invention is directed to linear circuits and, based on the Metis library, rearranges sparse matrices into a form in which non-zero elements are concentrated on the diagonal, right, and bottom sides, referred to as the BBD form. Based on the scale of the linear circuit, the ordinary differential equations of the linear circuit are constructed and converted into a large-scale sparse linear equation system according to the Euler iteration method. By modifying the existing block strategy of Metis, the recursive depth-first block strategy is modified to a loop-based breadth-first block strategy, which can control the number and size of blocks in the circuit matrix. An efficient solver for the circuit matrix is ​​used for each distributed node, thereby significantly reducing simulation time. According to the characteristics of the linear circuit equation, corresponding mathematical transformation processing is performed so that each distributed node does not need to obtain complete simulation results or calculate complete simulation inputs during the simulation process, thereby reducing the amount of calculation, reducing memory usage, reducing the number of distributed node communications, and increasing the acceleration ratio.

[0058] Exemplary Methods

[0059] An embodiment of the present invention provides a large-scale linear circuit simulation method that is deployed on electronic devices such as computers and servers. The application scenario is large-scale linear circuit simulation, targeting sparse matrix rearrangement and parallel processing. The type of physical quantity represented by each node in the above-mentioned large-scale linear circuit is not limited and can be a physical quantity existing in various linear circuits such as voltage and current. Specifically, as shown in Figures 1 and 2, the process of the method of this embodiment includes:

[0060] Step S100: constructing an ordinary differential equation of the linear circuit according to the scale of the linear circuit, and converting the ordinary differential equation of the linear circuit into a large-scale sparse linear equation system according to the Euler iteration method.

[0061] Specifically, since the core of circuit simulation is to solve a large sparse linear equation group Ax=b, this embodiment sets the number of processes N to be opened according to the scale of the linear circuit, and constructs a large sparse linear equation group Ax=b in the BBD form according to the number of processes N opened, where A is an N-order non-singular square matrix, and x and b are both vectors of length N.

[0062] First, we explain the mathematical form of solving the BBD matrix. Here, we define A to have a BBD form where the non-zero elements are concentrated on the diagonal, right, and bottom. The non-zero elements are distributed in blocks near the diagonal, denoted by A0,...,A N-1 The non-zero elements distributed on the lower and right boundaries are divided into matrix blocks E0,...,E according to the block size on the diagonal line. N-1 and F0,...,F N-1 The area where the two boundaries and the diagonal intersect is recorded as matrix block A N The vectors x and b are divided into corresponding segments according to the block partitioning method of A. The corresponding large sparse linear equations are

[0063] For x0 to x N-1 There is A i x i =b i -F i x N ,i=0,…,N-1 (2)

[0064] For x N The equation of the row, x0 to x N-1 According to formula (2), replace x N Afterwards, we sorted out

[0065] Among them, For local Shu Erbu, is the global Schur complement, denoted by S.

[0066] It should be noted that the size of N in formula (1) is the same as the number of opened processes, which represents the sum of the main nodes and child nodes in the circuit matrix (i.e., the coefficient matrix), and there is only one main node.

[0067] According to the Euler iteration method, the ordinary differential equation of the linear circuit is converted into a large-scale sparse linear equation system. In this embodiment, the ordinary differential equation of the large-scale linear circuit is defined as:

[0068] Among them, x is the voltage value of each node of the circuit and the current value of some branches, u is the input of the circuit, C represents the capacitance and inductance of the circuit, G represents the resistance of the circuit, and B is the input matrix of the circuit.

[0069] Since not all nodes have inputs, u needs to be processed. In this embodiment, the differential term is linearly approximated with a step size of h, and the ordinary differential equation is discretized into the form of backward Euler iteration (C+hG)x (k+1) =Cx (k) +hBu (k+1) (5)

[0070] This form is Ax=b, and C+hG is a sparse matrix. This embodiment uses the above matrix as input to perform circuit simulation.

[0071] Step S200: Rearrange the coefficient matrix of the large-scale sparse linear equation system so that all diagonals of the coefficient matrix are non-zero, thereby obtaining a pre-rearranged matrix.

[0072] Specifically, in order to apply the BBD algorithm, the rows and columns of the original matrix are first rearranged into the BBD form. The premise for the feasibility of solving the BBD matrix is ​​that each submatrix on the diagonal is reversible. Since it is difficult to ensure that the submatrix is ​​absolutely reversible, the condition is relaxed to structural reversibility, where the structural reversibility of the sparse matrix is ​​equivalent to the existence of a rearrangement method for the matrix so that the diagonal elements of the double-boundary diagonal matrix of rows and columns are all non-zero. Therefore, this embodiment first uses the existing MC64 library to rearrange the matrix, where the MC64 library is a library in the collection HSL of mathematical libraries for large-scale scientific computing developed by the Computational Mathematics Group under the UK Research and Innovation Agency and other experts. The corresponding result after MC64 processing is C+hG→U(C+hG)QV

[0073] Where Q is a column rearrangement matrix that makes all diagonals of a double-bounded diagonal matrix non-zero. U and V are row and column scaling matrices, respectively, that ensure that all diagonals of the matrix processed by MC64 have elements with an absolute value of 1, and that the absolute values ​​of other elements do not exceed 1. This provides a pre-rearranged matrix to facilitate subsequent LU decomposition.

[0074] Step S300: using a graph partitioning algorithm, rearrange the rows and columns of the pre-rearranged matrix so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix.

[0075] Specifically, based on Metis, a graph partitioning algorithm is used to rearrange the matrix into a BBD form. The schematic diagram of this principle is shown in Figure 3. Figure 3(a) shows the undirected graph corresponding to the pre-rearranged matrix, and Figure 3(b) shows the subgraph rearranged into a BBD matrix after bisection. Rearranging into BBD form is equivalent to finding a set of vertices in the undirected graph, generally called a vertex separator (hereafter referred to as VS), which is the circled portion in Figure 3(a). The vertex separator can be used to divide the undirected graph into several disconnected subgraphs. The existing Metis-based method for finding a VS is as follows: first, bisection the undirected graph corresponding to the matrix to obtain a left graph, a right graph, and a VS; then, recursively bisection the left graph until the subgraph is small enough; then, bisection the right graph in the same manner as the left graph; finally, the VS of each subgraph is obtained. The VS of all subgraphs is the VS of the original graph. Because this bisection of an undirected graph is a depth-first recursive method, it cannot obtain information about all subgraphs, making it difficult to control the number of blocks and the size of each block. The fundamental reason is that Metis's goal is to rearrange the matrix to reduce the complexity of its LU decomposition, rather than to obtain a BBD matrix.

[0076] Based on this, this embodiment modifies it into a loop-based breadth-first traversal algorithm, which is implemented as follows: create an original image stack for storing the original image and a subgraph stack for storing the subgraphs obtained by binary division, where the original image refers to the undirected graph corresponding to the coefficient matrix; after taking the original images out of the original image stack one by one, divide them into subgraphs to obtain bipartite subgraphs; and put the bipartite subgraphs into the subgraph stack until the original image stack is empty, and exchange the original image stack and the subgraph stack; repeat the process of dividing each original image into subgraphs and exchanging the original image stack and the subgraph stack until the number of bipartite subgraphs in the subgraph stack or the number of exchanges between the original image stack and the subgraph stack reaches a preset number; use all the bipartite subgraphs to rearrange the rows and columns of the pre-rearranged matrix so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, obtaining a double-boundary diagonal matrix.

[0077] Specifically, first prepare two stacks, one for storing the original images in the undirected graph, and one for storing the sub-graphs obtained after binary division. In the initial state, the original image stack contains the original image corresponding to the circuit matrix, and the sub-graph stack is empty. Then, pop the original images from the original image stack one by one, binary-divide each original image, and put the sub-graphs obtained by binary division into the sub-graph stack until the original image stack is empty, and swap the two stacks. Repeat the above steps of binary division of the original image until the number of sub-graphs in the sub-graph stack reaches the desired number, and finally store the matrix blocks corresponding to all the obtained sub-graphs in the container. For example, if the number of binary division operations performed on each original image is n, then the number of matrix blocks (i.e., sub-graphs in the undirected graph) finally divided is 2. n During the actual simulation, the number of matrix blocks can be preset, and the number of binary division operations required for each original image can be set based on the preset number of matrix blocks. During the binary division operation, the graph partitioning algorithm used in this embodiment can control the size difference between the two sub-graphs obtained by binary division of a graph to a certain extent. In other words, by setting the corresponding parameters of the graph partitioning algorithm, the size of the sub-graphs obtained by the binary division operation can be controlled to a certain extent.

[0078] At the same time, the size of each corresponding subgraph in the subgraph stack can be queried through the container storing the matrix block, and the secondary block can be targeted according to the size of the queried matrix block, thereby realizing the control of the number and size of the circuit matrix blocks, thereby ensuring the normal operation of the subsequent circuit simulation process. In the final subgraph stack, the size of each subgraph is the size of the block. These subgraphs are arranged in a certain order, which can be the order in the subgraph stack, or they can be rearranged according to the computational load based on the subgraph size and the computing power of each node, or in any order. Since the subgraphs correspond to matrix blocks, the order of the subgraphs here is the left and right (up and down) order of the diagonal matrix blocks of the BBD matrix.

[0079] It should be noted that after completing the binary split of any original image in the original image stack and putting the resulting sub-image into the sub-image stack, the size and other information of all original images and sub-images in the current original image stack and sub-image stack can be obtained. Moreover, these original images and sub-images are independent of each other and can be operated independently.

[0080] Furthermore, as another preferred embodiment, a balance process can be performed based on the modified Metis, so that the sizes of the matrix blocks on the main diagonal of the final BBD matrix are roughly equal. The specific implementation method is to obtain the sizes of all original images popped out of the original image stack; preset a bipartite image size threshold based on the global information of all bipartite subgraphs obtained from the previous bipartite image, and if the size of the original image exceeds the preset bipartite image size threshold, the original image is divided into subgraphs to obtain a bipartite subgraph; otherwise, the original image is set to a bipartite subgraph. It can be seen that this method only needs to perform bisection on the subgraphs whose size exceeds the set threshold, without the need to perform the same number of bisections on all the images in the original image stack, thereby achieving control over the number and size of circuit matrix blocks, and thus ensuring the normal operation of the subsequent circuit simulation process.

[0081] In this embodiment, a loop-based breadth-first traversal algorithm obtained by modifying Metis can be used to select a serial processing or a parallel processing mode according to actual needs when bisecting each original image or sub-image of the original image stack.

[0082] Based on the double-boundary diagonal rearrangement form constructed in formula (1), the pre-rearranged matrix obtained in the above steps is rearranged in columns and rows using the double-boundary diagonal rearrangement form. Since Metis performs the same rearrangement on the rows and columns of the coefficient matrix, the rearranged result is U(C+hG)VQ→PU(C+hG)QVP T

[0083] Where P is the rearrangement matrix, which is the same size as the column rearrangement matrix Q. The only difference is the positional relationship between the two during the rearrangement process, so that the non-zero elements of the pre-rearrangement matrix are distributed on the diagonal and the right and lower boundaries, obtaining a double-boundary diagonal matrix.

[0084] Step S400: using a number of computing nodes to form distributed nodes, solving the local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and summing the local Schur complements to obtain the global Schur complement.

[0085] Specifically, several computing nodes are used to form a distributed node, and the data of the double-boundary diagonal matrix is ​​stored on the target node, and the target node is recorded as the main node, and the nodes other than the main node are recorded as child nodes; the data on the main node is broadcast to each child node through the first message passing interface function, and the local Schur complement of all distributed nodes is solved; the local Schur complement is summed up through the second message passing interface function to obtain the global Schur complement.

[0086] This embodiment uses the Message Passing Interface (MPI) to solve the local Schur's complement and global Schur's complement of each node. MPI is a message passing programming model and standard for parallel computing. MPI allows communication and synchronization between multiple processors or computing nodes, thereby realizing parallel computing of programs. In MPI, processes communicate by sending and receiving messages. This embodiment mainly uses two MPI communication functions: the broadcast message function (MPI_Bcast) and the global reduction function (MPI_Allreduce). The function of the former is to broadcast data from one node to all other nodes. The function of the latter is to collect data from all nodes, operate on it, and then return the result to all nodes. The operation used in this embodiment is addition, that is, obtaining the sum of the data of all nodes.

[0087] After using multiple computing nodes to form a distributed node, the matrix data is usually stored in a certain node. This node is called the master node and is numbered 0. The remaining nodes are called child nodes. Since the circuit matrix is ​​multiplied on both sides, Equation (5) can be rewritten as PU(C+hG)QVP T ·(QVP T ) -1 x (k+1) =PUCx (k) +hPUBu (k+1) =b (k+1) (6)

[0088] For simplicity, let A = PU(C + hG)QVP T (7)

[0089] Formula (6) can be rewritten as

[0090] The first equal sign of formula (6) is The other side is x, which means that each time we solve it, we need to calculate equation (5) once. Rewriting equation (6) gives:

[0091] For simplicity, remember

[0092] Substituting equations (8) and (5) into equation (6), we have

[0093] The process of solving the local and global Schur complements of each distributed node is actually solving the local Schur complement in formula (3). and global Schur complement

[0094] First, the local Schur complement is calculated. In order to make full use of hardware resources, each distributed node calculates the corresponding local Schur complement. The child node needs to obtain the matrix A from the master node. i ,E i ,F i ,A N To calculate the local Schur complement, the master node extracts each sub-matrix and sends it to the child nodes. However, this wastes hardware resources when there are many child nodes. Since the MPI_Bcast function is fast and matrix A is sparse, based on the data on the master node, the elements in the double-bounded diagonal matrix corresponding to each distributed node are filtered out. A block matrix is ​​constructed using the elements corresponding to each distributed node. Parallel computing is used to solve each block matrix to obtain the local Schur complement of each distributed node.

[0095] This embodiment chooses to use this function to broadcast A to all child nodes, and then the child nodes obtain the corresponding blocks. For all nodes, construct the block matrix of formula (13), that is,

[0096] Use a solver that supports partial LU decomposition to solve the local Schur complement to improve the solution speed and help reduce the simulation time. Then call the function MPI_Allreduce to obtain the sum of the local Schur complements and add it to A. N You get the global Shul complement.

[0097] Step S500: Based on the global Schur complement and the solution results of each distributed node at the previous moment, the current state of each distributed node is solved in parallel; based on column rearrangement and row and column rearrangement, the solution results of each distributed node at all times are converted into large-scale linear circuit simulation results.

[0098] Then, calculate the right side of the equal sign of formula (12). Comparing formulas (7) and (11), it is noted that the set of non-zero element positions of matrix C is a subset of the set of non-zero elements of C+hG. Therefore, the row and column rearrangement matrix of C+hG will also rearrange C into a BBD matrix. In other words, the matrix is a BBD matrix, that is

[0099] and The sub-matrices of are the same size as the corresponding sub-matrices of A.

[0100] Note hPUB = [B0 T … B N-1 T B N T ] T(15)

[0101] Among them B i The number of rows and C i The number of rows is consistent, combined with formulas (12), (14), (15)

[0102] In order to make the best use of hardware resources, this embodiment requires that each node solve Equation (3). At the same time, since the simulation result is a dense vector, in order to reduce memory usage, the characteristic that the matrix C can be converted into a BBD matrix in the same way as C+hG is used to obtain the modified formula (16). According to formula (16), each node only needs to store You can solve b independently i (k+1) , so the summation on the right side of the equal sign can be implemented by the function MPI_Allreduce.

[0103] Combining formulas (12), (14), and (15), we can obtain

[0104] Substituting equations (16) and (17) into equation (3), we can obtain

[0105] remember

[0106] then

[0107] and then

[0108] remember

[0109] So there is

[0110] So far, the solution results of all distributed nodes at all times have been obtained And the circuit simulation result X is obtained according to formula (23).

[0111] Specifically, the states of each distributed node at the current moment are solved in parallel based on the global Schur complement and the solution results of each distributed node at the previous moment; the rows of the large-scale linear circuit simulation results corresponding to the solution results of each distributed node at all moments are found based on the column rearrangement matrix and the double-boundary diagonal rearrangement matrix; all elements on the row are scaled according to the column scaling matrix to obtain the large-scale linear circuit simulation results.

[0112] This embodiment uses the characteristic that the matrix C can be converted into a BBD matrix in the same way as C+hG, so that each distributed node only needs to store the unknown quantity (x i(k) ) and the unknown quantities of the coupled part And independently calculate the right side vector of the equal sign corresponding to the matrix block Compared with the traditional process of directly calculating the vector on the right side of equation (5), it has three advantages: First, solving b (k+1) The amount of computation is distributed to each node, and the amount of computation is reduced to 1 / N on average compared to the traditional process; secondly, storage x (k) The required memory is also distributed to each node, and the memory usage is reduced to 1 / N on average compared to the traditional process; thirdly, since there is no need to store the entire x (k) Compared with the traditional process, it reduces the collection of The present invention reduces the number of communications by at least one compared to the traditional process.

[0113] The present invention constructs ordinary differential equations of linear circuits based on the scale of linear circuits, and converts the ordinary differential equations of linear circuits into large-scale sparse linear equations according to the Euler iteration method, which can effectively control the number and size of blocks of large-scale linear circuits, thereby ensuring the normal progress of subsequent simulation processes; and performs multiple mathematical transformations on the coefficient matrix according to set rules to obtain a coefficient matrix that satisfies the BBD form, and simplifies the large-scale sparse linear equations, so that each distributed node in the simulation process does not need to obtain a complete simulation result and calculate a complete simulation input to obtain a circuit simulation result, thereby reducing the amount of calculation, reducing memory usage, reducing the number of distributed node communications, and increasing the acceleration ratio.

[0114] Exemplary Systems

[0115] As shown in FIG4 , corresponding to the above-mentioned large-scale linear circuit simulation method, an embodiment of the present invention further provides a large-scale linear circuit simulation system. The large-scale linear circuit simulation system includes:

[0116] Initialization module 410, configured to construct an ordinary differential equation of the linear circuit according to the scale of the linear circuit, and convert the ordinary differential equation of the linear circuit into a large-scale sparse linear equation system according to the Euler iteration method;

[0117] A matrix pre-rearrangement module 420 is used to rearrange the coefficient matrix of the large-scale sparse linear equation system by rows or columns so that all diagonal elements of the coefficient matrix are non-zero, thereby obtaining a pre-rearranged matrix;

[0118] The matrix rearrangement module 430 is configured to rearrange the rows and columns of the pre-rearranged matrix using a graph partitioning algorithm so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix.

[0119] A Schur complement calculation module 440 is configured to use a plurality of computing nodes to form distributed nodes, solve the local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and sum the local Schur complements to obtain the global Schur complement;

[0120] Circuit simulation module 450 is used to solve the current state of each distributed node in parallel based on the global Schur complement and the solution results of each distributed node at the previous moment; based on column rearrangement and row and column rearrangement, the solution results of each distributed node at all times are converted into large-scale linear circuit simulation results.

[0121] Specifically, in this embodiment, the specific functions of the large-scale linear circuit simulation system can also refer to the corresponding description in the large-scale linear circuit simulation method, which will not be repeated here.

[0122] Based on the above embodiments, the present invention further provides a circuit simulator, a functional block diagram of which may be shown in FIG5 . The circuit simulator includes a simulation chip, a memory, and a large-scale linear circuit simulation program stored in the memory and executable on the simulation chip. When executed by the simulation chip, the large-scale linear circuit simulation program implements any of the steps of the above-described large-scale linear circuit simulation method.

[0123] Those skilled in the art will understand that the principle block diagram shown in Figure 5 is only a block diagram of a partial structure related to the solution of the present invention, and does not constitute a limitation on the circuit simulator to which the solution of the present invention is applied. The specific circuit simulator may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0124] An embodiment of the present invention also provides a computer-readable storage medium, which stores a large-scale linear circuit simulation program. When the large-scale linear circuit simulation program is executed by a processor, it implements the steps of any large-scale linear circuit simulation method provided by an embodiment of the present invention.

[0125] It should be understood that the sequence numbers of the steps in the above embodiments do not imply a specific order of execution; the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0126] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the above-mentioned device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0127] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0128] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0129] In the embodiments provided by the present invention, it should be understood that the disclosed apparatus / terminal device and method can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For example, the division of the modules or units described above is merely a logical functional division. In actual implementation, other division methods may be used. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.

[0130] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A large-scale linear circuit simulation method, characterized in that: The following steps are involved: Constructing an ordinary differential equation of the linear circuit according to the scale of the linear circuit, and converting the ordinary differential equation of the linear circuit into a large-scale sparse linear equation group according to the Euler iteration method; Rearranging the coefficient matrix of the large-scale sparse linear equation system by columns so that all diagonal elements of the coefficient matrix are non-zero, thereby obtaining a pre-rearranged matrix; Using a graph partitioning algorithm, the pre-rearranged matrix is ​​rearranged in rows and columns so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix; Using a plurality of computing nodes to form distributed nodes, solving the local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and summing each of the local Schur complements to obtain a global Schur complement; According to the global Schur complement and the solution results of each distributed node at the previous moment, the state of each distributed node at the current moment is solved in parallel; according to the column rearrangement and row and column rearrangement, the solution results of each distributed node at all moments are converted into the large-scale linear circuit simulation results.

2. The large-scale linear circuit simulation method according to claim 1, characterized in that: The method of utilizing a graph partitioning algorithm to rearrange the rows and columns of the pre-rearranged matrix so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries to obtain a double-boundary diagonal matrix includes: Creating an original image stack for storing an original image and a sub-image stack for storing sub-images obtained by binary division, wherein the original image refers to an undirected graph corresponding to the pre-rearrangement matrix; After the original images are taken out of the original image stack one by one, they are divided into two sub-images to obtain two sub-images; and the two sub-images are put into the sub-image stack until the original image stack is empty, and the original image stack and the sub-image stack are exchanged; Repeat the process of dividing each of the original images into two sub-images and exchanging the original image stack and the sub-image stack until the number of the two sub-images in the sub-image stack or the number of times the original image stack and the sub-image stack are exchanged reaches a preset number; The pre-rearranged matrix is ​​rearranged in rows and columns by using all the bipartite subgraphs, so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix.

3. The large-scale linear circuit simulation method according to claim 2, characterized in that: The step of taking the original images out of the original image stack one by one and dividing them into two sub-images to obtain two sub-images comprises: Obtaining the sizes of all original images popped from the original image stack; A bipartite graph size threshold is preset based on the global information of all the bipartite subgraphs obtained in the previous bipartite division. If the size of the original image exceeds the preset bipartite graph size threshold, the original image is divided into subgraphs to obtain a bipartite subgraph; otherwise, the original image is set to the bipartite subgraph.

4. The large-scale linear circuit simulation method according to claim 2 or 3, characterized in that: The method of rearranging the rows and columns of the pre-rearranged matrix by using all the bipartite subgraphs so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries to obtain a double-boundary diagonal matrix includes: Based on the dimension of the coefficient matrix, a column rearrangement matrix, a double-boundary diagonal rearrangement matrix, a row expansion matrix and a column expansion matrix are preset; Based on the column rearrangement matrix, the row expansion matrix and the column expansion matrix, the coefficient matrix has elements on the diagonal and the absolute value is 1, and the absolute value of the elements other than the elements on the diagonal does not exceed 1, thereby obtaining a pre-rearrangement matrix; A double-boundary diagonal rearrangement form is constructed based on the graph partitioning algorithm, and the double-boundary diagonal rearrangement form is used to rearrange the columns and rows of the pre-rearranged matrix to obtain a double-boundary diagonal matrix.

5. The large-scale linear circuit simulation method according to claim 1, characterized in that: The method of using a plurality of computing nodes to form a distributed node, solving the local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and summing each of the local Schur complements to obtain a global Schur complement includes: Using a number of computing nodes to form a distributed node, storing the data of the double-boundary diagonal matrix on a target node, and recording the target node as a main node, and recording nodes other than the main node as child nodes; Broadcasting the data on the master node to each of the child nodes through a first message passing interface function, and solving the local Schur complement of all the distributed nodes; The local Schur complements are summed up through a second message passing interface function to obtain a global Schur complement.

6. The large-scale linear circuit simulation method according to claim 5, characterized in that: The method of broadcasting the data on the master node to each of the child nodes through the first message passing interface function and solving the local Schur complement of all the distributed nodes includes: Based on the data on the master node, filter out the elements in the double-boundary diagonal matrix corresponding to each of the distributed nodes, and construct a block matrix using the elements corresponding to each of the distributed nodes; Each of the block matrices is solved in a parallel computing manner to obtain the local Schur complement of each of the distributed nodes.

7. The large-scale linear circuit simulation method according to claim 4, characterized in that: Converting the solution results of each of the distributed nodes at all times into the large-scale linear circuit simulation results, including: Solving the status of each of the distributed nodes at the current moment in parallel according to the global Schur complement and the solution results of each of the distributed nodes at the previous moment; Finding the rows of the large-scale linear circuit simulation results corresponding to the solution results of each of the distributed nodes at all times according to the column rearrangement matrix and the double-boundary diagonal rearrangement matrix; All elements on the row are scaled according to the column scaling matrix to obtain the large-scale linear circuit simulation result.

8. A large-scale linear circuit simulation system, characterized in that: The system comprises: An initialization module, used for constructing an ordinary differential equation of the linear circuit according to the scale of the linear circuit, and converting the ordinary differential equation of the linear circuit into a large-scale sparse linear equation group according to the Euler iteration method; A matrix pre-rearrangement module, used for rearranging the coefficient matrix of the large-scale sparse linear equation system by columns so that all diagonal elements of the coefficient matrix are non-zero, thereby obtaining a pre-rearranged matrix; A matrix rearrangement module, used to rearrange the rows and columns of the pre-rearranged matrix by using a graph partitioning algorithm, so that the non-zero elements of the pre-rearranged matrix are distributed on the diagonal and the right and lower boundaries, thereby obtaining a double-boundary diagonal matrix; A Schur complement calculation module, configured to use a plurality of computing nodes to form a distributed node, solve the local Schur complement of each distributed node based on the double-boundary diagonal matrix data, and sum each of the local Schur complements to obtain a global Schur complement; The circuit simulation module is used to solve the status of each of the distributed nodes at the current moment in parallel based on the global Schur complement and the solution results of each of the distributed nodes at the previous moment; and convert the solution results of each of the distributed nodes at all moments into the large-scale linear circuit simulation results based on the column rearrangement and row-column rearrangement.

9. A circuit simulator, characterized in that The circuit simulator includes a simulation chip, a memory, and a large-scale linear circuit simulation program stored in the memory and executable on the simulation chip. When the large-scale linear circuit simulation program is executed by the simulation chip, the steps of the large-scale linear circuit simulation method as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a large-scale linear circuit simulation program, which, when executed by a processor, implements the steps of the large-scale linear circuit simulation method as described in any one of claims 1 to 7.

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