Gate driving circuit and display panel

Abstract

A gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded shift registers; an Nth-stage shift register comprises a stage transmission signal selection module, a pull-up control module, a first filtering module, a second filtering module and a first output module; and the first part having a fixed width in a first pulse is retained, and then the first output module is controlled to output a gate driving signal having a width-fixed pulse at a corresponding time.

Description

Gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] In a display panel, a gate driving circuit generally provides required gate driving signals to transistors corresponding to pixel circuits.

[0003] However, the pulses of the gate drive signals provided by the gate drive circuits are not always able to meet the driving timing of the pixel circuits in terms of time and width, which is one of the reasons for improving the gate drive circuits. SUMMARY OF THE INVENTION

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem that the pulse of the gate driving signal is difficult to meet the requirements in terms of time and width.

[0005] In the first aspect, the present application provides a gate drive circuit, which includes multiple cascaded shift registers, and the Nth stage shift register includes a stage transmission signal selection module, a pull-up control module, a first filter module, a second filter module and a first output module, the stage transmission signal selection module is electrically connected between the first node and the first wiring; the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; the first filter module is electrically connected between the second node and the third node, and the control end of the first filter module is connected to the reset signal; the second filter module is electrically connected between the first filter module and the third node, and the control end of the second filter module is connected to the filter control signal with multiple pulses in one frame; the first output module outputs the first gate drive signal according to the potential of the third node and the potential of the fourth node.

[0006] In a second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, the pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor; the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG1 is a schematic structural diagram of a pixel circuit in related art.

[0008] FIG. 2 is a timing diagram of the pixel circuit shown in FIG. 1 .

[0009] FIG3 is a schematic diagram of a first structure of a gate drive circuit provided in an embodiment of the present application.

[0010] FIG4 is a timing diagram of the gate driving circuit shown in FIG3 .

[0011] FIG. 5 is a schematic diagram of the gate driving circuit shown in FIG. 3 in the first stage shown in FIG. 4 .

[0012] FIG. 6 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the second stage shown in FIG. 4 .

[0013] FIG. 7 is a schematic diagram showing the state of the gate driving circuit shown in FIG. 3 in the third stage shown in FIG. 4 .

[0014] FIG. 8 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the fourth stage shown in FIG. 4 .

[0015] FIG. 9 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the fifth stage shown in FIG. 4 .

[0016] FIG. 10 is a schematic diagram illustrating the gate driving circuit shown in FIG. 3 in the sixth stage shown in FIG. 4 .

[0017] FIG. 11 is a schematic diagram showing the state of the gate driving circuit shown in FIG. 3 in the seventh stage shown in FIG. 4 .

[0018] FIG. 12 is a schematic diagram showing the state of the gate driving circuit shown in FIG. 3 in the eighth stage shown in FIG. 4 .

[0019] FIG. 13 is a schematic diagram showing the gate driving circuit shown in FIG. 3 in the ninth stage shown in FIG. 4 .

[0020] FIG. 14 is a schematic diagram illustrating the gate driving circuit shown in FIG. 3 in the tenth stage shown in FIG. 4 .

[0021] FIG. 15 is a schematic diagram showing the gate driving circuit shown in FIG. 3 in the eleventh stage shown in FIG. 4 .

[0022] FIG. 16 is a schematic diagram illustrating the gate driving circuit shown in FIG. 3 in the twelfth stage shown in FIG. 4 .

[0023] FIG. 17 is a schematic diagram showing the gate driving circuit shown in FIG. 3 in the thirteenth stage shown in FIG. 4 .

[0024] FIG. 18 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the fourteenth stage shown in FIG. 4 .

[0025] FIG19 is a schematic diagram showing the state of the gate driving circuit shown in FIG3 in the fifteenth stage shown in FIG4.

[0026] FIG20 is a second structural diagram of the gate drive circuit provided in an embodiment of the present application.

[0027] FIG21 is a timing diagram of the gate driving circuit shown in FIG20 .

[0028] FIG22 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the first stage in FIG21 .

[0029] FIG23 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the second stage in FIG21 .

[0030] FIG24 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the third stage in FIG21 .

[0031] FIG25 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the fourth stage in FIG21 .

[0032] FIG26 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the fifth stage in FIG21 .

[0033] FIG27 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the sixth stage in FIG21 .

[0034] FIG28 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the seventh stage in FIG21 .

[0035] FIG29 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the eighth stage shown in FIG21.

[0036] Figure 30 is a timing diagram of the generation of the Nth level negative pulse gate drive signal provided in an embodiment of the present application.

[0037] FIG31 is a schematic diagram of the cascade structure between shift registers in the gate drive circuit shown in FIG3 or FIG20.

[0038] FIG32 is a schematic diagram of the structure of the display panel provided in an embodiment of the present application.

[0039] FIG33 is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.

[0040] FIG34 is a timing diagram of the pixel circuit shown in FIG33 . Modes for Carrying Out the Invention

[0041] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0042] In the gate drive circuit in the invention application with application number 202310191137.9, the N-level negative pulse gate drive signal Pout[N] has one negative pulse in one frame. The N-level positive pulse gate drive signal Nout[N] has two positive pulses in one frame, and the pulse widths of the two positive pulses must be equal and both have a width of 2H. This restricts the width of the positive pulse of the N-level positive pulse gate drive signal Nout[N] to remain consistent and cannot be changed, so that when the width of the positive pulse of the N-level positive pulse gate drive signal Nout[N] is greater than 2H, the number of negative pulses of the N-level negative pulse gate drive signal Pout[N] in one frame will increase.

[0043] Therefore, this will limit the pixel circuit shown in Figure 1 to operate according to the timing shown in Figure 2. Specifically, the pixel circuit shown in Figure 1 may include at least one of a write transistor T2P, a drive transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and a bootstrap capacitor CbOst.

[0044] The first power line is electrically connected to the first electrode of the first light-emitting control transistor T5P and one end of the storage capacitor Cst, the second electrode of the first light-emitting control transistor T5P is electrically connected to the first electrode of the driving transistor T1P and the first electrode of the writing transistor T2P, the second electrode of the driving transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light-emitting control transistor T6P, the second electrode of the second light-emitting control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and the anode of the light-emitting device D1, and the cathode of the light-emitting device D1 is electrically connected to the second power line.

[0045] The light emission control line is electrically connected to the gate of the first light emission control transistor T5P and the gate of the second light emission control transistor T6P.

[0046] The second electrode of the write transistor T2P is electrically connected to the data line, and the gate of the write transistor T2P is electrically connected to the first scan line and one end of the bootstrap capacitor CbOst. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is electrically connected to the second scan line.

[0047] A second electrode of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and a gate of the compensation transistor T3P is electrically connected to the third scan line.

[0048] The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor CbOst, and the first electrode of the first initialization transistor T4P.

[0049] A second electrode of the first initialization transistor T4P is electrically connected to the first initialization line, and a gate of the first initialization transistor T4P is electrically connected to the fourth scan line.

[0050] A first electrode of the third initialization transistor T8P is electrically connected to the first electrode of the driving transistor T1P, a second electrode of the third initialization transistor T8P is electrically connected to the third initialization line, and a gate of the third initialization transistor T8P and a gate of the second initialization transistor T7P share the second scan line.

[0051] It should be noted that the second initialization line can also be replaced by the first initialization line, which can reduce one wiring required for the pixel circuit and help increase the density of the pixel circuit in the display panel.

[0052] In this application, the first electrode can be either a source electrode or a drain electrode, and the second electrode can be the other of the source electrode and the drain electrode. For example, when the first electrode is a source electrode, the second electrode is a drain electrode; or when the first electrode is a drain electrode, the second electrode is a source electrode.

[0053] The first power line is used to transmit a positive power signal VDD, and the second power line is used to transmit a negative power signal VSS. The potential of the positive power signal VDD is higher than that of the negative power signal VSS. The data line is used to transmit a data signal Data. The light control line is used to transmit a light control signal EM. The first initialization line is used to transmit a first initialization signal Vi1. The second initialization line is used to transmit a second initialization signal. The third initialization line is used to transmit a third initialization signal Vi3. The first scan line is used to transmit a gate drive signal Pout[N]. The second scan line is used to transmit a gate drive signal Pscan2. The third scan line is used to transmit a gate drive signal Nout[N]. The fourth scan line is used to transmit a gate drive signal Nout[N-1].

[0054] Among them, the gate drive signal Pout[N], the gate drive signal Nout[N-1], and the gate drive signal Nout[N] can be provided by the gate drive circuit in the invention application with application number 202310191137.9. The gate drive signal Pout[N] is derived from the Nth level negative pulse gate drive signal Pout[N], the gate drive signal Nout[N] is derived from the Nth level positive pulse gate drive signal Nout[N], and the gate drive signal Nout[N-1] is derived from the N-1th level positive pulse gate drive signal Nout[N-1].

[0055] As can be seen from the above, in the invention application with application number 202310191137.9, the principle of generating a negative pulse in a frame of the N-th level negative pulse gate drive signal Pout[N] is to filter out the first pulse of the start control signal STV or the NY-th level positive pulse gate drive signal Nout[NY] by the second pulse of the reset signal RST. Therefore, the widths of the two positive pulses of the start control signal STV or the NY-th level positive pulse gate drive signal Nout[NY] must be equal.

[0056] In the pixel circuit shown in FIG1 , in order to achieve synchronous conduction of the compensation transistor T3P and the first initialization transistor T4P, the pulse of the gate drive signal Nout[N-1] needs to partially overlap with the pulse of the gate drive signal Nout[N]. This is why the first initialization transistor T4P in the pixel circuit shown in FIG1 must be connected to the gate drive signal Nout[N-1].

[0057] Furthermore, in order to complete the transmission of the third initialization signal Vi3 via node A and node B to node Q in sequence to reset the potentials of node A, node B, and node Q, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously, which requires the pulse of the gate drive signal Pscan2 to partially overlap with the pulse of the gate drive signal Nout[N].

[0058] In order for the pixel circuit shown in Figure 1 to continue to use the gate drive signal Pscan2 with a pulse width of only 1H, it is necessary to adjust the drive timing of the pixel circuit shown in Figure 2. Correspondingly, it is also necessary to improve the gate drive circuit in the invention application with application number 202310191137.9.

[0059] In this context, in order to alleviate the technical problem that the pulse of the gate drive signal is difficult to meet the requirements in terms of time and width, the present embodiment provides a gate drive circuit, please refer to Figures 3 to 30. As shown in Figures 3 and 20, the gate drive circuit includes multiple cascaded shift registers, and the Nth stage shift register includes a stage signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80 and at least one of the first output module 46.

[0060] The stage transfer signal selection module 10 is electrically connected between the first node O and the first wiring, and Y is an integer greater than or equal to 1.

[0061] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O and the potential of the first clock signal.

[0062] The first filter module 30 is electrically connected between the second node K and the third node Q. The control terminal of the first filter module 30 is connected to the reset signal RST.

[0063] The second filtering module 80 is electrically connected between the first filtering module 30 and the third node Q. The control terminal of the second filtering module 80 is connected to the filtering control signal RST2 having a plurality of pulses in one frame.

[0064] The first output module 46 outputs a first gate driving signal according to the potential of the third node Q and the potential of the fourth node P.

[0065] It can be understood that the gate drive circuit provided in this embodiment filters out the first part of the second pulse that appears later than the second node K in a frame through the first filtering module 30, and filters out the second part of the first pulse that appears first and the second pulse that appears later than the second node K in a frame through the second filtering module 80. The first part of the fixed width in the first pulse can be retained, and then the first output module 46 is controlled to output the gate drive signal of the pulse with the fixed width at the corresponding time. After such improvement, it can be suitable for the driving requirements of the back end.

[0066] In one embodiment, the N-th stage shift register further includes a first inverting module 50 and a second output module 70. The first inverting module 50 is electrically connected between the second node K and the fourth node P; the second output module 70 outputs a second gate driving signal according to the potential of the second node K.

[0067] It can be understood that after the improvement shown in Figures 3 and 20 to Figure 1, since the first filtering module 30 can filter out the first part of the second pulse that appears later in a frame at the second node K, and the second filtering module 80 can filter out the second part of the first pulse that appears first and the second pulse that appears later in a frame at the second node K, the first part of the fixed width in the first pulse can be retained, and then the first output module 46 is controlled to output a gate drive signal with a pulse of the fixed width at a corresponding time. The pulse width of the N-level positive pulse gate drive signal Nout[N] provided by the second output module 70 does not affect the pulse width of the N-level negative pulse gate drive signal Pout[N]. Therefore, the two pulse widths of the N-level positive pulse gate drive signal Nout[N] in a frame can not only be modulated to a width greater than 2H, but also can be modulated separately without having to keep the two pulse widths equal. This provides support for improving the driving timing of the pixel circuit.

[0068] In one embodiment, the frequency of the second gate driving signal is the same as the frequency of the filter control signal RST2 , and the phase of the second gate driving signal is different from the phase of the filter control signal RST2 .

[0069] It should be noted that in this embodiment, the shifted N-th stage positive pulse gate drive signal Nout[N], for example, the N-2-th stage positive pulse gate drive signal Nout[N-2], can be used as the filter control signal RST2. This not only obtains the desired first gate drive signal and second gate drive signal, but also avoids the need to introduce an external control signal as the filter control signal RST2. In other embodiments, an external control signal can also be used as the filter control signal RST2. In other embodiments, the potential of the fourth node P in the N-2-th stage shift register can also be used as the filter control signal RST2.

[0070] In other embodiments, other levels of positive pulse gate driving signals may be selected according to the requirements of the first gate driving signal and the second gate driving signal.

[0071] In one embodiment, the frequency of the second gate driving signal is the same as the frequency of the reset signal RST, and the phase of the second gate driving signal is different from the phase of the reset signal RST.

[0072] It should be noted that in this embodiment, the shifted Nth-stage positive pulse gate drive signal Nout[N], for example, the NXth-stage positive pulse gate drive signal Nout[NX], can be used as the reset signal RST. This not only obtains the desired first gate drive signal and second gate drive signal, but also avoids the need for an external control signal to be used as the reset signal RST. In other embodiments, an external control signal can also be used as the reset signal RST. In other embodiments, the potential of the fourth node P in the NXth-stage shift register can also be used as the reset signal RST. Wherein, X is an integer greater than or equal to 2.

[0073] In one embodiment, as shown in Figures 3 and 20, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2, one of the source or the drain of the first filtering transistor T11 is electrically connected to the second node K, the other of the source or the drain of the first filtering transistor T11 is electrically connected to the third node Q, and the gate of the first filtering transistor T11 is connected to the reset signal RST; one end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or the drain of the first filtering transistor T11.

[0074] It should be noted that, as shown in FIG30 , the first filtering module 30 is used to filter out the first part of the second pulse that appears after the second node K in one frame.

[0075] In one embodiment, as shown in Figures 3 and 20, the second filtering module 80 includes a second filtering transistor T8, one of the source or the drain of the second filtering transistor T8 is electrically connected to the first filtering module 30, the other of the source or the drain of the second filtering transistor T8 is electrically connected to the third node Q, and the gate of the second filtering transistor T8 is connected to the filtering control signal RST2.

[0076] It should be noted that, as shown in FIG30 , the second filtering module 80 is used to filter out the latter part of the first pulse that appears first and the latter part of the second pulse that appears later at the second node K in a frame.

[0077] It can be seen from this that the first filtering module 30 and the second filtering module 80 are used to filter out the second pulse and retain the first portion of the first pulse with a fixed width.

[0078] In one embodiment, as shown in FIG20 , the Nth stage shift register further includes an isolation module 75 , which is connected in series between the second node K and the input end of the second output module 70 , and a control end of the isolation module 75 is connected to the first clock signal.

[0079] It should be noted that the isolation module 75 is used to reduce the coupling of the pulse amplitude of the N-th level negative pulse gate drive signal Pout[N] to the pulse amplitude of the N-th level positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the N-th level positive pulse gate drive signal Nout[N].

[0080] In one embodiment, as shown in FIG20 , the isolation module 75 includes an isolation transistor T14, one of the source or the drain of the isolation transistor T14 is electrically connected to the second node K, the other of the source or the drain of the isolation transistor T14 is electrically connected to the input end of the second output module 70, the gate of the isolation transistor T14 is connected to the first clock signal, and the isolation transistor T14 is a P-channel thin film transistor.

[0081] It should be noted that the isolation transistor T14 can reduce the coupling of the pulse amplitude of the N-th level negative pulse gate drive signal Pout[N] to the pulse amplitude of the N-th level positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the N-th level positive pulse gate drive signal Nout[N].

[0082] In other embodiments, the isolation module 75 may further include a transistor connected in series between the gate of the isolation transistor T14 and the node N.

[0083] The input end of the level transmission signal selection module 10 is electrically connected to the start control line or the NY-th level positive pulse scanning line, wherein N is an integer greater than or equal to 1, and Y is an integer greater than or equal to 1.

[0084] An input end of the pull-up control module 20 is electrically connected to an output end of the stage transmission signal selection module 10 , and a control end of the pull-up control module 20 is electrically connected to the first clock line.

[0085] An input terminal of the first filter module 30 is electrically connected to an output terminal of the pull-up control module 20 , and a control terminal of the first filter module 30 is electrically connected to a reset line.

[0086] The input end of the second output module 70 is electrically connected to the input end of the pull-up control module 20, and the output end of the second output module 70 is electrically connected to the N-th level positive pulse scanning line. The number of positive pulses output by the N-th level positive pulse scanning line in one frame is greater than the number of negative pulses output by the N-th level negative pulse scanning line in one frame.

[0087] In one embodiment, the first output module 46 includes a pull-up module 40 and a pull-down module 60. The control terminal of the pull-up module 40 is electrically connected to the output terminal of the first filter module 30, the input terminal of the pull-up module 40 is electrically connected to the second clock line, and the output terminal of the pull-up module 40 is electrically connected to the Nth stage negative pulse scan line. The input terminal of the first inverting module 50 is electrically connected to the output terminal of the pull-up control module 20.

[0088] The control end of the pull-down module 60 is electrically connected to the output end of the first inverting module 50 , the input end of the pull-down module 60 is electrically connected to the high potential line, and the output end of the pull-down module 60 is electrically connected to the Nth stage negative pulse scanning line.

[0089] It should be noted that the first wiring can be a starting control line or a NY-th level positive pulse scan line; when NY is less than or equal to 0, the first wiring is the starting control line. The N-th level positive pulse scan line, i.e., the second gate control line, is used to transmit the N-th level positive pulse gate drive signal Nout[N], i.e., the second gate drive signal. The N-th level negative pulse scan line, i.e., the first gate control line, is used to transmit the N-th level negative pulse gate drive signal Pout[N], i.e., the first gate drive signal.

[0090] In one embodiment, a ratio of a channel width of the first filter transistor T11 to a channel length of the first filter transistor T11 is greater than or equal to 0.5 and less than or equal to 1.5.

[0091] It should be noted that this embodiment is conducive to ensuring the output stability of the Nth-level negative pulse gate drive signal Pout[N], and avoids the coupling pull-down phenomenon before the negative pulse arrives.

[0092] In one embodiment, the pull-up module 40 includes a pull-up transistor T6 and a second capacitor C1, the gate of the pull-up transistor T6 is electrically connected to one of the source or drain of the first filter transistor T11, one of the source or drain of the pull-up transistor T6 is electrically connected to the second clock line, and the other of the source or drain of the pull-up transistor T6 is electrically connected to the N-level negative pulse scan line; one end of the second capacitor C1 is electrically connected to the gate of the pull-up transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the source or drain of the pull-up transistor T6; wherein, the ratio of the capacity of the first capacitor C2 to the second capacitor C1 is greater than or equal to 0.5.

[0093] It should be noted that the design of the capacitance ratio of the first capacitor C2 to the second capacitor C1 in this embodiment is conducive to further ensuring the output stability of the Nth level negative pulse gate drive signal Pout[N], and avoiding the coupling pull-down phenomenon before the negative pulse arrives.

[0094] Specifically, the capacity of the first capacitor C2 may be greater than or equal to 50 fF, and the capacity of the second capacitor C1 may be greater than or equal to 100 fF.

[0095] The ratio of the channel width of the pull-up transistor T6 to its channel length is greater than 30:1, which is beneficial to further ensure the output stability of the Nth stage negative pulse gate drive signal Pout[N]. The pull-up transistor T6 can be a P-channel thin film transistor.

[0096] In one embodiment, the stage transmission signal selection module 10 includes a transistor T13 and a transistor T12, one of the source or the drain of the transistor T13 is electrically connected to the low potential line, the other of the source or the drain of the transistor T13 is electrically connected to the input end of the pull-up control module 20, the first gate of the transistor T13 is electrically connected to the start control line or the NY-th stage positive pulse scan line, the first gate of the transistor T13 is electrically connected to the second gate of the transistor T13, and the transistor T13 is an N-channel thin film transistor; one of the source or the drain of the transistor T12 is electrically connected to the high potential line, the other of the source or the drain of the transistor T12 is electrically connected to the other of the source or the drain of the transistor T13, the gate of the transistor T12 is electrically connected to the first gate of the transistor T13, and the transistor T12 is a P-channel thin film transistor.

[0097] It should be noted that, in this embodiment, the level transmission signal selection module 10 not only objectively has an inverting effect, that is, the potentials of the input signal and the output signal are opposite at the same time, but also plays the role of making the N-th level positive pulse gate drive signal Nout[N] serve as the level transmission signal between the shift registers. Otherwise, level transmission cannot be achieved between the shift registers, which will cause the gate drive circuit to be unable to normally provide the corresponding gate drive signal.

[0098] The ratio of the channel width of the transistor T13 to the channel length of the transistor T13 is greater than 2:1. The ratio of the channel width of the transistor T12 to the channel length of the transistor T12 is in the range of 0.5:1 to 3:1.

[0099] The high-potential line is used to transmit a high-potential signal VGH, which can turn on an N-channel thin-film transistor or turn off a P-channel thin-film transistor. The low-potential line is used to transmit a low-potential signal VGL, which can turn on a P-channel thin-film transistor or turn off an N-channel thin-film transistor.

[0100] In one embodiment, the pull-up control module 20 includes a pull-up control transistor T2, one of the source or drain of the pull-up control transistor T2 is electrically connected to the output end of the stage transmission signal selection module 10, the other of the source or drain of the pull-up control transistor T2 is electrically connected to the input end of the first filtering module 30, and the gate of the pull-up control transistor T2 is electrically connected to the first clock line.

[0101] It should be noted that the pull-up control transistor T2 may be a P-channel thin film transistor, and the ratio of the channel width of the pull-up control transistor T2 to the channel length of the pull-up control transistor T2 is in the range of 0.5:1 to 3:1.

[0102] In one embodiment, the first inverting module 50 includes a transistor T3 and a transistor T1, one of the source or the drain of the transistor T3 is electrically connected to the high potential line, the other of the source or the drain of the transistor T3 is electrically connected to one of the source or the drain of the transistor T1 and the control end of the pull-down module 60, the other of the source or the drain of the transistor T1 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the transistor T3, the first gate of the transistor T1, and the second gate of the transistor T1.

[0103] It should be noted that the transistor T3 is a P-channel thin film transistor, and the transistor T1 is a dual-gate N-channel thin film transistor. This can improve the dynamic performance of the transistors T3 and T1, and further improve the dynamic performance of the first inverter module 50.

[0104] The ratio of the channel width of the transistor T3 to the channel length of the transistor T3 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the transistor T1 to the channel length of the transistor T1 is greater than or equal to 2:1.

[0105] In one embodiment, the pull-down module 60 includes a pull-down transistor T7, one of the source or drain of the pull-down transistor T7 is electrically connected to the high potential line, the other of the source or drain of the pull-down transistor T7 is electrically connected to the N-th level negative pulse scan line, and the gate of the pull-down transistor T7 is electrically connected to the output end of the first inverting module 50, namely the fourth node P.

[0106] It should be noted that the pull-down transistor T7 can be a P-channel thin film transistor. Under the joint action of the pull-down module 60 and the pull-up module 40, the required Nth level negative pulse gate driving signal Pout[N] can be modulated.

[0107] The ratio of the channel width of the pull-down transistor T7 to the channel length of the pull-down transistor T7 is greater than or equal to 30:1.

[0108] In one embodiment, the second output module 70 includes a transistor T9 and a transistor T10, one of the source or drain of the transistor T9 is electrically connected to the high potential line, the other of the source or drain of the transistor T9 is electrically connected to one of the source or drain of the transistor T10 and the N-th level positive pulse scan line, the other of the source or drain of the transistor T10 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the transistor T9, the first gate of the transistor T10, and the second gate of the transistor T10.

[0109] It should be noted that the transistor T9 is a P-channel thin film transistor and the transistor T10 is a dual-gate N-channel thin film transistor. This can improve the dynamic performance of the transistors T9 and T10, and thus improve the dynamic performance of the second output module 70.

[0110] The ratio of the channel width of the transistor T9 to the channel length of the transistor T9 is greater than or equal to 30:1. The ratio of the channel width of the transistor T10 to the channel length of the transistor T10 is greater than or equal to 30:1.

[0111] In one embodiment, the N-th stage shift register further includes a feedback module 90, which includes a transistor T4 and a transistor T5, wherein one of the source or the drain of the transistor T4 is electrically connected to the output end of the pull-up control module 20, the gate of the transistor T4 is electrically connected to the second clock line, the other of the source or the drain of the transistor T4 is electrically connected to one of the source or the drain of the transistor T5, the other of the source or the drain of the transistor T5 is electrically connected to the high potential line, and the gate of the transistor T5 is electrically connected to the output end of the first inversion module 50.

[0112] The ratio of the channel width of the transistor T4 to the channel length of the transistor T4 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the transistor T5 to the channel length of the transistor T5 is in the range of 0.5:1 to 3:1.

[0113] It should be noted that the feedback module 90 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the second clock line. That is, when the fourth node P is at a low potential and the second clock signal CK is at a low potential, the high potential line can control the potential of the second node K to the potential of the high potential signal VGH.

[0114] It should be noted that the N-th level positive pulse scan line is used to transmit the N-th level positive pulse gate drive signal Nout[N]. The N-th level negative pulse scan line is used to transmit the N-th level negative pulse gate drive signal Pout[N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The NY-th level positive pulse scan line is used to transmit the NY-th level positive pulse gate drive signal Nout[NY]. The NX-th level positive pulse scan line is used to transmit the NX-th level positive pulse gate drive signal Nout[NX]. The reset line is used to transmit the reset signal RST.

[0115] For other parts of the gate drive circuit shown in Figures 3 and 20, please refer to the detailed introduction of the gate drive circuit shown in Figure 1, and will not be described in detail here.

[0116] The operation process of the shift register shown in FIG3 in one frame may include the following stages as shown in FIG4:

[0117] Phase 1 S1: As shown in Figures 4 and 5, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the first clock signal XCK is at a high potential, the first node O, the second node K, the node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0118] Second stage S2: As shown in Figures 4 and 6, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the second clock signal CK is at a high potential, the first node O, the second node K, the node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0119] The third stage S3: as shown in Figures 4 and 7, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the first clock signal XCK are at a high potential, the first node O, the second node K, the node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0120] The fourth stage S4: as shown in Figures 4 and 8, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the first node O, the second node K, the node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0121] Fifth stage S5: As shown in Figures 4 and 9, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, the node W and the third node Q are all at a high potential, the first node O and the fourth node P are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0122] The sixth stage S6: as shown in Figures 4 and 10, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the node W, the fourth node P and the third node Q are all at a high potential, the second node K and the first node O are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0123] The seventh stage S7: as shown in Figures 4 and 11, the reset signal RST and the second clock signal CK are at a low level, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high level, the fourth node P and the third node Q are both at a high level, the node W, the second node K, and the first node O are at a low level, the Nth level positive pulse gate drive signal Nout[N] is at a high level, and the Nth level negative pulse gate drive signal Pout[N] is at a high level.

[0124] The eighth stage S8: as shown in Figure 4 and Figure 12, the reset signal RST and the first clock signal XCK are at a low potential, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the fourth node P and the third node Q are both at a high potential, the node W, the second node K, and the first node O are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0125] Ninth stage S9: As shown in Figures 4 and 13, the second clock signal CK and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST, the start control signal STV, and the first clock signal XCK are at a high potential, the node W, the first node O, the fourth node P and the third node Q are all at a high potential, the second node K is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0126] The tenth stage S10: As shown in Figures 4 and 14, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the second node K, the node W, the first node O and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0127] The eleventh stage S11: as shown in Figures 4 and 15, the reset signal RST and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the start control signal STV, the first clock signal XCK, and the second clock signal CK are at a high potential, the fourth node P and the third node Q are all at a high potential, the second node K, the node W, and the first node O are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0128] The twelfth stage S12: the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the fourth node P and the first node O are both at a high potential, the third node Q, the second node K, and the node W are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a low potential.

[0129] Thirteenth stage S13: as shown in Figures 4 and 17, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the node W, the third node Q, and the first node O are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0130] Fourteenth stage S14: as shown in Figures 4 and 18, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the second node K, the node W, the third node Q, and the first node O are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0131] Fifteenth stage S15: As shown in Figures 4 and 19, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the node W, the third node Q, and the first node O are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0132] It should be noted that the "cross" in Figures 5 to 19 indicates that the transistor covered by it is in the off state, and the transistor not covered by the "cross" is in the on state. The dotted arrows in Figures 5 to 19 indicate the direction of current.

[0133] The operation process of the shift register shown in FIG20 in one frame may include the following stages as shown in FIG21:

[0134] First stage S1: As shown in Figures 21 and 22, the start control signal STV and the second clock signal CK are both at a low potential, the first clock signal XCK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0135] Second stage S2: As shown in Figures 21 and 23, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0136] The third stage S3: As shown in Figures 21 and 24, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0137] Fourth stage S4: As shown in Figures 21 and 25, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0138] Fifth stage S5: As shown in Figures 21 and 26, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0139] Sixth stage S6: As shown in Figures 21 and 27, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0140] Seventh stage S7: As shown in Figure 21 and Figure 28, the start control signal STV and the second clock signal CK are at a low potential, the first clock signal XCK is at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0141] The eighth stage S8: As shown in Figures 21 and 29, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the N-th level positive pulse gate drive signal Nout[N] is switched from a high potential to a low potential.

[0142] It should be noted that the "crosses" in Figures 22 to 29 indicate that the transistors covered by them are in the off state, and the transistors not covered by the "crosses" are in the on state. The dotted arrows in Figures 22 to 29 indicate the direction of current.

[0143] Based on the above, Figure 30 illustrates the negative pulse generation process of the Nth-level negative pulse gate drive signal Pout[N]. For clarity, the two pulses from right to left in the same signal are referred to as the first pulse and the second pulse, respectively. The second node K transmits the first pulse and the second pulse in a frame. The high voltage of the first portion of the two pulses of the N-2th-level positive pulse gate drive signal Nout[N-2] controls the second filter module 80 to filter out the latter portions of the first pulse and the second pulse output from the second node K. The high voltage of the latter portion of the first pulse of the reset signal RST controls the first filter module 30 to filter out the former portion of the second pulse output from the second node K. At this point, the width of the second pulse at node W is also narrowed. The second pulse output from the second node K is completely filtered out, leaving only the former portion of the first pulse output from the second node K, forming a negative pulse at the third node Q. This negative pulse at the third node Q activates the pull-up module 40, forming a negative pulse of the Nth-level negative pulse gate drive signal Pout[N] with a fixed width.

[0144] FIG31 is a schematic diagram illustrating the cascaded structure of different shift registers in the gate drive circuit shown in FIG3 or FIG20 . Arranged from top to bottom are the first-stage shift register, the second-stage shift register, the third-stage shift register, the Nth-stage shift register, the N+1th-stage shift register, and so on. Each shift register operates based on the first clock signal XCK and the second clock signal CK.

[0145] The control terminals of the first filter module 30 and the second filter module 80 in the first-stage shift register are both connected to the low-voltage signal VGL, and the input terminal (IN) of the first-stage shift register connected to the start control line is connected to the start control signal STV. The first-stage shift register outputs the corresponding first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1]. The first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1] are used to drive dummy pixels (Dummy) or are left floating.

[0146] The control terminals of the first filter module 30 and the second filter module 80 in the second-stage shift register are both connected to the low-voltage signal VGL, and the starting control line connected to the second-stage shift register is connected to the cascade signal, namely the first-stage positive pulse gate drive signal Nout[1]. The second-stage shift register outputs the corresponding second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2]. The second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2] are used to drive dummy pixels (Dummy) or are left floating.

[0147] The control terminals of the first filter module 30 and the second filter module 80 in the third-stage shift register are both connected to the low-voltage signal VGL, and the starting control line connected to the third-stage shift register is connected to the cascade signal, namely the second-stage positive pulse gate drive signal Nout[2]. The third-stage shift register outputs the corresponding third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3]. The third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3] are used to drive dummy pixels (Dummy) or leave them floating.

[0148] The same logic can be applied to other control lines, until the control terminals of the first filter module 30 and the second filter module 80 in the N-th shift register are connected to the NX-th positive pulse gate drive signal Nout[NX] and the N-2-th positive pulse gate drive signal Nout[N-2], respectively. The starting control line connected to the N-th shift register is connected to the cascade signal, namely the N-1-th positive pulse gate drive signal Nout[N-1]. The N-th shift register outputs the corresponding N-th negative pulse gate drive signal Pout[N] and the N-th positive pulse gate drive signal Nout[N]. The N-th negative pulse gate drive signal Pout[N] and the N-th positive pulse gate drive signal Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0149] The control terminals of the first filter module 30 and the second filter module 80 in the N+1-stage shift register are connected to the N-X+1-stage positive pulse gate drive signal Nout[N-X+1] and the N-1-stage positive pulse gate drive signal Nout[N-1], respectively. The starting control line connected to the N+1-stage shift register is connected to the cascade signal, namely the N-stage positive pulse gate drive signal Nout[N]. The N+1-stage shift register outputs the corresponding N+1-stage negative pulse gate drive signal Pout[N+1] and the N+1-stage positive pulse gate drive signal Nout[N+1]. The N+1-stage negative pulse gate drive signal Pout[N+1] and the N+1-stage positive pulse gate drive signal Nout[N+1] are used to drive the second row of pixel circuits (Pixel).

[0150] The same logic can be applied to the other subsequent shift registers. It should be noted that, since the output terminals of some shift registers are connected to dummy pixels or left floating, the output terminals of the Nth stage shift register are not connected to the Nth row of pixel circuits. Instead, the number of rows of connected pixel circuits needs to be determined based on the number of shift registers connected to dummy pixels or left floating. For example, if the 1st to 3rd stage shift registers are connected to dummy pixels, then the output terminals of the Nth stage shift register are connected to the N-3rd row of pixel circuits.

[0151] The display panel shown in Figure 32 includes pixel circuits (Pixel) distributed in an array in the display area, a first gate driving circuit 151 providing a light-emitting control signal EM, a fourth gate driving circuit 154 providing a gate driving signal Pscan2, a second gate driving circuit 152 providing an N-level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan, and a third gate driving circuit 153 providing an N-level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan.

[0152] The first gate driving circuit 151 can be located on the left side of the display area. The output end of each shift register in the first gate driving circuit 151 provides a light emitting control signal EM to two adjacent rows of pixel circuits through the corresponding light emitting control line, which is a unilateral drive.

[0153] The fourth gate driving circuit 154 can be located on the right side of the display area. The output end of each shift register in the fourth gate driving circuit 154 provides a gate driving signal Pscan2 to a row of pixel circuits through a corresponding gate driving line, which is a unilateral driving.

[0154] The second gate drive circuit 152 is located between the first gate drive circuit 151 and the display area. The third gate drive circuit 153 is located between the fourth gate drive circuit 154 and the display area. A scan line that transmits the N-th level negative pulse gate drive signal Pout[N] is electrically connected to the output of a shift register in the second gate drive circuit 152, the output of a shift register in the third gate drive circuit 153, and a row of pixel circuits. A gate drive line that transmits the gate drive signal Nscan is electrically connected to the output of a shift register in the second gate drive circuit 152, the output of a shift register in the third gate drive circuit 153, and a row of pixel circuits, demonstrating bilateral drive.

[0155] The second gate drive circuit 152 and the third gate drive circuit 153 can both adopt the gate drive circuits shown in Figures 3 and 20. The gate drive signal Nscan can include the Nth level positive pulse gate drive signal Nout[N] and the N-3th level positive pulse gate drive signal Nout[N-3].

[0156] Since it is necessary for the gate of the first initialization transistor T4P in the pixel circuit shown in Figure 1 to be connected to the N-1th level positive pulse gate drive signal Nout[N-1], after the gate of the write transistor T2P in the pixel circuit shown in Figure 33 is connected to the Nth level negative pulse gate drive signal Pout[N] and the gate of the compensation transistor T3P is connected to the Nth level positive pulse gate drive signal Nout[N], not only can the gate of the third initialization transistor T8P continue to use the existing gate drive signal Pscan2 (there is no need to improve the fourth gate drive circuit 154), the gate of the first initialization transistor T4P can also be replaced with the N-3th level positive pulse gate drive signal Nout[N-3].

[0157] After that, the pixel circuit shown in Figure 33 can not only operate in the existing stage P12 in Figure 34 in one frame, but also add an additional stage P11. In this stage P11, the first initialization transistor T4P and the compensation transistor T3P can be synchronously turned on to reset the potentials of the three terminals (Q, A, B) of the driving transistor T1P, so as to reduce the drift of the threshold voltage of the driving transistor T1P and improve the flicker under different refresh frequencies.

[0158] In one embodiment, this embodiment provides a display panel, which includes the gate driving circuit and the pixel circuit in at least one of the above embodiments.

[0159] It can be understood that since the display panel provided in this embodiment includes the gate drive circuit of at least one of the above-mentioned embodiments, the first filtering module 30 can also filter out the first part of the second pulse that appears later than the second node K in a frame, and the second filtering module 80 can filter out the second part of the first pulse that appears first and the second part of the second pulse that appears later than the second node K in a frame. The first part of the fixed width in the first pulse can be retained, and then the first output module 46 can be controlled to output the gate drive signal of the pulse with the fixed width at the corresponding time. After such improvement, it can be suitable for the driving requirements of the back end.

[0160] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all these changes or substitutions should fall within the scope of protection of the claims attached to this application.

Claims

1. A gate drive circuit, wherein: The gate driving circuit includes a plurality of cascaded shift registers, and the Nth stage shift register includes: a level transmission signal selection module, wherein the level transmission signal selection module is electrically connected between the first node and the first wiring; A pull-up control module, wherein the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; A first filtering module, wherein the first filtering module is electrically connected between the second node and the third node, and a control terminal of the first filtering module is connected to a reset signal; A second filtering module, the second filtering module is electrically connected between the first filtering module and the third node, and a control end of the second filtering module is connected to a filtering control signal having a plurality of pulses in one frame; and A first output module, wherein the first output module outputs a first gate driving signal according to the potential of the third node and the potential of the fourth node.

2. The gate drive circuit according to claim 1, wherein: The Nth stage shift register further includes: A first inverting module, wherein the first inverting module is electrically connected between the second node and the fourth node; a second output module, wherein the second output module outputs a second gate driving signal according to the potential of the second node; The frequency of the second gate driving signal is the same as the frequency of the filter control signal, and the phase of the second gate driving signal is different from the phase of the filter control signal.

3. The gate driving circuit according to claim 2, wherein: The frequency of the second gate driving signal is the same as the frequency of the reset signal, and the phase of the second gate driving signal is different from the phase of the reset signal.

4. The gate driving circuit according to claim 1, wherein: The first filtering module comprises: a first filter transistor, wherein one of a source or a drain of the first filter transistor is electrically connected to the second node, the other of the source or the drain of the first filter transistor is electrically connected to the third node, and a gate of the first filter transistor is connected to the reset signal; A first capacitor, one end of the first capacitor is electrically connected to the gate of the first filter transistor, and the other end of the first capacitor is electrically connected to the other of the source or the drain of the first filter transistor.

5. The gate driving circuit according to claim 1, wherein: The second filtering module includes a second filtering transistor, one of the source or the drain of the second filtering transistor is electrically connected to the first filtering module, the other of the source or the drain of the second filtering transistor is electrically connected to the third node, and the gate of the second filtering transistor is connected to the filtering control signal.

6. The gate driving circuit according to claim 1, wherein: The N-th stage shift register further includes an isolation module, which is connected in series between the second node and the input end of the second output module, and a control end of the isolation module is connected to the first clock signal.

7. The gate driving circuit according to claim 6, wherein: The isolation module includes an isolation transistor, one of the source or the drain of the isolation transistor is electrically connected to the second node, the other of the source or the drain of the isolation transistor is electrically connected to the input end of the second output module, the gate of the isolation transistor is connected to the first clock signal, and the isolation transistor is a P-channel thin film transistor.

8. The gate driving circuit according to claim 6, wherein: The isolation module is used to reduce the coupling of the pulse amplitude of the first gate driving signal to the pulse amplitude of the second gate driving signal.

9. The gate driving circuit according to claim 1, wherein: The second node transmits a first pulse and a second pulse successively in one frame; the first filtering module is used to filter out a first part of the second pulse.

10. The gate driving circuit according to claim 1, wherein: The second node transmits a first pulse and a second pulse successively in one frame; the second filtering module is used to filter out a latter part of the first pulse and a latter part of the second pulse.

11. The gate driving circuit according to claim 1, wherein: The second node transmits a first pulse and a second pulse successively in one frame; the first filtering module and the second filtering module are used to filter out the second pulse and retain a front part of the first pulse with a fixed width.

12. A display panel, wherein: The display panel comprises: a pixel circuit including a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and According to the gate driving circuit of claim 1, the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

13. The display panel according to claim 12, wherein: The Nth stage shift register further includes: A first inverting module, wherein the first inverting module is electrically connected between the second node and the fourth node; a second output module, wherein the second output module outputs a second gate driving signal according to the potential of the second node; The frequency of the second gate driving signal is the same as the frequency of the filter control signal, and the phase of the second gate driving signal is different from the phase of the filter control signal.

14. The display panel according to claim 13, wherein: The frequency of the second gate driving signal is the same as the frequency of the reset signal, and the phase of the second gate driving signal is different from the phase of the reset signal.

15. The display panel according to claim 12, wherein: The first filtering module comprises: a first filter transistor, wherein one of a source or a drain of the first filter transistor is electrically connected to the second node, the other of the source or the drain of the first filter transistor is electrically connected to the third node, and a gate of the first filter transistor is connected to the reset signal; A first capacitor, one end of the first capacitor is electrically connected to the gate of the first filter transistor, and the other end of the first capacitor is electrically connected to the other of the source or the drain of the first filter transistor.

16. The display panel according to claim 12, wherein: The second filtering module includes a second filtering transistor, one of the source or the drain of the second filtering transistor is electrically connected to the first filtering module, the other of the source or the drain of the second filtering transistor is electrically connected to the third node, and the gate of the second filtering transistor is connected to the filtering control signal.

17. The display panel according to claim 12, wherein: The N-th stage shift register further includes an isolation module, which is connected in series between the second node and the input end of the second output module, and a control end of the isolation module is connected to the first clock signal.

18. The display panel according to claim 17, wherein: The isolation module includes an isolation transistor, one of the source or the drain of the isolation transistor is electrically connected to the second node, the other of the source or the drain of the isolation transistor is electrically connected to the input end of the second output module, the gate of the isolation transistor is connected to the first clock signal, and the isolation transistor is a P-channel thin film transistor.

19. The display panel according to claim 17, wherein: The isolation module is used to reduce the coupling of the pulse amplitude of the first gate driving signal to the pulse amplitude of the second gate driving signal.

20. The display panel according to claim 12, wherein: The second node transmits a first pulse and a second pulse successively in one frame; the first filtering module is used to filter out a first part of the second pulse.

Images