Shift register, scanning drive circuit, and display panel

Abstract

A shift register, a scanning drive circuit, and a display panel. The shift register comprises a control module (40), a first output module (41), and a second output module (42); at least on the basis of a starting signal (SIN), a first clock signal (CK1), a second clock signal (CK2), a first level signal (VGH), and a second level signal (VGL), the control module (40) controls the potentials of a first node (N1) and a second node (N2); under the potential control of the first node (N1) and the second node (N2), the first output module (41) transmits the first level signal (VGH) or the second clock signal (CK2) to a first output end to output a first scanning signal (S1); and at least under the potential control of a frequency control signal (SW), the second output module (42) outputs a second scanning signal (S2) of which the frequency is less than or equal to the frequency of the first scanning signal (S1). Thus, the same shift register can be used to output scanning signals having different frequencies, thereby reducing the width of a non-display area.

Description

A shift register, a scanning drive circuit and a display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310919204.4, filed on July 25, 2023, entitled “A shift register, a scan drive circuit and a display panel,” and the entire contents of that application are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a shift register, a scan drive circuit and a display panel.

[0004] Background of the Invention

[0005] With the development of display technology, the application of display panels is becoming more and more extensive, and the requirements for display panels are also becoming higher and higher. In order to meet the high screen-to-body ratio requirements of display panels, the width of the non-display area of ​​the display panel needs to be continuously reduced. However, it is currently difficult to further reduce the width of the non-display area.

[0006] Summary of the Invention

[0007] The present application discloses a shift register, a scan driving circuit and a display panel to further reduce the width of a non-display area of ​​the display panel.

[0008] In the first aspect, the present application discloses a shift register, comprising: a control module, for controlling the potential of a first node and a second node based at least on a start signal, a first clock signal, a second clock signal, a first level signal, and a second level signal; a first output module, for transmitting the first level signal or the second clock signal to a first output end under the potential control of the first node and the second node, so that the first output end outputs a first scan signal; a second output module, electrically connected to the control module and / or the first output module, for outputting a second scan signal at least under the potential control of a frequency control signal, the frequency of the second scan signal being less than or equal to the frequency of the first scan signal.

[0009] Optionally, the second output module is used to transmit the first level signal or the second clock signal to the second output end at a preset frequency at least under the potential control of the frequency control signal, the first node and the second node, or to transmit the first level signal or the first clock signal to the second output end at a preset frequency at least under the potential control of the frequency control signal, the first node and the first scan signal, or to transmit the first scan signal or the first level signal to the second output end at a preset frequency at least under the potential control of the frequency control signal, so that the second output end outputs the second scan signal.

[0010] Optionally, the second output module includes a first submodule, a second submodule, and a third submodule; the first submodule is configured to transmit the first level signal to the second output end under the control of the potential of the first node; the second submodule is configured to transmit the second clock signal to the second output end under at least the control of the potential of the second node; the third submodule is configured to transmit the potential of the second node or the first level signal to the second submodule at a preset frequency, or transmit the second clock signal output by the second submodule to the second output end at a preset frequency, under the control of the frequency control signal, so that the second output end outputs the second scanning signal at the preset frequency;

[0011] Alternatively, the second output module includes a first submodule, a second submodule and a third submodule; the first submodule is used to transmit the first level signal to the second output end under the potential control of the first node; the second submodule is used to transmit the first clock signal to the second output end at least under the control of the first scan signal; the third submodule is used to transmit the first scan signal or the first level signal to the second submodule at a preset frequency under the control of the frequency control signal, or to transmit the first clock signal output by the second submodule to the second output end at a preset frequency, so that the second output end outputs the second scan signal of the preset frequency.

[0012] Optionally, the first submodule includes a first transistor; the control terminal of the first transistor is electrically connected to the first node, the first terminal of the first transistor is used to receive the first level signal, and the second terminal of the first transistor is electrically connected to the second output terminal; the second submodule includes a second transistor, a third transistor and a first capacitor; the second terminal of the second transistor is electrically connected to the second output terminal, the first terminal of the second transistor is used to receive the second clock signal or the first clock signal, the control terminal of the second transistor is electrically connected to the second terminal of the third transistor; the control terminal of the third transistor receives the second level signal; one terminal of the first capacitor is electrically connected to the control terminal of the second transistor, and the other terminal of the first capacitor is electrically connected to the second terminal of the second transistor; the third submodule includes a fourth transistor and a fifth transistor; the first terminal of the fourth transistor is electrically connected to the second node or the first output terminal, the control terminal of the fourth transistor is used to receive the frequency control signal, and the second terminal of the fourth transistor is electrically connected to the first terminal of the third transistor; the first terminal of the fifth transistor is used to receive the first level signal, the control terminal of the fifth transistor is used to receive the frequency control signal, and the second terminal of the fifth transistor is electrically connected to the second terminal of the fourth transistor;

[0013] Alternatively, the first submodule includes a first transistor; the control end of the first transistor is electrically connected to the first node, the first end of the first transistor is used to receive the first level signal, and the second end of the first transistor is electrically connected to the second output end; the third submodule includes a sixth transistor; the control end of the sixth transistor is used to receive the frequency control signal, and the second end of the sixth transistor is electrically connected to the second output end; the second submodule includes a second transistor, a third transistor and a first capacitor; the second end of the second transistor is electrically connected to the first end of the sixth transistor, the first end of the second transistor is used to receive the second clock signal or the first clock signal, and the control end of the second transistor is electrically connected to the second end of the third transistor; the control end of the third transistor receives the second level signal, and the first end of the third transistor is electrically connected to the second node or the first output end; one end of the first capacitor is electrically connected to the control end of the second transistor, and the other end of the first capacitor is electrically connected to the second end of the second transistor.

[0014] Optionally, the fourth transistor and the fifth transistor are transistors of opposite conduction types, and the frequency control signal received by the control end of the fourth transistor and the frequency control signal received by the control end of the fifth transistor are the same signal; or, the fourth transistor and the fifth transistor are transistors of the same conduction type, the frequency control signal includes a first frequency control signal and a second frequency control signal, the second frequency control signal is a signal that is inverted to the first frequency control signal, the control end of the fourth transistor receives the first frequency control signal, and the control end of the fifth transistor receives the second frequency control signal.

[0015] Optionally, the second output module includes a seventh transistor and an eighth transistor; the first end of the seventh transistor is electrically connected to the first output end, the control end of the seventh transistor is used to receive the frequency control signal, and the second end of the seventh transistor is electrically connected to the second output end; the first end of the eighth transistor is used to receive the first level signal, the control end of the eighth transistor is used to receive the frequency control signal, and the second end of the eighth transistor is electrically connected to the second end of the seventh transistor.

[0016] Optionally, the first output module includes a fourth submodule and a fifth submodule; the fourth submodule is used to transmit the first level signal to the first output end under the potential control of the first node; the fifth submodule is used to transmit the second clock signal to the first output end under the potential control of the second node.

[0017] Optionally, the fourth submodule includes a ninth transistor and a second capacitor; the first end of the ninth transistor is used to receive the first level signal, the control end of the ninth transistor is electrically connected to the first node, and the second end of the ninth transistor is electrically connected to the first output end; one end of the second capacitor is electrically connected to the control end of the ninth transistor, and the other end of the second capacitor is electrically connected to the first end of the ninth transistor; the fifth submodule includes a tenth transistor and a third capacitor; the first end of the tenth transistor is used to receive the second clock signal, the control end of the tenth transistor is electrically connected to the second node, and the second end of the tenth transistor is electrically connected to the first output end; one end of the third capacitor is electrically connected to the control end of the ninth transistor, and the other end of the second capacitor is electrically connected to the first end of the ninth transistor. The control terminal of the tenth transistor is electrically connected, and the other end of the third capacitor is electrically connected to the second end of the tenth transistor; or, the fifth submodule includes a tenth transistor, an eleventh transistor and a third capacitor; the first end of the tenth transistor is used to receive the second clock signal, the control terminal of the tenth transistor is electrically connected to the second end of the eleventh transistor, and the second end of the tenth transistor is electrically connected to the first output terminal; one end of the third capacitor is electrically connected to the control terminal of the tenth transistor, and the other end of the third capacitor is electrically connected to the second end of the tenth transistor; the control terminal of the eleventh transistor is used to receive the second level signal, and the first end of the eleventh transistor is electrically connected to the second node.

[0018] Optionally, the control module is used to control the potential of the first node and the second node according to the start signal, the first clock signal, the second clock signal, the third clock signal, the first level signal and the second level signal; the control module includes a first control module, a second control module, a third control module and a fourth control module; the first control module is used to transmit the third clock signal or the second level signal to the first node under the control of the start signal and the third clock signal; the second control module is used to transmit the start signal to the second node under the control of the first clock signal; the third control module is used to transmit the first level signal to the first node under the control of the second clock signal and the potential of the second node; the fourth control module is used to transmit the first level signal to the second node under the control of the second clock signal and the potential of the first node.

[0019] Optionally, the first control module includes a twelfth transistor and a thirteenth transistor; the first end of the twelfth transistor is used to receive the third clock signal, the control end of the twelfth transistor is used to receive the start signal, the second end of the twelfth transistor is electrically connected to the second end of the thirteenth transistor, the first end of the thirteenth transistor is used to receive the second level signal, the control end of the thirteenth transistor is used to receive the third clock signal, and the second end of the thirteenth transistor is electrically connected to the first node; the second control module includes a fourteenth transistor; the first end of the fourteenth transistor is used to receive the start signal, the control end of the fourteenth transistor is used to receive the first clock signal, and the second end of the fourteenth transistor is electrically connected to the second node; the third control module includes a fifteenth transistor and a sixteenth transistor; the control end of the fifteenth transistor is electrically connected to the second node, the first end of the fifteenth transistor is used to receive the first level signal, and the second end of the fifteenth transistor is electrically connected to the first end of the sixteenth transistor; the second end of the sixteenth transistor is electrically connected to the first node, and the control end of the sixteenth transistor is used to receive the second clock signal; the fourth control module includes a seventeenth transistor and an eighteenth transistor; the control end of the seventeenth transistor is electrically connected to the first node, the first end of the seventeenth transistor is used to receive the first level signal, the second end of the seventeenth transistor is electrically connected to the first end of the eighteenth transistor, the second end of the eighteenth transistor is electrically connected to the second node, and the control end of the eighteenth transistor is used to receive the second clock signal.

[0020] Optionally, the control module includes a first control module, a second control module, a third control module and a fourth control module; the first control module is used to transmit the second level signal to the first node under the control of the first clock signal; the second control module is used to transmit the start signal to the second node under the control of the first clock signal; the third control module is used to transmit the first clock signal to the first node under the control of the potential of the second node; the fourth control module is used to transmit the first level signal to the second node under the control of the second clock signal and the potential of the first node.

[0021] Optionally, the first control module includes a nineteenth transistor; the first end of the nineteenth transistor is used to receive the second clock signal, the control end of the nineteenth transistor is used to receive the first clock signal, and the second end of the nineteenth transistor is electrically connected to the first node; the second control module includes a twentieth transistor; the first end of the twentieth transistor is used to receive the start signal, the control end of the twentieth transistor is used to receive the first clock signal, and the second end of the twentieth transistor is electrically connected to the second node; the third control module includes a twenty-first transistor; the control end of the twenty-first transistor is electrically connected to the second node, the first end of the twenty-first transistor is used to receive the first clock signal, and the second end of the twenty-first transistor is electrically connected to the first node; the fourth control module includes a twenty-second transistor and a twenty-third transistor; the control end of the twenty-second transistor is electrically connected to the first node, the first end of the twenty-second transistor is used to receive the first level signal, the second end of the twenty-second transistor is electrically connected to the first end of the twenty-third transistor, the second end of the twenty-third transistor is electrically connected to the second node, and the control end of the twenty-third transistor is used to receive the second clock signal.

[0022] In a second aspect, the present application discloses a scan driving circuit, comprising a plurality of cascaded shift registers, wherein the shift registers comprise the shift register as described in any one of the above items.

[0023] Optionally, in the multiple cascaded shift registers, the first scanning signal of the shift register is the starting signal of the next stage shift register.

[0024] In a third aspect, the present application discloses a display panel, comprising a display area and a non-display area, wherein the non-display area comprises the scan driving circuit as described above.

[0025] Optionally, the display area includes a plurality of pixel circuits, and the pixel circuits are electrically connected to at least a first output terminal and a second output terminal of a corresponding shift register in the scan driving circuit.

[0026] The shift register, scan drive circuit and display panel disclosed in the present application include a control module, a first output module and a second output module. The control module controls the potential of the first node and the second node based on at least a start signal, a first clock signal, a second clock signal, a first level signal and a second level signal. The first output module transmits the first level signal or the second clock signal to the first output end under the potential control of the first node and the second node, so that the first output end outputs a first scan signal. The second output module transmits the first level signal or the first clock signal or the second clock signal or the first scan signal to the second output end at a preset frequency under at least the potential control of the frequency control signal, so that the second output end outputs a second scan signal. The frequency of the second scan signal is less than or equal to the frequency of the first scan signal, so that the same shift register can be used to output multiple scan signals with different frequencies, thereby reducing the number of shift registers in the non-display area and further reducing the width of the non-display area.

[0027] BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0029] FIG1 is a schematic structural diagram of a display panel;

[0030] FIG2 is a schematic structural diagram of a pixel circuit;

[0031] FIG3 is a timing diagram of the pixel circuit shown in FIG2 ;

[0032] FIG4 is a schematic diagram of the structure of a shift register disclosed in an embodiment of the present application;

[0033] FIG5 is a schematic structural diagram of a second output module disclosed in an embodiment of the present application;

[0034] FIG6 is a timing diagram of a second output module disclosed in an embodiment of the present application;

[0035] FIG7 is a schematic structural diagram of another second output module disclosed in an embodiment of the present application;

[0036] FIG8 is a timing diagram of another second output module disclosed in an embodiment of the present application;

[0037] FIG9 is a schematic structural diagram of another second output module disclosed in an embodiment of the present application;

[0038] FIG10 is a schematic structural diagram of another shift register disclosed in an embodiment of the present application;

[0039] FIG11 is a schematic structural diagram of another second output module disclosed in an embodiment of the present application;

[0040] FIG12 is a timing diagram of another second output module disclosed in an embodiment of the present application;

[0041] FIG13 is a schematic structural diagram of another second output module disclosed in an embodiment of the present application;

[0042] FIG14 is a timing diagram of another second output module disclosed in an embodiment of the present application;

[0043] FIG15 is a schematic structural diagram of another second output module disclosed in an embodiment of the present application;

[0044] FIG16 is a schematic structural diagram of another shift register disclosed in an embodiment of the present application;

[0045] FIG17 is a schematic structural diagram of another second output module disclosed in an embodiment of the present application;

[0046] FIG18 is a timing diagram of another second output module disclosed in an embodiment of the present application;

[0047] FIG19 is a schematic structural diagram of another shift register disclosed in an embodiment of the present application;

[0048] FIG20 is a schematic structural diagram of another shift register disclosed in an embodiment of the present application;

[0049] FIG21 is a timing diagram of a shift register disclosed in an embodiment of the present application;

[0050] FIG22 is a schematic structural diagram of another control module disclosed in an embodiment of the present application;

[0051] FIG23 is a schematic structural diagram of a scan driving circuit disclosed in an embodiment of the present application;

[0052] FIG24 is a schematic structural diagram of a display panel disclosed in an embodiment of the present application.

[0053] Modes for Carrying Out the Invention

[0054] As shown in FIG1 , FIG1 is a schematic diagram of the structure of a display panel. The display panel includes a display area AA and a non-display area NA that at least partially surrounds the display area AA. The non-display area NA includes a scan driver circuit 10. The scan driver circuit 10 includes multiple cascaded shift registers 101. The multiple cascaded shift registers 101 sequentially output scan signals to the pixel circuits of multiple rows of sub-pixels 11. The scan signals control the writing of data signals into the pixel circuits row by row, thereby controlling the emission of the sub-pixels 11 row by row. FIG1 only illustrates the arrangement of the scan driver circuit 10 in the non-display area NA on one side of the display area AA as an example, but the present invention is not limited to this. In other embodiments, the scan driver circuits 10 may also be arranged in the non-display areas NA on opposite sides of the display area AA. This will not be described in detail here.

[0055] The inventors have found that current pixel circuits usually require multiple scanning signals with different frequencies, as shown in Figures 2 and 3. Figure 2 is a structural schematic diagram of a pixel circuit, and Figure 3 is a timing diagram of the pixel circuit shown in Figure 2. The frequencies of the first scanning signal S1 and the second scanning signal S2 are different, and the frequency of the second scanning signal S2 is less than the frequency of the first scanning signal S1. Based on this, a state reset stage h3 can be corresponding to each black insertion stage, so that the state of the driving transistor M0 can be reset once during each black insertion, thereby improving the problem of different hysteresis deviations of the driving transistors in adjacent pixel circuits due to different data voltages. However, a current shift register 101 can only output a scanning signal with one frequency. That is, multiple shift registers 101 need to be set in the non-display area NA to provide multiple scanning signals with different frequencies to the pixel circuits of the sub-pixels 11 in the same row, such as providing the first scanning signal S1 and the second scanning signal S2. This makes it difficult to further reduce the width of the non-display area NA.

[0056] Based on this, the present application discloses a shift register, which reduces the number of shift registers in the non-display area by adding a second output module in the shift register, and enables the second output module to output a second scanning signal with a frequency different from the first scanning signal output by the first output module, at least under the control of a frequency control signal, so as to further reduce the width of the non-display area.

[0057] As an optional implementation of the contents disclosed in this application, an embodiment of this application discloses a shift register, as shown in Figure 4, which is a structural diagram of a shift register disclosed in an embodiment of this application, and the shift register includes a control module 40, a first output module 41 and a second output module 42.

[0058] The control module 40 is configured to control the potentials of the first node N1 and the second node N2 according to at least the start signal IN, the first clock signal CK1 , the second clock signal CK2 , the first level signal VGH, and the second level signal VGL.

[0059] The first output module 41 is used for transmitting the first level signal VGH or the second clock signal CK2 to the first output end under the control of the potentials of the first node N1 and the second node N2 , so that the first output end outputs the first scan signal S1 .

[0060] The second output module 42 is electrically connected to the control module 40 and / or the first output module 41, and is used to output a second scanning signal S2 under at least the potential control of the frequency control signal SW, and the frequency of the second scanning signal S2 is less than or equal to the frequency of the first scanning signal S1.

[0061] Optionally, the second output module 42 is used to transmit at least the first level signal VGH or the second clock signal CK2 or the first clock signal CK1 or the first scan signal S1 to the second output end at a preset frequency under the potential control of the frequency control signal SW, so that the second output end outputs the second scan signal S2.

[0062] In the embodiments of the present application, only a shift register including one second output module 42 is used as an example for illustration. However, the present application is not limited thereto. In other embodiments, the shift register may include two, three, or even more second output modules 42. The frequencies of the second scanning signals S2 output by different second output modules 42 may be different or the same. The structures of different second output modules 42 may be the same or different. Each shift register may include at least one second output module 42 as shown in Figures 4 to 6.

[0063] Based on this, the same shift register can be used to output multiple scanning signals with different frequencies, such as the first scanning signal S1 and the second scanning signal S2. Compared with using different shift registers to output scanning signals with different frequencies, the number of shift registers in the non-display area can be reduced, or the number of devices such as transistors and capacitors in the shift register in the non-display area can be reduced, thereby further reducing the width of the non-display area.

[0064] In some embodiments of the present application, as shown in Figure 4, the second output module 42 is electrically connected to the control module 40, and is used to transmit the first level signal VGH or the second clock signal CK2 to the second output end at a preset frequency under the control of at least the frequency control signal SW, the potential of the first node N1 and the second node N2, so that the second output end outputs the second scan signal S2.

[0065] Based on the structure shown in Figure 4, in some embodiments of the present application, as shown in Figure 5, Figure 5 is a structural schematic diagram of a second output module 42 disclosed in an embodiment of the present application, and the second output module 42 includes a first sub-module 421, a second sub-module 422 and a third sub-module 423.

[0066] The first submodule 421 is electrically connected to the first node N1, the first level signal terminal that inputs the first level signal VGH, and the second output terminal that outputs the second scan signal S2. The first submodule 421 is used to transmit the first level signal VGH to the second output terminal under the potential control of the first node N1.

[0067] The second submodule 422 is electrically connected to the third submodule 423, the second level signal terminal that inputs the second level signal VGL, the second clock signal terminal that inputs the second clock signal CK2, and the second output terminal that outputs the second scan signal S2. The second submodule 422 is used to transmit the second clock signal CK2 to the second output terminal under at least the potential control of the second node N2.

[0068] The third submodule 423 is electrically connected to the second node N2, the frequency control signal terminal of the input frequency control signal SW, the first level signal terminal of the input first level signal VGH, and the second submodule 422. The third submodule 433 is used to transmit the potential of the second node N2 or the first level signal VGH to the second submodule 422 at a preset frequency under the control of the frequency control signal SW, so that the second submodule 422 transmits the second clock signal CK2 to the second output terminal at a preset frequency, so that the second output terminal outputs the second scan signal S2 of the preset frequency.

[0069] In some optional examples, as shown in Figure 5, the first submodule 421 includes a first transistor T1, the control end of the first transistor T1 is electrically connected to the first node N1, the first end of the first transistor T1 is used to receive the first level signal VGH, and the second end of the first transistor T1 is electrically connected to the second output end.

[0070] The second submodule 422 includes a second transistor T2, a third transistor T3 and a first capacitor C1, the second end of the second transistor T2 is electrically connected to the second output end, the first end of the second transistor T2 is used to receive the second clock signal CK2, the control end of the second transistor T2 is electrically connected to the second end of the third transistor T3; the control end of the third transistor T3 receives the second level signal VGL, one end of the first capacitor C1 is electrically connected to the control end of the second transistor T2, and the other end of the first capacitor C1 is electrically connected to the second end of the second transistor T2.

[0071] The third submodule 423 includes a fourth transistor T4 and a fifth transistor T5, the first end of the fourth transistor T4 is electrically connected to the second node N2, the control end of the fourth transistor T4 is used to receive the frequency control signal SW, the second end of the fourth transistor T4 is electrically connected to the first end of the third transistor T3, the first end of the fifth transistor T5 is used to receive the first level signal VGH, the control end of the fifth transistor T5 is used to receive the frequency control signal SW, and the second end of the fifth transistor T5 is electrically connected to the second end of the fourth transistor T4.

[0072] The control end of the transistor in the embodiment of the present application is the gate, and the first end and the second end of the transistor are the source and the drain respectively. For example, the first end of the transistor is the source and the second end is the drain, or the first end of the transistor is the drain and the second end is the source.

[0073] In some embodiments, as shown in FIG5 , the fourth transistor T4 and the fifth transistor T5 are transistors of the same conduction type. For example, the fourth transistor T4 and the fifth transistor T5 are both PMOS transistors, or the fourth transistor T4 and the fifth transistor T5 are both NMOS transistors. The frequency control signal SW includes a first frequency control signal SW1 and a second frequency control signal SW2. The second frequency control signal SW2 is a signal that is inverted from the first frequency control signal SW1. For example, when the first frequency control signal SW1 is high, the second frequency control signal SW2 is low, and when the first frequency control signal SW1 is low, the second frequency control signal SW2 is high. The control terminal of the fourth transistor T4 receives the first frequency control signal SW1, and the control terminal of the fifth transistor T5 receives the second frequency control signal SW2.

[0074] As shown in Figure 6, Figure 6 is a timing diagram of a second output module 42 disclosed in an embodiment of the present application. In the first frame, the first frequency control signal SW1 is at a low level and the second frequency control signal SW2 is at a high level. The third submodule 423 transmits the level of the second node N2 to the second submodule 422. For example, the fourth transistor T4 is turned on and the fifth transistor T5 is turned off. The turned-on fourth transistor T4 transmits the level of the second node N2 to the second submodule 422. When the level of the second node N2 is low and the level of the first node N1 is high, the first submodule 421 is turned off, such as the first transistor T1 is turned off, and the first level signal VGH is stopped from being transmitted to the second output terminal. The second submodule 422 is turned on, such as the second transistor T2 is turned on, and the second clock signal CK2 is transmitted to the second output terminal, so that the second scan signal S2 and the second clock signal CK2 have the same level, such as both are low. When the level of the second node N2 is high and the level of the first node N1 is low, the first submodule 421 is turned on, such as the first transistor T1 is turned on, and the first level signal VGH, such as a high level, is transmitted to the second output terminal. The second submodule 422 is turned off, such as the second transistor T2 is turned off, and the second clock signal CK2 is stopped from being transmitted to the second output terminal.

[0075] The control terminal of the third transistor T3 receives the second level signal VGL. The third transistor T3 is a PMOS transistor, and the second level signal VGL is always at a low level. Therefore, the third transistor T3 remains in an on state for a long time. It is understood that in other embodiments, the third transistor T3 can also be an NMOS transistor, and the second level signal VGL can also be always at a high level. In addition, in other embodiments, the second submodule 422 can also include only the second transistor T2 and the first capacitor C1, and the control terminal of the second transistor T2 is directly electrically connected to the second terminal of the fourth transistor T4. No further details are given here.

[0076] In the second frame, the first frequency control signal SW1 is at a high level and the second frequency control signal SW2 is at a low level. The third submodule 423 transmits the first level signal VGH to the second submodule 422. For example, the fourth transistor T4 is turned off and the fifth transistor T5 is turned on. The turned-on fifth transistor T5 transmits the first level signal VGH to the second submodule 422. Since the first level signal VGH is always at a high level, the second submodule 422 is turned off, for example, the second transistor T2 is turned off. When the first node N1 is at a low level, the first submodule 421 is turned on, for example, the first transistor T1 is turned on, and the first level signal VGH is transmitted to the second output terminal, for example, at a high level. When the first node N1 is at a high level, the first submodule 421 is turned off, for example, the first transistor T1 is turned off, and the level of the second output terminal remains at a high level.

[0077] In the embodiment of the present application, the first level signal VGH is high and the second level signal VGL is low as an example for description, but the present invention is not limited thereto. In other embodiments, for example, if the second transistor T2 is an NMOS transistor, the first level signal VGH may also be low. In this case, one of the first level signal VGH and the second level signal VGL is high and the other is low.

[0078] Figure 6 only uses the timing signal of two frames as an example for illustration, and is not limited to this. A display cycle of the display panel may include two frames, three frames or even more frames, such as a write frame and at least one hold frame. In the embodiment of the present application, the frequency of the second scanning signal S2 can be controlled to be a low level by controlling the first frequency control signal SW1 and the second frequency control signal SW2 to be a high level. That is, the frequency of the second scanning signal S2 can be controlled to be a preset frequency by controlling the frequencies of the first frequency control signal SW1 and the second frequency control signal SW2 to be a preset frequency, and the frequency of the second scanning signal S2 can be controlled to be less than or equal to the frequency of the first scanning signal S1.

[0079] For example, if the first frequency control signal SW1 is at a low level and the second frequency control signal SW2 is at a high level within a display cycle of the display panel, the frequency of the second scanning signal S2 is equal to the frequency of the first scanning signal S1. If the first frequency control signal SW1 is at a high level and the second frequency control signal SW2 is at a low level within at least one frame of a display cycle of the display panel, the frequency of the second scanning signal S2 is less than the frequency of the first scanning signal S1.

[0080] Of course, the present application is not limited to this. In other embodiments, as shown in Figure 7, Figure 7 is a structural schematic diagram of another second output module 42 disclosed in an embodiment of the present application. The fourth transistor T4 and the fifth transistor T5 are transistors with opposite conduction types, and the frequency control signal SW received by the control end of the fourth transistor T4 and the frequency control signal SW received by the control end of the fifth transistor T5 are the same signal.

[0081] Taking the fourth transistor T4 as a PMOS transistor and the fifth transistor T5 as an NMOS transistor as an example, as shown in FIG8 , FIG8 is a timing diagram of another second output module 42 disclosed in an embodiment of the present application. In the first frame, the frequency control signal SW is at a low level, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned off. In the second frame, the frequency control signal SW is at a high level, the fourth transistor T4 is turned off, and the fifth transistor T5 is turned on. Similarly, by controlling the frequency of the frequency control signal SW to a preset frequency, the frequency of the second scanning signal S2 can be controlled to be a preset frequency, and the frequency of the second scanning signal S2 can be controlled to be less than or equal to the frequency of the first scanning signal S1. Of course, in other embodiments, the fourth transistor T4 can also be an NMOS transistor, and the fifth transistor T5 can also be a PMOS transistor, which will not be repeated here.

[0082] In other optional examples, as shown in Figure 9, Figure 9 is a structural schematic diagram of another second output module 42 disclosed in an embodiment of the present application. The difference from the second output module 42 shown in Figure 5 is that the second sub-module 422 is electrically connected to the second level signal terminal of the input second level signal VGL, the second node N2 and the second clock signal terminal of the input second clock signal CK2, and the second sub-module 422 is used to transmit the second clock signal CK2 to the second output terminal under the potential control of the second node N2.

[0083] The third submodule 423 is electrically connected to the frequency control signal terminal of the input frequency control signal SW, the second output terminal and the second submodule 422. The third submodule 433 is used to transmit the second clock signal CK2 output by the second submodule 422 to the second output terminal according to the preset frequency under the control of the frequency control signal SW, so that the second output terminal outputs the second scanning signal S2 with the preset frequency.

[0084] In some optional examples, as shown in FIG9 , the difference from the second output module 42 shown in FIG5 is that the third submodule 423 includes a sixth transistor T6, a control terminal of the sixth transistor T6 is used to receive the frequency control signal SW, and a second terminal of the sixth transistor T6 is electrically connected to the second output terminal. The second terminal of the second transistor T2 is electrically connected to the first terminal of the sixth transistor T6, and the first terminal of the third transistor T3 is electrically connected to the second node N2.

[0085] Taking the sixth transistor T6 as a PMOS transistor as an example, with reference to FIG8 , in a first frame, the frequency control signal SW is at a low level, the third submodule 423 is turned on, such as the sixth transistor T6 is turned on, and when the level at the second node N2 is at a low level and the level at the first node N1 is at a high level, the first submodule 421 is turned off, such as the first transistor T1 is turned off, and stops transmitting the first-level signal VGH to the second output terminal. The second submodule 422 is turned on, such as the second transistor T2 is turned on, and transmits the second clock signal CK2 to the second output terminal. When the level at the second node N2 is at a high level and the level at the first node N1 is at a low level, the second submodule 422 is turned off, such as the second transistor T2 is turned off, and the first submodule 421 is turned on, such as the first transistor T1 is turned on, and transmits the first-level signal VGH, such as a high level, to the second output terminal.

[0086] In the second frame, the frequency control signal SW is at a high level, the third submodule 423 is turned off, such as the sixth transistor T6 is turned off, and no matter whether the second submodule 422 is turned on or off, the second clock signal CK2 cannot be transmitted to the second output terminal. When the first node N1 is at a low level, the first submodule 421 is turned on, such as the first transistor T1 is turned on, and the first level signal VGH is transmitted to the second output terminal, such as a high level. When the first node N1 is at a high level, the first submodule 421 is turned off, such as the first transistor T1 is turned off, and the level of the second output terminal is still maintained at a high level.

[0087] Of course, the present application is not limited to the structure shown in Figure 4. In other optional examples, as shown in Figure 10, Figure 10 is a structural schematic diagram of another shift register disclosed in an embodiment of the present application. The second output module 42 is electrically connected to the control module 40 and the first output module 41, and is used to transmit the first level signal VGH or the first clock signal CK1 to the second output end at a preset frequency under the potential control of the frequency control signal SW, the first node N1 and the first scan signal S1, so that the second output end outputs the second scan signal S2.

[0088] Based on the structure shown in Figure 10, in some embodiments of the present application, as shown in Figure 11, Figure 11 is a structural schematic diagram of another second output module 42 disclosed in an embodiment of the present application. The difference from the second output module 42 shown in Figure 5 is that the second submodule 422 is used to transmit the first clock signal CK1 to the second output end under the control of the first scan signal S1, and the third submodule 423 is used to transmit the first scan signal S1 or the first level signal VGH to the second submodule according to the preset frequency under the control of the frequency control signal SW.

[0089] In some optional examples, as shown in FIG11 , the difference from the second output module 42 shown in FIG5 is that the first end of the second transistor T2 is used to receive the first clock signal CK1 , and the first end of the fourth transistor T4 is electrically connected to the first output end.

[0090] Because the second clock signal CK2 has a certain delay compared to the first clock signal CK1, after the second clock signal CK2 is replaced with the first clock signal CK1, in order to avoid display confusion, the second output end of the shift register needs to be staggered, that is, the second scanning signal S2 output from the second output end of the shift register is transmitted to the next row of sub-pixels or the previous row of sub-pixels.

[0091] As shown in Figure 12, Figure 12 is a timing diagram of another second output module 42 disclosed in an embodiment of the present application. In the first frame, the first frequency control signal SW1 is at a low level and the second frequency control signal SW2 is at a high level. The third submodule 423 transmits the first scan signal S1 to the second submodule 422, such as the fourth transistor T4 is turned on and the fifth transistor T5 is turned off. The turned-on fourth transistor T4 transmits the level of the second node N2 to the second submodule 422. When the first scan signal S1 is at a low level and the level of the first node N1 is at a high level, the first submodule 421 is turned off, such as the first transistor T1 is turned off, and the second submodule 422 is turned on, such as the second transistor T2 is turned on, and the second clock signal CK2 is transmitted to the second output end as a low level.

[0092] In the second frame, the first frequency control signal SW1 is at a high level and the second frequency control signal SW2 is at a low level. The third submodule 423 transmits the first level signal VGH to the second submodule 422. For example, the fourth transistor T4 is turned off and the fifth transistor T5 is turned on. The turned-on fifth transistor T5 transmits the first level signal VGH to the second submodule 422. Since the first level signal VGH is always at a high level, the second submodule 422 is turned off, for example, the second transistor T2 is turned off. When the first node N1 is at a low level, the first submodule 421 is turned on, for example, the first transistor T1 is turned on, and the first level signal VGH is transmitted to the second output terminal, for example, at a high level. When the first node N1 is at a high level, the first submodule 421 is turned off, for example, the first transistor T1 is turned off, and the level of the second output terminal remains at a high level.

[0093] In other embodiments, as shown in Figure 13, Figure 13 is a structural schematic diagram of another second output module 42 disclosed in an embodiment of the present application. The difference from the second output module 42 shown in Figure 11 is that the fourth transistor T4 and the fifth transistor T5 are transistors of opposite conduction types, and the frequency control signal SW received by the control end of the fourth transistor T4 and the frequency control signal SW received by the control end of the fifth transistor T5 are the same signal.

[0094] Taking the fourth transistor T4 as a PMOS transistor and the fifth transistor T5 as an NMOS transistor as an example, as shown in FIG14, FIG14 is a timing diagram of another second output module 42 disclosed in an embodiment of the present application. In the first frame, the frequency control signal SW is at a low level, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned off. In the second frame, the frequency control signal SW is at a high level, the fourth transistor T4 is turned off, and the fifth transistor T5 is turned on. Similarly, by controlling the frequency of the frequency control signal SW to a preset frequency, the frequency of the second scanning signal S2 can be controlled to be a preset frequency, and the frequency of the second scanning signal S2 can be controlled to be less than or equal to the frequency of the first scanning signal S1. Of course, in other embodiments, the fourth transistor T4 can also be an NMOS transistor and the fifth transistor T5 can also be a PMOS transistor, which will not be repeated here.

[0095] In other embodiments, as shown in Figure 15, Figure 15 is a structural schematic diagram of another second output module 42 disclosed in an embodiment of the present application. The difference from the second output module 42 shown in Figure 9 is that the second submodule 422 is used to transmit the first clock signal CK1 to the second output end under the control of the first scanning signal S1; the third submodule 423 is used to transmit the first clock signal CK1 output by the second submodule 422 to the second output end at a preset frequency under the control of the frequency control signal SW, so that the second output end outputs the second scanning signal S2 of the preset frequency.

[0096] In some optional examples, as shown in FIG15 , the difference from the second output module 42 shown in FIG9 is that the first end of the second transistor T2 is used to receive the first clock signal CK1 , and the first end of the fourth transistor T4 is electrically connected to the first output end.

[0097] 14 , in a first frame, the frequency control signal SW is at a low level, the third submodule 423 is turned on, such as the sixth transistor T6 is turned on, and when the first scan signal S1 is at a low level and the first node N1 is at a high level, the first submodule 421 is turned off, such as the first transistor T1 is turned off, and the second submodule 422 is turned on, such as the second transistor T2 is turned on, transmitting the second clock signal CK2, such as a low level, to the second output terminal. When the first scan signal S1 is at a high level and the first node N1 is at a low level, the second submodule 422 is turned off, such as the second transistor T2 is turned off, and the first submodule 421 is turned on, such as the first transistor T1 is turned on, transmitting the first level signal VGH, such as a high level, to the second output terminal.

[0098] In the second frame, the frequency control signal SW is at a high level, the third submodule 423 is turned off, such as the sixth transistor T6 is turned off, and no matter whether the second submodule 422 is turned on or off, the second clock signal CK2 cannot be transmitted to the second output terminal. When the first node N1 is at a low level, the first submodule 421 is turned on, such as the first transistor T1 is turned on, and the first level signal VGH is transmitted to the second output terminal, such as a high level. When the first node N1 is at a high level, the first submodule 421 is turned off, such as the first transistor T1 is turned off, and the level of the second output terminal is still maintained at a high level.

[0099] Of course, the present application is not limited to the structures shown in Figures 4 and 10. In other embodiments, as shown in Figure 16, Figure 16 is a structural schematic diagram of another shift register disclosed in an embodiment of the present application. The second output module 42 is electrically connected to the first output module 41, and is used to transmit the first scan signal S1 or the first level signal VGH to the second output end at a preset frequency under the potential control of the frequency control signal SW, so that the second output end outputs the second scan signal S2.

[0100] Based on the structure shown in Figure 16, in some embodiments of the present application, as shown in Figure 17, Figure 17 is a structural schematic diagram of another second output module 42 disclosed in an embodiment of the present application, the second output module 42 includes a seventh transistor T7 and an eighth transistor T8, the first end of the seventh transistor T7 is electrically connected to the first output end, the control end of the seventh transistor T7 is used to receive a frequency control signal SW such as the first frequency control signal SW1, and the second end of the seventh transistor T7 is electrically connected to the second output end; the first end of the eighth transistor T8 is used to receive the first level signal VGH, the control end of the eighth transistor T8 is used to receive the frequency control signal SW such as the second frequency control signal SW2, and the second end of the eighth transistor T8 is electrically connected to the second end of the seventh transistor T7.

[0101] Referring to FIG. 18 , which is a timing diagram of another second output module 42 disclosed in an embodiment of the present application, in the first frame, the first frequency control signal SW1 is at a low level, the second frequency control signal SW2 is at a high level, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off, transmitting the first scan signal S1 to the second output terminal. In the second frame, the first frequency control signal SW1 is at a high level, the second frequency control signal SW2 is at a low level, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned on, ceasing to transmit the first scan signal S1 to the second output terminal and instead transmitting the first level signal VGH to the second output terminal.

[0102] In some embodiments of the present application, as shown in FIG19 , which is a schematic diagram of the structure of another shift register disclosed in an embodiment of the present application, the first output module 41 includes a fourth submodule 414 and a fifth submodule 415. The fourth submodule 414 is configured to transmit the first level signal VGH to the first output terminal under the control of the potential of the first node N1. The fifth submodule 415 is configured to transmit the second clock signal CK2 to the first output terminal under the control of the potential of the second node N2.

[0103] In some optional examples, as shown in Figure 19, the fourth submodule 414 includes a ninth transistor T9 and a second capacitor C2; the first end of the ninth transistor T9 is used to receive the first level signal VGH, the control end of the ninth transistor T9 is electrically connected to the first node N1, and the second end of the ninth transistor T9 is electrically connected to the first output end; one end of the second capacitor C2 is electrically connected to the control end of the ninth transistor T9, and the other end of the second capacitor C2 is electrically connected to the first end of the ninth transistor T9.

[0104] The fifth submodule 415 includes a tenth transistor T10 and a third capacitor C3; the first end of the tenth transistor T10 is used to receive the second clock signal CK2, the control end of the tenth transistor T10 is electrically connected to the second node N2, and the second end of the tenth transistor T10 is electrically connected to the first output end; one end of the third capacitor C3 is electrically connected to the control end of the tenth transistor T10, and the other end of the third capacitor C3 is electrically connected to the second end of the tenth transistor T10.

[0105] In some optional examples, as shown in Figure 20, Figure 20 is a structural diagram of another shift register disclosed in an embodiment of the present application, the fifth sub-module also includes an eleventh transistor T11, the control end of the tenth transistor T10 is electrically connected to the second end of the eleventh transistor T11, the control end of the eleventh transistor T11 is used to receive the second level signal VGL, and the first end of the eleventh transistor T11 is electrically connected to the second node N2.

[0106] In some embodiments of the present application, as shown in Figure 19 or Figure 20, the control module 40 is used to control the potential of the first node N1 and the second node N2 according to the start signal SIN, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the first level signal VGH and the second level signal CGL.

[0107] In some embodiments, as shown in FIG19 or FIG20 , the control module 40 includes a first control module 401, a second control module 402, a third control module 403, and a fourth control module 404. The first control module 401 is configured to transmit the third clock signal CK3 or the second level signal VGL to the first node N1 under the control of the start signal SIN and the third clock signal CK3. The second control module 402 is configured to transmit the start signal SIN to the second node N2 under the control of the first clock signal CK1. The third control module 403 is configured to transmit the first level signal VGH to the first node N1 under the control of the second clock signal CK2 and the potential of the second node N2. The fourth control module 404 is configured to transmit the first level signal VGH to the second node N2 under the control of the second clock signal CK2 and the potential of the first node N1.

[0108] In some optional examples, the first control module 401 includes a twelfth transistor T12 and a thirteenth transistor T13; the first end of the twelfth transistor T12 is used to receive the third clock signal CK3, the control end of the twelfth transistor T12 is used to receive the start signal SIN, the second end of the twelfth transistor T12 is electrically connected to the second end of the thirteenth transistor T13, the first end of the thirteenth transistor T13 is used to receive the second level signal VGL, the control end of the thirteenth transistor T13 is used to receive the third clock signal CK3, and the second end of the thirteenth transistor T13 is electrically connected to the first node N1.

[0109] The second control module 402 includes a fourteenth transistor T14 ; a first terminal of the fourteenth transistor T14 is used to receive the start signal SIN, a control terminal of the fourteenth transistor T14 is used to receive the first clock signal CK1 , and a second terminal of the fourteenth transistor T14 is electrically connected to the second node N2 .

[0110] The third control module 403 includes a fifteenth transistor T15 and a sixteenth transistor T16; the control end of the fifteenth transistor T15 is electrically connected to the second node N2, the first end of the fifteenth transistor T15 is used to receive the first level signal VGH, and the second end of the fifteenth transistor T15 is electrically connected to the first end of the sixteenth transistor T16; the second end of the sixteenth transistor T16 is electrically connected to the first node N1, and the control end of the sixteenth transistor T16 is used to receive the second clock signal CK2.

[0111] The fourth control module 404 includes a seventeenth transistor T17 and an eighteenth transistor T18; the control end of the seventeenth transistor T17 is electrically connected to the first node N1, the first end of the seventeenth transistor T17 is used to receive the first level signal VGH, the second end of the seventeenth transistor T17 is electrically connected to the first end of the eighteenth transistor T18, the second end of the eighteenth transistor T18 is electrically connected to the second node N2, and the control end of the eighteenth transistor T18 is used to receive the second clock signal CK2.

[0112] As shown in Figure 21, Figure 21 is a timing diagram of a shift register disclosed in an embodiment of the present application. In the first phase t1, the start signal SIN is low, the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is low. The fourteenth transistor T14, the twelfth transistor T12, the thirteenth transistor T13, and the seventeenth transistor T17 are turned on, the first node N1 and the second node N2 are pulled down to a low level, the ninth transistor T9 and the tenth transistor T10 are turned on, and the first scan signal S1 is high. When the first frequency control signal SW1 is low and the second frequency control signal SW2 is high, the first transistor T1 and the second transistor T2 are turned on, and the second scan signal S2 is high. When the first frequency control signal SW1 is high and the second frequency control signal SW2 is low, the first transistor T1 is turned on, the second transistor T2 is turned off, and the second scan signal S2 is high.

[0113] In the second stage t2, the start signal SIN is at a low level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a low level, and the third clock signal CK3 is at a high level. The fourteenth transistor T14, the twelfth transistor T12, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on, the thirteenth transistor T13 is turned off, the first node N1 becomes a high level, the second node N2 is still at a low level, the tenth transistor T10 and the second transistor T2 are turned on, the ninth transistor T9 and the first transistor T1 are turned off, the first scan signal S1 is at a low level, and the second scan signal S2 is at a low level.

[0114] In the third stage t3, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the third clock signal CK3 is at a high level. The twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are turned off, the first node N1 remains at a high level, the second node N2 remains at a low level, the tenth transistor T10 and the second transistor T2 remain turned on, the ninth transistor T9 and the first transistor T1 remain turned off, the first scan signal S1 continues to be at a low level, and the second scan signal S2 continues to be at a low level.

[0115] In the fourth stage t4, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, and the third clock signal CK3 is at a low level. The twelfth transistor T12 and the fourteenth transistor T14 remain off, the thirteenth transistor T13 is turned on, the first node N1 is pulled down to a low level, the second node N2 remains at a low level, the ninth transistor T9 and the tenth transistor T10 are turned on, and the first scan signal S1 is at a high level. When the first frequency control signal SW1 is at a low level and the second frequency control signal SW2 is at a high level, the first transistor T1 and the second transistor T2 are turned on, and the second scan signal S2 is at a high level. When the first frequency control signal SW1 is at a high level and the second frequency control signal SW2 is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the second scan signal S2 is at a high level.

[0116] In the fifth stage t5, the start signal SIN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the third clock signal CK3 is at a low level. The fourteenth transistor T14 is turned on, the second node N2 becomes a high level, the twelfth transistor T12 is turned off, the thirteenth transistor T13 is turned on, the first node N1 remains at a low level, the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the first scan signal S1 is at a high level, the first transistor T1 is turned on, and the second scan signal S2 is at a high level.

[0117] In the sixth stage t6, the start signal SIN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a low level, and the third clock signal CK3 is at a high level. The twelfth transistor T12 and the thirteenth transistor T13 are turned off, the first node N1 remains at a low level, the fourteenth transistor T14 is turned on, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the second node N2 is further pulled up to a high level, and the first scan signal S1 and the second scan signal S2 remain at a high level.

[0118] After the sixth phase t6 , the third phase t3 to the sixth phase t6 are repeated continuously until the start signal SIN becomes low level again.

[0119] Of course, the present application is not limited to the control module 40 shown in Figure 19 or Figure 20. In other embodiments, as shown in Figure 22, Figure 22 is a structural schematic diagram of another control module disclosed in an embodiment of the present application. The first control module 401 is used to transmit the second level signal VGL to the first node N1 under the control of the first clock signal CK1, the second control module 402 is used to transmit the start signal SIN to the second node N2 under the control of the first clock signal CK1, the third control module 403 is used to transmit the first clock signal CK1 to the first node N1 under the potential control of the second node N2, and the fourth control module 404 is used to transmit the first level signal VGL to the second node N2 under the control of the second clock signal CK2 and the potential of the first node N1.

[0120] In some optional examples, as shown in Figure 22, the first control module 401 includes a nineteenth transistor T19; the first end of the nineteenth transistor T19 is used to receive the second clock signal CK2, the control end of the nineteenth transistor T19 is used to receive the first clock signal CK1, and the second end of the nineteenth transistor T19 is electrically connected to the first node N1.

[0121] The second control module 402 includes a twentieth transistor T20 ; ​​a first terminal of the twentieth transistor T20 is used to receive the start signal SIN, a control terminal of the twentieth transistor T20 is used to receive the first clock signal CK1 , and a second terminal of the twentieth transistor T20 is electrically connected to the second node N2 .

[0122] The third control module 403 includes a 21st transistor T21; the control end of the 21st transistor T21 is electrically connected to the second node N2, the first end of the 21st transistor T21 is used to receive the first clock signal CK1, and the second end of the 21st transistor T21 is electrically connected to the first node N1.

[0123] The fourth control module 404 includes a twenty-second transistor T22 and a twenty-third transistor T23; the control end of the twenty-second transistor T22 is electrically connected to the first node N1, the first end of the twenty-second transistor T22 is used to receive the first level signal VGH, the second end of the twenty-second transistor T22 is electrically connected to the first end of the twenty-third transistor T23, the second end of the twenty-third transistor T23 is electrically connected to the second node N2, and the control end of the twenty-third transistor T23 is used to receive the second clock signal CK2.

[0124] It is understood that the operation process of the shift register shown in FIG22 is similar to that of the shift register shown in FIG19 or FIG20 and will not be described in detail here. In addition, the structures of the control module 40 and the first output module 41 in the embodiment of the present application are not limited to those shown in FIG19 or FIG20 or FIG22. As long as the output of the high-frequency first scanning signal S1 can be achieved, they can be applied to the shift register disclosed in the embodiment of the present application.

[0125] As an optional implementation of the contents disclosed in the present application, an embodiment of the present application discloses a scanning driving circuit, as shown in Figure 23. Figure 23 is a structural schematic diagram of a scanning driving circuit disclosed in an embodiment of the present application, and the scanning driving circuit includes a plurality of cascaded shift registers 101, and the shift register 101 includes a shift register disclosed in any of the above embodiments.

[0126] In some embodiments, in a plurality of cascaded shift registers, the start signal SIN of the subsequent shift register is the first scan signal S1 of the current shift register, or in other words, the first scan signal S1 of the shift register is the start signal SIN of the next shift register. For example, the start signal SIN of the second shift register is the first scan signal S1 of the first shift register, the start signal SIN of the third shift register is the first scan signal S1 of the second shift register, and so on. Of course, the present application is not limited to this. In other embodiments, the start signal SIN of the subsequent shift register may also be the second scan signal S2 of the current shift register, which will not be described in detail here.

[0127] As an optional implementation of the contents disclosed in this application, an embodiment of this application discloses a display panel, as shown in FIG24 . FIG24 is a structural schematic diagram of a display panel disclosed in an embodiment of this application, and the display panel includes a scanning drive circuit disclosed in any of the above embodiments.

[0128] Among them, the display panel includes a display area AA and a non-display area NA. In some embodiments, the scan driving circuit is located in the non-display area NA on one side of the display area AA. In other embodiments, the scan driving circuit is located in the non-display area NA on both sides of the display area AA, which will not be repeated here.

[0129] In some embodiments, the display area AA includes a plurality of sub-pixels 11, each of which includes a pixel circuit electrically connected to at least the first output terminal and the second output terminal of a corresponding shift register in the scan driver circuit. In other words, the first scan signal S1 and the second scan signal S2 output by the shift register can be input into the same pixel circuit. Referring to Figures 2 and 3 , each black insertion phase corresponds to a state reset phase t3, thereby resetting the state of the drive transistor T0 during each black insertion. This can alleviate the problem of different hysteresis deviations of the drive transistors in adjacent pixel circuits caused by different data voltages.

[0130] Of course, the present application is not limited to this. In other embodiments, a high-frequency first scanning signal S1 can be input to the sub-pixels 11 in a partial area, and a low-frequency second scanning signal S2 can be input to the sub-pixels 11 in another partial area to achieve different frequency displays in different areas.

[0131] As an optional implementation of the present disclosure, an embodiment of the present disclosure discloses a display device, comprising a display panel as disclosed in any of the above embodiments. The display device can be a smartphone, wearable product, computer, television, vehicle-mounted display device, or other display device with a display function, and this application does not impose specific limitations on this.

[0132] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be determined by the appended claims.

Claims

1. A shift register, comprising: A control module, configured to control the potential of the first node and the second node according to at least a start signal, a first clock signal, a second clock signal, a first level signal, and a second level signal; A first output module, configured to transmit the first level signal or the second clock signal to a first output terminal under the control of the potentials of the first node and the second node, so that the first output terminal outputs a first scanning signal; The second output module is electrically connected to the control module and / or the first output module, and is used to output a second scanning signal at least under the potential control of the frequency control signal, and the frequency of the second scanning signal is less than or equal to the frequency of the first scanning signal.

2. The shift register according to claim 1, wherein: The second output module is used to transmit the first level signal or the second clock signal to the second output end at a preset frequency at least under the control of the frequency control signal, the potential of the first node and the second node, or, at least under the control of the frequency control signal, the first node and the potential of the first scan signal, to transmit the first level signal or the first clock signal to the second output end at a preset frequency, or, at least under the control of the potential of the frequency control signal, to transmit the first scan signal or the first level signal to the second output end at a preset frequency, so that the second output end outputs the second scan signal.

3. The shift register according to claim 2, wherein: The second output module includes a first submodule, a second submodule and a third submodule; The first submodule is used for transmitting the first level signal to the second output terminal under the potential control of the first node; The second submodule is used for transmitting the second clock signal to the second output terminal at least under the control of the potential of the second node; The third submodule is used to transmit the potential of the second node or the first level signal to the second submodule at a preset frequency under the control of the frequency control signal, or to transmit the second clock signal output by the second submodule to the second output end at a preset frequency, so that the second output end outputs the second scanning signal of the preset frequency.

4. The shift register according to claim 2, wherein: The second output module includes a first submodule, a second submodule and a third submodule; The first submodule is used for transmitting the first level signal to the second output terminal under the potential control of the first node; The second submodule is used for transmitting the first clock signal to the second output terminal at least under the control of the first scanning signal; The third submodule is used to transmit the first scanning signal or the first level signal to the second submodule at a preset frequency under the control of the frequency control signal, or to transmit the first clock signal output by the second submodule to the second output end at a preset frequency, so that the second output end outputs the second scanning signal of the preset frequency.

5. The shift register according to claim 3 or 4, wherein: The first submodule includes a first transistor; a control terminal of the first transistor is electrically connected to the first node, a first terminal of the first transistor is used to receive the first level signal, and a second terminal of the first transistor is electrically connected to the second output terminal; The second submodule includes a second transistor, a third transistor and a first capacitor; the second end of the second transistor is electrically connected to the second output end, the first end of the second transistor is used to receive the second clock signal or the first clock signal, the control end of the second transistor is electrically connected to the second end of the third transistor; the control end of the third transistor receives the second level signal; one end of the first capacitor is electrically connected to the control end of the second transistor, and the other end of the first capacitor is electrically connected to the second end of the second transistor; The third submodule includes a fourth transistor and a fifth transistor; a first terminal of the fourth transistor is connected to the second The first node or the first output terminal is electrically connected, the control terminal of the fourth transistor is used to receive the frequency control signal, and the second terminal of the fourth transistor is electrically connected to the first terminal of the third transistor; the first terminal of the fifth transistor is used to receive the first level signal, the control terminal of the fifth transistor is used to receive the frequency control signal, and the second terminal of the fifth transistor is electrically connected to the second terminal of the fourth transistor.

6. The shift register according to claim 3 or 4, wherein: The first submodule includes a first transistor; a control terminal of the first transistor is electrically connected to the first node, a first terminal of the first transistor is used to receive the first level signal, and a second terminal of the first transistor is electrically connected to the second output terminal; The third submodule includes a sixth transistor; the control end of the sixth transistor is used to receive the frequency control signal, and the second end of the sixth transistor is electrically connected to the second output end; The second submodule includes a second transistor, a third transistor and a first capacitor; the second end of the second transistor is electrically connected to the first end of the sixth transistor, the first end of the second transistor is used to receive the second clock signal or the first clock signal, and the control end of the second transistor is electrically connected to the second end of the third transistor; the control end of the third transistor receives the second level signal, and the first end of the third transistor is electrically connected to the second node or the first output end; one end of the first capacitor is electrically connected to the control end of the second transistor, and the other end of the first capacitor is electrically connected to the second end of the second transistor.

7. The shift register according to claim 6, wherein: The fourth transistor and the fifth transistor are transistors of opposite conduction types, and the frequency control signal received by the control terminal of the fourth transistor and the frequency control signal received by the control terminal of the fifth transistor are the same signal; Alternatively, the fourth transistor and the fifth transistor are transistors of the same conduction type, the frequency control signal includes a first frequency control signal and a second frequency control signal, the second frequency control signal is a signal that is inverted from the first frequency control signal, the control end of the fourth transistor receives the first frequency control signal, and the control end of the fifth transistor receives the second frequency control signal.

8. The shift register according to claim 2, wherein: The second output module includes a seventh transistor and an eighth transistor; The first end of the seventh transistor is electrically connected to the first output end, the control end of the seventh transistor is used to receive the frequency control signal, and the second end of the seventh transistor is electrically connected to the second output end; the first end of the eighth transistor is used to receive the first level signal, the control end of the eighth transistor is used to receive the frequency control signal, and the second end of the eighth transistor is electrically connected to the second end of the seventh transistor.

9. The shift register according to any one of claims 1 to 8, wherein: The first output module includes a fourth submodule and a fifth submodule; The fourth submodule is used for transmitting the first level signal to the first output end under the potential control of the first node; The fifth submodule is used to transmit the second clock signal to the first output end under the control of the potential of the second node.

10. The shift register according to claim 9, wherein: The fourth submodule includes a ninth transistor and a second capacitor; the first end of the ninth transistor is used to receive the first level signal, the control end of the ninth transistor is electrically connected to the first node, and the second end of the ninth transistor is electrically connected to the first output end; one end of the second capacitor is electrically connected to the control end of the ninth transistor, and the other end of the second capacitor is electrically connected to the first end of the ninth transistor; The fifth submodule includes a tenth transistor and a third capacitor; the first end of the tenth transistor is used to receive the second clock signal, the control end of the tenth transistor is electrically connected to the second node, and the second end of the tenth transistor is electrically connected to the first output end; one end of the third capacitor is electrically connected to the control end of the tenth transistor, and the other end of the third capacitor is electrically connected to the second end of the tenth transistor; Alternatively, the fifth submodule includes a tenth transistor, an eleventh transistor and a third capacitor; the first end of the tenth transistor is used to receive the second clock signal, and the control end of the tenth transistor is connected to the first end of the eleventh transistor. The two ends are electrically connected, the second end of the tenth transistor is electrically connected to the first output end; one end of the third capacitor is electrically connected to the control end of the tenth transistor, and the other end of the third capacitor is electrically connected to the second end of the tenth transistor; the control end of the eleventh transistor is used to receive the second level signal, and the first end of the eleventh transistor is electrically connected to the second node.

11. The shift register according to any one of claims 1 to 10, wherein: The control module is used to control the potential of the first node and the second node according to the start signal, the first clock signal, the second clock signal, the third clock signal, the first level signal and the second level signal; The control module includes a first control module, a second control module, a third control module and a fourth control module; The first control module is used for transmitting the third clock signal or the second level signal to the first node under the control of the start signal and the third clock signal; The second control module is used for transmitting the start signal to the second node under the control of the first clock signal; The third control module is used for transmitting the first level signal to the first node under the control of the second clock signal and the potential of the second node; The fourth control module is used to transmit the first level signal to the second node under the control of the second clock signal and the potential of the first node.

12. The shift register according to claim 11, wherein: The first control module includes a twelfth transistor and a thirteenth transistor; the first end of the twelfth transistor is used to receive the third clock signal, the control end of the twelfth transistor is used to receive the start signal, the second end of the twelfth transistor is electrically connected to the second end of the thirteenth transistor, the first end of the thirteenth transistor is used to receive the second level signal, the control end of the thirteenth transistor is used to receive the third clock signal, and the second end of the thirteenth transistor is electrically connected to the first node; The second control module includes a fourteenth transistor; a first end of the fourteenth transistor is used to receive the start signal, a control end of the fourteenth transistor is used to receive the first clock signal, and a second end of the fourteenth transistor is electrically connected to the second node; The third control module includes a fifteenth transistor and a sixteenth transistor; the control end of the fifteenth transistor is electrically connected to the second node, the first end of the fifteenth transistor is used to receive the first level signal, the second end of the fifteenth transistor is electrically connected to the first end of the sixteenth transistor; the second end of the sixteenth transistor is electrically connected to the first node, and the control end of the sixteenth transistor is used to receive the second clock signal; The fourth control module includes a seventeenth transistor and an eighteenth transistor; The control end of the seventeenth transistor is electrically connected to the first node, the first end of the seventeenth transistor is used to receive the first level signal, the second end of the seventeenth transistor is electrically connected to the first end of the eighteenth transistor, the second end of the eighteenth transistor is electrically connected to the second node, and the control end of the eighteenth transistor is used to receive the second clock signal.

13. The shift register according to any one of claims 1 to 10, wherein: The control module includes a first control module, a second control module, a third control module and a fourth control module; The first control module is used for transmitting the second level signal to the first node under the control of the first clock signal; The second control module is used for transmitting the start signal to the second node under the control of the first clock signal; The third control module is used for transmitting the first clock signal to the first node under the potential control of the second node; The fourth control module is used to transmit the first level signal to the second node under the control of the second clock signal and the potential of the first node.

14. The shift register according to claim 13, wherein: The first control module includes a nineteenth transistor; a first end of the nineteenth transistor is used to receive the second clock signal, a control end of the nineteenth transistor is used to receive the first clock signal, and a second end of the nineteenth transistor is electrically connected to the first node; The second control module includes a twentieth transistor; a first end of the twentieth transistor is used to receive the start signal, a control end of the twentieth transistor is used to receive the first clock signal, and a second end of the twentieth transistor is electrically connected to the second node; The third control module includes a twenty-first transistor; the control end of the twenty-first transistor is electrically connected to the second node, the first end of the twenty-first transistor is used to receive the first clock signal, and the second end of the twenty-first transistor is electrically connected to the first node; The fourth control module includes a twenty-second transistor and a twenty-third transistor; the control end of the twenty-second transistor is electrically connected to the first node, the first end of the twenty-second transistor is used to receive the first level signal, the second end of the twenty-second transistor is electrically connected to the first end of the twenty-third transistor, the second end of the twenty-third transistor is electrically connected to the second node, and the control end of the twenty-third transistor is used to receive the second clock signal.

15. A scan driving circuit, comprising a plurality of cascaded shift registers, wherein the shift register comprises the shift register according to any one of claims 1 to 14.

16. The scan driving circuit according to claim 15, wherein: In the plurality of cascaded shift registers, the first scanning signal of the shift register is the starting signal of the next stage shift register. 17 . A display panel comprising a display area and a non-display area, wherein the non-display area comprises the scan drive circuit according to claim 15 or 16 .

18. The display panel according to claim 17, wherein: The display area includes a plurality of pixel circuits, and the pixel circuits are electrically connected to at least a first output terminal and a second output terminal of a corresponding shift register in the scan driving circuit.

Images