Scanning drive circuit, and display device and driving method therefor

Abstract

A scanning drive circuit, and a display device and a driving method therefor. The scanning drive circuit (100) comprises: a plurality of cascaded shift registers (10). Each shift register (10) comprises: a drive control module (11) and at least two scanning output modules (13). The drive control module (11) is used for controlling the electric potentials of a first output end (N1) and a second output end (N2) of the drive control module (11) according to an input signal (IN). Each scanning output module (13) is connected to the first output end (N1) and the second output end (N2) and accesses a frequency-switching control signal (SW), and the scanning output module (13) is used for outputting a scanning signal (OUT). Different scanning output modules (13) in the same-stage shift register (10) access different frequency-switching control signals (SW), and the different frequency-switching control signals (SW) are respectively used for controlling the frequencies of switch-on pulses appearing in the scanning signals (OUT) output by corresponding scanning output modules (13).

Description

Scan driving circuit, display device and driving method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 27, 2023, with application number 202310935856.7. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a scan driving circuit, a display device and a driving method thereof. Background Art

[0003] With the development of display technology, the application scenarios of display devices are increasing, and users’ display requirements for display devices are becoming more and more diverse. Based on the release of products such as foldable mobile phones and foldable laptops, the application scenarios of display devices have been further expanded. In response to users’ demand for simultaneous display of multiple applications on terminal products, some interfaces in the display screen (such as game interfaces) need to be displayed at high frequency to ensure the smoothness of the picture, while some interfaces can meet the display requirements with low frequency. This part expects to use low-frequency display to reduce product power consumption. However, in related technologies, in order to realize the regional frequency division control of the display panel, it is necessary to design multiple sets of scanning drive circuits, which makes the overall structure of the drive circuit in the border area of ​​the display panel complex, which is not conducive to the realization of a narrow border of the display panel.

[0004] Summary of the Invention

[0005] The present application provides a scan drive circuit, a display device, and a driving method thereof to simplify the structure of a drive circuit in a display panel frame area, thereby facilitating the realization of a narrow frame of the display panel.

[0006] In a first aspect, an embodiment of the present application provides a scan driving circuit, comprising: a plurality of shift registers arranged in cascade;

[0007] The n-th stage shift register among the plurality of shift registers comprises:

[0008] a driving control module, configured to control the potentials of the first output terminal and the second output terminal of the driving control module according to the input signal inputted by the n-th stage shift register;

[0009] At least two scanning output modules, each of which is connected to the first output terminal and the second output terminal and receives a frequency cutting control signal, and is used to output a scanning signal; wherein different scanning output modules receive different frequency cutting control signals, and different frequency cutting control signals are respectively used to control the frequency of conduction pulses appearing in the scanning signal output by the corresponding scanning output module, wherein n is an integer greater than 0.

[0010] In a second aspect, an embodiment of the present application further provides a display device, comprising: a pixel circuit and a scan drive circuit provided by any embodiment of the present application.

[0011] In a third aspect, an embodiment of the present application further provides a method for driving a display device, for driving a display device as provided in any embodiment of the present application to perform a zoned frequency display in a column direction; the driving method comprises:

[0012] According to the target display partition position of the display device in the column direction, the potential jump time of the frequency cutting control signal in one frame display is controlled so that the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located above the target display partition position is different from the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located below the target display partition position; and the frequency of the conduction pulse appearing in the scanning signal output by all the scanning output modules connected to the same pixel circuit is the same.

[0013] The scanning drive circuit provided in the embodiment of the present application includes a plurality of shift registers arranged in cascade, and each level of the shift register includes: a driving control module and at least two scanning output modules. Each frequency cutting control signal can independently control whether the corresponding scanning output module outputs a scanning signal with a conduction potential, thereby realizing separate control of the working modes of different scanning output modules in the same shift register. By controlling the potential jump time of at least two frequency cutting control signals to be different, the working mode combination of at least two scanning output modules in the same shift register can be made different, so that the same shift register outputs at least two scanning signals with different frequencies of conduction pulses, thereby providing conditions for different levels of shift registers to be connected to the same row of pixel circuits, and the same level of shift registers to be connected to different rows of pixel circuits, ensuring that when the display device performs a zoned frequency display, each row of pixel circuits can work normally, thereby effectively reducing the number of groups of scanning drive circuits in the display panel, which is conducive to simplifying the overall structure of the driving circuit in the display panel frame area, and is conducive to the realization of a narrow frame of the display panel.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic structural diagram of a display panel;

[0016] FIG2 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0017] FIG3 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0018] FIG4 is a driving timing diagram of a pixel circuit provided in an embodiment of the present application;

[0019] FIG5 is a schematic structural diagram of a shift register provided in an embodiment of the present application;

[0020] FIG6 is a schematic structural diagram of another shift register provided in an embodiment of the present application;

[0021] FIG7 is a schematic diagram of a driving timing sequence of a shift register provided in an embodiment of the present application;

[0022] FIG8 is a schematic structural diagram of another shift register provided in an embodiment of the present application;

[0023] FIG9 is a schematic diagram of a driving timing sequence of a display panel provided in an embodiment of the present application;

[0024] FIG10 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0025] FIG11 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0026] FIG12 is a schematic structural diagram of another shift register provided in an embodiment of the present application;

[0027] FIG13 is a schematic structural diagram of another shift register provided in an embodiment of the present application;

[0028] FIG14 is a schematic diagram of a driving timing sequence of another shift register provided in an embodiment of the present application;

[0029] FIG15 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application;

[0030] FIG16 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0031] FIG17 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] As described in the background art, in order to achieve regional frequency division control of the display panel, a complex driving circuit structure needs to be designed in the display panel frame area to provide various scanning signals to the pixel circuits. The following describes the reasons for the above situation with reference to FIG1.

[0033] FIG1 is a schematic diagram of the structure of a display panel. Referring to FIG1 , in the current display panel structure, in order to reduce the border of the display panel, a scheme is designed in which the scan lines connecting different functional modules in different rows of pixel circuits 02 are connected to the same level shift register 01 in the scan drive circuit 010. However, based on this connection method, when the display panel is partitioned and controlled, at least the last row of pixel circuits 02 in each display partition cannot realize its complete function, affecting the display effect. For example: the output signal OUT of the shift register 01 at this level is respectively used as the first scan signal S01 required by the pixel circuit 02 of this row and the second scan signal S02 required by the pixel circuit 02 of the previous row; the pixel circuit 02 can perform the gate reset operation of the driving transistor under the control of the first scan signal S01, and perform the data write operation under the control of the second scan signal S02. Taking the display partition position of the display panel as an example, which is located between the second and third rows of pixel circuits 02, if the first two levels of shift registers 01 are controlled to output on-pulses, and the other levels of shift registers 01 do not output on-pulses, then the first scanning signal S01 received by the second row of pixel circuits 02 has a on-pulse, and the gate reset operation of the second row of pixel circuits 02 can be performed normally, but the second scanning signal S02 received by the second row of pixel circuits 02 does not have a on-pulse, and the data writing operation of the second row of pixel circuits 02 cannot be performed normally, affecting the normal display of the second row of pixel circuits 02.

[0034] Therefore, in the related art, based on the requirements for frequency division control of the display panel by region, in order to prevent the last row of pixel circuits in the display area above the display partition from not displaying properly, it is necessary to design multiple groups of scan drive circuits for different functional modules in the pixel circuit. This makes it impossible to use the same shift register to provide different scan signals for different purposes to different rows of pixel circuits, and it is impossible to achieve functional multiplexing of the same scan drive circuit for different functional modules in different rows of pixel circuits. Excessive groups of scan drive circuits lead to a complex overall structure of the drive circuit in the display panel border area, which is not conducive to achieving a narrow border on the display panel.

[0035] In order to avoid the above situation, an embodiment of the present application provides a scanning drive circuit so that the shift register at the same level in the scanning drive circuit can provide at least two scanning signals with different frequencies of conduction pulses, providing conditions for the shift register at the same level to connect different rows of pixel circuits, which is conducive to reducing the number of groups of scanning drive circuits in the display panel and is conducive to achieving a narrow border of the display panel. Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present application. Referring to Figure 2, the display panel may include a display area AA and a non-display area NAA surrounding the display area AA. An array-arranged pixel circuit 20 may be provided in the display area AA, and a scanning drive circuit 100 may be provided in the non-display area NAA for providing scanning signals to each row of pixel circuits 20.

[0036] The scan drive circuit 100 includes: a plurality of shift registers 10 arranged in cascade. The nth (n is an integer greater than 0) stage shift register 10 of the plurality of shift registers 10 includes: a drive control module 11 and at least two scan output modules 13. The drive control module 11 is used to control the potential of the first output terminal N1 and the second output terminal N2 of the drive control module 11 according to the input signal IN connected to the shift register 10. The scan output module 13 is connected to the first output terminal N1 and the second output terminal N2, and is connected to the frequency cutting control signal SW. The scan output module 13 is used to output the scan signal OUT. Different scan output modules 13 in the same stage shift register 10 are connected to different frequency cutting control signals SW, and different frequency cutting control signals SW are used to control the frequency of the on-pulse in the scan signal OUT output by the corresponding scan output module 13.

[0037] As shown in FIG2 , each stage of the shift register 10 includes two scan output modules 13. The two scan output modules 13 actually have the same circuit structure. For ease of distinction, one of the scan output modules is referred to as the first scan output module and is labeled 131; and the other scan output module is referred to as the second scan output module and is labeled 132. Accordingly, the frequency cutting control signal received by the first scan output module 131 is recorded as the first frequency cutting control signal SW1, and the scan signal outputted is recorded as the first scan signal OUT1; the frequency cutting control signal received by the second scan output module 132 is recorded as the second frequency cutting control signal SW2, and the scan signal outputted is recorded as the second scan signal OUT2.

[0038] Exemplarily, the scan output module 13 selects whether to perform a shifted output of the input signal IN under the combined control of the potentials of the first output terminal N1 and the second output terminal N2, as well as the frequency-cutting control signal SW. Exemplarily, the frequency-cutting control signal SW can be used to control whether the potentials of the first output terminal N1 and / or the second output terminal N2 can be transmitted to an internal node of the scan output module 13, thereby controlling whether the scan output module 13 can output a conduction potential, thereby controlling the frequency of conduction pulses appearing in the scan signal. The conduction pulse can be understood as a pulse composed of a potential that can control the conduction of a functional module connected to the scan signal. For example, when the functional module includes an N-type transistor, the conduction pulse is a high-potential pulse.

[0039] Since different scan output modules 13 in the same level shift register 10 are connected to different frequency cutting control signals SW, based on each frequency cutting control signal SW, different scan output modules 13 in the same level shift register 10 can be independently controlled, so that the frequencies of the conduction pulses appearing in the multiple scan signals OUT output by the same shift register 10 can be freely matched according to actual needs without affecting each other.

[0040] On the basis of the above embodiments, optionally, as shown in Figure 2, the n-th stage shift register 10 may further include a stage transfer output module 12, which is respectively connected to the first output terminal N1 and the second output terminal N2 in the n-th stage shift register 10, and is used to output the stage transfer signal Carry in response to the potential of the first output terminal N1 and the second output terminal N2; the stage transfer signal Carry can be used as the input signal IN of the n+s-th stage shift register 10; wherein s is an integer greater than 0; Figure 2 exemplarily shows the case of s=1.

[0041] Exemplarily, the level transmission output module 12 is directly controlled by the potential of the first output terminal N1 and the second output terminal N2 to achieve shift output of the input signal IN. Since the shift registers 10 at each level are cascaded through the level transmission output module 12, when the input signal connected to the first-level shift register includes a conduction pulse, the conduction pulse of the first-level input signal can be shifted and output step by step through each level transmission output module 12, providing a high-frequency level transmission signal sequence with the same frequency as the first-level input signal. In this way, conditions can be provided for each scanning output module 13 in each level of the shift register 10 to select whether to output a conduction pulse based on the control of the corresponding frequency cutting control signal SW. In the following explanation process, the shift register 10 including the drive control module 11, the level transmission control module 12 and the two scanning output modules 13 are used as an example for explanation.

[0042] Specifically, under the control of the frequency switching control signal SW, each scanning output module 13 can have the following two working modes:

[0043] In the first operating mode, during a frame of display, the frequency-cutting control signal SW maintains a level that enables at least one of the potentials of the first output terminal N1 and the second output terminal N2 to be transmitted to an internal node of the scan output module 13, causing the scan output module 13 to have the same output state as the level output module 12. When the level output module 12 outputs an on-state potential, the scan signal output by the scan output module 13 also has an on-state potential. Therefore, in this mode, both the level output signal Carry and the scan signal OUT contain on-state pulses.

[0044] In the second operating mode, during a frame of display, the frequency-cutting control signal SW undergoes a potential jump, so that when the level-transmitting output module 12 outputs an on-state potential, at least one of the potentials at the first output terminal N1 and the second output terminal N2 cannot be transmitted to the internal nodes of the scan output module 13. This causes the scan output module 13 to have an output state different from that of the level-transmitting output module 12, and the scan signal output by the scan output module 13 does not include an on-state potential. Therefore, in this mode, only the level-transmitting signal Carry contains an on-state pulse, and the scan signal OUT does not contain an on-state pulse.

[0045] When a certain scan output module 13 operates in the first operating mode in each display frame, the frequency of the on-pulses appearing in the scan signal OUT output by the scan output module 13 is the same as the frequency of the on-pulses appearing in the level transfer signal Carry output by the level transfer output module 12 in the shift register 10 in which the scan output module 13 is located. When a certain scan output module 13 operates in the second operating mode in at least part of the display frames, the frequency of the on-pulses appearing in the scan signal OUT output by the scan output module 13 is lower than the frequency of the on-pulses appearing in the level transfer signal Carry output by the level transfer output module 12 in the shift register 10 in which the scan output module 13 is located. Therefore, by controlling the potential jump time of each frequency switching control signal SW in each display frame, the frequency of the on-pulses appearing in the scan signal OUT output by each scan output module 13 can be controlled separately, thereby providing conditions for the same scan drive circuit 100 to multiplex the functions of different functional modules in different rows of pixel circuits 20.

[0046] Exemplarily, in a display panel, the output ends of at least two scan output modules 13 in the same level of shift register 10 are respectively connected to at least two rows of pixel circuits 20, and the output ends of some scan output modules 13 in at least two levels of shift registers 10 are connected to different functional modules in the same row of pixel circuits 20. Exemplarily, some scan output modules 13 in the current level of shift register 10 and some scan output modules 13 in the previous level (previous level or multiple levels) of shift register 10 are connected to the same row of pixel circuits 20, and other scan output modules 13 in the current level of shift register 10 are connected to other rows (one or more rows) of pixel circuits 20. Specifically, the output of the nth-stage first scan output module 131 is connected to the nth-row pixel circuit 20, and the conduction pulse output by the nth-stage first scan output module 131 acts on the first phase of the nth-row pixel circuit 20; the output of the n+mth-stage second scan output module 132 is connected to the nth-row pixel circuit 20, and the conduction pulse output by the n+mth-stage second scan output module 132 acts on the second phase of the nth-row pixel circuit 20; wherein, for the same pixel circuit 20, in the same display frame, the first phase occurs before the second phase; m is an integer greater than 0. For example, as shown in FIG2 , when m=1, the outputs of the two scan output modules 13 in the rth-stage shift register 10 are connected to the r-1th and rth-row pixel circuits 20, respectively, where r is an integer greater than 1. Furthermore, the first scan output module 131 in the j-th stage shift register 10 and the second scan output module 132 in the j+1-th stage shift register 10 are both connected to the j-th row pixel circuit 20. The j-th stage first scan signal OUT1 serves as the first control signal S1 required for the j-th row pixel circuit 20, and the j+1-th stage second scan signal OUT2 serves as the second control signal S2 required for the j-th row pixel circuit 20, where j is an integer greater than 0. The first control signal S1 is used, for example, to control the gate reset process of the driving transistor in the pixel circuit 20, i.e., the first stage corresponds to the reset stage in the driving process of the pixel circuit 20; the second control signal S2 is used, for example, to control the data writing process in the pixel circuit 20, i.e., the second stage corresponds to the data writing stage in the driving process of the pixel circuit 20.

[0047] Each frequency switching control signal SW controls the frequency of on-pulses in the scan signal OUT output by the scan output module 13 connected to the pixel circuits 20 located above the display partition position, based on the display partition position of the display panel in the column direction. This frequency is different from the frequency of on-pulses in the scan signal OUT output by the scan output module 13 connected to the pixel circuits 20 located below the display partition position, thereby achieving a zoned frequency-controlled display in the column direction of the display panel. The on-pulse frequencies in the scan signal OUT output by multiple scan output modules 13 connected to the same row of pixel circuits 20 are the same, ensuring that the pixel circuits 20 in that row function normally throughout the entire display process.

[0048] Specifically, when the display partition position is located between the i-th (i is an integer greater than 0) row of pixel circuits 20 and the i+1-th row of pixel circuits 20, in some display frames, the first frequency cutting control signal SW1 undergoes a potential jump before the i-th level first scanning output module 131 outputs the on-pulse, so that the frequency of the on-pulse appearing in the scanning signal output by the i-th level first scanning output module 131 is different from the frequency of the on-pulse appearing in the scanning signal output by the i+1-th level first scanning output module 131, thereby realizing partitioned frequency display of the display panel in the column direction. In addition, in the display frame corresponding to the first frequency cutting control signal SW1 undergoing a potential jump, the second frequency cutting control signal SW2 undergoes a potential jump before the second scanning output module 132 of the i+mth level outputs the on-pulse, so that the frequency of the on-pulse appearing in the second scanning signal OUT2 output by the second scanning output module 132 connected to each row of pixel circuits 20 is the same as the frequency of the on-pulse appearing in the first scanning signal OUT1 output by the first scanning output module 131 connected to the corresponding row of pixel circuits 20, which can effectively ensure the normal display of each row of pixel circuits 20.

[0049] For multiple rows of pixel circuits 20, during a single frame of display, when the first scanning signals OUT1 output by the first scanning output modules 131 of the i-th to i+k-th stages do not have an on-pulse, the second scanning signals OUT2 output by the second scanning output modules 132 of the i+m-th to i+m+k-th stages also do not have an on-pulse. When the first scanning signals OUT1 output by the first scanning output modules 131 of the i-th to i+k-th stages have an on-pulse, the second scanning signals OUT2 output by the second scanning output modules 132 of the i+m-th to i+m+k-th stages also have an on-pulse. This effectively ensures that the on-pulse frequencies of the scanning signals OUT output by the multiple scanning output modules 13 connected to the same pixel circuit 20 are the same, thereby ensuring that the pixel circuit 20 can function normally. i and k are both integers greater than 0.

[0050] Still taking the specific connection relationship between the scan driving circuit 100 and the pixel circuit 20 in Figure 2 as an example, when the target display partition position is located between the first row of pixel circuits 20 and the second row of pixel circuits 20, for example, the data refresh frequency of the first row of pixel circuits 20 is higher than the data refresh frequency of the second row of pixel circuits 20, the frequency of the on-pulses in the first scan signal OUT1 output by the first scan output module 131 in the first-stage shift register can be controlled to be the same as the frequency of the on-pulses in the second scan signal OUT2 output by the second scan output module 132 in the second-stage shift register, and both can be controlled to be greater than the frequency of the on-pulses in the first scan signal OUT1 output by the first scan output module 131 in the second-stage shift register; and the frequency of the on-pulses in the first scan signal OUT1 output by the first scan output module 131 in the second-stage shift register can be controlled to be the same as the frequency of the on-pulses in the second scan signal OUT2 output by the second scan output module 132 in the third-stage shift register, so as to ensure that the first row of pixel circuits 20 operates at a high data refresh frequency and the second row of pixel circuits 20 operates at a low data refresh frequency.

[0051] The scan drive circuit provided in the embodiment of the present application includes multiple shift registers 10 arranged in cascade, and each level of the shift register 10 includes: a drive control module 11 and at least two scan output modules 13. Each frequency cutting control signal SW can independently control whether the corresponding scan output module 13 outputs a scan signal with a conductive potential, thereby realizing separate control of the operating modes of different scan output modules 13 in the same shift register 10. By controlling the potential jump time of at least two frequency cutting control signals SW to be different, the operating mode combinations of at least two scan output modules 13 in the same shift register 10 can be different, so that the same shift register 10 outputs at least two scan signals with different frequencies of conductive pulses. This provides conditions for connecting different levels of shift registers 10 to the same row of pixel circuits 20, and for connecting the same level of shift registers 10 to different rows of pixel circuits 20. This ensures that when the display device performs a zoned frequency display, each row of pixel circuits can operate normally, thereby effectively reducing the number of groups of scan drive circuits 100 in the display panel, simplifying the overall structure of the display panel frame area drive circuit, and facilitating the realization of a narrow frame of the display panel.

[0052] On the basis of the above-mentioned embodiments, when a level transmission output module 12 is provided in the shift register 10, based on the potential control of the first output terminal N1 and the second output terminal N2 by the driving control module 11, the level transmission output module 12 at each level can realize the step-by-step shift output of the first-level input signal, and provide a level transmission signal Carry with the same frequency as the first-level input signal, which provides a basis for each scanning output module 13 in the shift register 10 at each level to freely select the output of the scanning signal with the same frequency as the first-level input signal or the frequency of the conduction pulse lower than the first-level input signal based on the control of the frequency cutting control signal SW.

[0053] Based on the above embodiments, one scan output module 13 is optionally selected from each shift register 10 to collectively form a scan output group, with different scan output modules 13 in the same shift register 10 belonging to different scan output groups. For example, the first scan output module 131 in each shift register 10 constitutes one scan output group, and the second scan output module 132 in each shift register 10 constitutes another scan output group. Each scan output module 13 in the same scan output group can be connected to the same frequency-slicing control signal SW to simplify the structure of the scan driver circuit 100 and the wiring of the display panel, while also reducing the number of output ports on the driver chip, making the scan driver circuit 100 easier to implement and generalize. Furthermore, for any scan output group, the frequency-slicing control signal SW undergoes a potential jump during at least a portion of a display frame. This can cause the frequencies of the on-pulses in the scan signals output by at least two scan output modules 13 in the scan output group to differ within that display frame, thereby achieving display with different frequencies in the column direction of the display panel.

[0054] Based on the above embodiments, optionally, each scan output module 13 in the same scan output group is connected to the same functional module in each row of pixel circuits 20. For example, each first scan output module 131 is connected to the access terminal corresponding to the first control signal S1 in the pixel circuit 20; each second scan output module 132 is connected to the access terminal corresponding to the second control signal S2 in the pixel circuit 20. Furthermore, multiple scan output modules 13 connected to different functional modules in the same pixel circuit 20 belong to different scan output groups and are located in different stages of the shift register 10. For example, the first row of pixel circuits 20 is connected to the first scan output module 131 in the first stage of the shift register 10 and the second scan output module 132 in the second stage of the shift register 10, respectively. The first scan output module 131 and the second scan output module 132 belong to different scan output groups. This configuration allows each frequency switching control signal SW to control the frequency of the on-pulses in the scan signal OUT output by each scan output module 13 on a scan output group basis, which helps simplify the control logic.

[0055] Based on the above embodiments, optionally, any scan output module 13 may include a transmission control unit and a scan output unit. The scan output unit may have the same functional circuit structure as the level transmission output module 12, for example, including two control terminals, a conduction potential input terminal, a cutoff potential input terminal, and an output terminal. The potential of one control terminal is used to control whether the cutoff potential input terminal is connected to the output terminal, and the potential of the other control terminal is used to control whether the conduction potential input terminal is connected to the output terminal, so that the functional circuit can control the output signal of its output terminal to be a conduction potential or a cutoff potential based on the potentials of its two control terminals. The transmission control unit can control the on and off of its internal circuit based on the frequency switching control signal SW, thereby controlling whether at least one control terminal of the scan drive unit can be connected to the drive control module 11 through the transmission control unit, so as to control whether the scan output unit can output a conduction potential, thereby controlling the frequency of conduction pulses appearing in the scan signal. Exemplarily, the first connection terminal of the transmission control unit is connected to one of the first output terminal N1 and the second output terminal N2, and the second connection terminal of the transmission control unit is connected to the frequency cutting control signal SW; the first control terminal of the scanning output unit is connected to the third connection terminal of the transmission control unit, and the second control terminal of the scanning output unit is connected to the other of the first output terminal N1 and the second output terminal N2; then the transmission control unit can control the frequency of the conduction pulse appearing in the scanning signal output by the scanning output unit by controlling the potential of its third connection terminal.

[0056] The above embodiments exemplify the working principles of the functional modules in the scan driver circuit 100. The following describes the specific connection method between the scan driver circuit 100 and the pixel circuit 20, as well as the specific structure that each level of the shift register 10 may have, in combination with the specific structure of the pixel circuit 20.

[0057] FIG3 is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present application. Referring to FIG3, in one embodiment, optionally, the pixel circuit 20 includes: a driving module 21 including a driving transistor DTFT; a data writing module 22 including a data writing transistor M24; a threshold compensation module 23 including a threshold compensation transistor M25; a gate reset module 24 including a gate initialization transistor M22; an anode reset module 25 including an anode initialization transistor M23; a light emitting control module 26 including a first light emitting control transistor M26 and a second light emitting control transistor M27; and a storage module 27 including a storage capacitor Cst, forming a pixel circuit 20 with a 7T1C architecture.

[0058] Specifically, a first light-emitting control transistor M26, a driving transistor DTFT, a second light-emitting control transistor M27, and a light-emitting device OLED are connected in series in sequence; a data writing transistor M24 is connected to a data voltage Vdata and electrically connected to a first electrode of the driving transistor DTFT; a threshold compensation transistor M25 is connected between the gate and the second electrode of the driving transistor DTFT; a gate initialization transistor M22 is connected to a first initialization signal Vref1 and electrically connected to the gate of the driving transistor DTFT; an anode initialization transistor M23 is connected to a second initialization signal Vref2 and electrically connected to the anode of the light-emitting device OLED; a cathode of the light-emitting device OLED is connected to a second power supply signal VSS; one end of a storage capacitor Cst is connected to the gate of the driving transistor DTFT, and the other end is connected to the first power supply signal VDD. The gate of the gate initialization transistor M22 is connected to a first control signal S1, the gate of the threshold compensation transistor M25 is connected to a second control signal S2, the gate of the data writing transistor M24 is connected to a third control signal S3, and the gate of the anode initialization transistor M23 is connected to a fourth control signal S4. The gates of the first light-emitting control transistor M26 and the second light-emitting control transistor M27 are both connected to a light-emitting control signal EM. For example, the threshold compensation transistor M25 and the gate initialization transistor M22 may be N-type transistors, and the other transistors may be P-type transistors, forming a low temperature polycrystalline oxide (LTPO) pixel circuit.

[0059] FIG4 is a schematic diagram of a driving timing of a pixel circuit provided in an embodiment of the present application. In conjunction with FIG3 and FIG4 , illustratively, when the pixel circuit 20 is displayed at a low frequency, a display cycle may include one refresh frame FA and at least one hold frame FI. When displayed at a high frequency, a display cycle may include only the refresh frame FA. The refresh frame FA includes a reset phase T21, a data write phase T22, and a first light-emitting phase T23. The hold frame FI includes a black insertion phase T24 and a second light-emitting phase T25, and no data is written during the black insertion phase T24.

[0060] Specifically, based on the low-frequency refresh scenario, and taking the third control signal S3 and the fourth control signal S4 having the same timing as an example, the driving process of the pixel circuit 20 includes:

[0061] In the reset phase T21, the first control signal S1, the third control signal S3, the fourth control signal S4 and the light emitting control signal EM are all high, the gate initialization transistor M22 is turned on, and the first initialization signal Vref1 resets the gate of the driving transistor DTFT through the gate initialization transistor M22.

[0062] During the data writing phase T22, the first control signal S1, the third control signal S3, and the fourth control signal S4 are all at low levels, while the second control signal S2 and the light-emitting control signal EM are both at high levels. The gate initialization transistor M22 is turned off, and the anode initialization transistor M23, the data writing transistor M24, and the threshold compensation transistor M25 are all turned on. The data signal Vdata is transmitted to the gate of the drive transistor DTFT via the data writing transistor M24, the first and second electrodes of the drive transistor DTFT, and the threshold compensation transistor M25. Simultaneously, the second initialization signal Vref2 is transmitted via the anode initialization transistor M23 to reset the anode of the light-emitting device OLED.

[0063] In the first light-emitting stage T23, the first control signal S1, the second control signal S2, and the light-emitting control signal EM are all at low levels, while the third control signal S3 and the fourth control signal S4 are at high levels. The threshold compensation transistor M25 is turned off, the first light-emitting control transistor M26 and the second light-emitting control transistor M27 are both turned on, and the drive transistor DTFT generates a drive current to drive the light-emitting device OLED to emit light.

[0064] During the black insertion phase T24, the first control signal S1 and the second control signal S2 maintain a low potential, the third control signal S3 maintains a high potential, and the light-emitting control signal EM becomes a high potential. The first light-emitting control transistor M26 and the second light-emitting control transistor M27 are both turned off, and the light-emitting device OLED stops emitting light. During this phase, the fourth control signal S4 may have a conduction pulse (i.e., a low potential pulse) to control the anode initialization transistor M23 to turn on, resetting the anode of the light-emitting device OLED. This allows the light-emitting brightness of the light-emitting device OLED during the second light-emitting phase T25 to be closer to that during the first light-emitting phase T23.

[0065] In the second light-emitting stage T25, the first control signal S1 and the second control signal S2 maintain a low level, the third control signal S3 and the fourth control signal S4 maintain a high level, and the light-emitting control signal EM changes to a low level again. The first light-emitting control transistor M26 and the second light-emitting control transistor M27 are turned on again, and the driving transistor DTFT generates a driving current again, driving the light-emitting device OLED to emit light.

[0066] The subsequent stages repeat the driving process of the frame FI until the next refresh frame FA arrives.

[0067] From the above analysis, it can be seen that the driving process of the pixel circuit 20 in Figure 3 requires the first control signal S1 and the second control signal S2 to be turned on in a staggered manner. Therefore, a scanning drive circuit 100 capable of outputting a low-voltage scanning signal for a long time can be set accordingly to provide the first control signal S1 and the second control signal S2, and a specific connection method similar to that of the scanning drive circuit 100 and the pixel circuit 20 in Figure 2 is adopted to drive each row of pixel circuits 20. It should be noted that for the LTPO pixel circuit, the two scanning output modules 13 of the same shift register 10 in the scanning drive circuit 100 can be connected to two adjacent rows of pixel circuits 20, or to two non-adjacent rows of pixel circuits 20, and the specific setting can be based on actual needs. For example, when it is required that the turn-on pulses of the first control signal S1 and the second control signal S2 are completely non-overlapping, the two scanning output modules 13 of the same shift register 10 can be set to be connected to two non-adjacent rows of pixel circuits 20 respectively.

[0068] The structure of the scan drive circuit 100 that can output a low-potential scan signal for a long time (i.e., the conduction pulse output by the scan output module 13 is a high potential) is described below. Figure 5 is a schematic diagram of the structure of a shift register provided by an embodiment of the present application. Referring to Figure 5, in one embodiment, optionally, the drive control module 11 controls the potential of the first output terminal N1 and the second output terminal N2 in response to the first clock signal ECK1, the second clock signal ECK2, the input signal IN, the first potential signal VGL, and the second potential signal VGH. The level transmission output module 12 outputs the first potential signal VGL or the second potential signal VGH as the level transmission signal Carry according to the potential of the first output terminal N1 and the second output terminal N2. For any scan output module 13, the transmission control unit 1301 is used to control whether the potential of the second output terminal N2 is transmitted to the third connection terminal N3 of the transmission control unit 1301 according to the frequency cutting control signal and the level transmission signal Carry. The scan output unit 1302 is used to respond to the potential of the first output terminal N1 and the third connection terminal N3 and output the first potential signal VGL or the second potential signal VGH as the scan signal.

[0069] For example, the first potential signal VGL and the second potential signal VGH can be DC voltage signals with different potentials, for example, the first potential signal VGL is low and the second potential signal VGH is high. The first clock signal ECK1 and the second clock signal ECK2 are both clock signals with alternating high and low potentials.

[0070] Specifically, referring to FIG. 6 , the driving control module 11 includes a first input unit 111 , a first control unit 112 , a second control unit 113 , a first node control unit 114 , a second node control unit 115 and a third node control unit 116 .

[0071] The first input unit 111 includes a transistor M21 having a gate connected to the first clock signal ECK1, a first electrode connected to the input signal IN, and a second electrode connected to the first output terminal N1. The first input unit 111 is configured to transmit the input signal IN to the first output terminal N1 in response to the first clock signal ECK1.

[0072] The first control unit 112 includes a transistor M12, wherein a gate of the transistor M12 is connected to the first clock signal ECK1, a first electrode is connected to the first potential signal VGL, and a second electrode is connected to the output terminal of the first control unit 112. The first control unit 112 is configured to transmit the first potential signal VGL to the output terminal of the first control unit 112 in response to the first clock signal ECK1.

[0073] The second control unit 113 includes transistors M17 and M18, and a capacitor C13. The gate of transistor M17 is connected to the output terminal of the first control unit 112, the first electrode is connected to the second clock signal ECK2, and the second electrode is connected to the first electrode of transistor M18. The gate of transistor M18 is connected to the second clock signal ECK2, and the second electrode is connected to the second output terminal N2. Capacitor C13 is connected between the gate and the second electrode of transistor M17. The second control unit 113 is configured to control the potential of the second output terminal N2 based on the second clock signal ECK2 and the potential of the output terminal of the first control unit 112.

[0074] The first node control unit 114 includes a transistor M13. The gate of the transistor M13 is connected to the first output terminal N1, the first electrode is connected to the first clock signal ECK1, and the second electrode is connected to the output terminal of the first control unit 112. The first node control unit 114 is configured to control the potential of the output terminal of the first control unit 112 based on the potential of the first output terminal N1.

[0075] The second node control unit 115 includes transistors M14 and M15. Transistor M14 has a gate connected to the output terminal of the first control unit 112, a first electrode connected to the second potential signal VGH, and a second electrode connected to the first electrode of transistor M15. Transistor M15 has a gate connected to the second clock signal ECK2, and a second electrode connected to the first output terminal N1. Second node control unit 115 is configured to control the potential of first output terminal N1 based on the potential of the output terminal of first control unit 112.

[0076] The third node control unit 116 includes a transistor M19, whose gate is connected to the first output terminal N1, whose first electrode is connected to the second potential signal VGH, and whose second electrode is connected to the second output terminal N2. The third node control unit 116 is configured to control the potential of the second output terminal N2 based on the potential of the first output terminal N1.

[0077] The level transmission output module 12 includes a first output unit 121 and a second output unit 122 .

[0078] The first output unit 121 may include a transistor M31, the gate of the transistor M31 being connected to the first output terminal N1, the first electrode being connected to the first potential signal VGL, and the second electrode being connected to the output terminal of the stage transmission output module 12. The first output unit 121 is configured to respond to the potential of the first output terminal N1 and output the first potential signal VGL as the stage transmission signal Carry. Furthermore, the first output unit 121 may further include a capacitor C14, the first end of the capacitor C14 being connected to the second clock signal ECK2, the second end being connected to the first output terminal N1, and the capacitor C14 being configured to reduce the potential of the first output terminal N1 based on coupling at the falling edge of the second clock signal ECK2, so that the transistor M31 can be fully turned on.

[0079] The second output unit 122 may include a transistor M32 and a capacitor C12. The gate of the transistor M32 is connected to the second output terminal N2, the first electrode is connected to the second potential signal VGH, and the second electrode is connected to the output terminal of the stage transmission output module 12. The capacitor C12 is connected between the gate and the first electrode of the transistor M32. The second output unit 122 is configured to respond to the potential of the second output terminal N2 and output the second potential signal VGH as the stage transmission signal Carry.

[0080] Based on the above implementations, optionally, for any scan output module:

[0081] The transmission control unit 1301 includes: a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is connected to the output end of the stage transmission output module 12, the first electrode of the first transistor M1 is connected to the frequency cutting control signal, and the second electrode of the first transistor M1 is connected to the gate of the second transistor M2; the first electrode of the second transistor M2 is connected to the first connection end of the transmission control unit 1301, the first connection end is connected to the second output end N2, and the second electrode of the second transistor M2 is connected to the third connection end N3.

[0082] The scan output unit 1302 includes: a third transistor M3, a fourth transistor M4 and a first capacitor C1; the gate of the third transistor M3 is connected to the first output terminal N1, the first electrode of the third transistor M3 is connected to the first potential signal VGL, and the second electrode of the third transistor M3 is connected to the output terminal of the scan output unit 1302; the gate of the fourth transistor M4 is connected to the third connection terminal N3, the first electrode of the fourth transistor M4 is connected to the second potential signal CGH, and the second electrode of the fourth transistor M4 is connected to the output terminal of the scan output unit 1302; the first capacitor C1 is connected between the gate and the first electrode of the fourth transistor M4.

[0083] Based on the structure of the shift register 10 in FIG6 , the driving process of the shift register 10 will be described below in conjunction with FIG7 , taking the case where all transistors in the shift register 10 are P-type transistors as an example. In order to fully illustrate the working process of the circuit, FIG7 exemplifies the first scanning output module 131 operating in the first working mode and the second scanning output module 132 operating in the second working mode. However, this does not limit the present application. In essence, the first scanning output module 131 and the second scanning output module 132 have the same control logic. In actual applications, any scanning output module can be controlled to operate in any mode as needed. Below, in conjunction with FIG6 and FIG7 , the control method under the first working mode will be described first, taking the working process of the first scanning output module 131 as an example.

[0084] Exemplarily, the working process of the shift register 10 includes:

[0085] In the first stage T11, the first clock signal ECK1 and the first frequency-cutting control signal SW1 are at low levels, while the second clock signal ECK2 and the input signal IN are at high levels. Transistors M21 and M12 are turned on, while transistors M15 and M18 are turned off. The high level of the input signal IN is transmitted to the first output terminal N1 via transistor M21, causing the potential VN1 of the first output terminal N1 to be high, turning off transistors M13, M19, M31, and the third transistor M3. The low level of the first potential signal VGL is transmitted to the output terminal of the first control unit 112 via transistor M12, turning on transistors M14 and M17. Due to the storage function of capacitor C12, the potential VN2 of the second output terminal N2 remains at the high level of the previous stage, turning off transistor M32. Therefore, the stage transfer signal Carry remains at the low level of the previous stage. The stage transfer signal Carry controls the conduction of the first transistor M1, and the low level of the first frequency-cutting control signal SW1 is transmitted to the gate of the second transistor M2, turning on the second transistor M2. The high potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2 to control the fourth transistor M4 to be turned off, so the first scan signal OUT1 also maintains the low potential of the previous stage.

[0086] In the second stage T12, the second clock signal ECK2 and the first frequency cutting control signal SW1 are at a low potential, while the first clock signal ECK1 and the input signal IN are at a high potential. Transistors M15 and M18 are turned on, while transistors M21 and M12 are turned off. Due to the storage function of capacitor C13, the output terminal of the first control unit 112 maintains the low potential of the previous stage, turning on transistors M14 and M17. The high potential of the second potential signal VGH is transmitted to the first output terminal N1 through transistors M14 and M15, causing transistors M13, M19, M31, and the third transistor M3 to remain in an off state. The low potential of the second clock signal ECK2 is transmitted to the second output terminal N2 through transistors M17 and M18, causing the potential VN2 of the second output terminal N2 to change to a low potential, turning on transistor M32. The second potential signal VGH is output through transistor M32, causing the stage transfer signal Carry to change to a high potential. The stage transfer signal Carry controls the first transistor M1 to be turned off. The low potential of the first frequency-cutting control signal SW1 cannot be transmitted to the gate of the second transistor M2. The gate of the second transistor M2 maintains the low potential of the previous stage, controlling the second transistor M2 to be turned on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to be turned on. The second potential signal VGH is output through the fourth transistor M4, causing the first scan signal OUT1 to also be at a high potential.

[0087] In the third stage T13, the first clock signal ECK1 and the first frequency cutting control signal SW1 are at a low potential, while the second clock signal ECK2 and the input signal IN are at a high potential. Transistors M21 and M12 are turned on, while transistors M15 and M18 are turned off. The high potential of the input signal IN is transmitted to the first output terminal N1 via transistor M21, turning off transistors M13, M19, M31, and the third transistor M3. The low potential of the first potential signal VGL is transmitted to the output terminal of the first control unit 112 via transistor M12, turning on transistors M14 and M17. The high potential of the second clock signal ECK2 is output via transistor M17. However, since transistor M18 is turned off, this high potential cannot be transmitted to the second output terminal N2. Due to the storage function of capacitor C12, the second output terminal N2 maintains the low potential of the previous stage, causing transistor M32 to remain on and the stage transfer signal Carry to remain high. The first transistor M1 is turned off by the level transfer signal Carry. The low potential of the first frequency-cutting control signal SW1 cannot be transmitted to the gate of the second transistor M2. The gate of the second transistor M2 continues to maintain a low potential, turning on the second transistor M2. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, turning on the fourth transistor M4. The second potential signal VGH is output through the fourth transistor M4, causing the first scan signal OUT1 to also maintain a high potential.

[0088] In the fourth stage T14, the first clock signal ECK1 is at a high level, while the second clock signal ECK2, the first frequency-cutting control signal SW1, and the input signal IN are at a low level. Transistors M21 and M12 are turned off, while transistors M15 and M18 are turned on. Due to the storage function of capacitor C13, the output terminal of the first control unit 112 maintains the low level from the previous stage, turning on transistors M14 and M17. The high level of the second potential signal VGH is transmitted to the first output terminal N1 via transistors M14 and M15, turning off transistors M13, M19, M31, and the third transistor M3. The low level of the second clock signal ECK2 is transmitted to the second output terminal N2 via transistors M17 and M18, turning on transistor M32. The high level of the second potential signal VGH is transmitted via transistor M32, and the stage transfer signal Carry remains high. The stage transfer signal Carry still controls the first transistor M1 to be turned off, while the gate of the second transistor M2 continues to maintain a low level, controlling the second transistor M2 to be turned on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to be turned on. The second potential signal VGH is output through the fourth transistor M4, so that the first scan signal OUT1 also maintains a high potential.

[0089] In the fifth stage T15, the second clock signal ECK2 is at a high level, while the first clock signal ECK1, the first frequency-cutting control signal SW1, and the input signal IN are at a low level. Transistors M21 and M12 are turned on, while transistors M15 and M18 are turned off. The low level of the input signal IN is transmitted to the first output terminal N1 via transistor M21, causing the potential VN1 of the first output terminal N1 to change to a low level. This controls transistors M13, M19, M31, and the third transistor M3 to all turn on. The low level of the first clock signal ECK1 is transmitted to the output terminal of the first control unit 112 via transistor M13, causing transistors M14 and M17 to turn on. The high level of the second clock signal ECK2 is output via transistor M17. However, because transistor M18 is turned off, this high level cannot be transmitted to the second output terminal N2. The high level of the second potential signal VGH is transmitted to the second output terminal N2 via transistor M19, causing the potential VN2 of the second output terminal N2 to change to a high level, and controlling transistor M32 to turn off. The low potential of the first potential signal VGL is output through transistor M31, and the level transfer signal Carry changes to a low potential. The level transfer signal Carry controls the conduction of the first transistor M1, and the low potential of the first frequency cutting control signal SW1 is transmitted to the gate of the second transistor M2, controlling the conduction of the second transistor M2. The high potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the turn-off of the fourth transistor M4. The low potential of the first potential signal VGL is transmitted through the third transistor M3, and the first scan signal OUT1 also changes to a low potential.

[0090] In the sixth stage T16, the first clock signal ECK1 is high, while the second clock signal ECK2, the first frequency-cutting control signal SW1, and the input signal IN are low. Transistors M15 and M18 are turned on. Due to the coupling effect of capacitor C14, as the second clock signal ECK2 becomes low, the potential of the first output terminal N1 becomes lower than that in the fifth stage T15, causing transistors M31 and the third transistor M3 to be more fully turned on. The high potential of the first clock signal ECK1 is transmitted to the output terminal of the first control unit 112 via transistor M13, turning off transistors M17 and M14. The high potential of the second potential signal VGH is transmitted to the second output terminal N2 via transistor M19, turning off transistor M32. The low potential of the first potential signal VGL is output via transistor M31, and the stage transfer signal Carry remains low. Simultaneously, the low potential of the first potential signal VGL is output via the third transistor M3, and the first scan signal OUT1 also remains low.

[0091] Subsequently, the fifth stage T15 and the sixth stage T16 are repeated, and the stage transfer signal Carry and the first scan signal OUT1 both maintain a low level until the input signal IN becomes a high level again.

[0092] The above embodiment exemplifies that when the first scan output module 131 operates in the first operating mode, the first frequency cutting control signal SW1 maintains a low potential VL throughout the entire display frame, but this is not intended to limit the present application. In other embodiments, when the first scan output module 131 operates in the first operating mode, the first frequency cutting control signal SW1 may also undergo potential jumps, and may include at least one high potential holding stage. As long as the gate potential of the second transistor M2 can be controlled to maintain a low potential before and after each potential jump edge of the second output terminal N2, so that the third connection terminal N3 can change with the potential VN2 of the second output terminal N2, the driving process of the first operating mode can be achieved.

[0093] The control method in the second working mode is described below by taking the working process of the second scanning output module 132 as an example. The following mainly describes the differences between the driving processes in the second working mode and the first working mode, and the similarities are not repeated here.

[0094] Specifically, in the second operating mode, the rising edge of the second frequency cutting control signal SW2 occurs before the rising edge of the stage transfer signal Carry (i.e., before the falling edge of the potential VN2 of the second output terminal N2, for example, set at any position in the first stage T11), and the high potential holding stage of the second frequency cutting control signal SW2 covers the falling edge of the potential VN2 of the second output terminal N2. In this way, before the rising edge of the stage transfer signal Carry, during the period when the first transistor M1 remains on, the high potential of the second frequency cutting control signal SW2 can be transmitted to the gate of the second transistor M2 in advance, and this signal transmission process continues until the rising edge of the stage transfer signal Carry arrives; during the high potential holding stage of the stage transfer signal Carry, the first transistor M1 is turned off, and the gate of the second transistor M2 is maintained at a high potential. Therefore, the gate potential of the second transistor M2 changes to a high potential before the rising edge of the stage transfer signal Carry. Before the gate potential of the second transistor M2 changes to a high potential, the second output terminal N2 maintains a high potential. Therefore, until the second transistor M2 is turned off due to the high gate potential, the third connection terminal N3 maintains the same high potential as the second output terminal N2. During the period when the second transistor M2 remains off due to the high gate potential, the potential jump of the second output terminal N2 cannot be transmitted to the third connection terminal N3. Therefore, the third connection terminal N3 maintains a high potential during this display frame, and the fourth transistor M4 is always controlled to remain off, so that the scan output unit in the second scan output module 132 cannot output the high potential of the second potential signal VGH. Therefore, during this display frame, the second scan signal OUT2 always maintains a low potential.

[0095] The above embodiment exemplifies that in the second working mode, the falling edge of the second frequency cutting control signal SW2 occurs before the falling edge of the level transfer signal Carry, but it is not intended to limit the present application. In other embodiments, exemplarily, the falling edge of the second frequency cutting control signal SW2 may also occur after the falling edge of the level transfer signal Carry, or even the second frequency cutting control signal SW2 may not include a falling edge in the display frame. Then, after the falling edge of the level transfer signal Carry, the first transistor M1 is turned on again, and the second frequency cutting control signal SW2 can be transmitted to the gate of the second transistor M2. At this time, if the second frequency cutting control signal SW2 is a high potential, the second transistor M2 maintains the off state and the third connection terminal N3 maintains a high potential; if the second frequency cutting control signal SW2 is a low potential, the second transistor M2 is turned on, and the high potential of the second output terminal N2 is transmitted to the third connection terminal N3. Therefore, after the falling edge of the level transfer signal Carry, no matter what the potential of the second frequency cutting control signal SW2 is, it does not affect the high potential of the third connection terminal N3, and the control process in the second working mode can be achieved.

[0096] Continuing with FIG6 , based on the above embodiments, the drive control module 11 may optionally further include a transistor M20. The second electrode of the transistor M21 may be connected to the first output terminal N1 via the transistor M20, and the gate of the transistor M20 may be connected to the first potential signal VGL. The transistor M20 is configured to prevent an excessively low potential at the first output terminal N1 from being transmitted to the first electrode N11 of the transistor M20, thereby preventing the transistors connected to the first electrode N11 of the transistor M20 from being damaged due to excessive voltage stress. For example, the first node control unit 114 and the second node control unit 115 are both connected to the first output terminal N1 via the transistor M20.

[0097] Based on the same principle, the second control unit 113 may also include a transistor M16 to prevent the excessively low potential of the gate of the transistor M17 from being transmitted forward. The transistor M16 is connected between the output terminal of the first control unit 112 and the gate of the transistor M17, and the gate of the transistor M16 receives the first potential signal VGL.

[0098] 6 , based on the above embodiments, the transmission control unit 1301 may optionally further include a fifth transistor M5; the gate of the fifth transistor M5 is connected to the first output terminal N1, the first electrode of the fifth transistor M5 is connected to the second potential signal VGH, and the second electrode of the fifth transistor M5 is connected to the third connection terminal N3. The fifth transistor M5 provided in this embodiment can play a similar role to the third node control unit 116. The fifth transistor M5 is specifically configured to be turned on when the first output terminal N1 is at a low potential, stably transmitting the high potential of the second potential signal VGH to the third connection terminal N3, so that the fourth transistor M4 remains off, thereby ensuring the accuracy of the potential of the scan signal OUT. On this basis, when the scan output module 13 needs to operate in the first operating mode, the high potential holding stage of the corresponding frequency cutting signal SW can cover the falling edge of the level transfer signal Carry. After the falling edge of the level transfer signal Carry, the fifth transistor M5 can stably provide the high potential of the second potential signal VGH to the third connection terminal N3.

[0099] FIG8 is a schematic diagram of the structure of another shift register provided in an embodiment of the present application. Referring to FIG8 , on the basis of the above-mentioned embodiments, optionally, for any scan output module, it may further include: a third capacitor C93 to reliably maintain the gate potential of the second transistor M2 when the first transistor M1 is turned off, to prevent the gate of the second transistor M2 from coupling into other potential signals due to potential floating, thereby affecting the conduction state of the second transistor M2. Specifically, the first end of the third capacitor C93 is connected to the fixed potential signal, and the second end is connected to the second pole of the first transistor M1 (that is, connected to the gate of the second transistor M2). For example, any DC voltage signal required by the shift register 10 can be multiplexed into a fixed potential signal to simplify the wiring of the display panel, for example, the first potential signal VGL or the second potential signal VGH is used as the above-mentioned fixed potential signal.

[0100] Furthermore, the scan output module may further include: a twelfth transistor M92 to ensure that the output end of the scan output unit 1302 stably outputs a cutoff potential (i.e., a low potential) when the second transistor M2 is turned off. Specifically, the gate of the twelfth transistor M92 is connected to the second electrode of the first transistor M1, the first electrode of the twelfth transistor M92 is connected to the first potential signal VGL, and the second electrode of the twelfth transistor M92 is connected to the output end of the scan output unit 1302. The channel type of the twelfth transistor M92 is different from that of the second transistor M2, so that the potential of the second electrode of the first transistor M1 can control the conduction of the twelfth transistor M92 while controlling the turn-off of the second transistor M2. Exemplarily, the second transistor M2 is a P-type transistor, and the twelfth transistor M92 is an N-type transistor.

[0101] When the shift register 10 structure shown in FIG6 or FIG8 is used in conjunction with the display panel structure shown in FIG2, the driving timing of the display panel can be seen in FIG9. FIG9 exemplarily illustrates a case where the refresh frequency of the first and third rows of pixel circuits 20 is higher than the refresh frequency of the second row of pixel circuits 20. The dotted hatching in FIG9 indicates the stage of data refresh for the corresponding row of pixel circuits 20.

[0102] As shown in FIG9 , in display frame F1, all three rows of pixel circuits 20 are refreshed, and the corresponding scan signals all include on-pulses. Specifically, the data writing phase for the first row of pixel circuits 20 occurs, for example, after the on-pulse of the first-stage first scan signal OUT11 ends and before the on-pulse of the second-stage second scan signal OUT22 ends. The data writing phase for the second row of pixel circuits 20 occurs, for example, after the on-pulse of the second-stage first scan signal OUT12 ends and before the on-pulse of the third-stage second scan signal OUT23 ends, and so on.

[0103] In display frame F2, the first and third rows of pixel circuits 20 perform data refresh, and the corresponding scan signals all include on-pulses. The second row of pixel circuits 20 do not perform data refresh, and the corresponding scan signals do not include on-pulses. Specifically, the first-stage first scan signal OUT11 and the second-stage second scan signal OUT22 both include on-pulses to enable the first row of pixel circuits 20 to perform data refresh. The second-stage first scan signal OUT12 and the third-stage second scan signal OUT23 both do not include on-pulses to enable the second row of pixel circuits 20 to perform data retention. The third-stage first scan signal OUT13 and the fourth-stage second scan signal OUT24 both include on-pulses to enable the third row of pixel circuits 20 to perform data refresh. Then, the rising edge of the first frequency cutting control signal SW1 occurs between the rising edge of the first-stage transmission signal Carry1 and the rising edge of the second-stage transmission signal Carry2, so that the second-stage first scanning signal OUT12 has no conduction pulse. The falling edge of the first frequency cutting control signal SW1 occurs between the rising edge of the second-stage transmission signal Carry2 and the rising edge of the third-stage transmission signal Carry3, so that the third-stage first scanning signal OUT13 resumes outputting the conduction pulse. The rising edge of the second frequency cutting control signal SW2 occurs between the rising edge of the second-stage transmission signal Carry2 and the rising edge of the third-stage transmission signal Carry3, so that the third-stage second scanning signal OUT23 has no conduction pulse. The falling edge of the second frequency cutting control signal SW2 occurs between the rising edge of the third-stage transmission signal Carry3 and the rising edge of the fourth-stage transmission signal Carry4, so that the fourth-stage second scanning signal OUT24 resumes outputting the conduction pulse.

[0104] In summary, by controlling the potential jump time of different frequency cutting control signals SW, the frequency of the conduction pulses appearing in the scanning signal OUT output by each scanning output module 13 in each level of shift register 10 can be controlled, so as to realize the display of different frequencies in the column direction of the display panel.

[0105] The structures of the LTPO pixel circuit and its corresponding scan drive circuit are given as examples in the above embodiments, but are not intended to limit the present application. In other embodiments, as shown in Figure 10, after the threshold compensation transistor M25 and the gate initialization transistor M22 are replaced with P-type transistors, all transistors in the pixel circuit 20 are P-type transistors, forming a low-temperature polycrystalline silicon (LTPS) pixel circuit. The corresponding drive timing can be seen in Figure 11. The on-state potentials of the first control signal S1 and the second control signal S2 are both changed to low potentials. The specific driving process can still refer to the driving process of the LTPO pixel circuit and will not be repeated here. Another difference between Figure 11 and Figure 4 is that the third control signal S3 can also be a high-frequency signal. Then, in each black insertion stage T24, when the third control signal S3 is low, the data write transistor M24 can be controlled to turn on, and the data voltage Vdata can be transmitted to the first electrode of the driving transistor DTFT, thereby resetting the first electrode of the driving transistor DTFT and restoring the same characteristics as in the refresh frame FA as much as possible.

[0106] As shown in FIG11 , the driving process of the pixel circuit 20 in FIG10 requires the first control signal S1 and the second control signal S2 to be turned on with staggered pulses. Therefore, a corresponding scanning drive circuit 100 capable of outputting a high-voltage scanning signal for a long time can be provided to provide the first control signal S1 and the second control signal S2. The specific connection method between the scanning drive circuit 100 and the pixel circuit 20 as shown in FIG2 is still used to drive each row of pixel circuits 20. In addition, when the third control signal S3 is a low-frequency signal, the second control signal S2 can also be multiplexed into the third control signal S3; when the fourth control signal S4 is a low-frequency signal, the first control signal S1 or the second control signal S2 can also be multiplexed into the fourth control signal S4. Therefore, only a circuit for providing the light-emitting control signal EM needs to be provided at the display panel frame position, which can further simplify the panel structure and reduce the panel frame.

[0107] The structure of the scan drive circuit 100 that can output a high-voltage scan signal for a long time (that is, the conduction pulse output by the scan output module 13 is a low voltage) is described below. Figure 12 is a structural diagram of another shift register provided in an embodiment of the present application. Referring to Figure 12, in one embodiment, optionally, the drive control module 11 responds to the fourth clock signal SCK1, the third clock signal SCK2, the input signal IN, the first potential signal VGL and the second potential signal VGH to control the potential of the first output terminal N1 and the second output terminal N2. The level transmission output module 12 outputs the second potential signal VGH or the third clock signal SCK2 as the level transmission signal Carry according to the potential of the first output terminal N1 and the second output terminal N2. For any scan output module, the transmission control unit 1301 is used to control whether the potential of the first output terminal N1 is transmitted to the third connection terminal N3 according to the frequency cutting control signal; the scan output unit 1302 is used to respond to the potential of the third connection terminal N3 and the second output terminal N2, and output the second potential signal VGH or the third clock signal SCK2 as the scan signal OUT. Exemplarily, the fourth clock signal SCK1 and the third clock signal SCK2 are clock signals with alternating high and low potentials.

[0108] Specifically, referring to FIG. 13 , the driving control module 11 includes: a second input unit 1121 , a third control unit 1122 , a fourth node control unit 1123 and a fifth node control unit 1124 .

[0109] For example, the second input unit is connected to the first output end and is configured to transmit the input signal to the first output end in response to a fourth clock signal;

[0110] a third control unit, connected to the second output end, and configured to transmit the first potential signal to the second output end in response to the fourth clock signal;

[0111] a fourth node control unit, connected to the first output terminal and the second output terminal, respectively, and configured to transmit the fourth clock signal to the second output terminal in response to the potential of the first output terminal;

[0112] a fifth node control unit, connected to the first output terminal and the second output terminal respectively, and configured to transmit the second potential signal to the first output terminal in response to a third clock signal and the potential of the second output terminal;

[0113] The level transmission output module includes:

[0114] a third output unit, connected to the first output terminal, and configured to transmit the third clock signal to the output terminal of the stage transmission output module in response to the potential of the first output terminal;

[0115] The fourth output unit is connected to the second output terminal and is used to respond to the potential of the second output terminal and transmit the second potential signal to the output terminal of the stage transmission output module.

[0116] For example, the second input unit 1121 includes a transistor M41 having a gate connected to the fourth clock signal SCK1, a first electrode connected to the input signal IN, and a second electrode connected to the first output terminal N1. The second input unit 1121 is configured to transmit the input signal IN to the first output terminal N1 in response to the fourth clock signal SCK1.

[0117] The third control unit 1122 includes a transistor M42 having a gate connected to the fourth clock signal SCK1, a first electrode connected to the first potential signal VGL, and a second electrode connected to the second output terminal N2. The third control unit 1122 is configured to transmit the first potential signal VGL to the second output terminal N2 in response to the fourth clock signal SCK1.

[0118] The fourth node control unit 1123 includes a transistor M43. The gate of the transistor M43 is connected to the first output terminal N1, the first electrode is connected to the fourth clock signal SCK1, and the second electrode is connected to the second output terminal N2. The fourth node control unit 1123 is configured to transmit the fourth clock signal SCK1 to the second output terminal N2 in response to the potential of the first output terminal N1.

[0119] The fifth node control unit 1124 includes transistors M44 and M45. Transistor M44 has a gate connected to the second output terminal N2, a first electrode connected to the second potential signal VGH, and a second electrode connected to the first electrode of transistor M45. Transistor M45 has a gate connected to the third clock signal SCK2, and a second electrode connected to the first output terminal N1. Fifth node control unit 1124 is configured to transmit the second potential signal VGH to the first output terminal N1 in response to the third clock signal SCK2 and the potential of the second output terminal N2.

[0120] The level output module 12 includes a third output unit 123 and a fourth output unit 124. The third output unit 123 includes a transistor M47 and a capacitor C22. The gate of the transistor M47 is connected to the first output terminal N1, the first electrode is connected to the third clock signal SCK2, and the second electrode is connected to the output terminal of the level output module 12. The capacitor C22 is connected between the gate and the second electrode of the transistor M47. The third output unit 123 is configured to transmit the third clock signal SCK2 to the output terminal of the level output module 12 in response to the potential of the first output terminal N1. The fourth output unit 124 includes a transistor M48 and a capacitor C23. The gate of the transistor M48 is connected to the second output terminal N2, the first electrode is connected to the second potential signal VGH, and the second electrode is connected to the output terminal of the level output module 12. The capacitor C23 is connected between the gate and the first electrode of the transistor M48. The fourth output unit 124 is configured to transmit the second potential signal VGH to the output terminal of the level output module 12 in response to the potential of the second output terminal N2.

[0121] Based on the above implementations, optionally, for any scan output module:

[0122] The transmission control unit 1301 includes: a sixth transistor M6; a gate of the sixth transistor M6 is connected to the frequency cutting control signal SW, a first electrode of the sixth transistor M6 is connected to the first connection terminal, the first connection terminal is connected to the first output terminal N1, and a second electrode of the sixth transistor M6 is connected to the third connection terminal N3.

[0123] The scan output unit 1302 includes: a seventh transistor M7, an eighth transistor M8 and a second capacitor C2; the gate of the seventh transistor M7 is connected to the third connection terminal N3, the first electrode of the seventh transistor M7 is connected to the third clock signal SCK2, and the second electrode of the seventh transistor M7 is connected to the output terminal of the scan output unit 1302; the second capacitor C2 is connected between the gate and the second electrode of the seventh transistor M7; the gate of the eighth transistor M8 is connected to the second output terminal N2, the first electrode of the eighth transistor is connected to the second potential signal VGH, and the second electrode of the eighth transistor M8 is connected to the output terminal of the scan output unit 1302.

[0124] Based on the structure of the shift register 10 in FIG13 , and taking the case where all transistors in the shift register 10 are P-type transistors as an example, the driving process of the shift register 10 will be described in conjunction with FIG14 . To fully illustrate the operation of the circuit, FIG14 exemplifies the first scanning output module 131 operating in the first operating mode and the second scanning output module 132 operating in the second operating mode, but this does not limit the present application. In conjunction with FIG13 and FIG14 , the control method in the first operating mode will be described, first taking the operation of the first scanning output module 131 as an example.

[0125] Exemplarily, in the first operating mode, the first frequency cutting control signal SW1 maintains a low potential, so that the sixth transistor M6 remains turned on in the display frame, so that the potential of the third connection terminal N3 changes synchronously with the potential VN1 of the first output terminal N1, thereby making the scan output unit 1302 in the first scan output module 131 and the level output module 12 have the same output state and output signals of the same waveform. Exemplarily, the driving process of the shift register 10 includes:

[0126] In the first phase T31, the fourth clock signal SCK1, the input signal IN, and the first frequency-cutting control signal SW1 are all at low levels, and the third clock signal SCK2 is at a high level VH. Transistors M41 and M42 are turned on, and transistor M45 is turned off. The low level of the input signal IN is transmitted to the first output terminal N1 via transistor M41, controlling transistors M43 and M47 to turn on. Transistor M47 then outputs the high level of the third clock signal SCK2. The low level of the fourth clock signal SCK1 is transmitted to the second output terminal N2 via transistor M43. Furthermore, the low level of the first level signal VGL is transmitted to the second output terminal N2 via transistor M42, causing transistor M48 to turn on and output the high level of the second level signal VGH. Therefore, the stage transfer signal Carry is at a high level. Accordingly, the seventh transistor M7 and the eighth transistor M8 are also turned on, causing the first scan signal OUT1 to also be at a high level.

[0127] In the second stage T32, the third clock signal SCK2 is at a low potential, and the fourth clock signal SCK1 and the input signal IN are both at a high potential. Transistors M41 and M42 are turned off, and transistor M45 is turned on. Due to the storage function of capacitor C22, the first output terminal N1 maintains the low potential of the previous stage, causing transistor M43 to turn on, transmitting the high potential of the fourth clock signal SCK1 to the second output terminal N2, thereby causing transistors M48 and eighth transistor M8 to be turned off. At the same time, the low potential of the first output terminal N1 causes transistor M47 to turn on, outputting the low potential of the third clock signal SCK2. Since the level transfer signal Carry changes from a high potential to a low potential, based on the coupling effect of capacitor C22, the potential of the first output terminal N1 is further reduced, so that the low potential of the level transfer signal Carry is output stably. Accordingly, the seventh transistor M7 is turned on, outputting the low potential of the third clock signal SCK2 as a scan signal, and the second capacitor C2 plays a similar role to the second capacitor C22, controlling the low potential of the first scan signal OUT1 to be output stably.

[0128] In the third stage T33, the fourth clock signal SCK1 is at a low potential, and the third clock signal SCK2 and the input signal IN are both at a high potential. Transistors M41 and M42 are turned on, and transistor M45 is turned off. The high potential of the input signal IN is transmitted to the first output terminal N1 through transistor M41. The high potential control transistors M43, M47, and the seventh transistor M7 of the first output terminal N1 are all turned off. The low potential of the first potential signal VGL is transmitted to the second output terminal N2 through transistor M42, causing transistors M48 and the eighth transistor M8 to be turned on, and both output the high potential of the second potential signal VGH. Therefore, in this stage, the stage transfer signal Carry and the first scan signal OUT1 are both at a high potential.

[0129] In the fourth stage T34, the third clock signal SCK2 is at a low potential, and the fourth clock signal SCK1 and the input signal IN are both at a high potential. Transistors M41 and M42 are turned off, and transistor M45 is turned on. Due to the storage function of capacitor C23, the second output terminal N2 maintains the low potential of the previous stage, causing transistor M44 to be turned on, and the high potential of the second potential signal VGH is transmitted to the first output terminal N1 along transistors M44 and M45, controlling transistors M43, M47, and the seventh transistor M7 to be turned off. At the same time, the low potential of the second output terminal N2 controls the eighth transistor M8 and transistor M48 to be turned on, and both output the high potential of the second potential signal VGH. Therefore, in this stage, the stage transfer signal Carry and the first scan signal OUT1 both maintain a high potential.

[0130] The subsequent stages repeat the driving process of the third stage T33 and the fourth stage T34 until the input signal IN jumps to a low level again.

[0131] The above embodiment exemplifies that when the first scan output module 131 operates in the first operating mode, the first frequency cutting control signal SW1 maintains a low potential VL throughout the entire display frame, but this is not intended to be a limitation of the present application. In other embodiments, as long as the first frequency cutting control signal SW1 is maintained at a low potential during the second phase T32, the seventh transistor M7 can normally output the low potential of the third clock signal SCK2 during the second phase T32.

[0132] The control method in the second working mode is described below by taking the working process of the second scanning output module 132 as an example. The following mainly describes the differences between the driving processes in the second working mode and the first working mode, and the similarities are not repeated here.

[0133] Specifically, in the second operating mode, the rising edge of the second frequency-cutting control signal SW2 is set before the potential VN1 of the first output terminal N1 transitions to a low level, and the falling edge of the second frequency-cutting control signal SW2 is set after the potential VN1 of the first output terminal N1 transitions to a high level. This prevents the low level of the first output terminal N1 from being transmitted to the third connection terminal N3. Therefore, the third connection terminal N3 always maintains a high level during the display frame, causing the seventh transistor M7 to remain off. Therefore, in the second operating mode, the second scan signal OUT2 always maintains a high level.

[0134] Continuing to refer to FIG13 , based on the above embodiments, optionally, the shift register 10 may further include: a transistor M46 connected between the first output terminal N1 and the gate of the transistor M47, and the gate of the transistor M46 is connected to the first potential signal VGL. The transistor M46 is used to prevent the excessively low potential of the gate of the transistor M47 from being transmitted to the first output terminal N1, thereby preventing the transistors connected to the first output terminal N1 from being damaged due to excessive voltage stress. Exemplarily, after the transistor M46 is added, the first connection terminal of each transmission control unit 1301 can still be directly connected to the first output terminal N1, or can be connected to the first output terminal N1 through the transistor M46.

[0135] Based on the same principle, the transmission control unit 1301 may optionally further include an eleventh transistor M11. The eleventh transistor M11 is connected between the second electrode of the sixth transistor M6 and the third connection terminal N3, and the gate of the eleventh transistor M11 is connected to the first potential signal VGL. The eleventh transistor M11 is used to prevent an excessively low potential at the third connection terminal N3 from being transmitted forward.

[0136] Based on the above embodiments, the transmission control unit 1301 optionally further includes: a ninth transistor M9; the gate of the ninth transistor M9 is connected to a first switching signal (labeled as SK11 in the first scan output module 131 and as SK12 in the second scan output module 132), the first electrode of the ninth transistor M9 is connected to the second potential signal VGH, and the second electrode of the ninth transistor M9 is connected to the third connection terminal N3. The ninth transistor M9 is configured to transmit the second potential signal VGH to the third connection terminal N3 in response to the first switching signal. Specifically, when the scan output module in which it is located is operating in the second operating mode, when the sixth transistor M6 is turned off, the ninth transistor M7 is promptly provided with a cutoff potential to ensure that the seventh transistor M7 remains in the off state when the sixth transistor M6 is turned off. Exemplarily, the gates of the ninth transistors M9 in each scan output module in the same scan output group can be connected to the same first switching signal. Among them, when the channel types of the sixth transistor M6 and the ninth transistor M9 are the same, the frequency cutting control signal and the first switching signal can be set to be inverted signals with opposite high and low potentials; alternatively, when the channel types of the sixth transistor M6 and the ninth transistor M9 are different, the frequency cutting control signal can be set to be multiplexed as the first switching signal to reduce the signal lines required for the scan driving circuit and simplify the wiring of the display panel.

[0137] Based on the above embodiments, the transmission control unit 1301 optionally further includes: a tenth transistor M10; the gate of the tenth transistor M10 is connected to a second switching signal (labeled as SK21 in the first scan output module 131 and as SK22 in the second scan output module 132); the first electrode of the tenth transistor M10 is connected to the first potential signal VGL; and the second electrode of the tenth transistor M10 is connected to the third connection terminal N3. The tenth transistor M10 is configured to transmit the first potential signal VGL to the third connection terminal N3 in response to the second switching signal. Specifically, when the scan output module in which it is located is operating in the first operating mode, after the first phase T31 begins and before the second phase T32 begins, promptly provide the gate of the seventh transistor M7 with the conduction potential of the seventh transistor M7. For example, the input signal IN can be multiplexed into the second switching signal SK21 required by the first scan output module 131 and / or the second switching signal SK22 required by the second scan output module 132 to simplify the wiring of the display panel.

[0138] When the shift register 10 structure shown in FIG13 is used in conjunction with the display panel structure shown in FIG2, the driving timing of the display panel can be seen in FIG15. FIG15 also shows the case where the refresh frequencies of the first and third rows of pixel circuits 20 are both higher than the refresh frequency of the second row of pixel circuits 20.

[0139] As shown in FIG. 15 , in display frame F1, data is refreshed in all three rows of pixel circuits 20, and the corresponding scan signals all include on-pulses. Specifically, the first-stage first scan signal OUT11 through the third-stage first scan signal OUT13 all include on-pulses, and the second-stage second scan signal OUT22 through the fourth-stage second scan signal OUT24 all include on-pulses.

[0140] In display frame F2, the first and third rows of pixel circuits 20 perform data refresh, and the corresponding scan signals all include on-pulses. The second row of pixel circuits 20 do not perform data refresh, and the corresponding scan signals do not include on-pulses. Specifically, the first-stage first scan signal OUT11 and the second-stage second scan signal OUT22 both include on-pulses; the second-stage first scan signal OUT12 and the third-stage second scan signal OUT23 both include on-pulses; and the third-stage first scan signal OUT13 and the fourth-stage second scan signal OUT24 both include on-pulses. Therefore, the high-potential holding phase of the first frequency-cutting control signal SW1 overrides the on-pulse of the second-stage transfer signal Carry2, resulting in no on-pulse in the second-stage first scan signal OUT12. The high-potential holding phase of the second frequency-cutting control signal SW2 overrides the on-pulse of the third-stage transfer signal Carry3, resulting in no on-pulse in the third-stage second scan signal OUT23.

[0141] In summary, by controlling the potential jump time of different frequency cutting control signals SW, the frequency of the conduction pulses appearing in the scanning signal OUT output by each scanning output module 13 in each level of shift register 10 can be controlled, so as to realize the display of different frequencies in the column direction of the display panel.

[0142] The above embodiments exemplify the specific connection between the scan driver circuit 100 and the pixel circuit 20 for providing the first control signal S1 and the second control signal S2. Furthermore, corresponding driver circuits for providing the third control signal S3, the fourth control signal S4, and the emission control signal EM are also required to be provided at the display panel frame. The driver circuit for providing the emission control signal EM can employ any existing emission control driver circuit structure and will not be described in detail here. The following describes the configuration of the driver circuit for providing the third control signal S3 and the fourth control signal S4, primarily with reference to pixel circuits 20 having different structures.

[0143] For the LTPO pixel circuit shown in Figure 3:

[0144] When it is necessary to provide the third control signal S3 and the fourth control signal S4 as shown in FIG4 :

[0145] In one embodiment, two drive circuits may be optionally provided to provide the third control signal S3 and the fourth control signal S4, respectively. Specifically, the shift register unit in the drive circuit for providing the third control signal S3 may employ a structure similar to the shift register in FIG. 13 , but retaining only one scan output module for providing the third control signal S3. The shift register unit in the drive circuit for providing the fourth control signal S4 may employ any existing shift register circuit with a long-term high-voltage output, such as an 8T2C shift register circuit.

[0146] In another embodiment, a set of driving circuits can be optionally used to simultaneously provide the third control signal S3 and the fourth control signal S4. Specifically, the shift register unit in the driving circuit can adopt a structure similar to the shift register in FIG13 , but retain only one scan output module. In each shift register unit, the scan signal output by the scan output module serves as the third control signal S3, and the level transfer signal output by the level transfer output module serves as the fourth control signal S4.

[0147] When it is necessary to provide a third control signal S3 and a fourth control signal S4, both of which are high frequencies, a set of drive circuits can be used to simultaneously provide the third control signal S3 and the fourth control signal S4. Specifically, the shift register unit in the drive circuit can adopt any existing structure that outputs a high voltage for a long time, such as an 8T2C structure shift register circuit. The scanning signal output by the first-level shift register unit can serve as the third control signal S3 and the fourth control signal S4 required by the same row of pixel circuits 20, or as the third control signal S3 required by one row of pixel circuits 20 and the fourth control signal S4 required by another row of pixel circuits 20. The specific configuration method can be determined according to actual needs.

[0148] For the LTPS pixel circuit shown in Figure 10:

[0149] When it is necessary to provide the third control signal S3 and the fourth control signal S4 as shown in FIG11 :

[0150] In one embodiment, optionally, another set of driving circuits can be used to simultaneously provide the third control signal S3 and the fourth control signal S4. Specifically, the shift register unit in the driving circuit can adopt any existing shift register circuit with a long-term high-voltage output structure, such as an 8T2C shift register circuit.

[0151] In another embodiment, optionally, the level transfer signal Carry in the scan drive circuit 100 can be used to provide the pixel circuit 20 with a third control signal S3 and / or a fourth control signal S4 that always maintains a high frequency, so as to simplify the structure of the display panel. Figure 16 is a schematic structural diagram of another display panel provided in an embodiment of the present application. Referring to Figure 16, in one embodiment, optionally, based on the connection method of Figure 2, the j+1-th level transfer signal can also be used as the third control signal S3 required by the j-th row pixel circuit 20 to provide a high-frequency third control signal S3, and ensure that in the refresh frame FA, the conduction pulse of the third control signal S3 overlaps with the conduction pulse of the second control signal S2 to ensure the normal progress of the data writing process. In addition, the third control signal S3 in the same pixel circuit 20 can be multiplexed as the fourth control signal S4, that is, the j+1-th level transfer signal can simultaneously serve as the fourth control signal S4 required by the j-th row pixel circuit 20 to provide a high-frequency fourth control signal S4. Alternatively, in other embodiments, the j-th stage transmission signal may be set as the fourth control signal S4 required by the j-th row of pixel circuits 20, which can also control each driving phase of the pixel circuits 20 to execute normally.

[0152] When a low-frequency third control signal S3 is required, the second control signal S2 required by the pixel circuit 20 can be multiplexed into the third control signal S3; when a low-frequency fourth control signal S4 is required, the first control signal S1 or the second control signal S2 required by the pixel circuit 20 can be multiplexed into the fourth control signal S4.

[0153] The present application also provides a display device comprising a scan drive circuit according to any embodiment of the present application, and having corresponding beneficial effects. FIG17 is a schematic structural diagram of a display device according to an embodiment of the present application. Referring to FIG17 , the display device may include a display panel and a driver chip 50, for example. The scan drive circuit 100 and the pixel circuit 20 are both disposed in the display panel. Taking the example of each shift register 10 including two scan output modules, the scan drive circuit 100 can provide a first control signal and a second control signal to each row of pixel circuits 20 via each first scan line LS1 and a second scan line LS2. The driver chip 50 can provide a first frequency cutting control signal and a second frequency cutting control signal to different scan output modules in each shift register 10 via a first frequency cutting signal line LSW1 and a second frequency cutting signal line LSW2. In addition, the driver chip 50 can also provide an input signal to the first-stage shift register 10 in the scan drive circuit 100 via an input signal line LIN, and provide a data voltage to each column of pixel circuits 20 via each data line LD.

[0154] Based on the above embodiments, the pixel circuit 20 optionally includes: a driving module, a threshold compensation module, and a gate reset module; the gate reset module is connected to the control terminal of the driving module, and the threshold compensation module is connected between the control terminal and the output terminal of the driving module. The specific connection relationship between each level of shift register 10 in the scan driving circuit 100 and each row of pixel circuits 20 can be: one scan output module of the shift register 10 is connected to the control terminal of the gate reset module in one row of pixel circuits, and another scan output module of the shift register is connected to the control terminal of the threshold compensation module in another row of pixel circuits. The other row of pixel circuits is the first row or the i-th row of pixel circuits before the above row of pixel circuits, where i>1.

[0155] Furthermore, the pixel circuit also includes a data write module and an anode reset module. The data write module is connected to the input terminal of the driver module; the anode reset module is connected to the anode of the light-emitting device. When the data write module, the anode reset module, the gate reset module, and the threshold compensation module include transistors of the same channel type, and the shift register 10 includes a level output module, the level output module in the shift register 10 is also connected to the control terminal of the data write module and / or the control terminal of the anode reset module.

[0156] Furthermore, the two scanning output modules include a first scanning output module and a second scanning output module; the output end of the first scanning output module of the nth level is connected to the control end of the gate reset module in the nth row pixel circuit, and the output end of the second scanning output module of the n+mth level is connected to the control end of the threshold compensation module in the nth row pixel circuit; n and m are both integers greater than 0.

[0157] Furthermore, m=1.

[0158] It should be noted that in each embodiment of the scan driving circuit, specific descriptions are given for the structures of different display panels, which can all be considered as the specific structures of the display panel in the display device provided in the embodiments of the present application, and repeated content will not be repeated here.

[0159] The present application also provides a method for driving a display device, for driving the display device provided by any embodiment of the present application to perform a column-wise, zone-by-zone, frequency-divided display. The method includes:

[0160] According to the target display partition position of the display device in the column direction, the potential jump time of each frequency cutting control signal in one frame display is controlled so that the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located above the target display partition position is different from the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located below the target display partition position; and the frequency of the conduction pulse appearing in the scanning signal output by all scanning output modules connected to the same pixel circuit is the same.

[0161] It should be noted that in each embodiment of the scan driving circuit, specific descriptions are given for driving methods of different display devices, which can all be considered as driving methods of the display devices provided in the embodiments of the present application, and repeated content will not be repeated here.

[0162] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this application can be achieved. This is not limited herein.

Claims

1. A scan driving circuit, comprising: Multiple shift registers arranged in cascade; The nth stage shift register of the plurality of shift registers comprises: A driving control module, used for controlling the potential of the first output terminal and the second output terminal of the driving control module according to the input signal connected to the n-th stage shift register; At least two scanning output modules, the scanning output modules are connected to the first output end and the second output end, and are connected to a frequency cutting control signal, and the scanning output modules are used to output a scanning signal; wherein different scanning output modules are connected to different frequency cutting control signals, and different frequency cutting control signals are respectively used to control the frequency of conduction pulses appearing in the scanning signal output by the corresponding scanning output module, wherein n is an integer greater than 0.

2. The scan driving circuit according to claim 1, wherein: The nth stage shift register among the plurality of shift registers further comprises: a stage transmission output module, connected to the first output terminal and the second output terminal respectively, for outputting a stage transmission signal in response to the potentials of the first output terminal and the second output terminal; the stage transmission signal is used as an input signal of the n+sth stage shift register; Wherein, s is an integer greater than 0; Preferably, s=1.

3. The scan driving circuit according to claim 1, wherein: At least two of the scan output modules in the shift register at the same level are respectively connected to at least two rows of pixel circuits, and some of the scan output modules in at least two levels of the shift register are connected to the pixel circuits in the same row; Each of the frequency cutting control signals is configured to control the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located above the display partition position according to the display partition position in the column direction of the display panel, so that the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located above the display partition position is different from the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located below the display partition position.

4. The scanning driving circuit according to any one of claims 1 to 3, wherein: A scan output group in the scan driving circuit includes a scan output module in each level of the shift register, and different scan output modules in the same level of the shift register belong to different scan output groups; each scan output module in the same scan output group is connected to the same frequency switching control signal; For any of the scan output groups, the frequency cutting control signal undergoes a potential jump in at least a portion of display frames, so that the frequencies of the conduction pulses appearing in the scan signals output by at least two scan output modules in the scan output group are different.

5. The scan driving circuit according to claim 4, wherein: The scanning output modules in the same scanning output group are respectively connected to the same functional modules of the pixel circuits in each row; a plurality of scanning output modules connected to different functional modules in the same pixel circuit belong to different scanning output groups.

6. The scan driving circuit according to claim 4, wherein: The first-level shift register includes two scanning output modules, namely a first scanning output module and a second scanning output module; The output end of the nth level first scanning output module is connected to the nth row pixel circuit, and the conduction pulse output by the nth level first scanning output module acts on the first stage of the nth row pixel circuit; the output end of the n+mth level second scanning output module is connected to the nth row pixel circuit. The output end is connected to the n-th row pixel circuit, and the conduction pulse output by the n+m-th level second scanning output module acts on the second stage of the n-th row pixel circuit; wherein, for the same pixel circuit, in the same display frame, the first stage occurs before the second stage, and m is an integer greater than 0; Preferably, the first stage is a reset stage, and the second stage is a data writing stage; Preferably, m=1.

7. The scan driving circuit according to claim 6, wherein: In one frame display, when the scanning signal output by the first scanning output module from the i-th to i+k-th level has the conduction pulse, the scanning signal output by the second scanning output module from the i+m-th to i+m+k-th level has the conduction pulse; wherein i and k are integers greater than 0 respectively.

8. The scan driving circuit according to claim 6, wherein: defining the frequency cutting control signal connected to the first scanning output module as a first frequency cutting control signal, and defining the frequency cutting control signal connected to the second scanning output module as a second frequency cutting control signal; When the display partition position is located between the pixel circuit of the i-th row and the pixel circuit of the i+1-th row, in part of the display frame, the first frequency cutting control signal undergoes a potential jump before the i-th level first scanning output module outputs the conduction pulse, so that the frequency of the conduction pulse appearing in the scanning signal output by the i-th level first scanning output module is different from the frequency of the conduction pulse appearing in the scanning signal output by the i+1-th level first scanning output module, thereby realizing the partitioned frequency display of the display panel in the column direction; i is an integer greater than 0; And, corresponding to the display frame in which the potential jump occurs in the first frequency cutting control signal, the potential jump occurs in the second frequency cutting control signal before the second scanning output module of the i+mth level outputs the turn-on pulse, so that the frequency of the turn-on pulse appearing in the scanning signal output by the second scanning output module connected to each row of the pixel circuit is the same as the frequency of the turn-on pulse appearing in the scanning signal output by the first scanning output module connected to the corresponding row of the pixel circuit.

9. The scan driving circuit according to claim 2, wherein: The scanning output module comprises: A transmission control unit, wherein a first connection end of the transmission control unit is connected to one of the first output end and the second output end, and a second connection end of the transmission control unit is connected to the frequency cutting control signal; the transmission control unit is used to control the potential of the third connection end of the transmission control unit according to the potentials of the first connection end and the second connection end; A scanning output unit, wherein the first control end of the scanning output unit is connected to the third connection end, and the second control end of the scanning output unit is connected to the other of the first output end and the second output end; the scanning output unit is used to output the scanning signal according to the potential of the first control end and the second control end.

10. The scan driving circuit according to claim 9, wherein: The conduction pulse output by the scanning output module is a high potential; The transmission control unit includes: a first transistor and a second transistor; the gate of the first transistor is connected to the output end of the stage transmission output module, the first electrode of the first transistor is connected to the frequency cutting control signal, and the second electrode of the first transistor is connected to the gate of the second transistor; the first electrode of the second transistor is connected to the first connection end, the first connection end is connected to the second output end, and the second electrode of the second transistor is connected to the third connection end; The scanning output unit includes: a third transistor, a fourth transistor and a first capacitor; the gate of the third transistor The first output terminal is connected, the first electrode of the third transistor is connected to the first potential signal, and the second electrode of the third transistor is connected to the output terminal of the scan output unit; the gate of the fourth transistor is connected to the third connection terminal, the first electrode of the fourth transistor is connected to the second potential signal, and the second electrode of the fourth transistor is connected to the output terminal of the scan output unit; the first capacitor is connected between the gate and the first electrode of the fourth transistor.

11. The scan driving circuit according to claim 10, wherein: The transmission control unit also includes a fifth transistor; the gate of the fifth transistor is connected to the first output end, the first electrode of the fifth transistor is connected to the second potential signal, and the second electrode of the fifth transistor is connected to the third connection end.

12. The scan driving circuit according to claim 10, wherein: The scanning output module further includes: a third capacitor; a first end of the third capacitor is connected to a fixed potential signal, and a second end of the third capacitor is connected to a second electrode of the first transistor; Preferably, the scanning output module also includes: a twelfth transistor; the gate of the twelfth transistor is connected to the second electrode of the first transistor, the first electrode of the twelfth transistor is connected to the first potential signal, and the second electrode of the twelfth transistor is connected to the output end of the scanning output unit; the channel type of the twelfth transistor is different from that of the second transistor.

13. The scan driving circuit according to claim 10, wherein: The drive control module comprises: a first input unit, connected to the first output end, and configured to transmit the input signal to the first output end in response to a first clock signal; a first control unit, configured to transmit the first potential signal to an output end of the first control unit in response to the first clock signal; a second control unit connected between the output terminal of the first control unit and the second output terminal, and configured to control the potential of the second output terminal according to a second clock signal and the potential of the output terminal of the first control unit; a first node control unit, connected to the first output terminal and the output terminal of the first control unit respectively, and configured to control the potential of the output terminal of the first control unit according to the potential of the first output terminal; a second node control unit, connected to the first output terminal and the output terminal of the first control unit respectively, and configured to control the potential of the first output terminal according to the potential of the output terminal of the first control unit; a third node control unit, connected to the first output terminal and the second output terminal respectively, and configured to control the potential of the second output terminal according to the potential of the first output terminal; The level transmission output module comprises: a first output unit, connected to the first output terminal, and configured to respond to the potential of the first output terminal and transmit the first potential signal to the output terminal of the stage transmission output module; The second output unit is connected to the second output terminal and is used for responding to the potential of the second output terminal and transmitting the second potential signal to the output terminal of the stage transmission output module.

14. The scan driving circuit according to claim 9, wherein: The conduction pulse output by the scanning output module is a low potential; The transmission control unit comprises: a sixth transistor; a gate of the sixth transistor is connected to the frequency cutting control signal, A first electrode of the sixth transistor is connected to the first connection end, the first connection end is connected to the first output end, and a second electrode of the sixth transistor is connected to the third connection end; The scan output unit includes: a seventh transistor, an eighth transistor and a second capacitor; the gate of the seventh transistor is connected to the third connection terminal, the first electrode of the seventh transistor is connected to the third clock signal, and the second electrode of the seventh transistor is connected to the output terminal of the scan output unit; the second capacitor is connected between the gate and the second electrode of the seventh transistor; the gate of the eighth transistor is connected to the second output terminal, the first electrode of the eighth transistor is connected to the second potential signal, and the second electrode of the eighth transistor is connected to the output terminal of the scan output unit.

15. The scan driving circuit according to claim 14, wherein: The transmission control unit further includes: a ninth transistor; a gate of the ninth transistor is connected to the first switch signal, a first electrode of the ninth transistor is connected to the second potential signal, and a second electrode of the ninth transistor is connected to the third connection terminal.

16. The scan driving circuit according to claim 14, wherein: The transmission control unit further includes: a tenth transistor; a gate of the tenth transistor is connected to the second switch signal, a first electrode of the tenth transistor is connected to the first potential signal, and a second electrode of the tenth transistor is connected to the third connection terminal; Preferably, the transmission control unit further includes: an eleventh transistor; the eleventh transistor is connected between the second electrode of the sixth transistor and the third connection end, and a gate of the eleventh transistor is connected to the first potential signal.

17. The scan driving circuit according to claim 14, wherein: The drive control module comprises: a second input unit, connected to the first output end, and configured to transmit the input signal to the first output end in response to a fourth clock signal; a third control unit, connected to the second output terminal, and configured to transmit the first potential signal to the second output terminal in response to the fourth clock signal; a fourth node control unit, connected to the first output terminal and the second output terminal respectively, and configured to transmit the fourth clock signal to the second output terminal in response to the potential of the first output terminal; a fifth node control unit, connected to the first output terminal and the second output terminal respectively, and configured to respond to a third clock signal and the potential of the second output terminal and transmit the second potential signal to the first output terminal; The level transmission output module comprises: a third output unit, connected to the first output terminal, and configured to transmit the third clock signal to the output terminal of the stage transmission output module in response to the potential of the first output terminal; The fourth output unit is connected to the second output terminal and is used for transmitting the second potential signal to the output terminal of the stage transmission output module in response to the potential of the second output terminal.

18. A display device comprising: A pixel circuit and a scan drive circuit as claimed in any one of claims 1 to 17.

19. The display device according to claim 18, wherein: Each level of the shift register includes two scanning output modules; The pixel circuit comprises: a driving module, a threshold compensation module and a gate reset module; the gate reset module is connected to the control end of the driving module, and the threshold compensation module is connected between the control end and the output end of the driving module; One of the scan output modules of the shift register is connected to the gate reset modules in a row of pixel circuits. A control end, another scan output module of the shift register is connected to a control end of the threshold compensation module in another row of pixel circuits; Preferably, the pixel circuit further comprises a data writing module and an anode reset module, wherein the data writing module is connected to the input end of the driving module; the anode reset module is connected to the anode of the light-emitting device; the data writing module, the anode reset module, the gate reset module and the threshold compensation module comprise transistors of the same channel type; the shift register further comprises a level transmission output module, wherein the level transmission output module is also connected to at least one of the control end of the data writing module and the control end of the anode reset module; Preferably, the two scanning output modules include a first scanning output module and a second scanning output module; the output end of the first scanning output module of the nth level is connected to the control end of the gate reset module in the pixel circuit of the nth row, and the output end of the second scanning output module of the n+mth level is connected to the control end of the threshold compensation module in the pixel circuit of the nth row; n and m are integers greater than 0 respectively; Preferably, m=1.

20. A method for driving a display device, for driving the display device according to any one of claims 18 to 19 to perform a zone-by-zone frequency display in a column direction; the driving method comprising: According to the target display partition position of the display device in the column direction, the potential jump time of the frequency cutting control signal in one frame display is controlled so that the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located above the target display partition position is different from the frequency of the conduction pulse appearing in the scanning signal output by the scanning output module connected to the pixel circuit located below the target display partition position; and the frequency of the conduction pulse appearing in the scanning signal output by all the scanning output modules connected to the same pixel circuit is the same.

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