Circuit synthesis method and apparatus, electronic device and readable storage medium

Abstract

Provided in the embodiments of the present invention are a circuit synthesis method and apparatus, an electronic device and a readable storage medium, the method comprising: analyzing an assertion statement to be synthesized, and identifying a keyword and a verification mode that correspond to the assertion statement; instantiating the keyword in the assertion statement into a basic circuit module; on the basis of the verification mode, determining a connection mode corresponding to the basic circuit module; and, on the basis of the connection mode, connecting the basic circuit module so as to obtain an assertion circuit corresponding to the assertion statement.

Description

Circuit synthesis method, device, electronic device and readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 27, 2023, with application number 202310937005.6 and entitled “A circuit synthesis method, device, electronic device and readable storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of computer technology, and in particular to a circuit synthesis method, device, electronic device and readable storage medium. Background Art

[0004] As computer architecture and hardware design become increasingly complex, functional verification has become a time-consuming process in chip development. Verification accounts for up to 70% of the development cycle. One bottleneck in verification is software simulation of register-transfer level (RTL) circuits. While software simulation provides complete visibility into design details to aid debugging, RTL simulation can be extremely time-consuming for long simulations of complex designs, significantly reducing verification efficiency. Furthermore, software simulation still relies on manual judgment to examine waveforms and debug information to locate design issues.

[0005] Assertions are often used as an efficient verification method to reduce the debugging workload in digital circuit functional verification. More than 75% of ASIC designs and nearly 50% of FPGA designs use assertion-based verification (ABV). Compared to traditional debugging techniques using printf or display, ABV can simultaneously perform automatic monitoring and checking to verify that a given hardware design meets the expected behavior. Once an assertion is violated, the verification system automatically flags the issue. Engineers can use simulation software to investigate the cause of the assertion failure and trace it back to the root cause. In the industrial design process, design engineers often add assertions to prevent future unexpected behavior and identify potential errors. Assertions are very valuable when checking complex logical behavior with timing information. However, assertions are non-synthesizable structures and cannot be used directly for hardware testing, only for software simulation.

[0006] Summary of the Invention

[0007] Embodiments of the present invention provide a circuit synthesis method, apparatus, electronic device, and readable storage medium, which can solve the problem that assertion statements cannot be synthesized and cannot be used for hardware testing.

[0008] In order to solve the above problems, in a first aspect, an embodiment of the present invention discloses a circuit synthesis method, the method comprising:

[0009] Parsing the assertion statement to be synthesized, identifying the keywords and verification methods corresponding to the assertion statement;

[0010] Instantiating the keywords in the assertion statement into a basic circuit module;

[0011] Determining a connection method corresponding to the basic circuit module according to the verification method;

[0012] The basic circuit modules are connected according to the connection method to obtain an assertion circuit corresponding to the assertion statement.

[0013] In a second aspect, an embodiment of the present invention discloses a circuit integration device, comprising:

[0014] A parsing module, configured to parse the assertion statement to be synthesized and identify keywords and verification methods corresponding to the assertion statement;

[0015] An instantiation module, configured to instantiate keywords in the assertion statement into a basic circuit module;

[0016] A first determining module, configured to determine a connection mode corresponding to the basic circuit module according to the verification mode;

[0017] The first connection module is configured to connect the basic circuit modules according to the connection mode to obtain an assertion circuit corresponding to the assertion statement.

[0018] In a third aspect, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned circuit synthesis method.

[0019] In a fourth aspect, an embodiment of the present invention further discloses a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the aforementioned circuit synthesis method.

[0020] In a fifth aspect, an embodiment of the present invention further discloses a computer program product (the computer program product is stored in a non-volatile storage medium), and the computer program product is executed by at least one processor to implement the circuit synthesis method as described above.

[0021] In a sixth aspect, an embodiment of the present invention further discloses a transmission device / equipment, including the device / equipment (configured to) be used in the circuit synthesis method as described above.

[0022] The embodiments of the present invention include the following advantages:

[0023] An embodiment of the present invention provides a circuit synthesis method, which parses assertion statements, identifies keywords and verification methods of assertion statements, instantiates keywords into equivalent basic circuit modules, determines the connection methods corresponding to each basic circuit module according to the verification method, and connects each basic circuit module according to the determined connection method, thereby converting non-synthesizable assertion statements into equivalent synthesizable assertion circuits, so as to implement assertion-based verification in hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0025] FIG1 is a flow chart of steps of a circuit synthesis method embodiment of the present invention;

[0026] FIG2 is a schematic structural diagram of a basic circuit module of a signal detection operator of the present invention;

[0027] FIG3 is a schematic structural diagram of an assertion circuit of the present invention;

[0028] FIG4 is a schematic diagram of a $rose function operator of the present invention;

[0029] FIG5 is a schematic diagram of a non-overlapping implication operator of the present invention;

[0030] FIG6 is a schematic diagram of a delay operator of the present invention;

[0031] FIG7 is a schematic diagram of an OR operator of the present invention;

[0032] FIG8 is a block diagram of a circuit integration device of the present invention;

[0033] FIG9 is a structural block diagram of an electronic device for circuit synthesis provided by an example of the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0036] Method Example

[0037] An embodiment of the present invention provides a circuit synthesis method, which can convert non-synthesizable assertion statements into equivalent synthesizable assertion circuits, so as to implement assertion-based verification in hardware.

[0038] In order to facilitate understanding of the embodiments provided by the present invention, the following points are explained:

[0039] 1. SV language (SystemVerilog) and SV assertion (SystemVerilog Assertion, SVA)

[0040] SystemVerilog is a hardware description language (HDL) used to design and verify digital circuits. It extends Verilog HDL, providing many new features and capabilities, making it more suitable for complex hardware design and verification tasks.

[0041] SVA is a key feature of SystemVerilog, used to describe and verify the behavior and properties of a system during the design and verification process. SVA allows designers to insert assertions into the hardware description to express properties about the design's behavior and state. SVA uses a syntax similar to sequential logic, which has rich expressive capabilities and can describe properties such as time correlation, sequence, and concurrency. SVA statements can be used for design verification, formal verification, and error debugging. SVA statements typically include the following:

[0042] i. Property: describes an expected or specified system behavior.

[0043] ii. Sequence: describes a sequence of events or states.

[0044] iii. Assertion: Combines properties and sequences and specifies when they are true.

[0045] iv. Clocking Block: defines the clock and sampling timing.

[0046] v. Coverage: Used to evaluate the property coverage of the design.

[0047] 2. Assertion-based Verification

[0048] Assertions are an effective hardware design verification method used to ensure that a design meets specific specifications and requirements. Assertions are statements that describe the behavior and properties of a design and are used to verify that the design meets these properties at runtime. Assertion-based verification uses assertions to verify that a design meets specific specifications and requirements. It can improve verification efficiency, reduce errors, and help design teams quickly identify and resolve design issues.

[0049] In assertion verification, the design is divided into two parts: the Design Under Test (DUT) and the test environment (Testbench). The test environment includes components such as test vector generators, clocks, monitors, and assertion checkers. The test vector generator generates input data, the clock provides timing information, the monitor is used to detect the output of the design, and the assertion checker is used to check whether the design meets the specified assertions. The basic principle of assertion verification is that when the test vector drives the design to run, the monitor monitors the output of the design and compares it with the expected results. At the same time, the assertion checker evaluates the assertion statement and issues a verification error if the assertion fails (that is, the assertion is false). This method can quickly discover errors in the design during the verification process and help developers confirm whether the design meets the specification requirements.

[0050] 3. Circuit synthesis

[0051] In hardware circuit design, "synthesize" is used to describe whether hardware description language code can be converted into properties of equivalent hardware circuits. This conversion process is usually completed by circuit synthesis tools (such as logic synthesizers).

[0052] Synthesizable code is code that can be converted into hardware circuits using a logic synthesizer. Logic synthesis is the process of converting high-level, abstract code written in a hardware description language (such as SystemVerilog) into low-level hardware elements such as basic logic gates and registers. Synthesizable code should be clearly structured and timed, using only hardware primitives and constructs supported by the synthesis tool.

[0053] Non-synthesizable code is code that cannot be directly converted into hardware using a logic synthesizer. It contains features that make sense at a high level of abstraction but cannot be mapped to hardware, such as delays, loops, and conditional branches. This code is often used for non-synthesizable purposes such as simulation, verification, and testing.

[0054] Some syntax and features in SVA are not synthesizable because they are mainly used to describe and verify the behavior and properties of the system rather than directly describe the hardware structure. For example:

[0055] i. Behaviors with delays. The delays cannot be directly mapped to the hardware’s sequential logic during synthesis.

[0056] ii. Sampling functions, such as "$rose()," "$stable()," and "$past()," are typically used in simulation environments to verify and debug designs. However, these sampling functions are generally unsynthesizable during synthesis because they cannot be directly mapped to equivalent elements in hardware circuits. Synthesis tools cannot directly convert these functions into hardware logic.

[0057] iii. Sequence operation keywords, such as intersect and firstmatch, are often used in the verification phase to check whether the design meets specific timing properties. Synthesis tools cannot directly convert these operators into hardware logic.

[0058] Because these features cannot be directly mapped to hardware circuits, synthesis tools cannot convert SVA code containing non-synthesizable features into equivalent hardware circuits. In actual designs, SVA is typically used in the verification phase rather than for direct hardware generation. Synthesizable hardware description language code and non-synthesizable verification code are usually written and used separately.

[0059] 4. Register-Transfer Level (RTL) circuit

[0060] RTL circuits are a common type of hardware description-level circuit. RTL circuits describe the behavior and structure of digital circuits and are represented using the register transfer level (RTL). RTL circuit descriptions are typically written in a hardware description language (HDL), such as VHSIC Hardware Description Language (VHDL), Verilog HDL, and SystemVerilog HDL. Designers can use RTL-level descriptions to define and implement the desired digital circuit functionality, and then use synthesis tools to convert the RTL-level descriptions into physical implementations in field-programmable gate arrays (FPGAs). In the field of FPGA and chip design and verification, RTL-level descriptions are crucial for design, verification, and debugging. They provide a level of abstraction that enables designers to describe circuit behavior at a higher level of abstraction and use appropriate tools for simulation, verification, and synthesis, ultimately generating a bitstream file that can be configured into the FPGA chip to implement the specific digital circuit functionality.

[0061] 5. FPGA

[0062] FPGAs are reconfigurable integrated circuits with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs, adapting them to different applications and functions. FPGAs consist of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, and can perform various logic functions. Programmable interconnect resources are used to connect logic blocks to form the desired circuit structure. Using FPGAs, designers can describe the desired circuit functionality using a hardware description language (HDL) and, using programming tools, convert this into a bitstream compatible with the FPGA chip. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the main advantages of FPGAs is their programmability and flexibility. They allow designers to implement customized functions and algorithms at the hardware level without the traditional custom IC design and manufacturing process. This makes FPGAs crucial for prototyping and rapid design iteration.

[0063] 6. Dynamic Partial Reconfiguration (DPR)

[0064] Dynamic partial reconfiguration (DPR) of FPGAs refers to the ability to reconfigure portions of a circuit while the FPGA is running. In traditional FPGA designs, the entire circuit typically needs to be reprogrammed and reloaded into the FPGA to change its functionality. However, DPR technology allows only portions of the circuit to be reconfigured while the FPGA is running, without affecting other running circuits. The main advantages of dynamic partial reconfiguration lie in its flexibility and improved resource utilization. By using DPR, multiple functional modules can be implemented in the FPGA, each of which can be independently reconfigured as needed without reloading the entire design. This flexibility enables FPGAs to adapt to a variety of application requirements while reducing reprogramming and reloading time and accelerating design iterations.

[0065] 7. Abstract Syntax Tree

[0066] An Abstract Syntax Tree (AST) is a tree-like data structure used to represent the structure of program code. It is widely used in compilers and parsers to convert source code into a form that is easy to process and analyze. The AST reflects the grammatical structure of the code and discards unnecessary details such as whitespace, comments, and specific tags. It captures the logical structure and semantics of the code and provides a convenient way to analyze, transform, and optimize the code. In the AST, each code element (such as an expression, statement, function declaration, etc.) is represented as a node, and the nodes are connected through parent-child and sibling relationships. The root node of the tree represents the entire code, while the leaf nodes represent the most basic code units.

[0067] The advantages of AST include:

[0068] a. Structured representation: AST provides a structured way to represent code, making code parsing and analysis more intuitive and flexible.

[0069] b. Syntax independence: AST does not depend on the grammatical rules of a specific programming language, so it can be used to parse and process multiple programming languages.

[0070] c. Easy to analyze and transform: By traversing and manipulating AST nodes, static analysis, code optimization, refactoring, and other operations can be performed.

[0071] In short, an abstract syntax tree is a tree-shaped data structure used to represent the structure of program code. It provides a convenient way to analyze, transform, and optimize code.

[0072] 1 , there is shown a flowchart of a circuit synthesis method according to an embodiment of the present invention. The method may specifically include the following steps:

[0073] Step 101: Parse the assertion statement to be synthesized and identify the keywords and verification methods corresponding to the assertion statement;

[0074] Step 102: Instantiate the keywords in the assertion statement into a basic circuit module;

[0075] Step 103: Determine the connection mode corresponding to the basic circuit module according to the verification mode;

[0076] Step 104: Connect the basic circuit modules according to the connection method to obtain an assertion circuit corresponding to the assertion statement.

[0077] It should be noted that an assertion statement is a statement used during the test process to check whether a specific condition is met. A test project is a series of test activities performed to verify the correctness of software or systems. A test project for the design under test can contain multiple assertion statements. Through these assertion statements, the test objectives and expected results can be defined, thereby guiding the design and execution of the test. Specifically, by inserting assertion statements in the test code, various conditions and constraints in the test process can be automatically verified to ensure the correctness of the test results. When problems or errors occur in the test project, the failure information of the assertion statement can be used to quickly identify the specific conditions that caused the problem, thereby speeding up the troubleshooting and repair of the problem.

[0078] Assertion statements are not synthesizable and cannot be directly configured in hardware (e.g., FPGA chip) to implement hardware simulation of the design under test. Therefore, in an embodiment of the present invention, the assertion statement is first parsed to identify the keywords and verification methods of the assertion statement.

[0079] Keywords are used to reflect non-synthesizable feature operators or operators in assertion statements, such as clock signals, sampling functions, and sequence operator keywords. The assertion statement verification method reflects the assertion verification rules—the conditions that must be met for the assertion to be correct. Based on the logic of each keyword, hardware simulation is performed on the functions implemented by each keyword using various logic devices in the RTL circuit, such as logic registers, state machines, and flip-flops. The corresponding equivalent hardware circuit is then designed to obtain the basic circuit module corresponding to the keyword.

[0080] In the embodiment of the present invention, the keywords of assertion statements can be divided into six categories: immediate assertion, sequence sampling signal, sequence operator, signal detection (signal_check) operator, basic operator, and timing operator (delay and repeat). Each category includes several non-synthesizable keywords. Based on the type of keywords in the assertion statement, the basic circuit modules of the present invention can also be divided into the above six categories.

[0081] The corresponding connection method for each basic circuit module can be determined based on the verification method of the assertion statement. Specifically, the verification method of the assertion statement can determine information such as the order of each keyword in the assertion statement, the clock signal transmission logic, and the state matching rules. Based on this information, the input signals and output signals of each basic circuit module are connected to obtain the corresponding connection method for each basic circuit module.

[0082] By connecting the basic circuit modules corresponding to the assertion statement according to the determined connection mode, the assertion circuit corresponding to the assertion statement can be obtained. It is understood that the assertion circuit in the embodiment of the present invention can be represented by RTL code.

[0083] The circuit synthesis method provided by an embodiment of the present invention parses assertion statements, identifies the keywords and verification methods of the assertion statements, instantiates the keywords into equivalent basic circuit modules, determines the connection methods corresponding to each basic circuit module according to the verification method, and connects each basic circuit module according to the determined connection method, thereby converting non-synthesizable assertion statements into equivalent synthesizable assertion circuits, so as to implement assertion-based verification in hardware.

[0084] In an optional embodiment of the present invention, the step 103 of determining the connection mode corresponding to the basic circuit module according to the verification mode includes:

[0085] Step S11, determining the timing signals of each basic circuit module corresponding to the assertion statement and the signal connection information between the basic circuit modules according to the verification method;

[0086] Step S12: determining a connection mode corresponding to the basic circuit module according to the timing signal and signal connection information of the basic circuit module.

[0087] An assertion statement may contain one or more keywords, each of which corresponds to a basic circuit module with the same function. In an embodiment of the present invention, the timing signals of each basic circuit module corresponding to the assertion statement and the signal connection information between the basic circuit modules can be determined based on the verification method of the assertion statement.

[0088] Timing signals determine the execution period of micro-operations, specifying when a micro-operation (e.g., clock signal, enable signal, etc.) is issued. Timing signals can be used to determine the operating logic of basic circuit modules and the interaction logic between them.

[0089] A basic circuit module typically includes an enable terminal, an input terminal, and an output terminal. In an embodiment of the present invention, the basic circuit module typically has two output terminals, namely, an output terminal for outputting a "Match" signal indicating a successful assertion, and an output terminal for outputting a "Fail" signal indicating a failed assertion. Referring to Figure 2, a structural diagram of a basic circuit module of a signal detection operator (signal_check) is shown. The signal detection operator is used to detect whether the input signal is true. As shown in Figure 2, "EN" is the enable signal port of the basic circuit module. Only when the previous level basic circuit module matches, that is, when the output signal of the previous level basic circuit module meets the method in the assertion statement, the previous level match signal (that is, the output signal of the previous level basic circuit module) can enable the current basic circuit module and input the result. "MATCH" and "FAIL" are the output ports of the basic circuit module. After the current module is activated, it is output to the next level or the entire assertion circuit. The three port structures in the basic circuit module ensure that the clock signal transmitted in the assertion circuit maintains normal timing.

[0090] As an example, the assertion statement to be synthesized is as follows:

[0091] @(posedge clk)SIG_IN1##2 SIG_IN2[*2]##1 SIG_IN3|=>SIG_IN4##2 SIG_IN5

[0092] Among them, "|=>" is a nonoverlapped implication operator. The sequence on the left side of a nonoverlapping implication operator is called the cause sequence, and the sequence on the right side is called the result sequence. Assertion statements containing nonoverlapping implication operators have the following situations:

[0093] If the cause sequence does not match (that is, there is a conflict, and the actual running logic of the cause sequence is inconsistent with the logic in the assertion statement), the assertion does not take effect; if the result sequence also matches in the next clock cycle after the cause sequence matches (that is, there is no conflict, and the actual running logic of the result sequence is consistent with the logic in the assertion statement), the assertion matches (that is, the assertion succeeds); if the result sequence conflicts in the next clock cycle after the cause sequence matches, the assertion fails.

[0094] Taking the cause sequence in the above assertion statement as an example, Figure 3 shows the schematic diagram of the assertion circuit structure corresponding to the above example assertion statement. At each rising edge of the clock signal, SIG_IN1 in the cause sequence is checked to see if it is true. If it is true, SIG_IN2 must remain true for two clock cycles after two clock cycles (##2). If it is true, SIG_IN3 must also be true after one clock cycle. If all of these conditions are met, the entire cause sequence, SIG_IN1##2 SIG_IN2[*2]##1 SIG_IN3, matches.

[0095] The logic for determining whether the result sequence matches is the same as the cause sequence. Taking the result sequence in the above assertion statement as an example, in the next clock cycle after the cause sequence matches, check whether SIG_IN4 is true. If true, SIG_IN5 must also be true two clock cycles later (##2). If all these conditions are met, the result sequence "SIG_IN4##2 SIG_IN5" is considered a match.

[0096] The above assertion statement contains four keywords: signal check (signal_check), delay, repetitive signal check, and non-overlapping implication operator. Therefore, this assertion statement corresponds to four basic circuit modules:

[0097] 1) signal_check: used to detect whether the input signal is true;

[0098] 2) signal_repeat: used to perform repetitive signal detection function;

[0099] 3) time_delay: output the input signal after n clock cycles;

[0100] 4) nonoverlapped implication operators: used to implement the functionality of the nonoverlapping implication operator (|=>).

[0101] Based on the aforementioned assertion verification method, the timing signals of each basic circuit module and the signal connection information between these modules can be determined. Specifically, based on the cause sequence "SIG_IN1##2 SIG_IN2[*2]##1 SIG_IN3," the determination result of the SIG_IN3 signal must be output one cycle after two cycles after the SIG_IN1 signal is true and two cycles after the SIG_IN2 signal remains true. Therefore, the assertion circuit only outputs the result after the EN terminal receives the Match signal from the previous stage, and not at any time.

[0102] The nonoverlapped implication operators module determines that if the sequence on the right side matches in the next clock cycle after the cause sequence matches, the entire assertion matches and a Match signal is output, which is the match signal of the entire assertion circuit. If the sequence on the right side conflicts in the next clock cycle after the cause sequence matches, a Fail signal is output, indicating that the entire assertion fails. If the cause sequence does not match (conflict), the assertion does not take effect and neither MATCH nor FAIL is output.

[0103] Based on the timing signals and signal connection information of each basic circuit module, the connection mode between each basic circuit module corresponding to the assertion statement can be determined. By connecting the basic circuit modules according to the connection mode, the assertion circuit corresponding to the assertion statement can be obtained.

[0104] In an optional embodiment of the present invention, the instantiation of the keywords in the assertion statement into a basic circuit module in step 102 includes:

[0105] Step S21: determining the assertion operator included in the assertion statement according to the keyword;

[0106] Step S22: Obtain a basic circuit module corresponding to the assertion operator from a preset assertion equivalent hardware library.

[0107] Among them, the assertion operator is an operator that implements the basic assertion function in the assertion statement. The assertion operators in the embodiment of the present invention may include but are not limited to: immediate assertion, sequence sampling signal, sequence operator, signal detection (signal_check) operator, basic operator, timing operator (delay and repetition), each category contains several non-synthesizable keywords and operators, etc.

[0108] The main reason why assertion statements are not synthesizable is that they are usually written using complex procedural structures, time operators, functions, etc. These assertion operators cannot be directly converted into hardware elements. To convert assertion statements into synthesizable hardware equivalent circuits, these assertion operators need to be converted.

[0109] In an embodiment of the present invention, in order to improve the circuit synthesis efficiency of assertion statements, an assertion equivalent hardware library can be constructed in advance, and the basic circuit modules corresponding to each assertion operator can be stored in the assertion equivalent hardware library, so that in the process of performing circuit synthesis processing on the assertion statement, the corresponding basic circuit modules can be directly obtained from the assertion equivalent hardware library.

[0110] It should be noted that the basic circuit modules stored in the assertion equivalent hardware library of the embodiment of the present invention are composed of logic devices, which are used to implement the functions of the corresponding assertion operators. For example, the basic circuit module signal_check corresponds to the signal detection operator, which is used to detect whether the input signal is true; the basic circuit module nonoverlapped implication operators is used to implement the function of the non-overlapping implication operator (|=>). Among them, the logic devices may include but are not limited to: gate circuits and inverters, selectors, decoders, counters, registers, triggers, latches, buffer drivers, transceivers, bus switches, state machines, etc. The logic devices contained in the basic circuit module are determined according to the functions it implements. The functions of the basic circuit modules are different, and the logic devices contained are also different.

[0111] Optionally, before obtaining the basic circuit module corresponding to the assertion operator from a preset assertion equivalent hardware library, the method further includes:

[0112] Step S31: Determine the logical relationship between the input signal and the output signal of the assertion operator;

[0113] Step S32: determining a connection mode between the logic device corresponding to the assertion operator and the logic device according to the logical relationship;

[0114] Step S33: Connecting the logic devices corresponding to the assertion operator according to the connection mode to obtain a basic circuit module corresponding to the assertion operator;

[0115] Step S34: Add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

[0116] In this embodiment of the present invention, the logical relationships between the input and output signals of various assertion operators can be used to determine the logic devices corresponding to the assertion operators and the connection method between the logic devices. By connecting the logic devices according to the determined connection method, the basic circuit module corresponding to the assertion operator can be obtained. The generated basic circuit module is added to the assertion equivalent hardware library to implement the construction of the assertion equivalent hardware library.

[0117] For example, take the following assertion statement as an example:

[0118] The assertion statement involves multiple non-synthesizable assertion operators, and in different categories, they are "&&", "==", "|=>", "!=" belonging to basic operators; "$rose", "$past" belonging to sequence sampling signals; "or" belonging to sequence operators; "##4", "[*3]" belonging to timing operators. These assertion operators cannot directly generate RTL circuits and can only be used for software RTL simulation. However, through the method provided in the embodiment of the present invention, each assertion operator can be converted into an RTL circuit, thereby realizing hardware accelerated simulation. The hardware assertion operators in the present invention can be freely combined through a unified interface, and support multi-bit width input signals, and the signal bit width can be specified during compilation.

[0119] According to the above steps S31 to S34, each assertion operator in the above assertion statement is processed in sequence.

[0120] For basic operators or sequence sampling signals, the logical relationship between the input signal and the output signal of the assertion operator can be determined based on the logical operation rules corresponding to the assertion operator and the bit width of the input signal. For example, the basic operator "&&" has a symmetrical relationship between the inputs at both ends, and swapping the left and right sides will not affect the output result. When the inputs are all 1 bit wide, if the inputs are 1 at the same time, the output is 1; if the inputs are not 1 at the same time, the output is 0; when the inputs are multi-bit wide, you only need to perform a logical AND on the two inputs to get the correct result. Therefore, you only need to combine the logical relationships to solve this operator, and you only need to use the assign statement in the code. This principle can be used for most operators in the simple operator category, such as the basic operators "==", "!=", etc.

[0121] The implementation methods of the three serial sampling signals "$rose," "$fell," and "$stable" are very similar. "$rose" is used as an example for illustration. "$past" differs slightly from these three functions. Figure 4 shows a schematic diagram of a $rose function operator. As shown in Figure 4, the rose operator supports input signals signal_in with multiple bit widths. Just as "binary_out[7:0]" in the above statement is multi-bit wide, the method for handling multi-bit widths here is to use the bitwise AND symbol "&" to obtain an 8-bit signal, where "[7:1]" is 0 and "[0]" is 0 / 1. The rose function is used to detect whether there is a 0-1 transition. To do this, simply save the signal from the previous cycle and compare it with the value of the current cycle to obtain the match and fail values. Only when there is a 0-1 transition does the match output be 1 and the fail output be 0. In all other cases, the match output is 0 and the fail output is 1. The "en" signal is the start signal, which can be understood as the signal that activates the operator. Operators at this level are activated only when the previous level matches. This principle applies to all operators, unless they are combinational logic operators. Under this principle, the "rose" operator uses registers, gates, and wires, all of which exist in real circuits, thus becoming a synthesizable expression. The implementations of "$fell" and "$stable" differ from "$rose" in the slightly different types of gates, but are largely the same, thus enabling conversion to RTL circuits.

[0122] For overlapping implication operators or non-overlapping implication operators, the signal connection information between the cause sequence and the result sequence of the assertion operator can be determined according to the verification rules of the assertion operator, and then the logical relationship between the input signal and the output signal of the assertion operator can be determined according to the signal connection information. The difference between overlapping implication operators and non-overlapping implication operators is that overlapping implication operators require the cause sequence and the result sequence to be determined simultaneously. Obviously, these two operators are different from other simple operators. The clock cycle is introduced here, which means that a clock signal is definitely required to satisfy the logical relationship between the two operators. Referring to Figure 5, a schematic diagram of a non-overlapping implication operator is shown. As shown in Figure 5, op_input_left is the output of the statement "en&&$rose(binary_out[7:0])&&(binary_out[31:8]==24'b110)", and op_input_right is the output of the statement "(gray_in[2][*3]##4gray_in[2])or($past(gray_in,4)!=32'hfe)". Only when the output of op_input_left is 1, the output of op_input_right will be assigned to match and fail. Otherwise, match and fail are directly assigned to 0. This output method realizes the logical function of the non-overlapping implication operator, and only introduces registers and wires, thus realizing the RTL circuit of these two non-synthesizable operators.

[0123] For the timing operator, the delay period and level change corresponding to the input signal and output signal of the timing operator can be determined first; then, the logical relationship between the input signal and the output signal of the timing operator can be determined based on the delay period and the level change. Among them, the timing operator can be divided into a delay operator and a repeat operator. Referring to Figure 6, a schematic diagram of a delay operator is shown. As shown in Figure 6, neither the delay nor the repeat operator has an en signal. This is because the input signal_in of these two operators is the output match of the previous operator signal_check, and signal_check requires an en signal to be enabled, so these two operators are no longer needed. In the above assertion statement example, "gray[2][*3]" must first pass through the signal_check operator to determine whether the match is 0 or 1. The match result is then used as the signal_in of the delay operator. Only when signal_in is 1 will the delay function continue. If signal_in is 0, then the signal_out will be directly output as 0. At this time, the delay function will not be activated. The above statement example will ignore "##4" and will not delay four times. When signal_in is 1, the function of the delay operator is to delay the input signal for n cycles before outputting it. In the above example, the output is delayed for 4 clock cycles. This function can be implemented in the circuit using a counter. A counting parameter is added, and the value of the counting parameter is related to the value of n in "##n". At the same time, a state machine is added, divided into a basic state (IDLE_DELAY) and an active state (READ_DELAY). Only when signal_in is 1 will the state machine change from the basic state to the active state. After entering the active state, as long as the count variable is not greater than the count parameter, it will remain in the active state until the count reaches n and the output signal_out is 1. The whole process involves counters and state machines, which have corresponding RTL circuits, so the conversion of the delay operator's RTL circuit is realized.

[0124] The schematic diagrams of the repeat operator and the delay operator are the same. The difference is that the repeat operator needs to add a judgment on whether signal_in is 1 at each rising edge of the clock. This means that the judgment of the state machine needs to be modified. However, the overall implementation method is still the counter and state machine, which also corresponds to the RTL circuit, so the conversion of the repeat operator RTL circuit is realized.

[0125] For signal detection operators, the logical relationship between the input signal and output signal can be determined based on the operator type. These operator types include combinational and sequential logic. Essentially, every non-synthesizable operator requires the use of a signal_check operator. The function of a signal detection operator is to determine whether the input signal is true. For example, every signal entering a delay operator must first undergo a signal_check. After passing through the signal_check operator, the output match is passed to the delay operator for further verification. Signal_check is divided into combinational and sequential logic, with slightly different scopes of application. Combinatorial signal_check is generally used when clock-related operators such as delay and repetition are involved, as using sequential signal_check can introduce timing errors. However, when all operators are combinational, such as those in simple operators, since these operators lack clock signals and the entire statement is executed within a clock context, sequential signal_check is required to introduce clock signals. The signal_check of combinational logic uses gate circuits and lines, and the signal_check of sequential logic uses registers, gate circuits and lines, which are the basic components of RTL circuits.

[0126] For sequence operators, the matching rules between the two input sequences and the output signal of the sequence operator can be determined based on the assertion function corresponding to the sequence operator. Then, the logical relationship between the input signal and the output signal of the sequence operator can be determined based on the matching rules. Taking the "or" operator in the above assertion statement as an example, FIG7 shows a schematic diagram of an or operator. As shown in FIG7, the left input of the or operator is a sequence, and the right input is also a sequence. Therefore, the two input signals seqop_input_left and seqop_input_right can both be multi-bit wide. In the above example, they are (gray_in[2][*3]##4gray_in[2]) and ($past(gray_in,4)!=32'hfe) respectively. The function of the or operator is to detect whether at least one of the two sequences is true. When at least one of the two sequences is true, the output match is 1. This logical relationship is very similar to the or in digital circuits, but there are some differences. Because in SVA software simulation, there is no need to consider resource consumption and occupied area, the length of time for this judgment can be very long, even infinitely long; but this is impossible to achieve in hardware, so the en signal is added to enable this operator, and a counting clock cycle parameter NUM_CNT is also needed to be added. This parameter is used to limit the length of the judgment cycle so that this operator does not occupy too many resources. The same is true for the other three sequence operators and, intersect, and first_match. This is essentially due to hardware limitations. In software simulation, "or" only has one output. However, in hardware, if an output cannot be determined to be in three states: valid, invalid, and reset, match and fail need to be added. Unlike the above operators, match and fail here are often not simply inverse relationships. In the "or" operator, assuming the counting clock cycle parameter NUM_CNT is 5, only when both sequences remain in the false state for 5 cycles within the five cycles after being enabled by "en" will "match" be 0 and "fail" be 1. As long as any sequence is true for one clock cycle within the five cycles enabled by "en", the output will be "match" 1 and "fail" 0. The reset state is when both "match" and "fail" are 0. To implement such logic, match and fail need to be implemented separately. To implement the "match" function, you need to first obtain the result of the "|" of the two inputs, seq_or, and then extend the "en" signal to be valid high for NUM_CNT cycles. To achieve this step, you need to add a counter, and then "match" is the result of the extended "seq_or" and "en" signals.The fail state output requires the use of a state machine, which is divided into a basic state (IDLE_FAIL) and an active state (READ_FAIL). The state change is based on the input of the en signal. As long as seq_or is 1 at least once in a cycle, the fail output will no longer be 1. These two methods can implement the functionality of the or operator. The entire process primarily utilizes counters and state machines, functions that can be implemented in RTL circuits, making the or operator synthesizable.

[0127] Other sequence operators, such as the and operator and the intersect operator, are implemented similarly to the or operator, differing in their logic. The and operator differs from the "and" operator in digital circuits. Intersect is more similar to "and" in that it requires both sequences to be 1 simultaneously for the match operator to output 1. The and operator's logic is to detect that both sequences are true at once, initially outputting match as 1. It continues until both sequences are no longer true, at which point it outputs match as 0. The fail operator's logic is essentially the same as the or operator's: it outputs fail as 1 only if no matches are found within the entire determination cycle.

[0128] The logic of the first_match operator is that if there are multiple cycles of high-level input, it will only output a high level for one cycle. This logic is different from the above three operators, but the basic implementation methods are state machines and counters, which are functions that can be implemented by RTL circuits.

[0129] According to the above processing logic, each assertion operator is converted into a synthesizable basic circuit module, and the basic circuit module corresponding to each assertion operator is stored in the assertion equivalent hardware library. Therefore, in the process of circuit synthesis processing of the assertion statement, the corresponding basic circuit module can be directly obtained from the assertion equivalent hardware library, thereby improving the circuit synthesis efficiency of the assertion statement.

[0130] In an optional embodiment of the present invention, the step 101 of parsing the assertion statement to be synthesized and identifying the keywords and verification methods corresponding to the assertion statement includes:

[0131] Step S41: Obtain a design file; the design file includes a design under test and an assertion statement; the assertion statement is used to verify whether the design under test meets the test conditions;

[0132] Step S42: convert the design file into an abstract syntax tree; the abstract syntax tree is used to reflect the logical structure and semantics of the design file;

[0133] Step S43: traverse the abstract syntax tree to obtain a sentence tree of the segmentation language in the abstract syntax tree;

[0134] Step S44: Parse the assertion sentence tree to identify keywords and verification methods corresponding to the assertion sentences.

[0135] The design under test and assertion statements in the design file are usually described using a hardware description language (such as HDL), which is not easy to process and analyze. In an embodiment of the present invention, the design file can be parsed first and converted into an abstract syntax tree that is easier to process and analyze. The abstract syntax tree can reflect the logical structure and semantics of the design file (including the design under test and assertion statements). In practical applications, an abstract syntax tree generation tool, such as a parser, etc., can be used.

[0136] Then, the converted abstract syntax tree is traversed to find the assertion language sentence tree corresponding to the assertion statement. Each assertion language sentence tree in the abstract syntax tree is parsed to identify keywords (such as clock signals, sampling functions, sequence operation keywords, etc.) and the verification method of the assertion statement.

[0137] Optionally, the step S44 of parsing the assertion sentence tree to identify keywords and verification methods corresponding to the assertion statement includes:

[0138] Sub-step S441: performing grammatical analysis on the assertion sentence tree to identify keywords corresponding to the assertion sentence;

[0139] Sub-step S442: semantically parse the assertion sentence tree to identify a verification expression corresponding to the assertion statement.

[0140] During the parsing of the assertion sentence tree, grammatical analysis can be used to identify keywords in the assertion statement, such as immediate assertions, sequence sampling signals, sequence operators, signal detection (signal_check) operators, basic operators, and timing operators (delay and repeat). Each category contains several non-synthesizable keywords and operators. Semantic analysis can also be used to identify the verification expressions corresponding to the assertion statement, such as the timing signals, signal connection information, and matching rules of the basic circuit modules corresponding to each keyword.

[0141] Exemplarily, in an embodiment of the present invention, the assertion statement can be divided into 7 nodes and 5 levels. Specifically, the nodes of the assertion statement may include: sequence, constant, signal, sample subroutine, operator, time delay operator, repetition operator. The levels of the assertion statement may include: sequence expression, unary operator, sample subroutine, time delay operator and repetition operator. Among them, the unary operator level includes the left operator (operator left) and the right operator (operator right), the sample subroutine level includes the argument (Argument), the time delay operator level includes the time delay expression (time delay expression), and the repetition operator level includes the repetition expression (repetition expression).

[0142] In the process of analyzing the sentence tree of the broken language, we can first determine what type of node the current expression tree is, and based on the current level of the expression tree and the information of the previous level, instantiate the identified keywords into basic circuit modules, and determine the connection method between each basic circuit module.

[0143] For example, for the assertion statement "SIG_IN1##2 SIG_IN2[*2]##1 SIG_IN3|=>SIG_IN4##2SIG_IN5", the structure information of the assertion sentence tree corresponding to the assertion statement is as follows:

[0144] The tree structure of the above assertion statement is analyzed from top to bottom. The above assertion sentence tree includes the following four levels of analysis:

[0145] 1. The level identifier of this layer is "operator", and the level identifier of the previous layer is "sequence expression". "Operator" is parsed to be "nonoverlapped implication", and "nonoverlapped implication" is instantiated as a basic circuit module. Among them, "nonoverlapped implication" is used to implement the function of the nonoverlapping implication operator (|=>). The sequence on the left side of the nonoverlapping implication operator is called the cause sequence, and the sequence on the right side is called the result sequence. There are the following situations for assertion statements containing nonoverlapping implication operators:

[0146] If the cause sequence does not match (that is, there is a conflict, and the actual running logic of the cause sequence is inconsistent with the logic in the assertion statement), the assertion does not take effect; if the result sequence also matches in the next clock cycle after the cause sequence matches (that is, there is no conflict, and the actual running logic of the result sequence is consistent with the logic in the assertion statement), the assertion matches (that is, the assertion succeeds); if the result sequence conflicts in the next clock cycle after the cause sequence matches, the assertion fails.

[0147] Syntactically, the non-overlapping implication operator "|=>" divides the assertion statement into two left and right sequences, which correspond to "left" and "right" in the abstract syntax tree. The next step is to analyze "left" first.

[0148] 2. The level identifier of this layer becomes "operator left", and the level identifier of the previous layer becomes "operator". Parsing into left, there are three elements, and they contain delay. The first element is parsed and judged to be "signal", and is instantiated as a signal detection operator (signal_check) basic circuit module with a delay of 0. Among them, the signal detection operator is used to detect whether the input signal is true. The second element is parsed and judged to be "repetition operator() repetition operator", and the "repetition" basic circuit module is instantiated. Enter the recursion to complete the "repetition" basic circuit module and configure the repetition period to 2 clock cycles. After exiting the recursion, the delay is 2 clock cycles, and the first "time delay" basic circuit module is instantiated with a parameter of 2. Connect the "match" port of the first element to the input of the first "time delay" basic circuit module, and the output of the first "time delay" basic circuit module to the enable port (en) of the "repetition" basic circuit module. It should be noted that when the assertion is correct, the assertion circuit will output a high-level signal of "match", and when the assertion fails, the assertion circuit will output a high-level signal of "fail".

[0149] Connect the three elements in sequence, the level identifier of this layer becomes "operator right", and the level identifier of the previous layer becomes "operator", and enter the analysis of the right side of the operator.

[0150] 3. The level identifier of this layer is "operator right," and the level identifier of the previous layer is "operator." Parsing shows that right has two elements, and they are connected in the same way as on the left. This embodiment of the present invention is not further described here. Next, the level identifier of this layer becomes "operator," and the level identifier of the previous layer becomes "operator right."

[0151] 4. This layer is labeled "operator," and the previous layer is labeled "operator right." Connect the match signal outputs of the last left and right modules to the two inputs of the "nonoverlapped implication" basic circuit module, respectively. Connect the match signal output of the "nonoverlapped implication" basic circuit module to the match signal output of the entire assertion circuit, serving as the output signal indicating a successful match for the current assertion circuit. Connect the fail signal output of the "nonoverlapped implication" basic circuit module to the fail signal output of the entire assertion circuit, serving as the output signal indicating a failure for the current assertion circuit.

[0152] After the above processing, the circuit comprehensive processing of the assertion statement "SIG_IN1##2 SIG_IN2[*2]##1 SIG_IN3|=>SIG_IN4##2 SIG_IN5" is realized, that is, the assertion circuit of the assertion statement is obtained.

[0153] In an optional embodiment of the present invention, the method further includes:

[0154] Step S51: generating a target netlist based on the design under test and the assertion circuit;

[0155] Step S52: configuring the design under test and the assertion circuit into an integrated circuit chip according to the target netlist;

[0156] Step S53: running the integrated circuit chip and monitoring the assertion result of the design under test;

[0157] Step S54: If the assertion coverage of the design under test meets a preset condition, determine that the design under test passes verification.

[0158] It should be noted that in electronic design automation, a netlist refers to a method of describing the connections of digital circuits using basic logic gates. Because a logic gate array has a similar arrangement to a wirelist, it is called a "netlist." A netlist typically conveys information about circuit connections, such as module instances, nets, and related properties. If more hardware information is required, hardware description languages ​​such as Verilog, VHDL, or other specialized languages ​​are typically used for description, verification, and simulation. High-level abstraction hardware descriptions (such as the register transfer level) can be converted into a low-level abstraction (logic gate level) circuit connection netlist through logic synthesis. This step can now be automated using tools, significantly reducing the complexity for designers working with very large-scale integrated circuits (VLSIs). Hardware manufacturers use this netlist to manufacture specific application-specific integrated circuits or other circuits. Some relatively small circuits can also be implemented on field-programmable gate arrays.

[0159] In an embodiment of the present invention, the target netlist is used to describe the connection between the DUT and the assertion connection using logic gates. Specifically, in the target netlist, the input end of the assertion circuit is connected to the output end of the signal to be monitored in the DUT.

[0160] Based on the target netlist, the design under test and the assertion circuit can be configured into an integrated circuit chip. The integrated circuit chip in the embodiments of the present invention is an FPGA. It is understood that to run a design on an FPGA, it is necessary to first generate a corresponding bitstream file using software provided by the FPGA manufacturer, and then use the bitstream file to import the design into the FPGA. A bitstream file is a binary file used to store and transmit configuration information for a programmable logic device (such as an FPGA). It contains the bit information that configures the FPGA for specific hardware functions. In embodiments of the present invention, a target bitstream file can be generated based on the target netlist. The target bitstream file contains the bit information that configures the FPGA for hardware verification of the design under test using the assertion circuit. Specifically, the target bitstream file contains the FPGA's logic gate configuration, register settings, and connection information. Using the target bitstream file, the assertion circuit and the design under test can be burned into the FPGA board, completing the configuration of the FPGA. In the FPGA, the signal input of the assertion circuit is connected to the output of the signal to be monitored in the RTL circuit design of the design under test.

[0161] Run the PFGA and monitor the assertion results of the DUT. If a monitored signal in the DUT behaves in a manner that violates the assertion statement, the assertion circuit automatically flags the issue and outputs an assertion failure signal. Furthermore, the assertion circuit can pinpoint the moment of assertion failure and the associated signal. This failure information from the assertion circuit allows for quick identification of the specific conditions that caused the problem, accelerating troubleshooting and repair.

[0162] When the assertion coverage of the design under test meets the preset conditions, it can be determined that the design under test has passed the verification. Among them, the assertion coverage is a test metric indicator used to measure the extent to which assertion statements are executed during the test process. Assertion coverage is usually expressed in the form of a percentage, specifically the ratio between the number of assertion statements that have been correctly executed and the total number of assertion statements. For example, if there are 100 assertion statements in the design file, and 80 assertion statements are correctly executed in the test, then the assertion coverage is 80%. A higher assertion coverage indicates that the test covers more assertion statements, thereby providing a more comprehensive test guarantee. In an embodiment of the present invention, the preset conditions can be set according to specific verification requirements. For example, the preset condition can be that the assertion coverage of the design under test is greater than or equal to a preset threshold, and so on.

[0163] During actual testing, the circuit verification method provided by the present invention was used to verify the design under test on an FPGA using assertion circuits, achieving a performance improvement of up to 40,989 times compared to software simulation. Compared to debugging tools provided by existing vendors, the present invention minimizes area overhead and has no impact on the timing behavior of the device under test. The present invention uses hardware (FPGA) to accelerate debugging of the design under test, quickly reaching the assertion failure point and improving verification efficiency.

[0164] In summary, an embodiment of the present invention provides a circuit synthesis method, which parses assertion statements, identifies the keywords and verification methods of assertion statements, instantiates the keywords into equivalent basic circuit modules, determines the connection methods corresponding to each basic circuit module according to the verification method, and connects each basic circuit module according to the determined connection method, thereby converting non-synthesizable assertion statements into equivalent synthesizable assertion circuits, so as to implement assertion-based verification in hardware.

[0165] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0166] Device embodiment

[0167] 8 , there is shown a block diagram of a circuit integration device according to the present invention, which may include:

[0168] The parsing module 801 is used to parse the assertion statement to be synthesized and identify the keywords and verification methods corresponding to the assertion statement;

[0169] An instantiation module 802, configured to instantiate keywords in the assertion statement into a basic circuit module;

[0170] A first determining module 803 is configured to determine a connection mode corresponding to the basic circuit module according to the verification mode;

[0171] The first connection module 804 is configured to connect the basic circuit modules according to the connection mode to obtain an assertion circuit corresponding to the assertion statement.

[0172] Optionally, the first determining module includes:

[0173] A first determining submodule, configured to determine, according to the verification method, timing signals of each basic circuit module corresponding to the assertion statement and signal connection information between the basic circuit modules;

[0174] The second determining submodule is configured to determine a connection mode corresponding to the basic circuit module according to the timing signal and signal connection information of the basic circuit module.

[0175] Optionally, the instantiation module includes:

[0176] An assertion operator determination submodule, configured to determine the assertion operator included in the assertion statement according to the keyword;

[0177] The circuit acquisition submodule is used to obtain the basic circuit module corresponding to the assertion operator from a preset assertion equivalent hardware library.

[0178] Optionally, the device further comprises:

[0179] A second determination module, configured to determine a logical relationship between an input signal and an output signal of an assertion operator;

[0180] a third determining module, configured to determine a connection mode between the logic device corresponding to the assertion operator and the logic device according to the logical relationship;

[0181] A second connection module is used to connect the logic devices corresponding to the assertion operator according to the connection method to obtain a basic circuit module corresponding to the assertion operator;

[0182] An adding module is used to add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

[0183] Optionally, the parsing module includes:

[0184] An acquisition submodule is configured to acquire a design file, wherein the design file includes a design under test and an assertion statement, and the assertion statement is configured to verify whether the design under test meets the test conditions.

[0185] A conversion submodule, configured to convert the design file into an abstract syntax tree; the abstract syntax tree is configured to reflect the logical structure and semantics of the design file;

[0186] A traversal submodule, configured to traverse the abstract syntax tree to obtain a sentence tree of a segmentation language in the abstract syntax tree;

[0187] The parsing submodule is used to parse the assertion sentence tree and identify keywords and verification methods corresponding to the assertion sentences.

[0188] Optionally, the parsing submodule includes:

[0189] A grammar parsing unit, configured to perform grammar parsing on the assertion sentence tree and identify keywords corresponding to the assertion sentence;

[0190] The semantic parsing unit is used to perform semantic parsing on the assertion sentence tree and identify the verification expression corresponding to the assertion sentence.

[0191] Optionally, the device further comprises:

[0192] A netlist generation module, configured to generate a target netlist based on the design under test and the assertion circuit;

[0193] A chip configuration module, configured to configure the design under test and the assertion circuit into an integrated circuit chip according to the target netlist;

[0194] a monitoring module, configured to operate the integrated circuit chip and monitor assertion results of the design under test;

[0195] The fourth determining module is configured to determine that the design under test passes verification if the assertion coverage of the design under test meets a preset condition.

[0196] An embodiment of the present invention provides a circuit synthesis device, which parses assertion statements, identifies the keywords and verification methods of the assertion statements, instantiates the keywords into equivalent basic circuit modules, determines the connection methods corresponding to each basic circuit module according to the verification method, and connects each basic circuit module according to the determined connection method, thereby converting non-synthesizable assertion statements into equivalent synthesizable assertion circuits, so as to implement assertion-based verification in hardware.

[0197] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0198] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0199] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0200] Figure 9 is a block diagram of an electronic device for circuit synthesis according to an embodiment of the present invention. As shown in Figure 9, the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores executable instructions that cause the processor to execute the circuit synthesis method according to the aforementioned embodiment.

[0201] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0202] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG9 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0203] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0204] An embodiment of the present invention further provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is enabled to execute the circuit synthesis method shown in FIG1 .

[0205] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0206] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0207] It is understood that the embodiments described in the embodiments of the present invention can be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the modules, units, and sub-units can be implemented in one or more ASICs, DSPs, digital signal processing devices (DSP devices, DSPDs), programmable logic devices (PLDs), FPGAs, general-purpose processors, controllers, microcontrollers, microprocessors, and other electronic units used to perform the functions described in the present invention, or a combination thereof.

[0208] For software implementation, the techniques described in the embodiments of the present invention can be implemented through modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of the present invention. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0209] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0210] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0211] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0212] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0213] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0214] The above is a detailed introduction to a circuit synthesis method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A circuit synthesis method, the method comprising: Parsing the assertion statement to be synthesized, identifying keywords and verification methods corresponding to the assertion statement; Instantiating the keywords in the assertion statement into basic circuit modules; Determining a connection mode corresponding to the basic circuit module according to the verification mode; The basic circuit modules are connected according to the connection mode to obtain an assertion circuit corresponding to the assertion statement.

2. The method according to claim 1, wherein: The determining, according to the verification method, a connection method corresponding to the basic circuit module includes: Determine, according to the verification method, the timing signals of each basic circuit module corresponding to the assertion statement and the signal connection information between the basic circuit modules; The connection mode corresponding to the basic circuit module is determined according to the timing signal and signal connection information of the basic circuit module.

3. The method according to claim 1, wherein: The instantiation of the keywords in the assertion statement into a basic circuit module comprises: Determining, according to the keyword, an assertion operator included in the assertion statement; A basic circuit module corresponding to the assertion operator is obtained from a preset assertion equivalent hardware library.

4. The method according to claim 3, wherein: Before acquiring the basic circuit module corresponding to the assertion operator from the preset assertion equivalent hardware library, the method further includes: Determine the logical relationship between the input signal and the output signal of the assertion operator; Determine, according to the logical relationship, a connection mode between the logic device corresponding to the assertion operator and the logic device; Connecting the logic devices corresponding to the assertion operator in the connection manner to obtain a basic circuit module corresponding to the assertion operator; Add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

5. The method according to claim 1, wherein: The step of parsing the assertion statement to be synthesized and identifying keywords and verification methods corresponding to the assertion statement includes: Obtain a design file; the design file includes a design under test and an assertion statement; the assertion statement is used to verify whether the design under test meets the test conditions; Converting the design file into an abstract syntax tree; the abstract syntax tree is used to reflect the logical structure and semantics of the design file; Traversing the abstract syntax tree to obtain a sentence tree of the break words in the abstract syntax tree; The assertion sentence tree is parsed to identify keywords and verification methods corresponding to the assertion sentences.

6. The method according to claim 5, wherein: The step of parsing the assertion sentence tree and identifying keywords and verification methods corresponding to the assertion statements includes: Performing grammatical analysis on the assertion sentence tree to identify keywords corresponding to the assertion sentence; The assertion sentence tree is semantically parsed to identify a verification expression corresponding to the assertion sentence.

7. The method according to claim 5, wherein: The method further comprises: generating a target netlist based on the design under test and the assertion circuit; configuring the design under test and the assertion circuit into an integrated circuit chip according to the target netlist; Running the integrated circuit chip and monitoring the assertion results of the design under test; When the assertion coverage of the design under test meets a preset condition, it is determined that the design under test passes the verification.

8. A circuit integration device, comprising: A parsing module, used to parse the assertion statement to be synthesized, and identify the keywords and verification methods corresponding to the assertion statement; An instantiation module, used for instantiating the keywords in the assertion statement into a basic circuit module; A first determining module, used to determine a connection mode corresponding to the basic circuit module according to the verification mode; The first connection module is used to connect the basic circuit modules according to the connection mode to obtain the assertion circuit corresponding to the assertion statement.

9. The device according to claim 8, wherein: The first determining module includes: A first determination submodule, configured to determine, according to the verification method, timing signals of each basic circuit module corresponding to the assertion statement and signal connection information between the basic circuit modules; The second determining submodule is used to determine the connection mode corresponding to the basic circuit module according to the timing signal and signal connection information of the basic circuit module.

10. The device according to claim 8, wherein: The instantiation module comprises: An assertion operator determination submodule, used to determine the assertion operator included in the assertion statement according to the keyword; The circuit acquisition submodule is used to acquire the basic circuit module corresponding to the assertion operator from a preset assertion equivalent hardware library.

11. The device according to claim 10, wherein: The device also includes: A second determination module, used to determine the logical relationship between the input signal and the output signal of the assertion operator; A third determination module, used to determine the connection mode between the logic device corresponding to the assertion operator and the logic device according to the logical relationship; A second connection module, used to connect the logic devices corresponding to the assertion operator according to the connection mode to obtain a basic circuit module corresponding to the assertion operator; An adding module is used to add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

12. The device according to claim 8, wherein: The parsing module comprises: An acquisition submodule is used to acquire a design file; the design file includes a design under test and an assertion statement; the assertion statement is used to verify whether the design under test meets the test conditions; The conversion submodule is used to convert the design file into an abstract syntax tree; the abstract syntax tree is used to reflect the Describe the logical structure and semantics of the design document; A traversal submodule, used for traversing the abstract syntax tree to obtain a sentence tree of the segmentation language in the abstract syntax tree; The parsing submodule is used to parse the assertion sentence tree and identify keywords and verification methods corresponding to the assertion sentences.

13. The device according to claim 12, wherein: The parsing submodule includes: A grammar parsing unit, used to perform grammar parsing on the assertion sentence tree to identify keywords corresponding to the assertion sentence; The semantic parsing unit is used to perform semantic parsing on the assertion sentence tree to identify the verification expression corresponding to the assertion sentence.

14. The device according to claim 12, wherein: The device also includes: A netlist generation module, configured to generate a target netlist based on the design under test and the assertion circuit; A chip configuration module, configured to configure the design under test and the assertion circuit into an integrated circuit chip according to the target netlist; A monitoring module, used for running the integrated circuit chip and monitoring the assertion result of the design under test; The fourth determination module is used to determine that the design under test has passed the verification when the assertion coverage of the design under test meets a preset condition.

15. An electronic device, comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the circuit synthesis method as described in any one of claims 1 to 7. 16 . A readable storage medium, when instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the circuit synthesis method according to any one of claims 1 to 7.

17. A computer program product, (the computer program product is stored in a non-transitory storage medium,) the computer program product is executed by at least one processor to implement the circuit synthesis method according to any one of claims 1 to 7.

18. A transmission device / equipment, comprising the device / equipment (configured to be) used in the circuit synthesis method according to any one of claims 1 to 7.

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