Shift register unit, cascade circuit, driving method, display panel and display apparatus

Abstract

A shift register unit, comprising: an input sub-circuit, which is configured to set the level of a first node on the basis of the level of a first voltage signal end and the level of a first clock signal end; a start sub-circuit, which is configured to set the level of a second node on the basis of the level of a first control signal end, the level of a second control signal end, the level of a scanning start signal end and the level of the first clock signal end; and a dual-output sub-circuit, which is configured to output to a first output end a scanning signal delayed by a preset first period or output to a second output end a signal of an input end that is delayed by a preset second period.

Description

Shift register unit, cascade circuit, driving method, display panel and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 25, 2023, with application number 202310922145.6 and invention name “Shift register unit, cascade circuit, driving method, display panel and device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a shift register unit, a cascade circuit, a driving method, a display panel, and a device. Background Art

[0003] Currently, high-end mobile phones are increasingly using OLED (Organic Light-Emitting Diode) screens. Display driver technology has significantly improved display performance. Specifically, shift register (Gate Driver on Array) technology integrates the third-stage switching circuitry on the display panel's array substrate, eliminating the need for a third-stage driver integrated circuit. This reduces the display's bezel and reduces both material and manufacturing costs.

[0004] The most common AMOLED shift register circuit today is composed of 8T2C circuits, which consist of eight thin-film transistors and two capacitors. To achieve two Gout outputs, two 8T2C circuits are required. To achieve a narrower display bezel, reducing the space required for the shift register circuit becomes a pressing issue.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The embodiment of the present disclosure provides a shift register unit, comprising: an input subcircuit, a start subcircuit, and a dual output subcircuit;

[0008] The input sub-circuit is electrically connected to the first clock signal terminal, the first voltage signal terminal and the first node respectively, and is configured to set the level of the first node according to the levels of the first voltage signal terminal and the first clock signal terminal;

[0009] The start sub-circuit is electrically connected to the first control signal terminal, the second control signal terminal, the first clock signal terminal, the scan start signal terminal, the second node and the input terminal respectively, and is configured to set the level of the second node according to the levels of the first control signal terminal, the second control signal terminal, the scan start signal terminal and the first clock signal terminal;

[0010] The dual-output sub-circuit is electrically connected to the first control signal terminal, the second control signal terminal, the second clock signal terminal, the first node, the second node, the first output terminal and the second output terminal, respectively, and is configured to output the scanning signal of the scanning start signal terminal delayed by a preset first period to the first output terminal or to output the signal of the input terminal delayed by a preset second period to the second output terminal according to the levels of the first control signal terminal, the second control signal terminal, the second clock signal terminal, the first node and the second node.

[0011] In an exemplary embodiment, the shift register unit further includes: a first control subcircuit;

[0012] The first control subcircuit is electrically connected to the first clock signal terminal, the first node, and the second node, respectively, and is configured to set the level of the first node according to the levels of the second node and the first clock signal terminal.

[0013] In an exemplary embodiment, the shift register unit further includes: a second control subcircuit;

[0014] The second control subcircuit is electrically connected to the first node, the second clock signal terminal and the second voltage signal terminal respectively, and is configured to set the level of the second node according to the levels of the first node, the second clock signal terminal and the second voltage signal terminal.

[0015] In an exemplary embodiment, the shift register unit further includes: a voltage stabilizing subcircuit;

[0016] The voltage stabilizing subcircuit is electrically connected to the starting subcircuit and the dual-output subcircuit respectively, and is configured to connect or disconnect the starting subcircuit and the dual-output subcircuit.

[0017] In an exemplary embodiment, the input subcircuit includes a first transistor;

[0018] The third electrode of the first transistor is electrically connected to the first clock signal terminal; the first electrode of the first transistor is electrically connected to the first voltage signal terminal; and the second electrode of the first transistor is electrically connected to the first node.

[0019] In an exemplary embodiment, the startup subcircuit includes a second transistor, a third transistor, and a fourth transistor;

[0020] The third electrode of the second transistor is electrically connected to the first control signal terminal; the first electrode of the second transistor is electrically connected to the scan start signal terminal; the second electrode of the second transistor is electrically connected to the first electrode of the third transistor and the first electrode of the fourth transistor respectively;

[0021] The third electrode of the third transistor is electrically connected to the second control signal terminal; the second electrode of the third transistor is electrically connected to the input terminal;

[0022] The third electrode of the fourth transistor is electrically connected to the first clock signal terminal; the second electrode of the fourth transistor is electrically connected to the second node.

[0023] In an exemplary embodiment, the first control subcircuit includes a fifth transistor;

[0024] The third electrode of the fifth transistor is electrically connected to the second node; the first electrode of the fifth transistor is electrically connected to the first clock signal terminal; and the second electrode of the fifth transistor is electrically connected to the first node.

[0025] In an exemplary embodiment, the second control subcircuit includes a sixth transistor and a seventh transistor;

[0026] The third electrode of the sixth transistor is electrically connected to the first node; the first electrode of the sixth transistor is electrically connected to the second voltage signal terminal; the second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor;

[0027] The third electrode of the seventh transistor is electrically connected to the second clock signal terminal; the second electrode of the seventh transistor is electrically connected to the second node.

[0028] In an exemplary embodiment, the voltage stabilization subcircuit includes an eighth transistor;

[0029] The third electrode of the eighth transistor is electrically connected to the first voltage signal terminal; the first electrode of the eighth transistor is electrically connected to the second node; and the second electrode of the eighth transistor is electrically connected to the dual-output sub-circuit.

[0030] In an exemplary embodiment, the dual-output sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor, and a second capacitor;

[0031] The third electrode of the ninth transistor is electrically connected to the first node; the first electrode of the ninth transistor is electrically connected to the second voltage signal terminal; the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor; and the second electrode of the ninth transistor is electrically connected to the first output terminal.

[0032] The third electrode of the tenth transistor is electrically connected to the first control signal terminal; the second electrode of the tenth transistor is electrically connected to the first electrode of the thirteenth transistor;

[0033] The third electrode of the eleventh transistor is electrically connected to the first node; the first electrode of the eleventh transistor is electrically connected to the second voltage signal terminal; the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor; and the second electrode of the eleventh transistor is electrically connected to the second output terminal.

[0034] The third electrode of the twelfth transistor is electrically connected to the second control signal terminal; the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor;

[0035] The third electrode of the thirteenth transistor is electrically connected to the third electrode of the thirteenth transistor; the second electrode of the thirteenth transistor is electrically connected to the second clock signal terminal;

[0036] The first plate of the first capacitor is electrically connected to the second control signal terminal; the second plate of the first capacitor is electrically connected to the first node;

[0037] The first electrode of the second capacitor is electrically connected to the second electrode of the tenth transistor; the second electrode of the first capacitor is electrically connected to the dual-output sub-circuit.

[0038] The present disclosure further provides a shift register cascade circuit, the shift register cascade circuit comprising: a plurality of shift register sub-cascade circuits; each stage of the shift register sub-cascade circuit comprises a first shift register unit and a second shift register unit, the first shift register unit and the second shift register unit being the above-mentioned shift register units;

[0039] The second output end of the second shift register unit in the Nth stage shift register sub-cascade circuit is electrically connected to the scan start signal end of the first shift register unit in the N+1th stage shift register sub-cascade circuit; wherein N is an integer greater than or equal to 1.

[0040] In an exemplary embodiment, the input terminal of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the first output terminal of the second shift register unit in the shift register sub-cascade circuit;

[0041] The first output terminal of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the scan start signal terminal of the second shift register unit in the shift register sub-cascade circuit;

[0042] The second output end of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the input end of the second shift register unit in the shift register sub-cascade circuit.

[0043] In an exemplary embodiment, the first output terminal of the first shift register unit of the Nth stage shift register sub-cascade circuit is used as the 4N-3th output terminal of the shift register cascade circuit;

[0044] using the first output end of the second shift register unit of the Nth stage shift register sub-cascade circuit as the 4N-2th output end of the shift register cascade circuit;

[0045] using the second output end of the first shift register unit of the Nth stage shift register sub-cascade circuit as the 4N-1th output end of the shift register cascade circuit;

[0046] The second output end of the second shift register unit of the N-th stage shift register sub-cascade circuit is used as the 4Nth output end of the shift register cascade circuit.

[0047] The present disclosure also provides a driving method for a shift register unit, which is applied to the above-mentioned shift register unit.

[0048] The first clock signal terminal of the shift register unit is set to receive a first square wave signal with a preset period; the second clock signal terminal is set to receive a second square wave signal with a preset period; the first control signal terminal is set to receive a third square wave signal with a period twice the preset period; the second control signal terminal is set to receive a fourth square wave signal with a period twice the preset period; the scan start signal terminal is set to receive a pulse signal; the first square wave signal is opposite to the second square wave signal; and the third square wave signal is opposite to the fourth square wave signal.

[0049] In the first stage, the level of the first control signal terminal is set to a low level, the level of the second control signal terminal is set to a high level, the level of the first clock signal terminal is set to a low level, the level of the scan start signal terminal is set to a low level, the level of the second clock signal terminal is set to a high level, and the level of the input terminal is set to a high level; the first output terminal outputs a high level, and the second output terminal outputs a high level;

[0050] In the second stage, the level of the first control signal terminal is set to a low level, the level of the second control signal terminal is set to a high level, the level of the first clock signal terminal is set to a high level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a low level, and the level of the input terminal is set to a high level; the first output terminal outputs a low level, and the second output terminal outputs a high level;

[0051] In the third stage, the level of the first control signal terminal is set to a high level, the level of the second control signal terminal is set to a low level, the level of the first clock signal terminal is set to a low level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a high level, and the level of the input terminal is set to a low level; the first output terminal outputs a high level, and the second output terminal outputs a high level;

[0052] In the fourth stage, the level of the first control signal terminal is set to a high level, the level of the second control signal terminal is set to a low level, the level of the first clock signal terminal is set to a high level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a low level, and the level of the input terminal is set to a high level; the first output terminal outputs a high level, and the second output terminal outputs a low level.

[0053] The present disclosure provides a driving method for a shift register cascade circuit, which is applied to the above-mentioned shift register cascade circuit.

[0054] The first clock signal terminal of the first shift register unit of the shift register cascade circuit is set to be connected to a first square wave signal with a preset period; the second clock signal terminal of the first shift register unit is set to be connected to a second square wave signal with a preset period; the first clock signal terminal of the second shift register unit of the shift register cascade circuit is set to be connected to the second square wave signal; the second clock signal terminal of the second shift register unit is set to be connected to the first square wave signal; the first control signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a third square wave signal with a period twice the preset period; the second clock signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a third square wave signal with a period twice the preset period; The second control signal is set to be connected to a fourth square wave signal with a period twice the preset period; the first control signal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a fifth square wave signal with a period twice the preset period; the second control signal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a sixth square wave signal with a period twice the preset period; the scan start signal end of the first stage of the shift register sub-cascade circuit is set to be connected to a pulse signal; the first square wave signal is opposite to the second square wave signal; the third square wave signal is opposite to the fourth square wave signal; the fifth square wave signal is opposite to the sixth square wave signal; the duty cycle of the first square wave signal to the sixth square wave signal is 50%.

[0055] In an exemplary embodiment, in a first stage of a scan cycle, a level of a first control signal terminal of a first shift register unit in each stage of a shift register sub-cascade circuit is set to a low level, a level of a second control signal terminal of the first shift register unit in each stage of a shift register sub-cascade circuit is set to a high level, a level of a first control signal terminal of a second shift register unit in each stage of a shift register sub-cascade circuit is set to a high level, a level of a second control signal terminal of a second shift register unit in each stage of a shift register sub-cascade circuit is set to a low level, a level of a first clock signal terminal of the first shift register unit in each stage of a shift register sub-cascade circuit is set to a low level, a level of a second clock signal terminal of the first shift register unit in each stage of a shift register sub-cascade circuit is set to a high level; a level of a first clock signal terminal of the second shift register unit in each stage of a shift register sub-cascade circuit is set to a high level, a level of a second clock signal terminal of the second shift register unit in each stage of a shift register sub-cascade circuit is set to a low level; a level of a scan start signal terminal is set to a low level, and all output terminals of the shift register cascade circuit output a high level.

[0056] In an exemplary embodiment, in the Nth stage of the scanning cycle, according to the changes of the square wave signals, the N-1th output terminal of the shift register cascade circuit outputs a low level; and the remaining output terminals of the shift register cascade circuit output a high level.

[0057] The present disclosure provides a display panel including the above-mentioned shift register cascade circuit.

[0058] The present disclosure provides a display device including the above-mentioned display panel.

[0059] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0060] Summary of the Figures

[0061] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0062] FIG1 is a schematic structural diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0063] FIG2 is a schematic structural diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0064] FIG3 is a schematic structural diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0065] FIG4 is a timing diagram of the shift register unit shown in FIG3 ;

[0066] FIG5 is a schematic structural diagram of a shift register cascade circuit according to at least one embodiment of the present disclosure;

[0067] FIG6 is a schematic structural diagram of a shift register cascade circuit according to at least one embodiment of the present disclosure;

[0068] FIG7 is a schematic diagram of the shift register sub-cascade circuit shown in FIG3 ;

[0069] FIG8 is a timing diagram of the shift register cascade circuit shown in FIG3 .

[0070] Details

[0071] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0072] In the present disclosure, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In the present disclosure, "plurality" refers to a number of two or more.

[0073] In this disclosure, the functions of "source" and "drain" may be reversed when using transistors with opposite polarity or when the current direction changes during circuit operation. Therefore, in this disclosure, "source" and "drain" may be reversed. A "first electrode" may be a source, and a "second electrode" may be a drain. A "first electrode" may be a drain, and a "second electrode" may be a source.

[0074] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0075] In this disclosure, "electrically connected" includes components electrically connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the electrically connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0076] FIG1 is a schematic structural diagram of a shift register unit according to at least one embodiment of the present disclosure, wherein the shift register unit includes: an input subcircuit, a start subcircuit, and a dual output subcircuit;

[0077] The input sub-circuit is electrically connected to the first clock signal terminal, the first voltage signal terminal and the first node respectively, and is configured to set the level of the first node according to the levels of the first voltage signal terminal and the first clock signal terminal;

[0078] The start sub-circuit is electrically connected to the first control signal terminal, the second control signal terminal, the first clock signal terminal, the scan start signal terminal, the second node and the input terminal respectively, and is configured to set the level of the second node according to the levels of the first control signal terminal, the second control signal terminal, the scan start signal terminal and the first clock signal terminal;

[0079] The dual-output sub-circuit is electrically connected to the first control signal terminal, the second control signal terminal, the second clock signal terminal, the first node, the second node, the first output terminal and the second output terminal, respectively, and is configured to output the scanning signal of the scanning start signal terminal delayed by a preset first period to the first output terminal or to output the signal of the input terminal delayed by a preset second period to the second output terminal according to the levels of the first control signal terminal, the second control signal terminal, the second clock signal terminal, the first node and the second node.

[0080] In an exemplary embodiment, the shift register unit further includes: a first control subcircuit;

[0081] The first control subcircuit is electrically connected to the first clock signal terminal, the first node, and the second node, respectively, and is configured to set the level of the first node according to the levels of the second node and the first clock signal terminal.

[0082] In an exemplary embodiment, the shift register unit further includes: a second control subcircuit;

[0083] The second control subcircuit is electrically connected to the first node, the second clock signal terminal and the second voltage signal terminal respectively, and is configured to set the level of the second node according to the levels of the first node, the second clock signal terminal and the second voltage signal terminal.

[0084] In an exemplary embodiment, the shift register unit further includes: a voltage stabilizing subcircuit;

[0085] The voltage stabilizing subcircuit is electrically connected to the starting subcircuit and the dual-output subcircuit respectively, and is configured to connect or disconnect the starting subcircuit and the dual-output subcircuit.

[0086] In an exemplary embodiment, the input subcircuit includes a first transistor;

[0087] The third electrode of the first transistor is electrically connected to the first clock signal terminal; the first electrode of the first transistor is electrically connected to the first voltage signal terminal; and the second electrode of the first transistor is electrically connected to the first node.

[0088] In an exemplary embodiment, the startup subcircuit includes a second transistor, a third transistor, and a fourth transistor;

[0089] The third electrode of the second transistor is electrically connected to the first control signal terminal; the first electrode of the second transistor is electrically connected to the scan start signal terminal; the second electrode of the second transistor is electrically connected to the first electrode of the third transistor and the first electrode of the fourth transistor respectively;

[0090] The third electrode of the third transistor is electrically connected to the second control signal terminal; the second electrode of the third transistor is electrically connected to the input terminal;

[0091] The third electrode of the fourth transistor is electrically connected to the first clock signal terminal; the second electrode of the fourth transistor is electrically connected to the second node.

[0092] In an exemplary embodiment, the first control subcircuit includes a fifth transistor;

[0093] The third electrode of the fifth transistor is electrically connected to the second node; the first electrode of the fifth transistor is electrically connected to the first clock signal terminal; and the second electrode of the fifth transistor is electrically connected to the first node.

[0094] In an exemplary embodiment, the second control subcircuit includes a sixth transistor and a seventh transistor;

[0095] The third electrode of the sixth transistor is electrically connected to the first node; the first electrode of the sixth transistor is electrically connected to the second voltage signal terminal; the second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor;

[0096] The third electrode of the seventh transistor is electrically connected to the second clock signal terminal; the second electrode of the seventh transistor is electrically connected to the second node.

[0097] In an exemplary embodiment, the voltage stabilization subcircuit includes an eighth transistor;

[0098] The third electrode of the eighth transistor is electrically connected to the first voltage signal terminal; the first electrode of the eighth transistor is electrically connected to the second node; and the second electrode of the eighth transistor is electrically connected to the dual-output sub-circuit.

[0099] In an exemplary embodiment, the dual-output sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor, and a second capacitor;

[0100] The third electrode of the ninth transistor is electrically connected to the first node; the first electrode of the ninth transistor is electrically connected to the second voltage signal terminal; the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor; and the second electrode of the ninth transistor is electrically connected to the first output terminal.

[0101] The third electrode of the tenth transistor is electrically connected to the first control signal terminal; the second electrode of the tenth transistor is electrically connected to the first electrode of the thirteenth transistor;

[0102] The third electrode of the eleventh transistor is electrically connected to the first node; the first electrode of the eleventh transistor is electrically connected to the second voltage signal terminal; the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor; and the second electrode of the eleventh transistor is electrically connected to the second output terminal.

[0103] The third electrode of the twelfth transistor is electrically connected to the second control signal terminal; the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor;

[0104] The third electrode of the thirteenth transistor is electrically connected to the third electrode of the thirteenth transistor; the second electrode of the thirteenth transistor is electrically connected to the second clock signal terminal;

[0105] The first plate of the first capacitor is electrically connected to the second control signal terminal; the second plate of the first capacitor is electrically connected to the first node;

[0106] The first electrode of the second capacitor is electrically connected to the second electrode of the tenth transistor; the second electrode of the first capacitor is electrically connected to the dual-output sub-circuit.

[0107] The first node is a common electrical connection point of the first control subcircuit, the second control subcircuit and the dual output subcircuit; the second node is a common electrical connection point of the first control subcircuit, the second control subcircuit and the voltage stabilization subcircuit.

[0108] The shift register unit of the embodiment of the present disclosure can be electrically connected to a plurality of control signal terminals and is provided with a plurality of output terminals, thereby laying a foundation for reducing the space of the shift register circuit.

[0109] FIG2 is a schematic structural diagram of a shift register unit according to at least one embodiment of the present disclosure, wherein the shift register unit includes: an input subcircuit, a start subcircuit, a first control subcircuit, a second control subcircuit, a voltage stabilization subcircuit, and a dual output subcircuit;

[0110] The input subcircuit is electrically connected to the first clock signal terminal, the first voltage signal terminal and the first node respectively, and is configured to set the level of the first node according to the levels of the first voltage signal terminal and the first clock signal terminal;

[0111] The start sub-circuit is electrically connected to the first control signal terminal, the second control signal terminal, the first clock signal terminal, the scan start signal terminal, the second node and the input terminal respectively, and is configured to set the level of the second node according to the levels of the first control signal terminal, the second control signal terminal, the scan start signal terminal and the first clock signal terminal, or output a scan signal of the scan start signal terminal delayed by a preset first period to the input terminal;

[0112] The first control subcircuit is electrically connected to the first clock signal terminal, the first node, and the second node, respectively, and is configured to set the level of the first node according to the levels of the second node and the first clock signal terminal;

[0113] The second control subcircuit is electrically connected to the first node, the second clock signal terminal and the second voltage signal terminal respectively, and is configured to set the level of the second node according to the levels of the first node, the second clock signal terminal and the high level;

[0114] The voltage stabilizing subcircuit is electrically connected to the first node and the third node respectively, and is configured to connect or disconnect the second node and the third node;

[0115] The dual-output sub-circuit is electrically connected to the first control signal terminal, the second control signal terminal, the second clock signal, the first node, the third node, the first output terminal, and the second output terminal, respectively, and is configured to output a scan signal of the scan start signal terminal delayed by a preset first period to the first output terminal or output a signal of the input terminal delayed by a preset second period to the second output terminal according to the levels of the first control signal terminal, the second control signal terminal, the second clock signal, the first node, and the third node;

[0116] Among them, the first node is the common electrical connection point of the first control subcircuit, the second control subcircuit and the dual output subcircuit; the second node is the common electrical connection point of the first control subcircuit, the second control subcircuit and the voltage stabilization subcircuit; the third node is the common electrical connection point of the voltage stabilization subcircuit and the dual output subcircuit.

[0117] The first voltage signal terminal provides a low DC voltage signal, and the second voltage signal terminal provides a high DC voltage signal.

[0118] In one exemplary embodiment, the input subcircuit includes a first transistor;

[0119] The third electrode of the first transistor is electrically connected to the first clock signal terminal; the first electrode of the first transistor is electrically connected to the first voltage signal terminal; and the second electrode of the first transistor is electrically connected to the first node.

[0120] In an exemplary embodiment, the startup sub-circuit includes a second transistor, a third transistor, and a fourth transistor;

[0121] The third electrode of the second transistor is electrically connected to the first control signal terminal; the first electrode of the second transistor is electrically connected to the scan start signal terminal; the second electrode of the second transistor is electrically connected to the first electrode of the third transistor and the first electrode of the fourth transistor respectively;

[0122] The third electrode of the third transistor is electrically connected to the second control signal terminal; the second electrode of the third transistor is electrically connected to the input terminal;

[0123] The third electrode of the fourth transistor is electrically connected to the first clock signal terminal; the second electrode of the fourth transistor is electrically connected to the second node.

[0124] In an exemplary embodiment, the first control subcircuit includes a fifth transistor;

[0125] The third electrode of the fifth transistor is electrically connected to the second node; the first electrode of the fifth transistor is electrically connected to the first clock signal terminal; and the second electrode of the fifth transistor is electrically connected to the first node.

[0126] In an exemplary embodiment, the second control subcircuit includes a sixth transistor and a seventh transistor;

[0127] The third electrode of the sixth transistor is electrically connected to the first node; the first electrode of the sixth transistor is electrically connected to the second voltage signal terminal; the second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor;

[0128] The third electrode of the seventh transistor is electrically connected to the second clock signal terminal; the second electrode of the seventh transistor is electrically connected to the second node.

[0129] In an exemplary embodiment, the voltage regulation subcircuit includes an eighth transistor;

[0130] The third electrode of the eighth transistor is electrically connected to the first voltage signal terminal; the first electrode of the eighth transistor is electrically connected to the second node; and the second electrode of the eighth transistor is electrically connected to the third node.

[0131] In an exemplary embodiment, the dual output sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor, and a second capacitor;

[0132] The third electrode of the ninth transistor is electrically connected to the first node; the first electrode of the ninth transistor is electrically connected to the second voltage signal terminal; the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor; and the second electrode of the ninth transistor is electrically connected to the first output terminal.

[0133] The third electrode of the tenth transistor is electrically connected to the first control signal terminal; the second electrode of the tenth transistor is electrically connected to the first electrode of the thirteenth transistor;

[0134] The third electrode of the eleventh transistor is electrically connected to the first node; the first electrode of the eleventh transistor is electrically connected to the second voltage signal terminal; the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor; and the second electrode of the eleventh transistor is electrically connected to the second output terminal.

[0135] The third electrode of the twelfth transistor is electrically connected to the second control signal terminal; the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor;

[0136] The third electrode of the thirteenth transistor is electrically connected to the third node; the second electrode of the thirteenth transistor is electrically connected to the second clock signal terminal;

[0137] The first plate of the first capacitor is electrically connected to the second control signal terminal; the second plate of the first capacitor is electrically connected to the first node;

[0138] The first plate of the second capacitor is electrically connected to the second electrode of the tenth transistor; and the second plate of the second capacitor is electrically connected to the third node.

[0139] In an exemplary embodiment, the first transistor to the thirteenth transistor may be devices manufactured using a thin film transistor (TFT) process, which is the same as the manufacturing method of TFT transistors of existing active matrix liquid crystal displays.

[0140] In an exemplary embodiment, the first to thirteenth transistors may be P-type transistors, or all may be N-type transistors, or some may be P-type transistors. However, the electrical connection relationship in the shift register unit needs to be adaptively changed.

[0141] The shift register unit of the embodiment of the present disclosure can be electrically connected to a plurality of control signal terminals and is provided with a plurality of output terminals, thereby laying a foundation for reducing the space of the shift register circuit.

[0142] FIG3 is a schematic diagram of the structure of a shift register unit according to at least one embodiment of the present disclosure. As shown in FIG3 , the shift register unit includes an input subcircuit 10, a start subcircuit 20, a first control subcircuit 30, a second control subcircuit 40, a voltage regulation subcircuit 50, and a dual output subcircuit 60. The input subcircuit 10 includes a first transistor T1. A third electrode of the first transistor T1 is electrically connected to a first clock signal terminal CK; a first electrode of the first transistor T1 is electrically connected to a first voltage signal terminal VGL; and a second electrode of the first transistor T1 is electrically connected to a first node S1.

[0143] The starter subcircuit 20 includes a second transistor T2, a third transistor T3 and a fourth transistor T4; the third electrode of the second transistor T2 is electrically connected to the first control signal terminal a; the first electrode of the second transistor T2 is electrically connected to the scan start signal terminal STV; the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3 and the first electrode of the fourth transistor T4 respectively; the third electrode of the third transistor T3 is electrically connected to the second control signal terminal b; the second electrode of the third transistor T3 is electrically connected to the input terminal IN; the third electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CK; and the second electrode of the fourth transistor T4 is electrically connected to the second node S2.

[0144] The first control subcircuit 30 includes a fifth transistor T5 , a third electrode of which is electrically connected to the second node S2 , a first electrode of which is electrically connected to the first clock signal terminal CK, and a second electrode of which is electrically connected to the first node S1 .

[0145] The second control subcircuit 40 includes a sixth transistor T6 and a seventh transistor T7. A third electrode of the sixth transistor T6 is electrically connected to the first node S1; a first electrode of the sixth transistor T6 is electrically connected to the second voltage signal terminal VGH; a second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7; a third electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB; and a second electrode of the seventh transistor T7 is electrically connected to the second node S2.

[0146] The voltage stabilizing sub-circuit 50 includes an eighth transistor T8 , a third electrode of which is electrically connected to the first voltage signal terminal VGL, a first electrode of which is electrically connected to the second node S2 , and a second electrode of which is electrically connected to the third node S3 .

[0147] The dual-output sub-circuit 60 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2. The third electrode of the ninth transistor T9 is electrically connected to the first node; the first electrode of the ninth transistor T9 is electrically connected to the second voltage signal terminal VGH; the second electrode of the ninth transistor T9 is electrically connected to the first electrode of the tenth transistor T10; the second electrode of the ninth transistor T9 is electrically connected to the first output terminal OUT1; the third electrode of the tenth transistor T10 is electrically connected to the first control signal terminal a; the second electrode of the tenth transistor T10 is electrically connected to the first electrode of the thirteenth transistor T13; the third electrode of the eleventh transistor T11 is electrically connected to the first node S1; the first electrode of the eleventh transistor T11 is electrically connected to the second voltage signal terminal VGH; the second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the twelfth transistor T12 The first electrode of the 11th transistor T11 is electrically connected to the second output terminal OUT2; the third electrode of the 12th transistor T12 is electrically connected to the second control signal terminal b; the second electrode of the 12th transistor T12 is electrically connected to the first electrode of the 13th transistor T13; the third electrode of the 13th transistor T13 is electrically connected to the third node S3; the second electrode of the 13th transistor T13 is electrically connected to the second clock signal terminal CB; the first plate of the first capacitor C1 is electrically connected to the second control signal terminal b; the second plate of the first capacitor C1 is electrically connected to the first node S1; the first plate of the second capacitor C2 is electrically connected to the second electrode of the tenth transistor T10; the second plate of the first capacitor C1 is electrically connected to the third node S3.

[0148] The first transistor to the thirteenth transistor may be devices manufactured using a thin film transistor (TFT) process, which is the same as the manufacturing method of TFT transistors in existing active matrix liquid crystal displays.

[0149] The first to thirteenth transistors can be P-type transistors, or all can be N-type transistors, or some can be P-type transistors, but the electrical connection relationship in the shift register unit needs to be adaptively changed. In the embodiment of the present disclosure, all transistors are P-type as an example.

[0150] In an exemplary embodiment, the first voltage signal terminal VGL continuously provides a low-level signal, and the second voltage signal terminal VGH continuously provides a high-level signal.

[0151] The present disclosure provides a driving method for a shift register unit, which is applied to the above-mentioned shift register unit, comprising:

[0152] The first clock signal terminal of the shift register unit is set to receive a first square wave signal with a preset period; the second clock signal terminal is set to receive a second square wave signal with a preset period; the first control signal terminal is set to receive a third square wave signal with a period twice the preset period; the second control signal terminal is set to receive a fourth square wave signal with a period twice the preset period; the scan start signal terminal is set to receive a pulse signal; the first square wave signal is opposite to the second square wave signal; and the third square wave signal is opposite to the fourth square wave signal.

[0153] In the first stage, the level of the first control signal terminal is set to a low level, the level of the second control signal terminal is set to a high level, the level of the first clock signal terminal is set to a low level, the level of the scan start signal terminal is set to a low level, the level of the second clock signal terminal is set to a high level, and the level of the input terminal is set to a high level; the first output terminal outputs a high level, and the second output terminal outputs a high level;

[0154] In the second stage, the level of the first control signal terminal is set to a low level, the level of the second control signal terminal is set to a high level, the level of the first clock signal terminal is set to a high level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a low level, and the level of the input terminal is set to a high level; the first output terminal outputs a low level, and the second output terminal outputs a high level;

[0155] In the third stage, the level of the first control signal terminal is set to a high level, the level of the second control signal terminal is set to a low level, the level of the first clock signal terminal is set to a low level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a high level, and the level of the input terminal is set to a low level; the first output terminal outputs a high level, and the second output terminal outputs a high level;

[0156] In the fourth stage, the level of the first control signal terminal is set to a high level, the level of the second control signal terminal is set to a low level, the level of the first clock signal terminal is set to a high level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a low level, and the level of the input terminal is set to a high level; the first output terminal outputs a high level, and the second output terminal outputs a low level.

[0157] For example, the preset period may be 2t, and the duration of one stage is t. The duty cycle of the first square wave signal to the fourth square wave signal may be 50%. The low level duration of the pulse signal may be half the preset period.

[0158] FIG4 is a timing diagram of the shift register unit shown in FIG3. Taking the first transistor T1 to the thirteenth transistor T13 as P-type transistors as an example, as shown in FIG4, the operation process of the shift register unit provided by an exemplary embodiment includes the following stages:

[0159] In the first phase Q1, because the signal gck at the first clock signal terminal CK is low, the first transistor T1 is turned on, and the signal at the first voltage signal terminal VGL is written to the first node S1 via the first transistor T1. Because the signal at the first control signal terminal a is low, the second transistor T2 is turned on. Because the signal at the second control signal terminal b is high, the third transistor T3 is turned off. Because the signal gck at the first clock signal terminal CK is low, the fourth transistor T4 is turned on, and the GSTV signal at the scan start signal terminal STV is written to the second node S2 via the second and fourth transistors T2 and T4. The sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. At this time, the GSTV signal at the scan start signal terminal STV is low, and the level of the second node S2 is low. Because the third electrode of the eighth transistor T8 receives the low signal from the first voltage signal terminal VGL, the eighth transistor T8 is turned on. The signal at the second node S2 is written to the third node S3 via the eighth transistor T8. The low level of the third node S3 controls the conduction of the thirteenth transistor T13. The voltage level at the first node S1 controls the ninth transistor T9 to turn on. Since the signal at the first control signal terminal a is a low-level signal, the tenth transistor T10 is turned on. Since the third electrode of the eleventh transistor T11 is electrically connected to the first node S1, the eleventh transistor T11 is turned on. Since the signal at the second control signal terminal b is a high-level signal, the twelfth transistor T12 is turned off. The second voltage signal terminal VGH charges the first capacitor C1, and the second clock signal terminal CB charges the second capacitor C2. The high-level signal at the second voltage signal terminal VGH is written to the first output terminal OUT1 via the ninth transistor T9. The high-level signal at the second clock signal terminal CB is written to the first output terminal OUT1 via the turned-on thirteenth transistor T13 and tenth transistor T10. The high-level signal at the second voltage signal terminal VGH is written to the second output terminal OUT2 via the eleventh transistor T11. Consequently, the first output terminal OUT1 and the second output terminal OUT2 output high-level signals.

[0160] During the second phase Q2, the signal gck at the first clock signal terminal CK is high, the signal gcb at the second clock signal terminal CB is low, the signal at the first control signal terminal a is low, the signal at the second control signal terminal b is high, the signal GSTV at the scan start signal terminal STV is high, and the signal at the input terminal IN is high. Because the signal at the first clock signal terminal CK is high, the first transistor T1 and the fourth transistor T4 are turned off. Because the signal at the first control signal terminal a is low, the second transistor T2 and the tenth transistor T10 are turned on. Because the signal at the second control signal terminal b is high, the third transistor T3 and the twelfth transistor T12 are turned off. Because the signal at the second clock signal terminal CB is low, the seventh transistor T7 is turned on. The second plate of the second capacitor C2 maintains a low signal, the thirteenth transistor T13 is turned on, and the signal at the second clock signal terminal CB is written to the first output terminal OUT1 via the thirteenth transistor T13. The voltage level of the first plate of the second capacitor C2 is written into a low-level signal. Due to the bootstrap effect of the second capacitor C2, the eighth transistor T8 is turned off, the thirteenth transistor T13 can be turned on more effectively, and the signal at the output terminal first output terminal OUT1 is a low-level signal. Since the fourth transistor T4 is turned off, the second node S2 and the third node S3 maintain a low potential, the fifth transistor T5 is turned on, and the high-level signal of the first clock signal terminal CK is written into the first node S1 via the fifth transistor T5. As a result, the ninth transistor T9 and the eleventh transistor T11 are both turned off.

[0161] In the third phase Q3, the signal gck at the first clock signal terminal CK is a low-level signal, the signal gcb at the second clock signal terminal CB is a high-level signal, the signal at the first control signal terminal a is a high-level signal, the signal at the second control signal terminal b is a low-level signal, the signal GSTV at the scan start signal terminal STV is a high-level signal, and the level at the input terminal IN is a low-level signal. Because the signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the fourth transistor T4 are turned on, and the signal at the first voltage signal terminal VGL is written to the first node S1 via the first transistor T1. Because the signal at the second control signal terminal b is a low-level signal, the third transistor T3 and the twelfth transistor T12 are turned on. Since the low-level signal at the input terminal IN is written to the second node S2 via the turned-on third transistor T3 and fourth transistor T4, the level at the second node S2 is low. The fifth transistor T5 is turned on, and the low-level signal at the first clock signal terminal CK is transmitted to the first node S1. The level at the first node S1 is low, and the ninth transistor T9 and the eleventh transistor T11 are turned on. Because the signal at the first control signal terminal a is high, the tenth transistor T10 is turned off. The signal at the second voltage signal terminal VGH is written to the first output terminal OUT1 via the conductive ninth transistor T9, causing the first output terminal OUT1 to output a high signal. Because the signal at the second control signal terminal b is low, the twelfth transistor T12 is turned on. Because the eighth transistor T8 is turned on, the level of the third node S3 is low, causing the thirteenth transistor T13 to turn on. The signal at the second voltage signal terminal VGH is written to the second output terminal OUT2 via the conductive eleventh transistor T11, and the signal at the second clock signal terminal CB is written to the second output terminal OUT2 via the conductive thirteenth transistor T13 and the conductive twelfth transistor T12, causing the second output terminal OUT2 to output a high signal.

[0162] In the fourth phase Q4, the signal gck at the first clock signal terminal CK is high, the signal gcb at the second clock signal terminal CB is low, the signal at the first control signal terminal a is high, the signal at the second control signal terminal b is low, the signal GSTV at the scan start signal terminal STV is high, and the signal at the input terminal IN is high. Because the signal at the first clock signal terminal CK is high, the first transistor T1 and the fourth transistor T4 are turned off. The level of the third node S3 is low, and the thirteenth transistor T13 is turned on. The eighth transistor T8 is turned on, and the level of the second node S2 is low. The fifth transistor T5 is turned on, and the high level signal provided by the first clock signal terminal CK is written to the first node S1 via the turned-on fifth transistor T5. As a result, the level of the first node S1 is high, and therefore the sixth transistor T6, the ninth transistor T9, and the eleventh transistor T11 are turned off. Because the signal at the first control signal terminal a is high, the tenth transistor T10 is turned off. The low-level signal provided by the second clock signal terminal CB is written into the second output terminal OUT2 via the turned-on twelfth transistor T12 and the turned-on thirteenth transistor T13 . Therefore, the second output terminal OUT2 outputs a low-level signal.

[0163] In the fifth phase Q5, the signal gck at the first clock signal terminal CK is a low-level signal, the signal gcb at the second clock signal terminal CB is a high-level signal, the signal at the first control signal terminal a is a low-level signal, the signal at the second control signal terminal b is a high-level signal, the GSTV signal at the scan start signal terminal STV is a high-level signal, and the signal at the input terminal IN is a high-level signal. Because the signal gck at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the fourth transistor T4 are turned on. Because the signal at the first control signal terminal a is a low-level signal, the second transistor T2 and the tenth transistor T10 are turned on. Because the signal at the second control signal terminal b is a high-level signal, the third transistor T3 and the twelfth transistor T12 are turned off. The GSTV signal at the scan start signal terminal STV is written to the second node S2 via the second transistor T2 and the fourth transistor T4. The level of the second node S2 is high, so the fifth transistor T5 is turned off. Because the signal gcb at the second clock signal terminal CB is a high-level signal, the seventh transistor T7 is turned off. Since the first transistor T1 is turned on, the level of the first node S1 is low, and the ninth and eleventh transistors T9 and T11 are turned on. The eighth transistor T8 is turned on, the level of the third node S3 is high, and the thirteenth transistor T13 is turned off. The signal at the second voltage signal terminal VGH is written to the first output terminal OUT1 and the second output terminal OUT2 via the ninth and eleventh transistors T9 and T11, respectively. Therefore, the first output terminal OUT1 and the second output terminal OUT2 output high-level signals.

[0164] In the sixth phase Q6, the signal gck at the first clock signal terminal CK is high, the signal gcb at the second clock signal terminal CB is low, the signal at the first control signal terminal a is low, the signal at the second control signal terminal b is high, the signal GSTV at the scan start signal terminal STV is high, and the signal at the input terminal IN is high. Because the signal gck at the first clock signal terminal CK is high, the first transistor T1 and the fourth transistor T4 are turned off. Because the signal at the first control signal terminal a is low, the second transistor T2 and the tenth transistor T10 are turned on. Because the signal at the second control signal terminal b is high, the third transistor T3 and the twelfth transistor T12 are turned off. Because the signal gcb at the second clock signal terminal CB is low, the seventh transistor T7 is turned on. The levels of the second node S2 and the third node S3 are high, and the thirteenth transistor T13 is turned off. The level of the first node S1 is low, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 are turned on, and the high-level signal of the second voltage signal terminal VGH is written into the first output terminal OUT1 via the ninth transistor T9 and into the second output terminal OUT2 via the eleventh transistor T11. Therefore, the first output terminal OUT1 and the second output terminal OUT2 output high-level signals.

[0165] In the seventh phase Q7, the signal gck at the first clock signal terminal CK is a low-level signal, the signal gcb at the second clock signal terminal CB is a high-level signal, the signal at the first control signal terminal a is a high-level signal, the signal at the second control signal terminal b is a low-level signal, the signal GSTV at the scan start signal terminal STV is a high-level signal, and the signal at the input terminal IN is a high-level signal. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are turned on, while the second transistor T2, the fifth transistor T5, the tenth transistor T10, and the thirteenth transistor T13 are turned off. The level of the first node S1 is low, the levels of the second node S2 and the third node S3 are high, and the high-level signal of the second voltage signal terminal VGH is written to the first output terminal OUT1 via the ninth transistor T9 and to the second output terminal OUT2 via the eleventh transistor T11, respectively. Therefore, the first output terminal OUT1 and the second output terminal OUT2 output high-level signals.

[0166] In the eighth phase Q8, the signal gck at the first clock signal terminal CK is a high-level signal, the signal gcb at the second clock signal terminal CB is a low-level signal, the signal at the first control signal terminal a is a high-level signal, the signal at the second control signal terminal b is a low-level signal, the signal GSTV at the scan start signal terminal STV is a high-level signal, and the signal at the input terminal IN is a high-level signal. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the tenth transistor T10, and the thirteenth transistor T13 are turned off. The level of the first node S1 is low, the levels of the second node S2 and the third node S3 are high, and the high-level signal of the second voltage signal terminal VGH is written to the first output terminal OUT1 via the ninth transistor T9 and to the second output terminal OUT2 via the eleventh transistor T11, respectively. Therefore, the first output terminal OUT1 and the second output terminal OUT2 output high-level signals.

[0167] In the ninth phase Q9, the signal gck at the first clock signal terminal CK is a low-level signal, the signal gcb at the second clock signal terminal CB is a high-level signal, the signal at the first control signal terminal a is a low-level signal, the signal at the second control signal terminal b is a high-level signal, the signal GSTV at the scan start signal terminal STV is a high-level signal, and the signal at the input terminal IN is a high-level signal. The first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, while the third transistor T3, the fifth transistor T5, the seventh transistor T7, the twelfth transistor T12, and the thirteenth transistor T13 are turned off. The level of the first node S1 is low, the levels of the second node S2 and the third node S3 are high, and the high-level signal of the second voltage signal terminal VGH is written to the first output terminal OUT1 via the ninth transistor T9 and to the second output terminal OUT2 via the eleventh transistor T11, respectively. Therefore, the first output terminal OUT1 and the second output terminal OUT2 output high-level signals.

[0168] FIG5 is a schematic diagram of the structure of a shift register cascade circuit according to at least one embodiment of the present disclosure. As shown in FIG5 , the shift register cascade circuit includes: a plurality of shift register sub-cascade circuits; each stage of the shift register sub-cascade circuit includes a first shift register unit and a second shift register unit, and the first shift register unit and the second shift register unit are the shift register units described above;

[0169] The second output end of the second shift register unit in the Nth stage shift register sub-cascade circuit is electrically connected to the scan start signal end of the first shift register unit in the N+1th stage shift register sub-cascade circuit; wherein N is an integer greater than or equal to 1.

[0170] In an exemplary embodiment, the input terminal of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the first output terminal of the second shift register unit in the shift register sub-cascade circuit;

[0171] The first output terminal of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the scan start signal terminal of the second shift register unit in the shift register sub-cascade circuit;

[0172] The second output end of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the input end of the second shift register unit in the shift register sub-cascade circuit.

[0173] In an exemplary embodiment, the scan start signal terminal of the first shift register unit in the first shift register sub-cascade circuit is configured to receive a scan start signal;

[0174] The first control signal terminal of the first shift register unit in each stage of the shift register sub-cascade circuit is configured to receive the first control signal;

[0175] The second control signal terminal of the first shift register unit in each stage of the shift register sub-cascade circuit is configured to receive the second control signal;

[0176] The first control signal terminal of the second shift register unit in each stage of the shift register sub-cascade circuit is configured to receive a third control signal;

[0177] The second control signal terminal of the second shift register unit in each stage of the shift register sub-cascade circuit is configured to receive the fourth control signal.

[0178] In an exemplary embodiment, the first output terminal of the first shift register unit of the Nth stage shift register sub-cascade circuit is used as the 4N-3th output terminal of the shift register cascade circuit;

[0179] using the first output terminal of the second shift register unit of the Nth stage shift register sub-cascade circuit as the 4N-2th output terminal of the shift register cascade circuit;

[0180] using the second output terminal of the first shift register unit of the Nth stage shift register sub-cascade circuit as the 4N-1th output terminal of the shift register cascade circuit;

[0181] The second output end of the second shift register unit in the N-th stage shift register sub-cascade circuit is used as the 4Nth output end of the shift register cascade circuit.

[0182] By cascading multiple shift register sub-cascade circuits, the disclosed embodiment can achieve the output of two shift register cascade circuits using 13 transistors and two capacitors. Compared to a shift register cascade circuit composed of two 8T2C circuits, this reduces the number of TFT devices and two capacitor devices, thereby reducing the space required for the shift register circuit.

[0183] FIG6 is a schematic diagram of the structure of a shift register cascade circuit according to at least one embodiment of the present disclosure. The shift register cascade circuit includes multiple stages of shift register sub-cascade circuits. Each stage of the shift register sub-cascade circuit (as shown in FIG7 ) includes a first shift register unit and a second shift register unit.

[0184] For the remaining shift register sub-cascade circuits except the first-stage shift register sub-cascade circuit, the second output terminal OUT2 of the second shift register unit in the previous-stage shift register sub-cascade circuit is electrically connected to the scan enable signal terminal STV of the first shift register unit in the current-stage shift register sub-cascade circuit. The current-stage shift register sub-cascade circuit is enabled when the second output terminal OUT2 of the second shift register unit in the previous-stage shift register sub-cascade circuit is at a low level.

[0185] The scan start signal terminal STV of the first shift register unit of the first stage shift register sub-cascade circuit is set to be connected to the GSTV signal of the scan start signal terminal STV.

[0186] The input terminal IN of the first shift register unit of each stage of the shift register sub-cascade circuit is electrically connected to the first output terminal OUT1 of the second shift register unit of the shift register sub-cascade circuit of the same stage.

[0187] The first output terminal OUT1 of the first shift register unit of each stage of the shift register sub-cascade circuit is electrically connected to the scan start signal terminal STV of the second shift register unit of the same stage of the shift register sub-cascade circuit.

[0188] The second output terminal OUT2 of the first shift register unit of each stage of the shift register sub-cascade circuit is electrically connected to the input terminal IN of the second shift register unit of the shift register sub-cascade circuit of the same stage.

[0189] The first output terminal OUT1 and the second output terminal OUT2 of the first shift register unit in the first-stage shift register sub-cascade circuit serve as outputs Gout1 and Gout3 of the shift register cascade circuit, respectively. The first output terminal OUT1 and the second output terminal OUT2 of the second shift register unit in the first-stage shift register sub-cascade circuit serve as outputs Gout2 and Gout4 of the shift register cascade circuit, respectively. The first output terminal OUT1 and the second output terminal OUT2 of the first shift register unit in the second-stage shift register sub-cascade circuit serve as outputs Gout5 and Gout7 of the shift register cascade circuit, respectively. The first output terminal OUT1 and the second output terminal OUT2 of the second shift register unit in the second-stage shift register sub-cascade circuit serve as outputs Gout6 and Gout8 of the shift register cascade circuit, respectively. The first output terminal OUT1 and the second output terminal OUT2 of the first shift register unit in the (N-1)th stage shift register sub-cascade circuit serve as outputs Gout(4N-7) and Gout(4N-5) of the shift register cascade circuit, respectively. The first output terminal OUT1 and the second output terminal OUT2 of the second shift register unit in the N-1th stage shift register sub-cascade circuit serve as the outputs Gout(4N-6) and Gout(4N-4) of the shift register cascade circuit, respectively. The first output terminal OUT1 and the second output terminal OUT2 of the first shift register unit in the Nth stage shift register sub-cascade circuit serve as the outputs Gout(4N-3) and Gout(4N-1) of the shift register cascade circuit, respectively. The first output terminal OUT1 and the second output terminal OUT2 of the second shift register unit in the Nth stage shift register sub-cascade circuit serve as the outputs Gout(4N-2) and Gout(4N) of the shift register cascade circuit, respectively.

[0190] By cascading multiple shift register sub-cascade circuits, the disclosed embodiment can achieve the output of two shift register cascade circuits using 13 transistors and two capacitors. Compared to a shift register cascade circuit composed of two 8T2C circuits, this reduces the number of TFT devices and two capacitor devices, thereby reducing the space required for the shift register circuit.

[0191] The present disclosure proposes a driving method for a shift register cascade circuit, which uses the above-mentioned shift register cascade circuit, including:

[0192] The first clock signal terminal of the first shift register unit of the shift register cascade circuit is set to be connected to a first square wave signal with a preset period; the second clock signal terminal of the first shift register unit is set to be connected to a second square wave signal with a preset period; the first clock signal terminal of the second shift register unit of the shift register cascade circuit is set to be connected to the second square wave signal; the second clock signal terminal of the second shift register unit is set to be connected to the first square wave signal; the first control signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a third wave signal with a period twice the preset period; the second clock signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a third wave signal with a period twice the preset period; the second The control signal is set to be connected to a fourth square wave signal having a period twice the preset period; the first control signal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a fifth square wave signal having a period twice the preset period; the second control signal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to be connected to a sixth square wave signal having a period twice the preset period; the scan start signal terminal of the first stage of the shift register sub-cascade circuit is set to be connected to a pulse signal; the first square wave signal is opposite to the second square wave signal; the third square wave signal is opposite to the fourth square wave signal; the fifth square wave signal is opposite to the sixth square wave signal; and the duty cycle of the first to sixth square wave signals is 50%;

[0193] In the first phase Q1 of the scan cycle, the level of the first control signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a low level, the level of the second control signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a high level, the level of the first control signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a high level, the level of the second control signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a low level, the level of the first clock signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a low level, and the level of the second clock signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a high level; the level of the first clock signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a high level, and the level of the second clock signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a low level; the level of the scan start signal terminal is set to a low level, and all output terminals of the shift register cascade circuit output a high level;

[0194] In the Nth phase QN of the scanning cycle, according to the changes of the square wave signals, the N-1th output terminal of the shift register cascade circuit outputs a low level; and the remaining output terminals of the shift register cascade circuit output a high level.

[0195] The scanning period is the row scanning period of the display device. Each phase takes up half the duration of the preset period. For example, in FIG8 , the duration of the Q1 phase is half the duration of the preset period.

[0196] Figure 8 is a timing diagram of a shift register cascade circuit according to at least one embodiment of the present disclosure. As an example, taking the first transistor T1 through the thirteenth transistor T13 as P-type transistors, as shown in Figure 8 , the signal gck at the first clock signal terminal CK is a square wave signal with a period of 2t, and the signal gcb at the second clock signal terminal CB is a square wave signal with a period of 2t. The signal odd_a at the first control signal terminal a of the first shift register unit is a square wave signal with a period of 4t, the signal odd_b at the second control signal terminal b of the first shift register unit is a square wave signal with a period of 4t, the signal even_a at the first control signal terminal a of the second shift register unit is a square wave signal with a period of 4t, and the signal even_b at the second control signal terminal b of the second shift register unit is a square wave signal with a period of 4t. The high level duration of gck and gcb is 2t, and the low level duration is 2t. The high level duration of odd_a, odd_b, even_a, and even_b is 2t, and the low level duration is 2t. The high and low levels of gck and gcb are opposite. The high and low levels of odd_a and odd_b are opposite. The high and low levels of even_a and even_b are opposite. even_a has a phase delay of 1t compared to odd_a. even_b has a phase delay of 1t compared to odd_b.

[0197] An exemplary embodiment provides a shift register cascade circuit whose operation process includes the following stages:

[0198] In the first phase Q1, for the first shift register unit of the first stage shift register sub-cascade circuit:

[0199] Because the signal gck at the first clock signal terminal CK is low, the first transistor T1 is turned on, and the signal at the first voltage signal terminal VGL is written to the first node S1 via the first transistor T1. Because the signal odd_a at the first control signal terminal a is low, the second transistor T2 is turned on. Because the signal odd_b at the second control signal terminal b is high, the third transistor T3 is turned off. Because the signal gck at the first clock signal terminal CK is low, the fourth transistor T4 is turned on, and the GSTV signal at the scan start signal terminal STV is written to the second node S2 via the second and fourth transistors T2 and T4. The sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. At this time, the GSTV signal at the scan start signal terminal STV is low, and the level of the second node S2 is low. Because the third electrode of the eighth transistor T8 receives the low signal from the first voltage signal terminal VGL, the eighth transistor T8 is turned on. The signal at the second node S2 is written to the third node S3 via the eighth transistor T8. The low level of the third node S3 controls the conduction of the thirteenth transistor T13. The voltage level at the first node S1 turns on the ninth transistor T9. Since the signal at the first control signal terminal a is a low-level signal, the tenth transistor T10 turns on. Since the third electrode of the eleventh transistor T11 is electrically connected to the first node S1, T11 turns on. Since the signal gcb at the second control signal terminal b is a low-level signal, the twelfth transistor T12 turns off. The high-level signal at the second voltage signal terminal VGH is written to the first output terminal OUT1 via the ninth transistor T9, and the high-level signal at the second voltage signal terminal VGH is written to the second output terminal OUT2 via the eleventh transistor T11. Both the first output terminal OUT1 and the second output terminal OUT2 are at a high level.

[0200] For the second shift register unit of the first-stage shift register sub-cascade circuit:

[0201] The signal gcb of the first clock signal terminal CK is a high-level signal, the signal gck of the second clock signal terminal CB is a low-level signal, the signal even_a of the first control signal terminal a is a high-level signal, the signal even_b of the second control signal terminal b is a low-level signal, and the GSTV signal of the scan start signal terminal STV is a high-level signal.

[0202] Since the signal gcb at the first clock signal terminal CK is a high-level signal, the first transistor T1 and the fourth transistor T4 are turned off, and the level of the first node S1 remains low. Therefore, the sixth transistors T6, T9, and T11 are turned on. The signal VGH is written to the first output terminal OUT1 and the second output terminal OUT2 via the ninth transistor T9 and the eleventh transistor T11. The levels of the first output terminal OUT1 and the second output terminal OUT2 are high. The levels of the second node S2 and the third node S3 are also high. Because the level of the first output terminal OUT1 of the first shift register unit is high, the level of the input terminal IN of the second shift register unit is high.

[0203] In the second phase Q2, for the first shift register unit of the first stage shift register sub-cascade circuit:

[0204] The signal gck at the first clock signal terminal CK is a high-level signal, the signal gcb at the second clock signal terminal CB is a low-level signal, the signal odd_a at the first control signal terminal a is a low-level signal, the signal odd_b at the second control signal terminal b is a high-level signal, and the signal GSTV at the scan start signal terminal STV is a high-level signal. Because the signal at the first clock signal terminal CK is a high-level signal, the first transistor T1 and the fourth transistor T4 are turned off. Because the signal at the first control signal terminal a is a low-level signal, the second transistor T2 and the tenth transistor T10 are turned on. Because the signal at the second control signal terminal b is a high-level signal, the third transistor T3 and the twelfth transistor T12 are turned off. Because the signal at the second clock signal terminal CB is a low-level signal, the seventh transistor T7 is turned on. The voltage level of the second plate of the second capacitor C2 becomes the signal at the first voltage signal terminal VGL, turning on the thirteenth transistor T13, and the signal at the second clock signal terminal CB is written to the first output terminal OUT1 via the thirteenth transistor T13. Due to the bootstrap effect of the second capacitor C2, the eighth transistor T8 is turned off, the thirteenth transistor T13 can be turned on more effectively, and the signal at the first output terminal OUT1 is a low-level signal. The fifth transistor T5 is turned on, and the high-level signal at the first clock signal terminal CK is written to the first node S1 via the fifth transistor T5. As a result, the ninth transistor T9 and the eleventh transistor T11 are both turned off. Since the signal at the second clock signal terminal CB is a low-level signal, the seventh transistor T7 is turned on. Therefore, the level of the second output terminal OUT2 is high, and the level of the first output terminal OUT1 is low. Since the first output terminal OUT1 serves as Gout1 of the shift register cascade circuit, the level of Gout1 is low.

[0205] For the second shift register unit of the first-stage shift register sub-cascade circuit:

[0206] The signal gcb at the first clock signal terminal CK is a low-level signal, the signal gck at the second clock signal terminal CB is a high-level signal, the signal even_a at the first control signal terminal a is a low-level signal, and the signal even_b at the second control signal terminal b is a high-level signal. The scan start signal terminal STV is electrically connected to the second output terminal OUT2 of the first shift register unit. Therefore, the GSTV signal at the scan start signal terminal STV is a high-level signal. The first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 of the second shift register unit are turned on, and the third transistor T3, the fifth transistor T5, the twelfth transistor T12, and the thirteenth transistor T13 are turned off. The level of the first node S1 is low, the levels of the second nodes S2 and S3 are high, and the first output terminal OUT1 and the second output terminal OUT2 are high.

[0207] Since the first output terminal OUT1 of the second shift register unit serves as Gout2, Gout2 is at a high level. Since the second output terminal OUT2 of the first shift register unit serves as Gout3, Gout3 is at a high level. Since the second output terminal OUT2 of the second shift register unit serves as Gout4, Gout4 is at a high level.

[0208] In the third phase Q3, for the first shift register unit of the first stage shift register sub-cascade circuit:

[0209] The signal gck at the first clock signal terminal CK is a low-level signal, the signal gcb at the second clock signal terminal CB is a high-level signal, the signal odd_a at the first control signal terminal a is a high-level signal, the signal odd_b at the second control signal terminal b is a low-level signal, and the signal GSTV at the scan start signal terminal STV is a high-level signal. Because the signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the fourth transistor T4 are turned on, and the signal at the first voltage signal terminal VGL is written to the first node S1 via the first transistor T1. Because the signal at the second control signal terminal b is a low-level signal, the third transistor T3 and the twelfth transistor T12 are turned on. The level of the first node S1 is low, and the ninth transistor T9 and the eleventh transistor T11 are turned on. Because the signal at the first control signal terminal a is a high-level signal, the tenth transistor T10 is turned off. The level of the first output terminal OUT1 is high. Because the signal at the second control signal terminal b is a low-level signal, the twelfth transistor T12 is turned on. The thirteenth transistor T13 is turned on, and the level of the second output terminal OUT2 is high. Since the eighth transistor T8 is turned on, the levels of the second node S2 and the third node S3 are low.

[0210] For the second shift register unit of the first-stage shift register sub-cascade circuit:

[0211] The signal gcb at the first clock signal terminal CK is a high-level signal, the signal gck at the second clock signal terminal CB is a low-level signal, the signal even_a at the first control signal terminal a is a low-level signal, and the signal even_b at the second control signal terminal b is a high-level signal. The second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the twelfth transistor T12 are turned off, the level of the first node S1 is low, the levels of the second node S2 and the third node S3 are high, the first output terminal OUT1 is high, and the second output terminal OUT2 is high.

[0212] Since the first output terminal OUT1 of the first shift register unit of the first-stage shift register sub-cascade circuit serves as Gout1 of the shift register cascade circuit, the level of Gout1 is a high level.

[0213] Since the first output terminal OUT1 of the second shift register unit serves as Gout2, Gout2 is at a low level.

[0214] Since the second output terminal OUT2 of the first shift register unit serves as Gout3, Gout3 is at a high level.

[0215] Since the second output terminal OUT2 of the second shift register unit serves as Gout4, Gout4 is at a high level.

[0216] In the fourth phase Q4, for the first shift register unit of the first stage shift register sub-cascade circuit:

[0217] The signal gck at the first clock signal terminal CK is high, the signal gcb at the second clock signal terminal CB is low, the signal odd_a at the first control signal terminal a is high, the signal odd_b at the second control signal terminal b is low, and the signal GSTV at the scan start signal terminal STV is high. Because the signal at the first clock signal terminal CK is high, the first transistor T1 and the fourth transistor T4 are turned off. The level of the third node S3 is low, and the thirteenth transistor T13 is turned on. The eighth transistor T8 is turned on, and the level of the second node S2 is low. The fifth transistor T5 is turned on, and the level of the first node S1 is high. Therefore, the sixth transistor T6, the ninth transistor T9, and the eleventh transistor T11 are turned off. Because the signal at the first control signal terminal a is high, the tenth transistor T10 is turned off. The signal at the second clock signal terminal CB is written to the second output terminal OUT2 via the twelfth transistor T12 and the thirteenth transistor T13. The level of the second output terminal OUT2 is low. The level of the first output terminal OUT1 is high.

[0218] For the second shift register unit of the first-stage shift register sub-cascade circuit:

[0219] The signal gcb at the first clock signal terminal CK is a low-level signal, the signal gck at the second clock signal terminal CB is a high-level signal, the signal even_a at the first control signal terminal a is a high-level signal, and the signal even_b at the second control signal terminal b is a low-level signal. The level of the scan start signal terminal STV is a high-level signal. The first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned on, and the second transistor T2, the seventh transistor T7, and the tenth transistor T10 are turned off. The first node S1 is a low-level signal, the second node S2 and the third node S3 are low-level signals, and the levels of the first output terminal OUT1 and the second output terminal OUT2 are high-level signals.

[0220] Since the first output terminal OUT1 of the first shift register unit of the first-stage shift register sub-cascade circuit serves as Gout1 of the shift register cascade circuit, the level of Gout1 is a high level.

[0221] Since the first output terminal OUT1 of the second shift register unit serves as Gout2 of the shift register cascade circuit, Gout2 is at a high level.

[0222] Since the second output terminal OUT2 of the first shift register unit serves as Gout3 of the shift register cascade circuit, Gout3 is at a low level.

[0223] Since the second output terminal OUT2 of the second shift register unit serves as Gout4 of the shift register cascade circuit, Gout4 is at a high level.

[0224] In the fifth stage Q5, for the first shift register unit of the first stage shift register sub-cascade circuit:

[0225] The signal gck at the first clock signal terminal CK is a low-level signal, the signal gcb at the second clock signal terminal CB is a high-level signal, the signal odd_a at the first control signal terminal a is a low-level signal, the signal odd_b at the second control signal terminal b is a high-level signal, and the GSTV signal at the scan start signal terminal STV is a high-level signal. Because the signal gck at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the fourth transistor T4 are turned on. Because the signal at the first control signal terminal a is a low-level signal, the second transistor T2 and the tenth transistor T10 are turned on. Because the signal at the second control signal terminal b is a high-level signal, the third transistor T3 and the twelfth transistor T12 are turned off. The GSTV signal at the scan start signal terminal STV is written to the second node S2 via the second transistor T2 and the fourth transistor T4. The level of the second node S2 is high, so the fifth transistor T5 is turned off. Because the signal gcb at the second clock signal terminal CB is a high-level signal, the seventh transistor T7 is turned off. Since the first transistor T1 is turned on, the level of the first node S1 is low, and the ninth and eleventh transistors T9 and T11 are turned on. The eighth transistor T8 is turned on, the level of the third node S3 is high, and the thirteenth transistor T13 is turned off. The signal at the second voltage signal terminal VGH is written to the first output terminal OUT1 and the second output terminal OUT2 via the ninth and eleventh transistors T9 and T11, respectively. Therefore, the levels of the first and second output terminals OUT1 and OUT2 are high.

[0226] For the second shift register unit of the first-stage shift register sub-cascade circuit:

[0227] The signal gcb at the first clock signal terminal CK is a high-level signal, the signal gck at the second clock signal terminal CB is a low-level signal, the signal even_a at the first control signal terminal a is a high-level signal, and the signal even_b at the second control signal terminal b is a low-level signal. The GSTV signal at the scan start signal terminal STV is a high-level signal. The third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned off. The first node S1 is a high-level signal, the second node S2 and the third node S3 are low-level signals, the first output terminal OUT1 is a high-level signal, and the second output terminal OUT2 is a low-level signal.

[0228] Since the first output terminal OUT1 of the first shift register unit of the first-stage shift register sub-cascade circuit serves as Gout1 of the shift register cascade circuit, the level of Gout1 is a high level.

[0229] Since the first output terminal OUT1 of the second shift register unit serves as Gout2, Gout2 is at a high level.

[0230] Since the second output terminal OUT2 of the first shift register unit serves as Gout3, Gout3 is at a high level.

[0231] Since the second output terminal OUT2 of the second shift register unit serves as Gout4, Gout4 is at a low level.

[0232] In the sixth phase Q6 , the levels of the first output terminal OUT1 and the second output terminal OUT2 of the first shift register unit and the second shift register unit of the first stage shift register sub-cascade circuit are both high.

[0233] For the first shift register unit of the second-stage shift register sub-cascade circuit:

[0234] The signal gck at the first clock signal terminal CK is a high-level signal, the signal gcb at the second clock signal terminal CB is a low-level signal, the signal odd_a at the first control signal terminal a is a low-level signal, the signal odd_b at the second control signal terminal b is a high-level signal, and the signal at the scan start signal terminal STV, which is the second output terminal OUT2 of the second shift register unit of the first-stage shift register sub-cascade circuit, is a high-level signal during the period t6-t7. The signal GSTV at the scan start signal terminal STV is a high-level signal. Because the signal gck at the first clock signal terminal CK is a high-level signal, the first transistor T1 and the fourth transistor T4 are turned off. Because the signal at the first control signal terminal a is a low-level signal, the second transistor T2 and the tenth transistor T10 are turned on. Because the signal at the second control signal terminal b is a high-level signal, the third transistor T3 and the twelfth transistor T12 are turned off. The fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13 are turned on, and the ninth transistor T9 and the eleventh transistor T11 are turned off. The first output terminal OUT1 of the first shift register unit is a low-level signal, and the second output terminal OUT2 is a high-level signal.

[0235] For the second shift register unit of the second-stage shift register sub-cascade circuit:

[0236] The signal gcb at the first clock signal terminal CK is a low-level signal, the signal gck at the second clock signal terminal CB is a high-level signal, the signal even_a at the first control signal terminal a is a high-level signal, the signal even_b at the second control signal terminal b is a low-level signal, the GSTV signal at the scan start signal terminal STV is a low-level signal, the second transistor T2, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, and the thirteenth transistor T13 are turned off, and the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are turned on. The first node S1 is at a low level, the levels of the second node S2 and the third node S3 are at a high level, and the levels of the first output terminal OUT1 and the second output terminal OUT2 of the second shift register unit are at a high level.

[0237] Since the first output terminal OUT1 of the first shift register unit of the first-stage shift register sub-cascade circuit serves as Gout1 of the shift register cascade circuit, the level of Gout1 is a high level.

[0238] Since the first output terminal OUT1 of the second shift register unit serves as Gout2, Gout2 is at a high level.

[0239] Since the second output terminal OUT2 of the first shift register unit serves as Gout3, Gout3 is at a high level.

[0240] Since the second output terminal OUT2 of the second shift register unit serves as Gout4, Gout4 is at a high level.

[0241] The first output terminal OUT1 of the first shift register unit of the second-stage shift register sub-cascade circuit serves as Gout5 of the shift register cascade circuit. Therefore, the level of Gout5 is low.

[0242] The outputs of other stages can be obtained according to the timing diagram shown in FIG8 , which will not be described in detail here.

[0243] By cascading multiple shift register sub-cascade circuits, the disclosed embodiment can achieve the output of two shift register cascade circuits using 13 transistors and two capacitors. Compared to a shift register cascade circuit composed of two 8T2C circuits, this reduces the number of TFT devices and two capacitor devices, thereby reducing the space required for the shift register circuit.

[0244] The embodiment of the present disclosure discloses a display panel, including the above-mentioned shift register cascade circuit.

[0245] An embodiment of the present disclosure discloses a display device, including the above-mentioned display panel.

[0246] For example, the display device here can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0247] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to general designs. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0248] It should be understood by those skilled in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A shift register unit, comprising: an input subcircuit, a starter subcircuit, and a dual output subcircuit; The input subcircuit is electrically connected to the first clock signal terminal, the first voltage signal terminal and the first node respectively, and is configured to set the level of the first node according to the levels of the first voltage signal terminal and the first clock signal terminal; The start subcircuit is electrically connected to the first control signal terminal, the second control signal terminal, the first clock signal terminal, the scan start signal terminal, the second node and the input terminal respectively, and is configured to set the level of the second node according to the levels of the first control signal terminal, the second control signal terminal, the scan start signal terminal and the first clock signal terminal; The dual output sub-circuit is electrically connected to the first control signal terminal, the second control signal terminal, the second clock signal terminal, the first node, the second node, the first output terminal and the second output terminal, respectively, and is configured to output a scanning signal of the scanning start signal terminal delayed by a preset first period to the first output terminal or to output a signal of the input terminal delayed by a preset second period to the second output terminal according to the levels of the first control signal terminal, the second control signal terminal, the second clock signal terminal, the first node and the second node.

2. The shift register unit according to claim 1, further comprising: a first control subcircuit; The first control subcircuit is electrically connected to the first clock signal terminal, the first node and the second node respectively, and is configured to set the level of the first node according to the levels of the second node and the first clock signal terminal.

3. The shift register unit according to claim 1, further comprising: a second control subcircuit; The second control subcircuit is electrically connected to the first node, the second clock signal terminal and the second voltage signal terminal respectively, and is configured to set the level of the second node according to the levels of the first node, the second clock signal terminal and the second voltage signal terminal.

4. The shift register unit according to claim 1, further comprising: Voltage stabilization subcircuit; The voltage stabilizing subcircuit is electrically connected to the starting subcircuit and the dual output subcircuit respectively, and is configured to connect or disconnect the starting subcircuit and the dual output subcircuit.

5. The shift register unit according to claim 1, wherein: The input subcircuit includes a first transistor; The third electrode of the first transistor is electrically connected to the first clock signal terminal; the first electrode of the first transistor is electrically connected to the first voltage signal terminal; and the second electrode of the first transistor is electrically connected to the first node.

6. The shift register unit according to claim 1, wherein: The starter subcircuit includes a second transistor, a third transistor and a fourth transistor; The third electrode of the second transistor is electrically connected to the first control signal terminal; the first electrode of the second transistor is electrically connected to the scan start signal terminal; the second electrode of the second transistor is electrically connected to the first electrode of the third transistor and the first electrode of the fourth transistor respectively; The third electrode of the third transistor is electrically connected to the second control signal terminal; the second electrode of the third transistor is electrically connected to the input terminal; The third electrode of the fourth transistor is electrically connected to the first clock signal terminal; the second electrode of the fourth transistor is electrically connected to the second node.

7. The shift register unit according to claim 2, wherein: The first control subcircuit includes a fifth transistor; The third electrode of the fifth transistor is electrically connected to the second node; the first electrode of the fifth transistor is electrically connected to the first clock signal terminal; and the second electrode of the fifth transistor is electrically connected to the first node.

8. The shift register unit according to claim 3, characterized in that: The second control subcircuit includes a sixth transistor and a seventh transistor; The third electrode of the sixth transistor is electrically connected to the first node; the first electrode of the sixth transistor is electrically connected to the second voltage signal terminal; the second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor; The third electrode of the seventh transistor is electrically connected to the second clock signal terminal; the second electrode of the seventh transistor is electrically connected to the second node.

9. The shift register unit according to claim 1, wherein: The dual output sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor and a second capacitor; A third electrode of the ninth transistor is electrically connected to the first node; The first electrode of the ninth transistor is electrically connected to the second voltage signal terminal; the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor; the second electrode of the ninth transistor is electrically connected to the first output terminal; The third electrode of the tenth transistor is electrically connected to the first control signal terminal; the second electrode of the tenth transistor is electrically connected to the first electrode of the thirteenth transistor; The third electrode of the eleventh transistor is electrically connected to the first node; the first electrode of the eleventh transistor is electrically connected to the second voltage signal terminal; the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor; the second electrode of the eleventh transistor is electrically connected to the second output terminal; The third electrode of the twelfth transistor is electrically connected to the second control signal terminal; the second An electrode is electrically connected to the first electrode of the thirteenth transistor; The second electrode of the thirteenth transistor is electrically connected to the second clock signal terminal; The first plate of the first capacitor is electrically connected to the second control signal terminal; the second plate of the first capacitor is electrically connected to the first node; The first electrode of the second capacitor is electrically connected to the second electrode of the tenth transistor; the second electrode of the first capacitor is electrically connected to the dual-output sub-circuit.

10. The shift register unit according to claim 4, wherein: The voltage stabilization subcircuit includes an eighth transistor; The third electrode of the eighth transistor is electrically connected to the first voltage signal terminal; the first electrode of the eighth transistor is electrically connected to the second node; and the second electrode of the eighth transistor is electrically connected to the dual output sub-circuit.

11. A shift register cascade circuit, the shift register cascade circuit comprising: A plurality of shift register sub-cascade circuits; each stage of the shift register sub-cascade circuit comprises a first shift register unit and a second shift register unit, wherein the first shift register unit and the second shift register unit are the shift register units according to any one of claims 1 to 10; The second output end of the second shift register unit of the Nth shift register sub-cascade circuit is electrically connected to the scan start signal end of the first shift register unit of the N+1th shift register sub-cascade circuit; wherein N is an integer greater than or equal to 1.

12. The shift register cascade circuit as claimed in claim 11, wherein: The input end of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the first output end of the second shift register unit in the shift register sub-cascade circuit; The first output terminal of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the scan start signal terminal of the second shift register unit in the shift register sub-cascade circuit; The second output end of the first shift register unit in each stage of the shift register sub-cascade circuit is electrically connected to the input end of the second shift register unit in the shift register sub-cascade circuit.

13. The shift register cascade circuit as claimed in claim 12, wherein: Using the first output end of the first shift register unit of the Nth stage shift register sub-cascade circuit as the 4N-3th output end of the shift register cascade circuit; The first output terminal of the second shift register unit of the N-th stage shift register sub-cascade circuit is used as the shift The 4N-2th output terminal of the register cascade circuit; Using the second output end of the first shift register unit of the Nth stage shift register sub-cascade circuit as the 4N-1th output end of the shift register cascade circuit; The second output end of the second shift register unit of the Nth stage shift register sub-cascade circuit is used as the 4Nth output end of the shift register cascade circuit.

14. A driving method of a shift register unit, applied to the shift register unit according to claims 1 to 10, comprising: The first clock signal terminal of the shift register unit is configured to receive a first square wave signal with a preset period; The second clock signal terminal is set to access a second square wave signal with a preset period; the first control signal terminal is set to access a third square wave signal with a period twice the preset period; the second control signal terminal is set to access a fourth square wave signal with a period twice the preset period; the scan start signal terminal is set to access a pulse signal; the first square wave signal is opposite to the second square wave signal; the third square wave signal is opposite to the fourth square wave signal; In the first stage, the level of the first control signal terminal is set to a low level, the level of the second control signal terminal is set to a high level, the level of the first clock signal terminal is set to a low level, the level of the scan start signal terminal is set to a low level, the level of the second clock signal terminal is set to a high level, and the level of the input terminal is set to a high level; the first output terminal outputs a high level, and the second output terminal outputs a high level; In the second stage, the level of the first control signal terminal is set to a low level, the level of the second control signal terminal is set to a high level, the level of the first clock signal terminal is set to a high level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a low level, and the level of the input terminal is set to a high level; the first output terminal outputs a low level, and the second output terminal outputs a high level; In the third stage, the level of the first control signal terminal is set to a high level, the level of the second control signal terminal is set to a low level, the level of the first clock signal terminal is set to a low level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a high level, and the level of the input terminal is set to a low level; the first output terminal outputs a high level, and the second output terminal outputs a high level; In the fourth stage, the level of the first control signal terminal is set to a high level, the level of the second control signal terminal is set to a low level, the level of the first clock signal terminal is set to a high level, the level of the scan start signal terminal is set to a high level, the level of the second clock signal terminal is set to a low level, and the level of the input terminal is set to a high level; the first output terminal outputs a high level, and the second output terminal outputs a low level.

15. A driving method of a shift register cascade circuit, applied to the shift register cascade circuit according to claims 11 to 13, comprising: The first clock signal terminal of the first shift register unit of the shift register cascade circuit is set to be connected to a first square wave signal with a preset period; the second clock signal terminal of the first shift register unit is set to be connected to a first square wave signal with a preset period; Assume a second square wave signal with a period; the first clock signal end of the second shift register unit of the shift register cascade circuit is set to access the second square wave signal; the second clock signal end of the second shift register unit is set to access the first square wave signal; the first control signal end of the first shift register unit of each stage of the shift register sub-cascade circuit is set to access a third square wave signal with a period twice the preset period; the second control signal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to access a fourth square wave signal with a period twice the preset period; the first control signal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to access a fifth square wave signal with a period twice the preset period; the second control signal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to access a sixth square wave signal with a period twice the preset period; the scan start signal end of the first stage of the shift register sub-cascade circuit is set to access a pulse signal; the first square wave signal is opposite to the second square wave signal; the third square wave signal is opposite to the fourth square wave signal; the fifth square wave signal is opposite to the sixth square wave signal; the duty cycle of the first square wave signal to the sixth square wave signal is 50%.

16. The driving method of the shift register cascade circuit according to claim 15, further comprising: In the first stage of the scanning cycle, the level of the first control signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a low level, the level of the second control signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a high level, the level of the first control signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a high level, the level of the second control signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a low level, the level of the first clock signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a low level, and the level of the second clock signal terminal of the first shift register unit of each stage of the shift register sub-cascade circuit is set to a high level; the level of the first clock signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a high level, and the level of the second clock signal terminal of the second shift register unit of each stage of the shift register sub-cascade circuit is set to a low level; the level of the scan start signal terminal is set to a low level, and all output terminals of the shift register cascade circuit output a high level.

17. The driving method of the shift register cascade circuit according to claim 16, further comprising: In the Nth stage of the scanning cycle, according to the changes of the square wave signals, the N-1th output terminal of the shift register cascade circuit outputs a low level; The remaining output terminals of the shift register cascade circuit output high level.

18. A display panel comprising the shift register cascade circuit according to any one of claims 11 to 13.

19. A display device comprising the display panel according to claim 18.

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