Opto-electro-mechanical control system for arrayed digital lithography machine

Abstract

An opto-electro-mechanical control system for an arrayed digital lithography machine, and an arrayed digital lithography machine, which relate to the technical field of lithography machines. The opto-electro-mechanical control system comprises a master control FPGA (10) and a plurality of slave control FPGAs (20), wherein the master control FPGA (10) is used for communicating with a workstation and each slave control FPGA (20), forwarding to each slave control FPGA (20) an exposure instruction data message sent by the workstation, and controlling each slave control FPGA (20) to execute a parallel exposure task; and each slave control FPGA (20) is used for executing the parallel exposure task on the basis of the exposure instruction data message; and each slave control FPGA (20) independently controls c×c×m paths of laser light, and c×c×m×p≥N×N, c×c representing a logic array, m being the number of layers, p being the number of slave control FPGAs (20), and N×N representing the size of an optical fiber area array. By using the opto-electro-mechanical control system, the lithography efficiency of a maskless lithography machine can be effectively improved.

Description

An optomechanical control system for arrayed digital lithography machines

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on July 26, 2023, with application number 202310929492.1 and invention name “A photomechanical control system for arrayed digital lithography machines”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of lithography machines, and in particular to an optomechanical control system for an arrayed digital lithography machine and an arrayed digital lithography machine. Background Art

[0003] Photolithography is the most critical step in chip manufacturing. Photolithography is the process of "printing" a pre-designed circuit pattern on the wafer placed on it by moving the worktable with nanometer-level precision to perform field-by-field exposure. Traditional photolithography technology has high photolithography accuracy, but the mask manufacturing cost is high, the cycle is long, and the flexibility is poor. It is not suitable for large-scale production, and it is difficult to improve the photolithography resolution as the device feature size decreases. Therefore, maskless digital lithography technology that does not require a physical mask is becoming increasingly popular. Commonly used maskless digital lithography technologies include electron beam lithography, focused ion beam lithography, interference lithography, laser direct writing technology, and digital lithography technology based on digital micro-mirror devices (DMD). Due to the extremely low chip manufacturing efficiency of current maskless lithography machines, chip manufacturing still mostly uses masked lithography technology.

[0004] Micro-Electro-Mechanical Systems (MEMS) are devices that integrate multiple functions such as optomechanical, biological, and chemical. They are widely used in the automotive, medical, Internet of Things, artificial intelligence and other fields, and are becoming an important source of emerging industries. At present, MEMS generally uses traditional lithography machines, which face the problems of long time consumption, high cost, and low efficiency. Therefore, under the premise that factors such as resolution, consistency, uniformity, smoothness, and cost can be controlled, accelerating the improvement of the lithography efficiency of maskless lithography machines to meet the application requirements of MEMS with multiple categories, small batches, rapid production, and flexible changes has become a technical problem that needs to be solved urgently by those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide an optomechanical control system for an arrayed digital lithography machine, which can effectively improve the lithography efficiency of a maskless lithography machine. Another purpose of this application is to provide an arrayed digital lithography machine, which also has the above technical effects.

[0007] To solve the above technical problems, the present application provides an optomechanical control system for an arrayed digital lithography machine, comprising:

[0008] Master FPGA and multiple slave FPGAs;

[0009] The master FPGA is used to communicate with the workstation and each of the slave FPGAs, forward the exposure instruction data message sent by the workstation to the slave FPGAs, and control the slave FPGAs to perform parallel exposure tasks;

[0010] The slave control FPGA is used to perform parallel exposure tasks according to exposure instruction data; wherein, each slave control FPGA independently controls c×c×m lasers, and c×c×m×p≥N×N; c×c represents a logic array, m is the number of layers, p is the number of the slave control FPGAs, and N×N represents the size of the fiber array.

[0011] Optionally, the slave FPGA is specifically used for:

[0012] According to the exposure instruction data, c×c×m PWM square waves are modulated to control the constant current source array to output c×c×m analog current signals in parallel, so as to control the exposure time of the laser through the analog current signals.

[0013] Optionally, the master FPGA forwards the exposure instruction data message to the slave FPGA via an SPI bus.

[0014] Optionally, the master FPGA controls the slave FPGAs through GPIO pins to execute parallel exposure tasks.

[0015] Optionally, the master control FPGA is further used to:

[0016] Control the movement of the workpiece stage; wherein, the workpiece stage includes a coarse movement stage and a fine movement stage; the main control FPGA enables the motor driver to drive the fine movement stage to move by sending a fine movement stage movement message to the motor driver, and enables the motor driver to drive the coarse movement stage to move by sending a coarse movement stage movement message to the motor driver.

[0017] Optionally, the master control FPGA is further used to:

[0018] Receive the motion feedback message sent by the motor driver.

[0019] Optionally, the main control FPGA is further used to receive a command message sent by the workstation, and determine whether to initialize and whether to control the movement of the workpiece stage according to the command message.

[0020] Optionally, the master control FPGA is further used to:

[0021] Send a request or feedback message to the workstation.

[0022] Optionally, data packets between the master FPGA and the workstation are transmitted based on the UDP protocol.

[0023] In order to solve the above technical problems, the present application also provides an arrayed digital lithography machine, which includes the optomechanical control system for the arrayed digital lithography machine as described above.

[0024] The optomechanical control system for an arrayed digital lithography machine provided in the present application includes: a master FPGA and multiple slave FPGAs; the master FPGA is used to communicate with a workstation and each of the slave FPGAs, forward the exposure instruction data message sent by the workstation to the slave FPGA, and control the slave FPGA to perform parallel exposure tasks; the slave FPGA is used to perform parallel exposure tasks according to the exposure instruction data; wherein each of the slave FPGAs independently controls c×c×m lasers, and c×c×m×p≥N×N; c×c represents a logic array, m is the number of layers, p is the number of the slave FPGAs, and N×N represents the size of the fiber array.

[0025] It can be seen that the optomechanical control system for arrayed digital lithography machines provided in this application adopts a master-slave collaborative control method, and completes parallel exposure tasks through the collaboration of the master FPGA and each slave FPGA, which can realize the control of c×c×m×p lasers, and can effectively improve the lithography efficiency of maskless lithography machines, meet the application requirements of MEMS with multiple categories, small batches, rapid production, and flexible and changeable, and can effectively solve the problems of high concurrency and limited GPIO pins, and has high stability, reliability and scalability.

[0026] The arrayed digital lithography machine provided in this application also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] FIG1 is a schematic diagram of an optomechanical control system for an arrayed digital lithography machine provided in an embodiment of the present application;

[0029] FIG2 is a system block diagram of an arrayed digital lithography machine provided in an embodiment of the present application;

[0030] FIG3 is a schematic diagram of a master-slave collaborative control solution provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The core of this application is to provide an optomechanical control system for arrayed digital lithography machines, which can effectively improve the lithography efficiency of maskless lithography machines. Another core of this application is to provide an arrayed digital lithography machine, which also has the above-mentioned technical effects.

[0032] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] Please refer to FIG1 , which is a schematic diagram of an optomechanical control system for an arrayed digital lithography machine provided in an embodiment of the present application. As shown in FIG1 , the optomechanical control system includes:

[0034] A master FPGA 10 and multiple slave FPGAs 20;

[0035] The master FPGA 10 is used to communicate with the workstation and each of the slave FPGAs 20, forward the exposure instruction data message sent by the workstation to the slave FPGAs 20, and control the slave FPGAs 20 to perform parallel exposure tasks;

[0036] The slave control FPGA20 is used to perform parallel exposure tasks according to the exposure instruction data; wherein, each slave control FPGA20 independently controls c×c×m lasers, and c×c×m×p≥N×N; c×c represents a logic array, m is the number of layers, p is the number of the slave control FPGA20, and N×N represents the size of the fiber array.

[0037] Traditional laser direct writing technology is a maskless lithography technology that uses a single-channel power-adjustable laser beam to perform variable-dose exposure on the resist material on the substrate surface. After development, the required pattern is formed on the surface of the resist layer. The single-chip writing time of laser direct writing technology is long and is not suitable for large-scale production. Given that laser direct writing technology has a high resolution, this embodiment integrates and designs a fiber laser array (N×N fiber array) to improve the efficiency of lithography processing by parallel direct writing. Compared with multi-electron beams and DMD micromirror arrays, it can further improve controllability, resolution, beam spot density, exposure efficiency, etc.

[0038] As shown in Figure 2, an arrayed digital lithography system includes a workpiece stage, an optical system, an optomechanical control system, and a workstation. The workpiece stage utilizes a stacked structure consisting of a coarse and fine motion stage. The coarse motion stage is used for stepping motion over large strokes. The fine motion stage is used for high-precision scanning over short strokes and can compensate for positioning errors of the coarse motion stage in real time.

[0039] The optical system includes an array light source, a fiber array, and a microlens array. To produce high-precision, dense, arrayed spot images, this embodiment integrates multiple single-channel laser light sources to form an array light source. The multiple laser beams output by the array light source system are concentrated into a smaller area to form a fiber array. The microlens array focuses and homogenizes the laser beams output by the fiber array. The workstation provides functions such as die layout design, layout data conversion, system control, and database management.

[0040] The optomechanical control system controls the workpiece stage and array light source. Key performance indicators for workpiece stage control include motion accuracy, positioning stability duration, and overlay accuracy. Array light source control primarily involves optical switching array on / off, energy regulation, and exposure duration.

[0041] For an N×N fiber array, when N is large, the concurrency is higher and the lithography efficiency is higher, but the GPIO pins on the controller used to control the optical switch array will be insufficient. Therefore, the optomechanical control system in this embodiment adopts a master-slave collaborative control design, which can better resolve the contradiction between high concurrency and limited GPIO pins, and has high stability, reliability, and scalability.

[0042] Specifically, the optomechanical control system in this embodiment includes a master FPGA 10 and multiple slave FPGAs 20. An FPGA (Field Programmable Gate Array) is a semi-custom digital integrated circuit featuring high real-time performance, strong parallel processing capabilities, and considerable flexibility. The master FPGA 10 is primarily used for real-time communication with the workstation and the slave FPGAs 20. It receives exposure command data messages from the workstation, forwards these messages to the slave FPGAs 20, and controls the execution of parallel exposure tasks by the slave FPGAs 20.

[0043] In some embodiments, data packets between the master FPGA 10 and the workstation are transmitted based on the UDP protocol.

[0044] Specifically, a Gigabit Ethernet interface can be used between the workstation and the master FPGA 10, supporting communication rates of 10 Mbps, 100 Mbps, and 1000 Mbps in full-duplex mode. Data packets between the workstation and the master FPGA 10 are transmitted using the User Datagram Protocol (UDP), with CRC32 checksums used for data frame verification. Ethernet technology utilizes the IEEE 802.3 standard, and data packet transmission follows the Ethernet MAC layer frame format. The Ethernet UDP transmission packet format can be defined as shown in Table 1, with a total packet length not exceeding 1526 bytes.

[0045] Table 1

[0046] In Table 1, the default preamble is 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55. The default Start Frame Delimiter (SFD) is 0xD5. The destination MAC address, which is the MAC address of the receiving end, occupies 6 bytes and includes three types: unicast address, multicast address, and broadcast address. A unicast address is used to identify a unique device, and the least significant bit of the first byte of the data segment is 0, such as 0x00, 0x00, 0x00, 0x11, 0x11, 0x11. A multicast address is used to identify multiple devices belonging to the same group, and the least significant bit of the first byte of the data segment is 1, such as 0x01, 0x00, 0x00, 0x11, 0x11, 0x11. A broadcast address is used to identify all devices on the same network segment and defaults to 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF. The source MAC address is the MAC address of the sender and occupies 6 bytes. Length: When the value of these two bytes is less than 0x0600, it represents the length of the data segment; otherwise, it indicates the protocol. For example, 0x0800 represents the IP protocol (Internet Protocol), 0x0806 represents the ARP protocol (Address Resolution Protocol), etc. Data: The minimum length of the data segment is 46 bytes and the maximum does not exceed 1500 bytes. Among them, the 46 bytes include a 20-byte IP header, an 8-byte UDP header, 18 bytes of padding data (generally all 0s), and the rest is custom data. CRC check: A 4-byte CRC-32 checksum is added to the end of the data to detect whether there are any transmission errors in the data. Based on the above-mentioned Ethernet UDP transmission data packet format, user data messages can be formulated in the custom part of the data segment.

[0047] The exposure instruction data message sent by the workstation can be defined as shown in Table 2, and the message length is 1409 bytes.

[0048] Table 2

[0049] The slave FPGA 20 receives and stores exposure command data. After the master FPGA 10 initiates a parallel exposure task, the slave FPGAs 20 execute the parallel exposure task according to the exposure command data. Each slave FPGA 20 independently controls c×c×m laser channels, achieving a total of c×c×m×p laser channels. c×c represents a logic array, m is the number of layers, and p is the number of slave FPGAs 20. c×c×m×p ≥ N×N.

[0050] In some embodiments, the slave FPGA 20 is specifically configured to:

[0051] According to the exposure instruction data, c×c×m PWM square waves are modulated to control the constant current source array to output c×c×m analog current signals in parallel, so as to control the exposure time of the laser through the analog current signals.

[0052] In some embodiments, the master FPGA 10 forwards the exposure instruction data message to the slave FPGA 20 via an SPI bus.

[0053] In this embodiment, the master FPGA 10 and the slave FPGA 20 are connected using a serial peripheral interface (SPI). The SPI bus is a full-duplex, high-speed, synchronous communication bus that is a one-master-multiple-slave interface and uses a CS chip select to control communication between the master and slave devices.

[0054] The master FPGA 10 forwards the exposure instruction data message sent by the workstation to the corresponding slave FPGA 20 according to the ID of the slave FPGA 20 .

[0055] In some embodiments, the master FPGA 10 controls the slave FPGA 20 through GPIO pins to perform parallel exposure tasks.

[0056] In this embodiment, the master FPGA 10 and slave FPGA 20 are connected via GPIO pins, using a push-pull output mode. The master FPGA 10 outputs high and low levels to the slave FPGA 20 via the GPIO pins to control whether the slave FPGA 20 executes or does not execute parallel exposure tasks. For example, a high level indicates exposure, while a low level indicates no exposure. When the master FPGA 10 outputs a high level via the GPIO pins, the corresponding slave FPGA 20 executes the parallel exposure task. When the master FPGA 10 outputs a low level via the GPIO pins, the corresponding slave FPGA 20 does not execute the parallel exposure task.

[0057] In some embodiments, the master FPGA 10 is further configured to:

[0058] Control the movement of the workpiece stage; wherein, the workpiece stage includes a coarse movement stage and a fine movement stage; the main control FPGA 10 enables the motor driver to drive the fine movement stage to move by sending a fine movement stage movement message to the motor driver, and enables the motor driver to drive the coarse movement stage to move by sending a coarse movement stage movement message to the motor driver.

[0059] In this embodiment, the workpiece stage is controlled by the master FPGA 10. The workpiece stage includes a coarse motion stage and a fine motion stage. The master FPGA 10 sends coarse motion stage motion messages to the motor driver, which then drives the coarse motion stage based on these messages. The master FPGA 10 also sends fine motion stage motion messages to the motor driver, which then drives the fine motion stage based on these messages.

[0060] The coarse motion stage movement message sent by the master FPGA 10 can be defined as shown in Table 3, and the message length is 7 bytes.

[0061] Table 3

[0062] The micro-motion stage motion message sent by the master FPGA 10 can be defined as shown in Table 4, and the message length is 7 bytes.

[0063] Table 4

[0064] In some embodiments, the master FPGA 10 is further configured to:

[0065] Receive the motion feedback message sent by the motor driver.

[0066] The motion feedback message sent by the motor driver can be defined as shown in Table 5, and the message length is 10 bytes.

[0067] Table 5

[0068] In some embodiments, the master FPGA 10 is further configured to receive a command message sent by the workstation, and determine whether to initialize and control the movement of the workpiece stage according to the command message.

[0069] The command message sent by the workstation can be defined as shown in Table 6, and the message length is 5 bytes.

[0070] Table 6

[0071] In some embodiments, the master FPGA 10 is further configured to:

[0072] Send a request or feedback message to the workstation.

[0073] The request or feedback message sent by the master FPGA 10 can be defined as shown in Table 6, and the message length is 5 bytes.

[0074] Table 7

[0075] In conjunction with FIG3 , a specific embodiment of master-slave collaborative control is described below:

[0076] Assume the wafer size is W inches and the center-to-center distance between adjacent fibers is Lμm. Thus, for an N×N fiber array, the exposure field area is (L×N)μm×(L×N)μm. The workpiece stage's translational motion is defined as consisting of three directions: X, Y, and Z. A movement that completes an exposure field is called a step, with a step length of (L×N)μm. Movement within the exposure field is called a scan, with a step length of sμm. Each step or scan motion is called a single step, where X represents the column, Y represents the row, and Z represents the normal direction.

[0077] The master-slave collaborative control based on the master FPGA 10 and the slave FPGA 20 may include the following steps:

[0078] Step 1: Initialization, including calibration of the initial position of the workpiece stage, system alignment, leveling and focusing, each slave FPGA 20 receiving and storing the corresponding exposure instruction data, suspending various event monitoring tasks, etc.

[0079] Step 2: After receiving the START command from the workstation, the main control FPGA 10 triggers the workpiece table motion event.

[0080] Step 3: The main control FPGA 10 determines whether the workpiece stage movement is coarse or fine motion based on the size of the workpiece stage's travel, current position and other information, and then sends a motion instruction message in the XYZ direction.

[0081] Step 4: The main control FPGA 10 calculates the control quantity or control increment through an intelligent algorithm based on the expected target, actual feedback and other information, and sends it to the motor driver.

[0082] Step 5: According to the coarse motion command or fine motion command, the motor driver drives the coarse motion stage or fine motion stage accordingly, and ensures the positioning accuracy through precise correction technology.

[0083] Step 6: After the master FPGA 10 receives the feedback information indicating that the movement is completed, it starts the parallel exposure task.

[0084] Step 7: Each slave FPGA 20 modulates c×c×m PWM square waves based on the current exposure command data to control the constant current source array. This in turn outputs c×c×m analog current signals in parallel to control the laser exposure duration. P slave FPGAs 20 can perform c×c×m×p parallel exposure tasks.

[0085] Step 8: Each slave FPGA 20 updates the current exposure instruction data.

[0086] Step 9: Using a non-handshake mechanism, when the exposure delay is reached, the main control FPGA 10 considers that one scan exposure is completed.

[0087] Step 10: The workpiece table moves s μm in the Y direction, and repeats Step 3-Step 9 until it moves After times, it is considered that one row scan exposure is completed, where Indicates floor operation.

[0088] Step 11: The workpiece stage moves s μm in the X direction, and Step 10 is repeated to complete the next row of scanning exposure tasks. This process is deduced from the original text until the Lth row of scanning exposure tasks is completed. This is considered to be one exposure field completed.

[0089] Step 12: The workpiece stage moves (L×N) μm in the Y direction to prepare for the exposure task of the next exposure field.

[0090] Step 13: When the preset conditions are triggered, the master FPGA 10 takes some necessary synchronization strategies or compensation measures to ensure positioning accuracy and system reliability and stability;

[0091] Step 14: Follow Step 3-Step 13 to complete the exposure task of the next exposure field, and so on until the exposure task is completed. The exposure task of an exposure field is considered to be completed for one row of exposure on the wafer surface.

[0092] Step 15: The workpiece stage moves (L×N) μm in the X direction, and then the exposure task of the next row of the wafer surface is completed according to the above steps. This process is repeated until the exposure of the entire wafer surface is completed.

[0093] To sum up, the optomechanical control system for arrayed digital lithography machines provided in this application adopts a master-slave collaborative control method, and completes parallel exposure tasks through the collaboration of the master FPGA and each slave FPGA, which can realize the control of c×c×m×p lasers, and can effectively improve the lithography efficiency of maskless lithography machines, meet the application requirements of MEMS with multiple categories, small batches, rapid production, and flexible and changeable, and can effectively solve the problems of high concurrency and limited GPIO pins, and has high stability, reliability and scalability.

[0094] The present application also provides an arrayed digital lithography machine, including the above-mentioned optomechanical control system for the arrayed digital lithography machine. For the arrayed digital lithography machine provided by the present application, reference can be made to the above-mentioned embodiment of the optomechanical control system, which will not be repeated here.

[0095] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to in detail.

[0096] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0098] The above is a detailed introduction to the optomechanical control system for arrayed digital lithography provided by this application. This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. An optomechanical control system for an arrayed digital lithography machine, characterized in that: include: Master FPGA and multiple slave FPGAs; The master control FPGA is used to communicate with the workstation and each of the slave control FPGAs, forward the exposure instruction data message sent by the workstation to the slave control FPGA, and control the slave control FPGA to perform parallel exposure tasks; The slave control FPGA is used to execute parallel exposure tasks according to exposure instruction data; wherein each slave control FPGA independently controls c×c×m lasers, and c×c×m×p≥N×N; c×c represents a logic array, m is the number of layers, p is the number of the slave control FPGAs, and N×N represents the size of the optical fiber array.

2. The optomechanical control system according to claim 1, characterized in that: The slave control FPGA is specifically used for: According to the exposure instruction data, c×c×m PWM square waves are modulated to control the constant current source array to output c×c×m analog current signals in parallel, so as to control the exposure time of the laser through the analog current signal.

3. The optomechanical control system according to claim 1, characterized in that: The master control FPGA forwards the exposure instruction data message to the slave control FPGA via the SPI bus.

4. The optomechanical control system according to claim 1, characterized in that: The master control FPGA controls the slave control FPGA to execute parallel exposure tasks through GPIO pins.

5. The optomechanical control system according to claim 1, characterized in that: The master control FPGA is also used for: Control the movement of the workpiece stage; wherein the workpiece stage includes a coarse movement stage and a fine movement stage; the main control FPGA enables the motor driver to drive the fine movement stage to move by sending a fine movement stage movement message to the motor driver, and enables the motor driver to drive the coarse movement stage to move by sending a coarse movement stage movement message to the motor driver.

6. The optomechanical control system according to claim 5, characterized in that: The master control FPGA is also used for: Receive the motion feedback message sent by the motor driver.

7. The optomechanical control system according to claim 5, characterized in that: The main control FPGA is also used to receive the command message sent by the workstation, and determine whether to initialize and whether to control the movement of the workpiece platform according to the command message.

8. The optomechanical control system according to claim 1, characterized in that: The master control FPGA is also used for: Send a request or feedback message to the workstation.

9. The optomechanical control system according to claim 1, characterized in that: The data messages between the master control FPGA and the workstation are transmitted based on the UDP protocol.

10. An array digital lithography machine, characterized in that: The arrayed digital lithography machine comprises an optomechanical control system for an arrayed digital lithography machine as described in any one of claims 1 to 9.

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