Image data processing method and apparatus, electronic device, and readable storage medium

Abstract

The present application relates to the technical field of image processing, and discloses an image data processing method and apparatus, an electronic device, and a readable storage medium. The method comprises: grouping image data streams of a first image, each group of image data streams comprising M rows of image data, or each group of image data streams comprising at least one image data block, wherein M is a positive integer; for each group of image data streams, generating a read address when writing a group of image data into a corresponding storage space, the read address being used for indicating the address of each piece of image data in the group of image data in the storage space, wherein said piece of image data needs to be read by blocks; and on the basis of the read address, reading each piece of image data in the group of image data from the storage space, and writing each piece of image data in a next group of image data into the storage space of the read image data.

Description

Image data processing method, device, electronic device and readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310914113.1 filed in China on July 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of image processing technology, and specifically relates to an image data processing method, device, electronic device and readable storage medium. Background Art

[0004] In the field of image processing, block-by-block processing is often required to better reference neighboring pixels. This is often the case in applications such as 3D noise reduction algorithms, image encoding and decoding, and image compression. Currently, image sensors typically output video data streams in a line-scan format. Therefore, image signal processor (ISP) chips often perform image conversions, converting rows to blocks and blocks to rows.

[0005] In related technologies, when converting between rows and blocks, a ping-pong buffering approach is used to ensure that the real-time video data stream is not overwritten. Specifically, two buffers are used. For example, in the case of row-to-block (M*N) conversion, the M rows of input data stream to be converted are first stored in buffer 1. Then, data is read from buffer 1 in blocks M*N. Simultaneously, the subsequent M rows of input data are synchronously stored in buffer 2 in a row-by-row manner. This process is repeated, alternating between block reading and row writing in the two buffers.

[0006] Since the above method requires two buffer spaces, it consumes a lot of storage resources, resulting in high costs.

[0007] Summary of the Invention

[0008] The purpose of the embodiments of the present application is to provide an image processing method, device, electronic device and readable storage medium, which can realize row-block conversion of image data and save storage space.

[0009] In a first aspect, an embodiment of the present application provides an image processing method, the method comprising: grouping an image data stream of a first image; each group of image data streams comprises M rows of image data, or each group of image data streams comprises at least one image data block; M is a positive integer; for each group of image data streams, when a group of image data is written into a corresponding storage space, a read address is generated, the read address being used to indicate an address in the storage space of each image data in a group of the image data that needs to be read out in blocks; according to the read address, each image data in a group of image data is read out from the storage space, and each image data in the next group of image data is written into the storage space of the read image data.

[0010] In a second aspect, an embodiment of the present application provides an image processing device, which includes: a splitting module, a generation module and a processing module, wherein: the above-mentioned splitting module is used to group the image data stream of the first image; each group of image data stream includes M rows of image data, or each group of image data stream includes at least one image data block; M is a positive integer; the above-mentioned generation module is used to generate a read address for each group of image data stream obtained after grouping by the splitting module, when the processing module writes a group of image data into the corresponding storage space, and the above-mentioned read address is used to indicate the address of each image data in a group of image data that needs to be read out in blocks in the storage space; the above-mentioned processing module is used to read out each image data in a group of image data from the storage space according to the read address generated by the generation module, and write each image data in the next group of image data into the storage space of the read image data.

[0011] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0012] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0013] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the method described in the first aspect.

[0014] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the method described in the first aspect.

[0015] In an embodiment of the present application, an image processing device groups an image data stream of a first image; each group of image data streams includes M rows of image data, or each group of image data streams includes at least one image data block; M is a positive integer; for each group of image data streams, when writing a group of image data into a corresponding storage space, a read address is generated, the read address being used to indicate the address in the storage space of each image data block to be read out from the group of image data; each image data block in the group of image data is read from the storage space according to the read address, and each image data block in the next group of image data is written into the storage space of the read image data. Through this method, the image processing device can generate the required read address, and when reading image data from the storage space according to the read address, quickly write the new image data into the storage location corresponding to the read image data, thereby achieving alternating reading and writing of image data in a single storage space, thereby efficiently writing image data by row and reading it by block, achieving row-block conversion of the image data stream and saving storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a schematic diagram of a method flow of an image data processing method provided by an embodiment of the present application;

[0017] FIG2(A) is a schematic diagram of image data obtained based on line scanning according to an embodiment of the present application;

[0018] FIG2(B) is a schematic diagram of a read address of image data provided in an embodiment of the present application;

[0019] FIG3 is a schematic diagram of image data converted from line blocks according to an embodiment of the present application;

[0020] FIG4 is a schematic diagram of a flow chart of an image data processing method provided in an embodiment of the present application;

[0021] FIG5 is a schematic diagram of the structure of an image data processing device provided in an embodiment of the present application;

[0022] FIG6 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0023] FIG7 is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0025] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this application can be implemented in an order other than that illustrated or described herein. Furthermore, the terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects are in an "or" relationship.

[0026] The embodiments of the present application can be applied to scenarios of video noise reduction, image noise reduction, video editing code, image encoding and decoding, video compression, and image compression.

[0027] Currently, in the field of image processing, block-by-block processing is often required to better reference neighboring pixels, such as in 3D noise reduction algorithms, image encoding and decoding, and image compression. However, typical CMOS image sensors output video data streams in a line-scan format. Therefore, image signal processor (ISP) chips often perform image conversions, converting rows to blocks and blocks to rows.

[0028] In conventional processing schemes, when converting between rows and blocks, a ping-pong cache method is used to ensure that the real-time video data stream is not overwritten. Specifically, two blocks of storage space are used. Taking the row-to-block (M*N) conversion as an example, the data stream input in M ​​rows to be converted is first stored in the first block of storage space, and then the data is read out from the first block of storage space according to the block M*N. At the same time, the subsequent M rows of continuously input data are synchronously stored in the second block of storage space by row, and the above steps are repeated, and block reading and row writing are performed alternately in the two blocks of storage space. This method can ensure that the data stream will not be overwritten, and the operation is relatively simple, but it requires the consumption of two blocks of storage space, resulting in a waste of storage space.

[0029] The image data processing method provided by the embodiment of the present application is such that the image processing device can generate the required read address and, when reading the image data from the storage space according to the read address, quickly write the new image data into the storage location corresponding to the read image data, thereby realizing alternating reading and writing of image data in one storage space without the need to use two storage spaces to realize row-to-block conversion of data. Thus, the image data can be efficiently written row by row and read out block by block, realizing row-to-block conversion of the image data stream and saving costs.

[0030] In addition, in the related art, in order to save storage space, the required operation address can be obtained by performing a simple shift operation on the initial read and write addresses, and then the periodic changes of the write address and the read address are obtained, so as to achieve the row-to-block operation using only one storage space.

[0031] However, the related technology has the following defects:

[0032] First, to be able to write and read data at the same time, a dual-port SRAM is used to store pixel values, and the instantiated SRAM depth must be 2^n. For example, to store a 1920*1080 image, an 8*8 block requires an SRAM with a depth of 8*2048, resulting in higher chip power consumption and area.

[0033] Second, the size of the data block is restricted. For example, for an M*N data block, M must be equal to 2^i, where i is a positive integer. This limits its application scope.

[0034] Third, it only involves the conversion from data rows to blocks. How to achieve the conversion from data blocks to data rows through a piece of storage space is still a problem to be solved.

[0035] In order to solve the above problems, the image data processing method provided in the embodiment of the present application, on the one hand, uses a single-port SRAM to replace the dual-port SRAM through the method of single-cycle multi-pixel writing and read-write interleaving, and the depth of the SRAM is configured according to the actual image width, and there is no need to waste SRAM space for 2^n depth alignment, thereby effectively reducing the power consumption and area of ​​the chip; on the other hand, it supports the conversion of blocks of any size M*N (generally M and N are even numbers) without the restriction that M must be 2^i; on the other hand, it can support the rapid conversion of data rows to data blocks and the rapid conversion of data blocks to data rows, thereby greatly improving the flexibility of row data and block data conversion.

[0036] The image processing method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0037] The execution subject of the image data processing method provided in the embodiment of the present application can be an electronic device, or at least one of the functional modules and functional entities in the electronic device that can implement the image data processing method. The specific execution subject can be determined according to actual usage requirements and is not limited by the embodiment of the present invention.

[0038] FIG1 is an image data processing method provided by an embodiment of the present application. As shown in FIG1 , the image data processing method may include the following steps S201 to S203:

[0039] Step S201: The image data processing apparatus groups the image data stream of the first image.

[0040] Each set of image data streams includes M lines of image data, or each set of image data streams includes at least one image data block; M is a positive integer;

[0041] Optionally, in an embodiment of the present application, the first image may be an image or a video frame.

[0042] Further optionally, in the case where the first image is an image, the first image may be an image captured by a camera, or a downloaded image.

[0043] Optionally, when the first image is a video frame, the first image may be a video frame of an online video or a video frame of an offline video.

[0044] Optionally, in an embodiment of the present application, the image data processing device may scan the first image row by row in a row scanning manner to obtain at least one row of image data of the first image.

[0045] In some possible implementations, the image data processing device may scan each row of pixels of the first image sequentially from left to right to obtain at least one row of image data, where one row of image data corresponds to one row of pixels.

[0046] It should be noted that the specific implementation method of scanning the image line by line to obtain image data can refer to related technologies and will not be described in detail here.

[0047] Optionally, in the embodiment of the present application, the image resolution of the first image may be 480p, 960p or 1080p, etc., which is not limited in the embodiment of the present application.

[0048] For example, when the resolution of the first image is 1080p, the first image includes 1920×1080 pixels, wherein the number of pixels in the horizontal direction is 1920 and the number of pixels in the vertical direction is 1080.

[0049] Optionally, in an embodiment of the present application, after obtaining at least one line of image data of the first image, the image data processing device may generate an image data stream of the first image according to the order in which the image data are obtained.

[0050] It should be noted that a data stream may also be referred to as stream data, which refers to a collection of continuous data, and an image data stream refers to a sequence of image data in a sequential order.

[0051] Optionally, in an embodiment of the present application, after the image data processing device scans the first image row by row to obtain at least one row of image data of the first image, it can group the at least one row of image data based on the preset number of rows of image data included in each image data block.

[0052] Exemplarily, the image data processing apparatus may group the acquired image data stream into groups of M rows each to obtain at least one group of image data.

[0053] Exemplarily, the number of rows of image data included in each image data block may be 4 rows, 8 rows, or 12 rows, etc., which may be specifically set according to actual needs and is not limited in the embodiments of the present application.

[0054] For example, taking M as 8, the number of pixels in the vertical direction of image 1 is 480, that is, the image 1 includes 480 rows of pixels. After scanning the image 1 row by row, 480 rows of image data can be obtained. The image data processing device groups the image data stream corresponding to the 480 rows of image data into groups of 8 rows, and 60 groups of image data can be obtained.

[0055] Optionally, in the embodiment of the present application, the above-mentioned image data may include pixel values ​​of the image. For example, one piece of image data may be the pixel value of one pixel point of the image.

[0056] In some other possible implementations, the image data processing device may scan the image area of ​​the first image block in blocks to obtain at least one image data block.

[0057] Optionally, in an embodiment of the present application, the above-mentioned image data block may be a 4*4 image data block or an 8*8 image data block, etc., which is not limited in this embodiment of the present application.

[0058] Optionally, in the embodiment of the present application, the image data blocks included in each group of image data streams are the number of data blocks in the row direction of the first image.

[0059] For example, assuming that the first image includes 80 rows of pixels, each row has 240 pixels, and after scanning the first image according to 8*8 blocks, 300 image data blocks are obtained, where the first image includes 30 image data blocks in the row direction, that is, one row of image data corresponds to 30 image data blocks.

[0060] Step S202: For each set of image data streams, the image data processing apparatus generates a read address when writing a set of image data into a corresponding storage space.

[0061] The read address is used to indicate the address in the storage space of each image data that needs to be read out in blocks in a group of the image data.

[0062] Optionally, in an embodiment of the present application, the above-mentioned set of image data may be any set of image data among the above-mentioned at least one set of image data.

[0063] Optionally, in the embodiment of the present application, the above-mentioned storage space is the storage space of a single-port random access memory SPRAM, the storage space of a dual-port random access memory, or the storage space of other memories.

[0064] It should be noted that the single-port random access memory is a single-port random access memory (Single-Port RAM, SPRAM); the dual-port random access memory is a true dual-port random access memory (True Dual-Port RAM).

[0065] It should be noted that single-port RAM has only one set of data lines and one set of address lines for input, a single clock, shared address lines for read and write, and a single output port. Therefore, single-port RAM cannot perform read and write operations simultaneously. Dual-port RAM has two sets of address lines and two sets of data lines for input, two clocks, and two separate data lines for output. Therefore, dual-port RAM has both read and write ports, allowing for simultaneous read and write operations without interfering with each other. Single-port RAM generally cannot perform simultaneous read and write operations compared to dual-port RAM, but it consumes less power than single-port RAM.

[0066] Optionally, in an embodiment of the present application, the size of the above-mentioned storage space can be determined based on the number of image data blocks corresponding to each row of image data and the number of data rows in each image data block.

[0067] It can be understood that the number of image data blocks corresponding to each row of image data is the number of image data blocks in the image row direction.

[0068] For example, taking a line of image data including 240 pixel values ​​as an example, assuming that an 8*8 data block needs to be output, each line of pixel values ​​corresponds to 30 data blocks, and each data block includes 8 lines of pixel values.

[0069] Optionally, in an embodiment of the present application, the image data processing device can determine the addresses of each image data that needs to be read in blocks in the storage space based on the change pattern of the addresses of each image data that needs to be read in rows in the storage space, that is, the above-mentioned read address.

[0070] Optionally, in an embodiment of the present application, the image data processing device may write the input M lines of image data into the storage space in sequence, and the addresses of the stored image data are accumulated sequentially.

[0071] Optionally, in the embodiment of the present application, the image data processing device may write each group of image data streams into the storage space in sequence.

[0072] Exemplarily, assuming that the image data includes 60 sets of image data, the 60 sets of data can be cyclically written into the above storage space.

[0073] Step S203: the image data processing device reads out each image data in the above set of image data from the above storage space according to the above read address, and writes the next set of image data into the storage space of the read-out image data.

[0074] Optionally, in an embodiment of the present application, the image data processing device can generate a read address based on the address of the image data to be read out in blocks in the storage space as needed, read out each image data in blocks according to the read address, and write the image data in the next group of image data into the storage location of the read image data in the storage space.

[0075] Optionally, in an embodiment of the present application, the image data processing device can read out the data stream by block after the Mth row of image data in each group of image data stream is written; or, the image data processing device can read out the data stream by row after all the image data streams in each group are written.

[0076] Optionally, in an embodiment of the present application, the image data processing device may write and read multiple groups of image data in the above-mentioned image data stream through multiple cycles.

[0077] Exemplarily, in the first loop, the image data processing device writes the first group of image data into the SPRAM storage space in sequence; in the second loop, the first group of image data written for the first time is read out according to image data blocks of M*N size, and the second group of image data is written to the SPRAM storage space that has been read out by block; in the third loop, the image data written in the second loop is read out according to M*N blocks, and the third group of image data is written to the SPRAM storage space that has been read out by block, and so on, until the last group of image data is read out by block.

[0078] Wherein, M is the number of rows of image data included in an image data block of the first image, N is the number of data in a row of data in an image data block, and N is a positive integer.

[0079] For example, the above M*N may be 8*8, 8*4, 4*8, or 16*16, etc.

[0080] Optionally, in an embodiment of the present application, the image data processing device may, when reading out an image data block in a group of image data, store the next group of image data in the storage space from which the image data block was read; or, the image data processing device may, when reading out an image data block in a group of image data, store an image data in the next group of image data in the storage space from which the image data was read.

[0081] Each group of image data streams obtained after grouping can be written into the storage space by executing the above-mentioned step S202 and step S203 and related solutions.

[0082] An image data processing method provided by an embodiment of the present application comprises an image processing device that groups an image data stream of a first image; each group of image data streams includes M rows of image data, or each group of image data streams includes at least one image data block; M is a positive integer; for each group of image data streams, when writing a group of image data into a corresponding storage space, a read address is generated, the read address being used to indicate the address in the storage space of each image data block to be read out from the group of image data; each image data block in the group of image data is read out from the storage space according to the read address, and each image data block in the next group of image data is written into the storage space of the read image data. Through this method, the image processing device can generate the required read address, and when reading image data from the storage space according to the read address, quickly write new image data into the storage location corresponding to the read image data, thereby achieving alternating reading and writing of image data in a storage space, thereby efficiently writing image data by row and reading it out by block, achieving row-block conversion of the image data stream and saving storage space.

[0083] Optionally, in the embodiment of the present application, each set of image data streams includes M lines of image data; the process of the image data processing device generating a read address in step S202 may include the following steps S202a and S202b:

[0084] Step S202a: The image data processing apparatus calculates the address of the target image data to be read out in the storage space in a group of image data based on the number of image data blocks in the row direction in the first image.

[0085] Step S202b: The image data processing apparatus generates a read address corresponding to the target image data according to the address of the target image data in the storage space.

[0086] Optionally, in an embodiment of the present application, the image data block in the row direction of the first image is determined based on the number of pixels in a row of the first image and the size of the image data block.

[0087] Optionally, in an embodiment of the present application, one target image data includes N image data.

[0088] Optionally, in an embodiment of the present application, the target image data is image data in an image data block to be output.

[0089] For example, taking the need to output an 8*8 image data block as an example, one 8*8 image data block includes 8 target image data, and one target image data includes 8 pixel values.

[0090] For example, assuming that the first image includes 100 rows of pixels and the number of pixels in each row is 240, and taking the size of the image data block as 8*8 as an example, the number of image data blocks in the row direction in the first image is 30, that is, 240 / 8.

[0091] Exemplarily, in combination with the above embodiment, taking a group of image data including 8 rows of image data and each row of image data including 240 pixel values ​​as an example, after the group of image data is written into a RAM storage space of size 30*8, the first row of storage units of the RAM storage space stores 30 data blocks corresponding to the first row of pixel values, and the address range of the first row of storage units is 0-29; the second row of storage units of the RAM storage space stores 30 data blocks corresponding to the second row of pixel values, and the address range of the second row of storage units is 30-59, and so on. The eighth row of storage units of the RAM storage space stores 30 data blocks corresponding to the eighth row of pixel values, and the address range of the eighth row of storage units is 210-239. According to the addresses of each data block in the storage space, it can be determined that the address of the first target pixel value corresponding to the first data block to be read out in the group of pixel values ​​is 0, the address of the second target pixel value is 30, the address of the third target pixel value is 60, and so on.

[0092] It should be noted that a RAM size of 30*8 means that the RAM storage space includes 8 rows of storage cells, each row of storage cells includes 30 storage cells, each storage cell can store 8 pixel values, and 8 pixel values ​​constitute a row of data in a data block. The storage address range corresponding to the storage cells of this RAM storage space is 0-239.

[0093] Optionally, in an embodiment of the present application, the image data processing device uses the address of the target image data in the storage space as the read address corresponding to the target image data.

[0094] Exemplarily, in combination with the above embodiment, the address of the first target pixel value corresponding to the first data block to be read out in the group of pixel values ​​is 0, then the reading address corresponding to the first target pixel value corresponding to the first data block is 0, that is, the image processing device can read the first target pixel value in the storage unit with address 0.

[0095] Optionally, in the embodiment of the present application, the above step S202a can be implemented by the following step S202a1:

[0096] Step S202a1: The image data processing apparatus calculates the address of the i+1th target image data to be read out in the storage space from a set of image data using a first formula based on the number of image data blocks in the row direction of the image and the number of rows of image data corresponding to each image data block; i∈[0, tile_num*M-1], where i is an integer;

[0097] Among them, the above first formula is: An(i) = (i*tile_num^n-1)% (tile_num*M-1)+1, tile_num is the number of image data blocks in the row direction of the image, and n is equal to the group where the image data is located minus 1.

[0098] For example, taking tile_num equal to 30 and M equal to 8 as an example, when using the first formula to calculate the address of the first target image data of the first group of image data in the storage space, tile_num equal to 30, M equal to 8, i equal to 0, and n equal to 0 (i.e., 1-1) are substituted into the above first formula, and An(0) equal to 0 is obtained, that is, the address of the first target image data of the first group of image data in the storage space is 0.

[0099] The following is an explanation of the process of determining the read address in the embodiment of the present application through a specific embodiment.

[0100] For example, taking the conversion of multiple lines of image data obtained by scanning a 1080P image row by row into an 8*8 block as an example, as shown in FIG2(A), after scanning the image row, 1080 lines of pixel values ​​are obtained, each line having 1920 pixel values, and every 8 lines of pixel values ​​are divided into a group. Among them, the first pixel value of the first row is represented by Y0_0, the second pixel value of the first row is represented by Y0_1, ..., the 1920th pixel value of the first row is represented by Y0_1919. Similarly, the first pixel value of the second row is represented by Y1_0, the second pixel value of the second row is represented by Y1_1, ..., the 1920th pixel value of the second row is represented by Y1_1919. The pixel values ​​within the solid-line box represent all image data contained in the first image data block obtained by converting the first group of image data. P11, P21 to P81 respectively represent a line of pixel values ​​in the image data block. The line of pixel values ​​can be regarded as a pixel value set, i.e., the target image data.

[0101] In conjunction with FIG2(A) above, in the first cycle, the image data processing device writes the pixel values ​​of the image into the SPRAM, and one address stores 8 pixel values. As shown in FIG2(B), Content(N=240) indicates that there are 240 image data blocks corresponding to the row direction. In the first cycle, the image processing device stores the first set of image data into the corresponding address space. In FIG2(B), P11 indicates the first row of image data of the first image data block corresponding to the first set of pixel values, P12 indicates the first row of image data of the second image data block corresponding to the first set of pixel values, ..., P1N indicates the first row of image data of the Nth image data block corresponding to the first set of pixel values. Image data, P21 represents the second row of image data of the first image data block corresponding to the first group of pixel values, P22 represents the second row of image data of the second image data block corresponding to the second row of pixel values, ..., P2N represents the second row of image data of the Nth image data block corresponding to the first group of pixel values. Similarly, P81 represents the eighth row of image data of the first image data block corresponding to the first group of pixel values, P82 represents the eighth row of image data of the second image data block corresponding to the first group of pixel values, ..., P8N represents the eighth row of image data of the Nth image data block corresponding to the first group of pixel values. The address of P11 is 0, the address of P12 is 1, ..., the address of P8N is 1919. After writing the above set of pixel values ​​into the SPRAM, a second loop begins. The image data processing device calculates the addresses of the target pixel values ​​to be read for each image data block corresponding to the above set of pixel values ​​according to the first formula. The target image data is then read out block by block based on the addresses, and the second set of pixel values ​​is written into the SPRAM storage space that has been read out block by block. As shown in FIG2(B), the addresses of the target pixel values ​​read out block by block are 0, 240, 480, ..., 1919. In a third loop, the image data processing device calculates the addresses of the target pixel values ​​to be read for each image data block corresponding to the previous set of pixel values ​​according to the first formula. The target image data is then read out block by block based on the addresses, and the third set of pixel values ​​is written into the SPRAM storage space that has been read out block by block. As shown in FIG2(B), the addresses of the target pixel values ​​read out block by block are 0, 30, 60, ..., 1919. This process continues in this manner until all 135 sets of pixel values ​​for the image have been converted into block pixel outputs.

[0102] In conjunction with Figures 2(A) and 2(B) above, Figure 3 is a schematic diagram of the image data converted by row block provided by an embodiment of the present application. As shown in Figure 3, the left figure is a schematic diagram of storing the pixel values ​​obtained by row scanning into the storage space by row. Each column of pixel values ​​in the left figure constitutes an image data block, and one pixel value in each column of pixel values ​​contains the pixel values ​​of 8 pixels, that is, 8 pixel values ​​are stored in one storage unit. As shown in Figure 3, P0_0 represents the 1st to 8th pixel values, and N represents the number of data blocks in the row direction. The right figure in Figure 3 shows the arrangement of each data block when the pixel values ​​written by row are converted into data blocks. As shown in Figure 3, the pixel values ​​of the first row constitute a data block.

[0103] The derivation process of the first formula is explained in detail below.

[0104] For example, first define "tile_num" as the number of blocks in the image row direction, that is, tile_num is equal to the image width divided by N, that is, img_width / N. "tile_height" is the number of rows associated with the image block, which is also equal to M, indicating that a block contains M rows. The read and write cycle of each M row of image pixels is a cyclic operation, and the write operation has a higher priority than the read operation. For the input image data stream of k ppc (pixel per cycle) scanned by row, the pixels are first merged according to 2k ppc. The purpose of this is to interleave the data reading and writing of SPRAM. The width of SPRAM is the pixel bit width multiplied by 2k, that is, pixel_width*2k, and the depth of SPRAM is the image width multiplied by M divided by 2k, that is, img_width*M / 2k.

[0105] In the first loop, the input M lines of image data are sequentially written into the SPRAM as 2k pixels, with the addresses incremented. After all M lines of image data are written, the data stream can be read out in blocks of M*N. To minimize data readout latency, reading the first M*N block of data can begin when the Mth line of data has filled a block. For ease of description, we assume N = 2k. Generally, N is an integer multiple of 2k.

[0106] In the second loop, the data written in the first loop is read out in M*N blocks in the second loop, and the new M lines of image video stream are written to the SPRAM storage space that has been read out in blocks. The address jump rules for the first data block read are:

[0107] 0,

[0108] tile_num,

[0109] 2*tile_num,

[0110] 3*tile_num,

[0111] …,

[0112] (M-1)*tile_num;

[0113] The read address jump rule for the second data block is

[0114] 1,

[0115] 1+tile_num,

[0116] 1+2*tile_num,

[0117] 1+3*tile_num,

[0118] …,

[0119] 1+(M-1)*tile_num;

[0120] By analogy, we can get the address jump rule of the last data block as follows:

[0121] tile_num-1,

[0122] tile_num-1+tile_num,

[0123] tile_num-1+2*tile_num,

[0124] tile_num-1+3*tile_num,

[0125] …,

[0126] tile_num-1+(M-1)*tile_num;

[0127] It should be noted that, since in the second loop, the new M lines of image data stream need to be written to the space that has been read out by block, the write address rule of the new M lines of image data stream in the second loop follows the read address rule of the previous M*N blocks.

[0128] In the third loop, the video data stream written in the second loop is read out in M*N blocks, and the new M lines of image video stream are written to the SPRAM storage space that has been read out in blocks. The address jump rules for the first data block read are:

[0129] 0,

[0130] (tile_num^2-1)%(tile_num*M-1)+1,

[0131] (2*tile_num^2-1)%(tile_num*M-1)+1,

[0132] (3*tile_num^2-1)%(tile_num*M-1)+1,

[0133] …,

[0134] ((M-1)*tile_num^2-1)%(tile_num*M-1)+1,

[0135] The address jump rule read from the second block is

[0136] 1,

[0137] 1+(tile_num^2-1)%(tile_num*M-1)+1,

[0138] 1+(2*tile_num^2-1)%(tile_num*M-1)+1,

[0139] 1+(3*tile_num^2-1)%(tile_num*M-1)+1,

[0140] …,

[0141] 1+((M-1)*tile_num^2-1)%(tile_num*M-1)+1,

[0142] By analogy, we can get the address jump rule of the last block as

[0143] tile_num - 1,

[0144] tile_num-1+(tile_num^2-1)%(tile_num*M-1)+1,

[0145] tile_num-1+(2*tile_num^2-1)%(tile_num*M-1)+1,

[0146] tile_num-1+(3*tile_num^2-1)%(tile_num*M-1)+1,

[0147] …,

[0148] tile_num-1+((M-1)*tile_num^2-1)%(tile_num*M-1)+1,

[0149] Summarizing the above description, we can get the following general rules:

[0150] For the first loop:

[0151] A0(i)=i, i∈[0,tile_num*M-1], where "A0" represents the first loop write address, and i represents the i+1th 2k pixel of the input image data stream.

[0152] For the second loop:

[0153] A1(i)=(i*tile_num-1)%(tile_num*M-1)+1,

[0154] For the third loop:

[0155] A2(i)=(i*tile_num^2-1)%(tile_num*M-1)+1,

[0156] …,

[0157] And so on, for the n+1th loop:

[0158] An(i)=(i*tile_num^n-1)%(tile_num*M-1)+1,

[0159] Optionally, in the above formula, tile_num*M is the address space size of the SPRAM. When tile_num^n is implemented in hardware, the image data processing device can first save the value of tile_num^(n-1) in the previous cycle and multiply it by tile_num when using it in the current cycle, thereby improving computing efficiency.

[0160] Based on the above calculation results, the general rules can be obtained as follows:

[0161] For the first loop:

[0162] A0(i)=i,i∈[0,tile_num*M-1], “A” represents the first loop write address, and i represents the i-th 2k pixel of the input image data stream.

[0163] For the second loop:

[0164] A1(i)=(i*tile_num-1)%(tile_num*M-1)+1,

[0165] For the third loop:

[0166] A2(i)=(i*tile_num^2-1)%(tile_num*M-1)+1,

[0167] …,

[0168] And so on, for the n+1th loop:

[0169] An(i)=(i*tile_num^n-1)%(tile_num*M-1)+1,

[0170] It should be noted that, in the above formula, tile_num*M is the address space size of the SPRAM.

[0171] Optionally, in an embodiment of the present application, during hardware implementation, the image data processing device may first save the value of tile_num^(n-1) of the previous loop, and multiply it by tile_num when used in the current loop, thereby improving the efficiency of data operations.

[0172] In the image data processing method provided by the embodiment of the present application, the image data processing device can use a first formula to calculate the address of each target image data to be read out in a group of image data in the storage space based on the number of image data blocks in the row direction of the image and the number of rows of image data corresponding to each of the image data blocks, thereby being able to efficiently and accurately read out each image data in blocks according to the address of each target image data to be read out.

[0173] Optionally, in the embodiment of the present application, the process of reading each image data in a group of image data from the storage space according to the read address in the above step S203 and writing each image data in the next group of image data into the storage space of the read image data can be implemented by the following step S203a:

[0174] Step S203a: The image data processing device reads the above-mentioned i+1th target image data from the above-mentioned storage space according to the read address corresponding to the above-mentioned i+1th target image data, and writes the jth image data in the next group of image data into the storage space from which the above-mentioned i+1th target image data has been read.

[0175] Where j∈[1, tile_num*M].

[0176] In the embodiment of the present application, after extracting a target image data, the image data processing device may write a new image data into the storage space from which the target image data was extracted.

[0177] Exemplarily, in combination with the above embodiments, the image data processing device first takes out the first target pixel value corresponding to the first data block in the first group of pixel values ​​from a storage unit corresponding to a storage address, and after taking out the target pixel value from the storage space corresponding to its storage address, writes the first pixel value in the second group of pixel values ​​to the storage space. Then, the image data processing device continues to take out the second target pixel value corresponding to the first data block in the first group of pixel values ​​from the storage space corresponding to its storage address, and after taking out the second target pixel value, writes the second pixel value in the second group of pixel values ​​to the storage space, and so on, until all pixel values ​​written in rows are read out in blocks.

[0178] It should be noted that after the last set of pixel values ​​is written into the storage space, it is only necessary to read out the last set of pixel values ​​in blocks without writing pixel values ​​again.

[0179] In an embodiment of the present application, each time the image data processing device reads an image data from the storage space, it writes a new image data into the storage space from which the image data was read. By alternating between reading and writing, the efficiency of row-to-block processing of the image data is greatly improved.

[0180] Optionally, in the embodiment of the present application, each group of image data streams includes at least one image data block; illustratively, the process of generating the read address in step S202 may include the following steps S202c and S202d:

[0181] Step S202c: The image data processing apparatus calculates the address of the target image data to be read out in the storage space in a group of image data based on the number of image data blocks in the row direction in the first image and the number of rows of image data corresponding to one image data block.

[0182] Step S202d: The image data processing apparatus generates a read address corresponding to the target image data according to the address of the target image data in the storage space.

[0183] Optionally, in an embodiment of the present application, the image data processing device may use the address of the target image data in the storage space as the read address corresponding to the target image data.

[0184] Exemplarily, in combination with the above embodiments, taking the case where the number of image data blocks in the row direction in the first image is 30, a row of image data includes 240 image data, and the number of rows of image data corresponding to one image data block is 8, the address of the first image data of the first row of image data to be read out is 0, the address of the second image data of the first row of image data to be read out is 8, the address of the third image data of the first row of image data to be read out row by row is 16, and so on. The address of the last image data of the first row of image data to be read out row by row is 232, that is, 29*8.

[0185] It should be noted that the block-to-row conversion described in the above embodiment can be considered the inverse of the row-to-block conversion. To implement the block-to-row conversion, the definitions of 'tile_num' and 'tile_height' can be swapped. This is because, based on pixel processing, the row-based image matrix and the block-based image matrix are transposed matrices.

[0186] In an image data processing method provided by an embodiment of the present application, an image processing device groups a received image data stream according to grouping to obtain L groups of image data. When writing the hth group of image data into a storage space, a read address is generated according to a second address jump rule, where 0≤h≤L-1; then, according to the above read address, the hth group of image data is read out from the above storage space, and the h+1th group of image data is written into the storage space corresponding to the read image data.

[0187] In an embodiment of the present application, the image processing device can obtain the read address corresponding to the image data that needs to be read out row by row, and when the image data is read out from the storage space according to the read address, quickly write the new image data into the storage location corresponding to the read image data, thereby realizing alternating reading and writing of image data in a storage space, so that the image data can be efficiently written in blocks and read out in rows, realizing row-block conversion of the image data stream and saving storage space.

[0188] Optionally, in the embodiment of the present application, the above step S202c can be implemented by the following step S202c1:

[0189] Step S202c1: The image processing device uses the second formula to calculate the address of the i-th target image data to be read out in the storage space based on the number of image data blocks in the row direction of the image and the number of rows of image data corresponding to one image data block.

[0190] Where i∈[0, tile_height*tile_num-1], and i is a positive integer.

[0191] Among them, the above second formula is: An(i)=(i*tile_height^n-1)%(tile_height*tile_num-1)+1; tile_num is the number of image data blocks of the first image in the row direction, and tile_height is the number of rows of image data contained in an image data block.

[0192] For example, taking tile_height equal to 8 as an example, when using the second formula to calculate the address of the first target image data of the first group of image data in the storage space, tile_height equal to 8, i equal to 0, and n equal to 0 (that is, 1-1) are substituted into the above first formula to obtain An(0) equal to 0, that is, the address of the first target image data of the first group of image data in the storage space is 0.

[0193] The derivation process of the second formula is explained in detail below.

[0194] Using the above parameter definitions for row-to-block conversion, the following are the change rules for the write / read addresses in the first two cycles of block conversion, as well as the inferred change rules for the cycle addresses.

[0195] In the first cycle, the input M*N block image data stream writes M N-pixel block data into the SPRAM in sequence, and the addresses are accumulated in sequence.

[0196] In the second loop, the block data stream written in the first loop is read out row by row in the second loop, and the new M rows of M*N block image video stream are written to the SPRAM storage space that has been read out row by row. The address jump rule for the first row read is

[0197] 0,

[0198] tile_height,

[0199] 2*tile_height,

[0200] 3*tile_height,

[0201] …,

[0202] (tile_num-1)*tile_height;

[0203] The read address jump rule for the second line is

[0204] 1,

[0205] 1+tile_height,

[0206] 1+2*tile_height,

[0207] 1+3*tile_height,

[0208] …,

[0209] 1+(tile_num-1)*tile_height;

[0210] By analogy, we can get the address jump rule of the last line as

[0211] tile_height-1,

[0212] tile_height-1+tile_height,

[0213] tile_height-1+2*tile_height,

[0214] tile_height-1+3*tile_height,

[0215] …,

[0216] tile_height-1+(tile_num-1)*tile_height;

[0217] It should be noted that, since in the second loop, the new M rows of M*N block image data stream need to be written to the space that has been read out row by row, the write address rule of the new M rows of M*N block image data stream in the second loop follows the read address rule of the previous M rows.

[0218] According to the above-mentioned change rules of read address and write address, the general rules can be obtained as follows:

[0219] For the first loop:

[0220] A0(i)=i,i∈[0,tile_height*tile_num-1], “A0” represents the first loop write address, and i represents the i-th pixel of the input image block data stream.

[0221] For the second loop:

[0222] A1(i)=(i*tile_height-1)%(tile_height*tile_num-1)+1,

[0223] For the third loop:

[0224] A2(i)=(i*tile_height^2-1)%(tile_height*tile_num-1)+1,

[0225] …,

[0226] And so on, for the n+1th loop:

[0227] An(i)=(i*tile_height^n-1)%(tile_height*tile_num-1)+1,

[0228] Optionally, in the embodiment of the present application, the process of writing a set of image data into a corresponding storage space in the above step S202 can be implemented by the following steps A1:

[0229] Step A1: the image data processing device merges two adjacent image data in a group of image data, and writes each merged image data into the storage space of the SPRAM in one clock cycle.

[0230] Optionally, in the embodiment of the present application, the image data processing device may alternately perform reading and writing of image data.

[0231] Optionally, in an embodiment of the present application, when the image data processing device scans the first image row by row to obtain an input image data stream, it first merges two adjacent image data to obtain a merged image data, and then transmits and writes the merged image data to the storage space within one clock cycle.

[0232] Exemplarily, the image data processing apparatus may perform pixel merging on two adjacent pixel data in the image data stream to obtain merged pixel data.

[0233] It should be noted that for the specific process of pixel merging, please refer to the relevant technology, and the embodiments of this application will not go into details.

[0234] Optionally, in an embodiment of the present application, the image data processing device can write image data within one clock cycle and read the image data within the next clock cycle of the clock cycle; or, the image data processing device can read the image data within one clock cycle and write the image data within the next clock cycle of the clock cycle.

[0235] In one example, taking a group of image data including 500 pixel values ​​as an example, assuming that the total number of clock cycles is 500, the image data processing device merges adjacent pixel values ​​among the above 500 pixel values ​​to obtain 250 merged pixel data, and writes the above 250 pixel data to the corresponding storage space through 250 clock cycles respectively, and then reads out the above 250 pixel data in blocks through the remaining 250 clock cycles to alternately perform reading and writing operations on the image data.

[0236] In another example, the image data processing device reads out M rows of pixel data that have been written in blocks, reads out one pixel data in one clock cycle, and writes a new pixel data in the next cycle of the clock cycle, so as to alternately perform reading and writing operations on the image data.

[0237] In an embodiment of the present application, by merging the data and transmitting them, two image data can be actually transmitted in one clock cycle, so that one clock cycle can be left for writing new image data, thereby enabling alternate reading and writing of image data through a single-port RAM. While ensuring the efficiency of image data processing, the use of a single-port RAM can effectively reduce system power consumption.

[0238] Optionally, in the embodiment of the present application, after the image processing device reads the hth group of image data from the storage space according to the read address, it can split the merged image data to obtain each independent image data.

[0239] Exemplarily, the image data processing device may split the merged pixel data to obtain pixel data corresponding to each pixel point.

[0240] It should be noted that the above pixel data may include pixel values.

[0241] In conjunction with the above embodiments, FIG4 is a flow diagram of an image data processing method provided by an embodiment of the present application. As shown in FIG4 , for an input image data stream of k ppc (pixels per cycle) scanned row by row, pixels are first merged at 2k ppc to enable the SPRAM to interleave data write and read operations. The SPRAM width is the pixel bit width multiplied by 2k, i.e., pixel_width*2k, and the SPRAM depth is the image width multiplied by M divided by 2k, i.e., img_width*M / 2k. Then, a write address is generated, and the merged pixels are written to the SPRAM storage space according to the write address. A read address is generated according to the first address jump rule described above, and the written pixel values ​​are read out in blocks according to the read address. The read pixel values ​​are then split to obtain the pixel value corresponding to each pixel.

[0242] The image data processing method provided in the embodiment of the present application can support conversion between image resolutions of any size and M*N blocks of any size. By finding the change pattern of the read and write addresses through multiple cycles, a single-port SPRAM is used to store image row or image block data. Compared with the general row-block conversion scheme, the image data processing method proposed in the present application can save chip area and power consumption. In addition, based on the transposition characteristics between row-block conversion image matrices, the idea and implementation method of block-to-row conversion are proposed, which also makes the application range of the image data processing method of the present application wider.

[0243] The image data processing method provided in the embodiment of the present application can be executed by an image data processing device. In the embodiment of the present application, the image data processing device provided in the embodiment of the present application is described by taking the image data processing device executing the image data processing method as an example.

[0244] Figure 5 is a structural schematic diagram of an image data processing device provided by an embodiment of the present application. As shown in Figure 5, the above-mentioned image data processing device includes a splitting module 501, a generation module 502 and a processing module 503, wherein: the splitting module 501 is used to group the image data stream of the first image; each group of the image data includes M rows of image data, or each group of the image data includes at least one image data block; M is a positive integer; the generation module 502 is used to generate a read address for each group of the image data obtained after the grouping by the splitting module, when the processing module writes a group of the image data into the corresponding storage space, and the read address is used to indicate the address of each image data in the group of the image data that needs to be read out in block in the storage space; the processing module 503 is used to read each image data in a group of the image data from the storage space according to the read address generated by the generation module, and write each image data in the next group of image data into the storage space of the read image data.

[0245] Optionally, in the embodiment of the present application, each group of image data includes M lines of image data;

[0246] The generating module is specifically configured to calculate, based on the number of image data blocks in the row direction of the first image, addresses of target image data to be read out of a group of the image data in the storage space;

[0247] The generating module is specifically configured to generate a read address corresponding to the target image data according to the address of the target image data in the storage space.

[0248] Optionally, in an embodiment of the present application, the generating module is specifically configured to calculate, using a first formula, an address in the storage space of the i+1th target image data to be read out from a group of the image data according to the number of image data blocks in a row direction in the first image and the number of rows of image data corresponding to each of the image data blocks; i∈[0, tile_num*M-1], where i is an integer;

[0249] Among them, the first formula is: An(i) = (i*tile_num^n-1)% (tile_num*M-1)+1, tile_num is the number of image data blocks in the row direction of the image, and n is equal to the group where the image data is located minus 1.

[0250] Optionally, in an embodiment of the present application, the processing module is specifically used to read the i-th target image data from the storage space according to the read address corresponding to the i-th target image data, and write the j-th image data in the next group of image data into the storage space from which the i-th target image data has been read; j∈[1, tile_num*M].

[0251] Optionally, in the embodiment of the present application, each group of the image data includes at least one image data block;

[0252] The generating module is specifically configured to calculate the address of target image data to be read out in the storage space from a group of the image data based on the number of image data blocks in the row direction of the first image and the number of image data rows corresponding to one image data block;

[0253] The generating module is specifically configured to generate a read address corresponding to the target image data according to the address of the target image data in the storage space.

[0254] Optionally, in an embodiment of the present application, the generating module is specifically configured to calculate, using a second formula, an address in the storage space of an i-th target image data to be read out from a set of the image data according to the number of image data blocks in a row direction of the image and the number of rows of image data corresponding to one image data block; i∈[0, tile_height*tile_num-1], where i is a positive integer;

[0255] Among them, the second formula is: An(i) = (i*tile_height^n-1)% (tile_height*tile_num-1)+1; tile_num is the number of image data blocks of the first image in the row direction, and tile_height is the number of rows of image data contained in an image data block.

[0256] Optionally, in an embodiment of the present application, the processing module is specifically configured to merge two adjacent image data in a group of the image data, and write each merged image data into the storage space of the SPRAM through one clock cycle.

[0257] An image data processing device provided in an embodiment of the present application groups an image data stream of a first image; each group of image data streams includes M rows of image data, or each group of image data streams includes at least one image data block; M is a positive integer; for each group of image data streams, when writing a group of image data into a corresponding storage space, a read address is generated, the read address being used to indicate the address in the storage space of each image data in the group of image data that needs to be read out block by block; each image data in the group of image data is read out from the storage space according to the read address, and each image data in the next group of image data is written into the storage space of the read image data. Through this method, the image processing device can generate the required read address, and when reading image data from the storage space according to the read address, quickly write new image data to the storage location corresponding to the read image data, thereby achieving alternating reading and writing of image data in a storage space, thereby efficiently writing image data by row and reading it out by block, achieving row-block conversion of the image data stream and saving storage space.

[0258] The image data processing device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., and the embodiment of the present application does not specifically limit it.

[0259] The image data processing device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0260] The image data processing device provided in the embodiment of the present application can implement each process implemented in the method embodiments of Figures 1 to 4. To avoid repetition, they will not be described here.

[0261] Optionally, as shown in Figure 6, an embodiment of the present application also provides an electronic device 600, including a processor 601 and a memory 602, and the memory 602 stores a program or instruction that can be run on the processor 601. When the program or instruction is executed by the processor 601, the various steps of the above-mentioned image data processing method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0262] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0263] FIG7 is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0264] The electronic device 100 includes but is not limited to components such as a radio frequency unit 101 , a network module 102 , an audio output unit 103 , an input unit 104 , a sensor 105 , a display unit 106 , a user input unit 107 , an interface unit 108 , a memory 109 , and a processor 110 .

[0265] Those skilled in the art will appreciate that the electronic device 100 may further include a power source (such as a battery) for powering various components. The power source may be logically connected to the processor 110 via a power management system, thereby enabling the power management system to manage charging, discharging, and power consumption. The electronic device structure shown in FIG8 does not limit the electronic device. The electronic device may include more or fewer components than shown, or may combine certain components or arrange the components differently, which will not be described in detail here.

[0266] The processor 110 is configured to group the image data stream of the first image; each group of the image data includes M rows of image data, or each group of the image data includes at least one image data block; M is a positive integer; the processor 110 is configured to generate a read address for each group of the image data obtained after the processor 110 groups the image data, when the processor 110 writes a group of the image data into the corresponding storage space, the read address being used to indicate the address in the storage space of each image data in the group that needs to be read out in blocks; the processor 110 is configured to read each image data in a group of the image data from the storage space according to the read address generated by the processor 110, and write each image data in the next group of image data into the storage space of the read image data.

[0267] Optionally, in the embodiment of the present application, each group of image data includes M lines of image data;

[0268] The processor 110 is specifically configured to calculate, based on the number of image data blocks in the row direction of the first image, addresses of target image data to be read out from a group of the image data in the storage space;

[0269] The processor 110 is specifically configured to generate a read address corresponding to the target image data according to the address of the target image data in the storage space.

[0270] Optionally, in the embodiment of the present application, the processor 110 is specifically configured to calculate, using a first formula, an address in the storage space of an i+1th target image data to be read out from a group of image data according to the number of image data blocks in a row direction in the first image and the number of rows of image data corresponding to each image data block; i∈[0, tile_num*M-1], where i is an integer;

[0271] Among them, the first formula is: An(i) = (i*tile_num^n-1)% (tile_num*M-1)+1, tile_num is the number of image data blocks in the row direction of the image, and n is equal to the group where the image data is located minus 1.

[0272] Optionally, in an embodiment of the present application, the processor 110 is specifically used to read the i-th target image data from the storage space according to the read address corresponding to the i-th target image data, and write the j-th image data in the next group of image data into the storage space from which the i-th target image data has been read; j∈[1, tile_num*M].

[0273] Optionally, in the embodiment of the present application, each group of the image data includes at least one image data block;

[0274] The processor 110 is specifically configured to calculate an address in the storage space of target image data to be read out from a group of the image data based on the number of image data blocks in the row direction of the first image and the number of image data rows corresponding to one image data block;

[0275] The processor 110 is specifically configured to generate a read address corresponding to the target image data according to the address of the target image data in the storage space.

[0276] Optionally, in the embodiment of the present application, the processor 110 is specifically configured to calculate, using a second formula, an address of an i-th target image data to be read out in a group of the image data in the storage space according to the number of image data blocks in a row direction of the image and the number of rows of image data corresponding to one image data block; i∈[0, tile_height*tile_num-1], where i is a positive integer;

[0277] The second formula is: An(i)=(i*tile_height^n-1)%(tile_height*tile_num-1)+1; tile_num is the number of image data blocks of the first image in the row direction, and tile_height is the number of rows of image data contained in one image data block.

[0278] Optionally, in an embodiment of the present application, the processor 110 is specifically configured to merge two adjacent image data in a group of the image data, and write each merged image data into the storage space of the SPRAM through one clock cycle.

[0279] An electronic device provided in an embodiment of the present application groups an image data stream of a first image; each group of image data streams includes M rows of image data, or each group of image data streams includes at least one image data block; M is a positive integer; for each group of image data streams, when writing a group of image data into a corresponding storage space, a read address is generated, the read address being used to indicate the address in the storage space of each image data in the group of image data that needs to be read out in blocks; according to the read address, each image data in the group of image data is read out from the storage space, and each image data in the next group of image data is written into the storage space of the read image data. Through this method, the electronic device can generate the required read address, and when reading image data from the storage space according to the read address, quickly write new image data to the storage location corresponding to the read image data, thereby achieving alternating reading and writing of image data in a storage space, thereby efficiently writing image data in rows and reading it in blocks, achieving row-block conversion of the image data stream and saving storage space.

[0280] It should be understood that in an embodiment of the present application, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042, and the graphics processor 1041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 107 includes a touch panel 1071 and at least one of other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include two parts: a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0281] The memory 109 can be used to store software programs and various data. The memory 109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 109 may include a volatile memory or a non-volatile memory, or the memory x09 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM), and a direct memory bus random access memory (DRRAM). The memory 109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0282] Processor 110 may include one or more processing units. Optionally, processor 110 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 110.

[0283] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned image data processing method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0284] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0285] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned image data processing method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0286] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0287] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned image data processing method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0288] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0289] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0290] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A method for processing image data, the method comprising: grouping an image data stream of a first image; Each group of the image data streams includes M lines of image data, or each group of the image data streams includes at least one image data block; M is a positive integer; For each group of the image data, when writing a group of the image data into a corresponding storage space, generating a read address, the read address being used to indicate an address in the storage space of each image data in the group of the image data that needs to be read out in blocks; According to the read address, each image data in a group of the image data is read out from the storage space, and each image data in the next group of image data is written into the storage space of the read-out image data.

2. The method according to claim 1, wherein: Each group of the image data streams includes M lines of image data; generating a read address includes: Calculating addresses of target image data to be read out in a group of the image data in the storage space based on the number of image data blocks in the row direction of the first image; A read address corresponding to the target image data is generated according to the address of the target image data in the storage space.

3. The method according to claim 2, wherein: The calculating, based on the number of image data blocks in the row direction of the image, addresses of target image data to be read out in a group of the image data in the storage space comprises: Using the first formula, according to the number of image data blocks in the row direction of the image and the number of rows of image data corresponding to each of the image data blocks, the address of the i+1th target image data to be read out in a group of the image data in the storage space is calculated; i∈[0, tile_num*M-1], and i is an integer; Among them, the first formula is: An(i)=(i*tile_num^n-1)%(tile_num*M-1)+1, tile_num is the number of image data blocks in the row direction of the image, and n is equal to the group where the image data is located minus 1.

4. The method according to claim 3, wherein: The step of reading each image data in a group of the image data from the storage space according to the read address, and writing each image data in a next group of the image data into the storage space of the read image data, comprises: According to the read address corresponding to the i+1th target image data, the i+1th target image data is read out from the storage space, and the jth image data in the next group of image data is written into the storage space where the i+1th target image data has been read out; j∈[1, tile_num*M].

5. The method according to claim 1, wherein: Each group of the image data streams comprises at least one image data block; The generating of the read address comprises: Calculate the address of target image data to be read out in a group of the image data in the storage space based on the number of image data blocks in the row direction in the first image and the number of rows of image data corresponding to one image data block; A read address corresponding to the target image data is generated according to the address of the target image data in the storage space.

6. The method according to claim 5, wherein: The calculating, based on the number of image data blocks in the row direction of the image and the number of rows of image data corresponding to one image data block, the address of the target image data to be read out in the storage space of a group of the image data comprises: The second formula is used to calculate the address of the i-th target image data to be read out in the storage space in a group of the image data according to the number of image data blocks in the row direction of the image and the number of rows of the image data corresponding to one image data block; i∈[0, tile_height*tile_num-1], and i is a positive integer; Among them, the second formula is: An(i)=(i*tile_height^n-1)%(tile_height*tile_num-1)+1; tile_num is the number of image data blocks of the first image in the row direction, and tile_height is the number of rows of image data contained in an image data block.

7. The method according to claim 1, wherein: Writing a set of the image data into a corresponding storage space comprises: Two adjacent image data in a group of the image data are merged, and each merged image data is written into the storage space of the SPRAM through one clock cycle.

8. An image data processing device, the device comprising: Splitting module, generating module and processing module, where: The splitting module is used to group the image data stream of the first image; each group of the image data stream includes M lines of image data, or each group of the image data stream includes at least one image data block; M is a positive integer; The generating module is used for generating a read address for each group of the image data obtained after the grouping by the splitting module, when the processing module writes a group of the image data into a corresponding storage space, wherein the read address is used to indicate the address in the storage space of each image data in the group of the image data that needs to be read out in blocks; The processing module is used to read out each image data in a group of the image data from the storage space according to the read address generated by the generating module, and write each image data in the next group of image data into the storage space of the read image data.

9. The device according to claim 8, wherein: Each group of image data includes M lines of image data; The generating module is specifically configured to calculate the address of the target image data to be read out in a group of the image data in the storage space based on the number of image data blocks in the row direction in the first image; The generating module is specifically configured to generate a read address corresponding to the target image data according to the address of the target image data in the storage space.

10. The device according to claim 9, wherein: The generating module is specifically used to calculate the address of the i+1th target image data to be read out in a group of the image data in the storage space by using the first formula according to the number of image data blocks in the row direction in the first image and the number of rows of image data corresponding to each of the image data blocks; i∈[0, tile_num*M-1], and i is an integer; Among them, the first formula is: An(i)=(i*tile_num^n-1)%(tile_num*M-1)+1, tile_num is the number of image data blocks in the row direction of the image, and n is equal to the group where the image data is located minus 1.

11. The device according to claim 10, wherein: The processing module is specifically configured to read the i-th target image data from the storage space according to the read address corresponding to the i-th target image data, and write the j-th image data in the next group of image data into the storage space from which the i-th target image data has been read; j∈[1, tile_num*M].

12. The device according to claim 8, wherein: Each group of the image data includes at least one image data block; The generating module is specifically used to calculate the address of the target image data to be read out in a group of the image data in the storage space based on the number of image data blocks in the row direction in the first image and the number of rows of image data corresponding to one image data block; The generating module is specifically configured to generate a read address corresponding to the target image data according to the address of the target image data in the storage space.

13. The device according to claim 12, wherein: The generating module is specifically used to calculate the address of the i-th target image data to be read out in the storage space in a group of the image data by using the second formula according to the number of image data blocks in the row direction of the image and the number of rows of image data corresponding to one image data block; i∈[0, tile_height*tile_num-1], and i is a positive integer; Among them, the second formula is: An(i)=(i*tile_height^n-1)%(tile_height*tile_num-1)+1; tile_num is the number of image data blocks of the first image in the row direction, and tile_height is the number of rows of image data contained in an image data block.

14. The device according to claim 8, wherein: The processing module is specifically used to merge two adjacent image data in a group of the image data, and write each merged image data into the storage space of the SPRAM through one clock cycle.

15. An electronic device comprising a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the image processing method according to any one of claims 1 to 7 are implemented.

16. A readable storage medium storing a program or instruction, wherein the program or instruction, when executed by a processor, implements the steps of the image processing method according to any one of claims 1 to 7. 17 . A computer program product, wherein the computer program product is stored in a storage medium and is executed by at least one processor to implement the image processing method according to claim 1 .

18. A chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the image processing method according to any one of claims 1 to 7.

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