Multi-mode phase-locked loop

Abstract

A voltage-controlled oscillator having a high-performance mode and a low-power mode, includes a first switch having first and second terminals, a second switch having first and second terminals, a first power supply circuit coupled to the first terminal of the first switch, a second power supply circuit coupled to the first terminal of the second switch, a first oscillator coupled to the second terminal of the first switch, a second oscillator coupled to the second terminal of the second switch, wherein the second terminal of the first switch is coupled to the second terminal of the second switch, the first power supply is coupled to a first voltage source, the second power supply is coupled to a second voltage source, the first voltage source is configured to provide a greater voltage than the second voltage source, and the first oscillator and the second oscillator are cross-coupled with each other.

Description

MULTI-MODE PHASE-LOCKED LOOPBACKGROUND

[0001] Embodiments of this disclosure relate to a multi-mode phase-locked loop with a voltage-controlled oscillator consuming different amounts of power in each of multiple modes.

[0002] Phase-locked loop (PLL) circuits may include a voltage-controlled oscillator (VCO), and such PLLs may be found in a wide variety of high-frequency applications. Integrated circuits designed for use in wireless communication networks and systems may include one or more PLLs each having a VCO. Multiple PLLs consume more power and more chip area than a single PLL.SUMMARY

[0003] According to one aspect of this disclosure, a VCO having a first mode of operation and a second mode of operation includes a first switch having a first terminal and a second terminal, a second switch having a first terminal and a second terminal, a first power supply circuit coupled to the first terminal of the first switch, a second power supply circuit coupled to the first terminal of the second switch, a first oscillator coupled to the second terminal of the first switch, and a second oscillator coupled to the second terminal of the second switch, wherein the second terminal of the first switch is coupled to the second terminal of the second switch, the first power supply circuit is coupled to a first voltage source, the second power supply circuit is coupled to a second voltage source, and the first voltage source is configured to provide a greater voltage than the second voltage source.

[0004] According to another aspect of this disclosure, a method of operating a VCO includes transitioning to a low-power mode from a high-performance mode, and transitioning to a high-performance mode from a low-power mode, wherein transitioning to the low-power mode includes increasing a resistance between a high-performance power supply and an oscillator from a first resistance to a second resistance, coupling a low-power power supply to the oscillator, increasing the resistance between the high-performance power supply and the oscillator from the second resistance to a third resistance; and decoupling the high- performance power supply from the oscillator, and wherein transitioning to the high- performance mode includes coupling the high-performance power supply to the oscillator, decreasing the resistance between the high-performance power supply and the oscillator fromthe third resistance to the second resistance, decoupling the low-power power supply from the oscillator, and decreasing the resistance between the high-performance power supply and the oscillator from the second resistance to the first resistance.

[0005] According to yet another aspect of this disclosure, a multi-mode phase-locked loop includes a phase frequency detector, a loop filter coupled to the phase frequency detector, a VCO coupled to the loop filter, and a divider coupled between the VCO and the phase frequency detector, wherein the VCO comprises a high-performance power supply circuit switchably coupled to an oscillator circuit, and a low-power power supply circuit switchably coupled to the oscillator circuit.

[0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 is a high-level block diagram of a phase-locked loop including a voltage- controlled oscillator.

[0009] FIG. 2 is a high-level diagram of a multi-mode phase-locked loop in accordance with this disclosure.

[0010] FIG. 3 A is a schematic diagram of an illustrative oscillator in accordance with this disclosure.

[0011] FIG. 3B is a waveform diagram showing the output of the oscillator of FIG. 3 A as a function of the oscillator’s power supply voltage.

[0012] FIG. 4 is a schematic diagram of a multi-mode phase-locked loop having crosscoupled oscillators in accordance with this disclosure.

[0013] FIG. 5A is a schematic diagram of a first portion of a multi-mode phase-locked loop (the second portion being in FIG. 5B) in accordance with this disclosure.

[0014] FIG. 5B is a schematic diagram of a second portion of the multi-mode phase- locked loop of FIG. 5 A, in accordance with this disclosure.

[0015] FIG. 6 is a flow diagram of a method of operating a voltage-controlled oscillator in accordance with this disclosure.

[0016] FIG. 7 is a flow diagram of a method of transitioning a VCO from a high- performance mode to a low-power mode while maintaining phase lock in accordance with this disclosure.

[0017] FIG. 8 is a flow diagram of a method of transitioning a VCO from a low-power mode to a high-performance mode while maintaining phase lock in accordance with this disclosure.

[0018] Various illustrative embodiments of this disclosure will be described with reference to the accompanying drawings.DETAILED DESCRIPTION

[0019] An important design consideration for many electronic products in general, and in particular for mobile products that rely on battery power, is reducing the amount of power needed to operate those products.

[0020] There are several well-known general techniques for reducing power consumption, such as but not limited to, reducing the magnitude of a power supply voltage, reducing operating frequency, reducing parasitic capacitance, and reducing leakage currents, for example. Additional approaches to reduction of power consumption, in accordance with this disclosure, are available in modern wireless communication products such as, but not limited to, Wi-Fi and 5G communication products, for example. In order to meet the specifications for such wireless communication products and their various modes of operation, two or more PLLs may be required. For example, a first PLL may be used for an active mode of operation, and a second PLL may be used for a low-power mode of operation. However, two PLLs occupy more chip area than a single PLL, fast switching between two PLLs is difficult, and there may be a higher level of power consumption during the switching between two PLLs because both PLLs may be “on” during the transition from active mode to low- power mode.

[0021] Various embodiments in accordance with this disclosure provide a multi-mode PLL that may replace two single-mode PLLs, advantageously resulting in both reduced power consumption and, for integrated circuit implementations, reduced chip area. Reduced chip area may result not just from replacing the circuitry of two PLLs with a single PLL in accordance with this disclosure, but also from reducing the number of control signals routed to two different PLLs, and the simpler local oscillator routing resulting from replacing two PLLs with one.

[0022] Various embodiments in accordance with this disclosure provide a single PLL that supports switching between a high-performance mode and a low-power mode while maintaining phase lock with an input reference signal.

[0023] PLLs are used in applications such as, but not limited to, wireless communication, data transmission, audio processing, and instrumentation. A PLL locks the frequency and phase of its output signal to that of an input reference signal. A PLL may achieve the frequency and phase locking by comparing the phases of its output signal to an input reference signal, generating an error signal indicative of the phase difference between the input reference signal and the PLL output signal, and adjusting the frequency of the output signal via the operation of a VCO. In this way, synchronized operation between the input reference signal and the VCO output signal may be obtained.

[0024] FIG. 1 illustrates a general architecture of a PLL suitable for implementation on an integrated circuit. A PLL is an electronic control system that is widely used in various applications, including communications, signal processing, and frequency synthesis. A PLL is designed to generate an output signal with a frequency and phase that is locked, or synchronized, to an input reference signal. A typical PLL includes three main components, i.e., a phase detector (or phase comparator), a VCO, and a feedback loop, and of those three, the VCO typically consumes the most power. The phase detector compares the phase of the input reference signal and the output signal generated by the VCO. Generally, the phase detector produces an error signal that represents the phase difference between the reference signal and the VCO output signal. The error signal is then filtered and provided to the VCO, which generates an output signal with a frequency that is proportional to the voltage of the error signal. The VCO frequency is adjusted frequently during operation based on the error signal to minimize the phase difference between the input reference signal and the VCO output signal. This feedback loop completes the PLL system by connecting the output of theVCO back to the phase detector. This feedback mechanism allows the PLL to adjust the VCO frequency until the input and output signals are in phase lock. It is noted that, in some PLL implementations, the VCO output signal may undergo one or more signal processing operations, and the output of those signal processing operations is presented to the phase detector rather than the VCO output being directly presented to the phase detector. By way of example, and not limitation, the frequency of the VCO output signal may be reduced by a “divide-by-N” circuit. Divide-by-N circuits may be configured to divide the frequency of the VCO output signal by fixed number N. Alternatively, divide-by-N circuits may be configured as programmable (or presettable) counters where the value of N can be changed. In some PLLs, a phase frequency detector is used rather than a phase detector. Like a phase detector, the phase frequency detector generates a signal indicative of the phase difference between an input reference signal and the PLL’s feedback signal which is derived from the VCO. However, the phase frequency detector also compares the frequency of the reference and feedback signals to provide additional information about the frequency difference. Such frequency information may be used for control and tracking algorithms within a PLL.

[0025] FIG. l is a high-level block diagram of an illustrative phase-locked loop 100 including a voltage-controlled oscillator. A phase-locked loop 100 receives a reference signal FREF at a node 102. Node 102 is coupled to a first input terminal of a phase detector 104. Phase detector 104 has an output terminal coupled to a node 106. Node 106 is further coupled to an input terminal of a low-pass filter 108. Low-pass filter 108 has an output terminal coupled to a node 110. Node 110 is further coupled to an input terminal of a voltage- controlled oscillator 112. Voltage-controlled oscillator 112 has an output terminal coupled to a node 114. Node 114 is further coupled to an input terminal of a divide-by-N counter 116. Divide-by-N counter 116 has an output terminal coupled to a node 118. Node 118 is further coupled to a second input terminal of phase detector 104.

[0026] FIG. 2 is a high-level diagram of a multi-mode phase-locked loop 200 in accordance with this disclosure. Like the phase-locked loop of FIG. 1, multi-mode phase- locked loop 200 includes a phase frequency detector block 202, a low-pass filter block 204, a VCO 206, and a divide-by-N circuit 208 in the feedback path of the loop. Phase frequency detector block 202 detects both phase and frequency differences between an input reference signal and the feedback signal of multi-mode phase-locked loop 200.

[0027] Unlike the phase-locked loop of FIG. 1, multi-mode phase-locked loop 200 includes a multi-mode power supply 210. Multi-mode power supply 210 is configured to transition from a first voltage to a second voltage such that the output signal of VCO 206 transitions from a high-swing high-performance mode to a low-swing low-power mode without losing phase lock with the input reference signal of multi-mode phase-locked loop 200.

[0028] FIGs. 3 A and 3B show, respectively, an oscillator suitable for use in a VCO, configured with a variable power supply, and a waveform diagram of the oscillator’s output signal. More particularly, the oscillator provides a high-swing, high-performance output signal at a first power supply voltage, and a low-swing, low-power output signal at a second power supply voltage that is lower than the first power supply voltage. Together FIGs. 3 A and 3B illustrate the reduction in voltage swing of the oscillator’s output signal due to a corresponding reduction in the oscillator’s power supply voltage. The reduction of the oscillator’s output voltage swing results in a reduction of the oscillator’s power consumption. As used herein, “high-performance mode” refers to operating a VCO’s oscillator at a first power supply voltage, and “low-power mode” refers to operating the VCO’s oscillator at a second power supply voltage that is lower in magnitude than the first power supply voltage.

[0029] FIG. 3 A is a schematic diagram of an oscillator 300 coupled to a variable power supply. In this example, the variable power supply is a variable, e.g.., adjustable, resistor disposed between a DC power supply node and oscillator 300. A first transistor 302 is coupled drain-to-source between a node 304 and a tail tune circuit 306. A second transistor 308 is coupled drain-to-source between a node 310 and tail tune circuit 306. A first capacitor 312 and a second capacitor 314 are coupled in series between node 304 and node 310. A first inductor 316 is coupled between node 304 and a node 317, and a second inductor 318 is coupled between node 317 and node 310. A variable resistor 320 is coupled between a power supply node, VDD, and node 317. In this example, first transistor 302 is an n-channel field effect transistor (FET) and second transistor 308 is an n-channel FET.

[0030] Still referring to FIG. 3 A, tail tune circuit 306 includes an inductor and a capacitor coupled in parallel between the respective source terminals of first transistor 302 and second transistor 308 and a ground node.

[0031] FIG. 3B is a waveform diagram 350 showing the output signal of oscillator 300 of FIG. 3 A as a function of the oscillator’s power supply voltage. As can be seen in FIG. 3B, when the power supply voltage applied to oscillator 300 is at a level 352, the voltage swing of the oscillator output signal is greater than the voltage swing of the oscillator output signal when the power supply voltage applied to oscillator 300 is at a level 354. In other words, the magnitude of the oscillator’s output signal voltage swing increases as its power supply voltage is made greater.

[0032] FIG. 4 is a schematic diagram of an illustrative multi-mode phase-locked loop having cross-coupled oscillators, in accordance with this disclosure, having a first switch 402 having a first terminal and a second terminal, and a second switch 404 having a first terminal and a second terminal. The second terminal of first switch 402 is coupled to the second terminal of second switch 404.

[0033] The illustrative multi-mode phase-locked loop of FIG. 4 further includes a first power supply circuit 406 coupled to the first terminal of first switch 402, and a second power supply circuit 408 coupled to the first terminal of second switch 404. The illustrative multimode phase-locked loop, further includes a first oscillator circuit 410 coupled to the second terminal of first switch 402, and a second oscillator circuit 412 coupled to the second terminal of second switch 404. In the illustrative embodiment of FIG. 4, first oscillator circuit 410 and second oscillator circuit 412 are cross-coupled with each other (through switch 434), as shown in the figure. It is noted that each of first oscillator circuit 410 and second oscillator circuit 412 is configured as oscillator 300 shown in FIG. 3 A.

[0034] Still referring to FIG. 4, the illustrative multi-mode phase-locked loop further includes a third switch 414 and a fourth switch 416. Note that switch 434, which may be configured as a double-pole single-throw switch and implemented for example with field effect transistors, is used to reconfigure the multi-mode phase-locked loop between a dualcore VCO mode and a single-core VCO mode. Dual-core VCO mode, i.e., high-performance mode, is configured with switch 434 being closed, and single-core VCO mode, i.e., low-power mode, is configured with switch 434 being open. In one example, third switch 414 is closed, fourth switch 416 is closed, and switch 434 is closed for dual-core VCO operation. In this example, first switch 402 is closed and second switch 404 is open. In this state, i.e., configuration, first power supply circuit 406 is coupled to first oscillator circuit 410 and second oscillator circuit 412. In this configuration, the second terminal of first switch 402 iscoupled to first oscillator circuit 410 through closed third switch 414. Likewise, in this configuration, the second terminal of first switch 402 is coupled to second oscillator circuit 412 through closed fourth switch 416. Switch 434 is opened to configure the multi-mode PLL for low-power operation.

[0035] Still referring to FIG. 4, first power supply circuit 406 includes a first low dropout voltage regulator 418 having an output terminal coupled to the gate terminal of a first p- channel FET 420. The source terminal of first p-channel FET 420 is coupled to a first voltage source. In this illustrative embodiment, the first voltage source is a 1.8-volt DC supply, but other embodiments are not limited to a particular voltage. It would be appreciated that the aforementioned 1.8 volt DC supply nominally provides 1.8 volts, i.e., it is understood that there may be some variation from this voltage due to non-ideal factors including, but not limited to, manufacturing tolerances. The drain terminal of first p-channel FET 420 is coupled to a first terminal of a variable resistor 422, and further coupled to a first input terminal of first low dropout voltage regulator 418. A second input terminal of first low dropout voltage regulator 418 is coupled to a first reference voltage source. In this illustrative embodiment, the first reference voltage source provides a voltage that is less than that of the first voltage source, and nominally provides a 1.5 volt DC level. A second terminal of variable resistor 422 is coupled to the first terminal of first switch 402.

[0036] Still referring to FIG. 4, a second power supply circuit 408 includes a second low dropout voltage regulator 424 having an output terminal coupled to the gate terminal of a second p-channel FET 426. The source terminal of second p-channel FET 426 is coupled to a second voltage source. In this illustrative embodiment, the second voltage source is a 0.95- volt DC supply, but other embodiments are not limited to a particular voltage. It will be appreciated that the aforementioned 0.95 volt DC supply nominally provides 0.95 volts, i.e., it is understood that there may be some variation from this voltage due to non-ideal factors including, but not limited to, manufacturing tolerances. The drain terminal of second p- channel FET 426 is coupled to a first terminal of a variable resistor 428, and further coupled the first terminal of second switch 404. A second terminal of variable resistor 428 is coupled to a first input terminal of second low dropout voltage regulator 424, and further coupled to a first terminal of a variable resistor 430. A second terminal of variable resistor 430 is coupled to the ground node. A second input terminal of second low dropout voltage regulator 424 is coupled to a first reference voltage source. In this illustrative embodiment, the secondreference voltage source provides a voltage that is less than that of the second voltage source, and nominally provides a 0.4 volt DC level.

[0037] Still referring to FIG. 4, a capacitor 432 is coupled between the ground node and the second terminal of first switch 402 and the second terminal of second switch 404. The capacitance value of capacitor 432 may be chosen to help smooth the transition of the voltage supplied to first oscillator circuit 410 and second oscillator circuit 412 from high-to-low and low-to-high.

[0038] The configurations of first switch 402, second switch 404, variable resistor 422, variable resistor 428, and variable resistor 430, and changes thereto, are described below with reference to FIGs. 6, 7, and 8, which describe the method of transitioning between high- performance and low-power modes of operation.

[0039] FIGs. 5A-5B are two halves of a schematic diagram of a multi-mode phase-locked loop in accordance with this disclosure.

[0040] FIG. 5 A illustrates a first half of a multi-mode phase-locked loop showing a phase frequency detector block 502, and a low-pass filter block 504. The specific details of low- pass filter block 504 shown in FIG. 5 A are for illustrative purposes and are not to be considered a limitation on the design of PLLs in accordance with this disclosure.

[0041] FIG. 5B illustrates a second half of the multi-mode phase-locked loop, in accordance with this disclosure, showing a first power supply circuit 506, and a second power supply circuit 508. First power supply circuit 506 is coupled to a first terminal of a first switch 510, and second power supply circuit 508 is coupled to a first terminal of a second switch 512. A second terminal of first switch 510 is coupled to a second terminal of second switch 512. The second terminal of first switch 510 and the second terminal of second switch 512 are coupled to VCO 514. An output terminal of VCO 514 is coupled to a PLL feedback path that includes a divide-by-N circuit 516.

[0042] Still referring to FIG. 5B, divide-by-N circuit 516 may be any suitable circuit for dividing the frequency of the VCO output signal by a factor of N, including but not limited to a counter. Divide-by-N circuit 516 may be programmable such that the factor N may be changed. Such circuits may be referred to as a programmable divide-by-N counter, or as a presettable divide-by-N counter.

[0043] Still referring to FIG. 5B, first power supply circuit 506 includes a low dropout voltage regulator 518, a variable resistor 520 coupled between an output terminal of low dropout voltage regulator 518 and a first input terminal of low dropout voltage regulator 518, and a resistor 521 coupled between the first input terminal of low dropout voltage regulator 518 and a ground node. A second input terminal of low dropout voltage regulator 518 is coupled to a first reference voltage, which is nominally a first DC level.

[0044] Still referring to FIG. 5B, second power supply circuit 508 includes a low dropout voltage regulator 522, a variable resistor 524 coupled between an output terminal of low dropout voltage regulator 522 and a first input terminal of low dropout voltage regulator 522, and a resistor 526 coupled between the first input terminal of low dropout voltage regulator 522 and the ground node. A second input terminal of low dropout voltage regulator 522 is coupled to a second reference voltage, which is nominally a second DC level. In this illustrative embodiment, low dropout voltage regulator 518 is coupled to a first voltage source (not shown), low dropout voltage regulator 522 is coupled to a second voltage source (not shown), and the first voltage source provides a voltage that is greater the voltage provided by the second voltage source. Further, the first reference voltage coupled to the second input terminal of low dropout voltage regulator 518 is greater than the second reference voltage coupled to the second input terminal of low dropout voltage regulator 522. As explained in greater detail below, and with reference to FIGs. 6-8, various embodiments of this disclosure provide a multi-mode PLL that can transition between a high-swing, high-performance mode, and a low-swing, low-power mode while maintaining phase lock with an input reference signal.

[0045] In various PLL implementations, temperature compensation circuitry is added to help maintain the desired performance of the PLL over a range of temperatures. Various embodiments in accordance with the disclosure further include temperature compensation circuitry.

[0046] FIG. 6 is a flow diagram of a method 600 of operating a voltage-controlled oscillator in accordance with this disclosure. Method 600 includes transitioning at 602 to a low-power mode from a high-performance mode, and transitioning at 604 to a high- performance mode from a low-power mode. In this illustrative embodiment, transitioning to a low-power mode from a high-performance mode, involves smoothly reducing the supply voltage that is supplied to the oscillator of a VCO in a PLL from a first voltage to a secondvoltage wherein the second voltage is less than the first voltage by switching from a first power supply circuit to a second power supply circuit while maintaining the PLL’s phase lock with an input reference signal (see FIG. 7). And, in this illustrative embodiment, transitioning to a high-performance mode from a low-power mode involves smoothly increasing the supply voltage that is supplied to the oscillator of a VCO in a PLL from a second voltage to a first voltage wherein the first voltage is greater than the second voltage by switching from a second power supply circuit to a first power supply circuit while maintaining the PLL’s phase lock with an input reference signal (see FIG. 8). Various embodiments of this disclosure are not limited to a particular order of transitioning between low-power mode and high performance mode. Whether the VCO power supply in a multi-mode PLL, in accordance with this disclosure, initially starts in the high-performance mode or in the low-power mode is a designer’s choice.

[0047] FIG. 7 is a flow diagram of a method 700 of transitioning a VCO in a PLL from a high-performance mode to a low-power mode while maintaining phase lock in accordance with this disclosure. Method 700 includes increasing, at 702, a resistance between a high- performance power supply and an oscillator from a first resistance to a second resistance, and coupling, at 704, a low-power power supply to the oscillator. Method 700 further includes increasing, at 706, the resistance between the high-performance power supply and the oscillator from the second resistance to a third resistance, and decoupling, at 708, the high- performance power supply from the oscillator.

[0048] FIG. 8 is a flow diagram of a method 800 of transitioning a VCO in a PLL from a low-power mode to a high-performance mode while maintaining phase lock in accordance with this disclosure. Method 800 includes coupling, at 802, the high-performance power supply to the oscillator, and decreasing, at 804, the resistance between the high-performance power supply and the oscillator from the third resistance to the second resistance. Method 800 further includes decoupling, at 806, the low-power power supply from the oscillator, and decreasing, at 808, the resistance between the high-performance power supply and the oscillator from the second resistance to the first resistance.

[0049] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only.

[0050] A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to a person skilled in the pertinent art that this disclosure can also be employed in a variety of other applications.

[0051] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

[0052] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0053] As used herein, the term “nominal / nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and / or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances.

[0054] As used herein, the acronym “SoC” refers to System-on-a-Chip. An SoC is an integrated circuit (IC) with the circuits and subsystems to implement a particular system, such as, for example, a smartphone, smart watch, or other product of similar complexity. Various embodiments in accordance with this disclosure may be implemented on an SoC.

[0055] Integrated circuits in accordance with this disclosure may be implemented in any suitable process technology including, but not limited to, complementary metal oxide semiconductor (CMOS). Such integrated circuits may be custom designed, synthesized, or a combination of both. And, embodiments of the architecture and circuits disclosed herein may be implemented on a single chip, or partitioned over one or more chips, or one or more die in a single package, or one or more chiplets in a single package, or any combination of these or similar integrated circuit and packaging configurations.

[0056] Further, embodiments of the architecture and circuits disclosed herein may be implemented with one or more chiplets. In some embodiments, chiplets may be disposed on an interposer in a single package. The interposer may be a silicon interposer. Various embodiments in accordance with this disclosure may be implemented with any suitable packaging technology.

[0057] Various integrated circuit embodiments of this disclosure may further include “power-down” circuitry to reduce leakage currents that result in unwanted power consumption.

[0058] In some embodiments, one or more circuit blocks or subsystems of an integrated circuit in accordance with this disclosure may be configured to enter a power-down state responsive to one or more signals indicating that those circuit blocks or subsystems do not have work to do at the moment. A power-down state refers to an integrated circuit operating in a manner that reduces or eliminates at least some unneeded power consumption. The power-down state may be achieved by any suitable circuit technique. In one illustrative circuit technique, the power-down state may be achieved by stopping the clock signal or signals to a circuit block or subsystem of the integrated circuit. Stopping the clock signal or signals may be appropriate if the circuit block is implemented with a static logic design in CMOS process technology. However, since static logic design may consume more chip area than dynamic logic design, a different trade-off that may make stopping the clocks an appropriate approach may be to ensure that the period for which the clocks are stopped is less than the period of time for the charge on one or more dynamic nodes in the circuit block or subsystem to decay to a point that the logic state on the one or more dynamic nodes cannot be reliably maintained. Such charge decay may occur through mechanisms such as, e.g., leakage, or capacitive coupling to nearby circuit nodes. Alternatively, the power-down state may be achieved by decoupling the circuit block or subsystem from one or more power supply nodes. Forexample, the circuit block or subsystem may have a transistor coupled in series between itself and a positive power supply node such that the circuit block or subsystem is decoupled from the positive power supply node when the transistor is turned off. In another example, the circuit block or subsystem may have a transistor coupled in series between itself and a ground supply node such that the circuit block or subsystem is decoupled from the ground supply node when the transistor is turned off. In still another example, the circuit block or subsystem may have a first transistor coupled in series between itself and a positive power supply node, and a second transistor coupled in series between itself and a ground supply node such that the circuit block or subsystem is decoupled from the positive power supply node and from the ground supply node when both the first and second transistors are turned off.

[0059] Power consumption is related to the magnitude of a circuit’s power supply voltage, and is also related to its operating frequency. Many integrated circuits, including but not limited to those designed for use in wireless communication, are designed to be used in products that rely, at least in part, on batteries for power. Since extending battery life is important to customers of such products, it is also important for designers to reduce the amount of power needed for the integrated circuits to perform their intended functions, and to provide hardware support for integrated circuits to enter one of one or more states in which unneeded power consumption is reduced or eliminated. In further examples of low-power operation, it is possible to reduce power consumption in circuits that are unused or unneeded for a period of time, by reducing the magnitude of the circuit’s power supply voltage, reducing its operating frequency, or both.Some Embodiments

[0060] In one embodiment, a VCO having a first mode of operation and a second mode of operation, includes a first switch having a first terminal and a second terminal, a second switch having a first terminal and a second terminal, a first power supply circuit coupled to the first terminal of the first switch, a second power supply circuit coupled to the first terminal of the second switch, a first oscillator coupled to the second terminal of the first switch, and a second oscillator coupled to the second terminal of the second switch, wherein the second terminal of the first switch is coupled to the second terminal of the second switch, the first power supply circuit is coupled to a first voltage source, the second power supply circuit is coupled to a second voltage source, and the first voltage source is configured to provide a greater voltage than the second voltage source. The first and second switches may beimplemented with any structures suitable for use on an integrated circuit. The first switch may be implemented by a FET, such as a p-channel FET, an n-channel FET, or a p-channel FET in parallel with an n-channel FET. Likewise, the second switch may be implemented by a FET, such as a p-channel FET, an n-channel FET, or a p-channel FET in parallel with an n-channel FET. A MEMS (microelectricalmechanical) switch can also be used to implement the first switch and / or the second switch.

[0061] In some embodiments, the first oscillator and the second oscillator are crosscoupled with each other.

[0062] In some embodiments, the first oscillator includes a first transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a first node and a first tail tune circuit, a second transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a second node and the first tail tune circuit, a first capacitor and a second capacitor, and a first inductor and a second inductor, wherein the first tail tune circuit is coupled to the source terminal of the first transistor, coupled to the source terminal of the second transistor, and coupled to a ground node, wherein the gate terminal of the first transistor is coupled to the drain terminal of the second transistor, and the gate terminal of the second transistor is coupled to the drain terminal of the first transistor, wherein the first capacitor and the second capacitor are coupled in series with each other between the drain terminal of the first transistor and the drain terminal of the second transistor, and wherein the first inductor and the second inductor are coupled in series with each other between the drain terminal of the first transistor and the drain terminal of the second transistor.

[0063] In some embodiments, the second oscillator includes a third transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a third node and a second tail tune circuit, a fourth transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a fourth node and the second tail tune circuit, a third capacitor and a fourth capacitor, and a third inductor and a fourth inductor, wherein the second tail tune circuit is coupled to the source terminal of the first transistor, coupled to the source terminal of the second transistor, and coupled to the ground node, wherein the gate terminal of the third transistor is coupled to the drain terminal of the fourth transistor, and the gate terminal of the fourth transistor is coupled to the drain terminal of the third transistor, wherein the third capacitor and the fourth capacitor are coupled in series with each other between the drain terminal of the third transistor and the drain terminal of thefourth transistor, and wherein the third inductor and the fourth inductor are coupled in series with each other between the drain terminal of the third transistor and the drain terminal of the fourth transistor.

[0064] In some embodiments, the gate terminal of the first transistor is coupled to the gate terminal of the fourth transistor, and the gate terminal of the second transistor is coupled to the gate terminal of the third transistor.

[0065] In some embodiments, the VCO further includes a third switch having a first terminal coupled to the first oscillator, and a second terminal coupled to the second terminal of the first switch; and a fourth switch having a first terminal coupled to the second oscillator, and a second terminal coupled to the second terminal of the first switch.

[0066] In some embodiments, the first power supply circuit includes a first low-dropout voltage regulator, a first p-channel transistor having a gate terminal coupled to an output terminal of the first low-dropout voltage regulator, and a first variable resistor having a first terminal coupled to a drain terminal of the first p-channel transistor; and the second power supply circuit includes a second low-dropout voltage regulator, a second p-channel transistor having a gate terminal coupled to an output terminal of the second low-dropout voltage regulator, and a second variable resistor having a first terminal coupled to a drain terminal of the second p-channel transistor. Although some embodiments use p-channel transistors, those of ordinary skill in the art will recognize that other types of transistors can be used.

[0067] In some embodiments of the first power supply circuit, a source terminal of the first p-channel transistor is coupled to the first voltage source; and in some embodiments of the second power supply circuit, a source terminal of the second p-channel transistor is coupled to the second voltage source.

[0068] In some embodiments, the VCO further includes a third variable resistor coupled to the second variable resistor, and further coupled to the second low-dropout voltage regulator.

[0069] In some embodiments, the third variable resistor is further coupled to a ground node.

[0070] In another embodiment, a method of operating a VCO includes transitioning to a low-power mode from a high-performance mode, and transitioning to a high-performancemode from a low-power mode. In some embodiments, transitioning to a low-power mode from a high-performance mode includes increasing a resistance between a high-performance power supply and an oscillator from a first resistance to a second resistance, coupling a low- power power supply to the oscillator, increasing the resistance between the high-performance power supply and the oscillator from the second resistance to a third resistance, and decoupling the high-performance power supply from the oscillator. In some embodiments, transitioning to the high-performance mode includes coupling the high-performance power supply to the oscillator, decreasing the resistance between the high-performance power supply and the oscillator from the third resistance to the second resistance, decoupling the low-power power supply from the oscillator, and decreasing the resistance between the high-performance power supply and the oscillator from the second resistance to the first resistance.

[0071] In some embodiments, increasing the resistance between the high-performance power supply and the oscillator from a first resistance to a second resistance includes adjusting a variable resistor. In some embodiments, increasing the resistance between the high- performance power supply and the oscillator from the second resistance to the third resistance includes adjusting the variable resistor. In some embodiments, the variable resistor may be implemented as one or more field effect transistors, the resistance of which may be adjusted by changing the applied gate voltage to at least one of the one or more field effect transistors.It will be recognized by those skilled in the art that other circuit arrangements for implementing a variable resistor are known in the art.

[0072] In some embodiments, decreasing the resistance between the high-performance power supply and the oscillator from the third resistance to the second resistance includes adjusting a variable resistor. In some embodiments, decreasing the resistance between the high-performance power supply and the oscillator from the second resistance to the first resistance comprises adjusting the variable resistor.

[0073] In some embodiments, coupling the low-power power supply to the oscillator includes closing a second switch, and coupling the high-performance power supply to the oscillator includes closing a first switch. In some embodiments, the first switch may be implemented as one or more field effect transistors, where switching on and off is accomplished by turning the field effect transistors on and off by controlling the voltage applied to the corresponding gate terminals of those field effect transistors. Likewise, the second switch may be implemented as one or more field effect transistors. In alternativeembodiments, the first switch and / or the second switch may be implemented as a MEMS (microelectricalmechanical) switch. In still other alternative embodiments, any suitable switching mechanism may be used.

[0074] In some embodiments, decoupling the high-performance power supply from the oscillator includes opening a first switch, and decoupling the low-power power supply from the oscillator includes opening a second switch.

[0075] In a further embodiment, a multi-mode phase-locked loop includes a phase frequency detector, a loop filter coupled to the phase frequency detector, a VCO coupled to the loop filter, and a divider coupled between the VCO and the phase frequency detector, wherein the VCO includes a high-performance power supply circuit switchably coupled to an oscillator circuit, and a low-power power supply circuit switchably coupled to the oscillator circuit.

[0076] In some embodiments of the multi-mode phase-locked loop, the high-performance power supply circuit is coupled to a first voltage source, the low-power power supply circuit is coupled to a second voltage source, and the first voltage source is configured to provide a greater voltage than the second voltage source.

[0077] In some embodiments of the multi-mode phase-locked loop, the high-performance power supply circuit includes a first low-dropout voltage regulator, and the low-power power supply circuit includes a second low-dropout voltage regulator.

[0078] In some embodiments of the multi-mode phase-locked loop, the oscillator circuit includes a first oscillator and a second oscillator cross-coupled with each other.

[0079] In some embodiments of the multi-mode phase-locked loop, a first switch is disposed between the high-performance power supply circuit and the oscillator circuit, and a second switch is disposed between the low-power power supply circuit and the oscillator circuit.

[0080] The foregoing description of the specific embodiments will so reveal the general nature of this disclosure that others can, by applying knowledge within the skill of the art, readily modify and / or adapt for various applications of such specific embodiments, without undue experimentation, and without departing from the general concept of this disclosure. Therefore, such adaptations and modifications are intended to be within the meaning andrange of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of this specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0081] Embodiments of this disclosure have been described above with the aid of functional building blocks illustrating the embodiment of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0082] The Summary and Abstract sections may set forth one or more but not all embodiments of this disclosure as contemplated by the inventor(s), and thus, are not intended to limit this disclosure and the subjoined claims in any way.

[0083] The breadth and scope of the present disclosure should not be limited by any of the above-described illustrative embodiments, but should be defined only in accordance with the subjoined claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A voltage-controlled oscillator (VCO) having a first mode of operation and a second mode of operation, comprising: a first switch having a first terminal and a second terminal; a second switch having a first terminal and a second terminal; a first power supply circuit coupled to the first terminal of the first switch; a second power supply circuit coupled to the first terminal of the second switch; a first oscillator coupled to the second terminal of the first switch; and a second oscillator coupled to the second terminal of the second switch, wherein the second terminal of the first switch is coupled to the second terminal of the second switch, the first power supply circuit is coupled to a first voltage source, the second power supply circuit is coupled to a second voltage source, and the first voltage source is configured to provide a greater voltage than the second voltage source.

2. The VCO of claim 1, wherein the first oscillator and the second oscillator are crosscoupled with each other.

3. The VCO of claim 1, wherein the first oscillator comprises: a first transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a first node and a first tail tune circuit; a second transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a second node and the first tail tune circuit; a first capacitor and a second capacitor; and a first inductor and a second inductor, wherein the first tail tune circuit is coupled to the source terminal of the first transistor, coupled to the source terminal of the second transistor, and coupled to a ground node, wherein the gate terminal of the first transistor is coupled to the drain terminal of the second transistor, and the gate terminal of the second transistor is coupled to the drain terminal of the first transistor, wherein the first capacitor and the second capacitor are coupled in series with each other between the drain terminal of the first transistor and the drain terminal of the second transistor, andwherein the first inductor and the second inductor are coupled in series with each other between the drain terminal of the first transistor and the drain terminal of the second transistor.

4. The VCO of claim 3, wherein the second oscillator comprises: a third transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a third node and a second tail tune circuit; a fourth transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a fourth node and the second tail tune circuit; a third capacitor and a fourth capacitor; and a third inductor and a fourth inductor, wherein the second tail tune circuit is coupled to the source terminal of the first transistor, coupled to the source terminal of the second transistor, and coupled to the ground node, wherein the gate terminal of the third transistor is coupled to the drain terminal of the fourth transistor, and the gate terminal of the fourth transistor is coupled to the drain terminal of the third transistor, wherein the third capacitor and the fourth capacitor are coupled in series with each other between the drain terminal of the third transistor and the drain terminal of the fourth transistor, and wherein the third inductor and the fourth inductor are coupled in series with each other between the drain terminal of the third transistor and the drain terminal of the fourth transistor.

5. The VCO of claim 4, wherein the gate terminal of the first transistor is coupled to the gate terminal of the fourth transistor, and the gate terminal of the second transistor is coupled to the gate terminal of the third transistor.

6. The VCO of claim 2, further comprising: a third switch having a first terminal coupled to the first oscillator, and a second terminal coupled to the second terminal of the first switch; and a fourth switch having a first terminal coupled to the second oscillator, and a second terminal coupled to the second terminal of the first switch.

7. The VCO of claim 2, wherein the first power supply circuit comprises:a first low-dropout voltage regulator; a first p-channel transistor having a gate terminal coupled to an output terminal of the first low-dropout voltage regulator; and a first variable resistor having a first terminal coupled to a drain terminal of the first p-channel transistor; and wherein the second power supply circuit comprises: a second low-dropout voltage regulator; a second p-channel transistor having a gate terminal coupled to an output terminal of the second low-dropout voltage regulator; and a second variable resistor having a first terminal coupled to a drain terminal of the second p-channel transistor.

8. The VCO of claim 7, wherein a source terminal of the first p-channel transistor is coupled to the first voltage source, and a source terminal of the second p-channel transistor is coupled to the second voltage source.

9. The VCO of claim 7, further comprising: a third variable resistor coupled to the second variable resistor, and further coupled to the second low-dropout voltage regulator.

10. The VCO of claim 9, wherein the third variable resistor is further coupled to a ground node.

11. A method of operating a voltage-controlled oscillator (VCO), comprising: transitioning to a low-power mode from a high-performance mode; and transitioning to a high-performance mode from a low-power mode, wherein transitioning to the low-power mode comprises: increasing a resistance between a high-performance power supply and an oscillator from a first resistance to a second resistance; coupling a low-power power supply to the oscillator; increasing the resistance between the high-performance power supply and the oscillator from the second resistance to a third resistance; anddecoupling the high-performance power supply from the oscillator; wherein transitioning to the high-performance mode comprises: coupling the high-performance power supply to the oscillator; decreasing the resistance between the high-performance power supply and the oscillator from the third resistance to the second resistance; decoupling the low-power power supply from the oscillator; and decreasing the resistance between the high-performance power supply and the oscillator from the second resistance to the first resistance.

12. The method of claim 11, wherein increasing the resistance between the high-performance power supply and the oscillator from a first resistance to a second resistance comprises adjusting a variable resistor, and increasing the resistance between the high-performance power supply and the oscillator from the second resistance to the third resistance comprises adjusting the variable resistor.

13. The method of claim 11, wherein decreasing the resistance between the high-performance power supply and the oscillator from the third resistance to the second resistance comprises adjusting a variable resistor, and decreasing the resistance between the high-performance power supply and the oscillator from the second resistance to the first resistance comprises adjusting the variable resistor.

14. The method of claim 11, wherein coupling the low-power power supply to the oscillator comprises closing a second switch, and coupling the high-performance power supply to the oscillator comprises closing a first switch.

15. The method of claim 11, wherein decoupling the high-performance power supply from the oscillator comprises opening a first switch, and decoupling the low-power power supply from the oscillator comprises opening a second switch.

16. A multi-mode phase-locked loop, comprising: a phase frequency detector; a loop filter coupled to the phase frequency detector;a voltage-controlled oscillator (VCO) coupled to the loop filter; and a divider coupled between the VCO and the phase frequency detector, wherein the VCO comprises a high-performance power supply circuit switchably coupled to an oscillator circuit, and a low-power power supply circuit switchably coupled to the oscillator circuit.

17. The multi-mode phase-locked loop of claim 16, wherein the high-performance power supply circuit is coupled to a first voltage source, the low-power power supply circuit is coupled to a second voltage source, and the first voltage source is configured to provide a greater voltage than the second voltage source.

18. The multi-mode phase-locked loop of claim 17, wherein the high-performance power supply circuit comprises a first low-dropout voltage regulator, and the low-power power supply circuit comprises a second low-dropout voltage regulator.

19. The multi-mode phase-locked loop of claim 16, wherein the oscillator circuit comprises a first oscillator and a second oscillator cross-coupled with each other.

20. The multi-mode phase-locked loop of claim 16, wherein a first switch is disposed between the high-performance power supply circuit and the oscillator circuit, and a second switch is disposed between the low-power power supply circuit and the oscillator circuit.

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