Stackable chip rack and related methods

Abstract

A rack (10) for holding a plurality of chips (32) is provided. The rack (10) includes a receptacle portion (12) having receptacle sides 16 defining a first periphery (15). The receptacle portion (12) also has a plurality of chip cradles (18) that are configured to hold the plurality of chips (32). The rack (10) further includes a skirt portion (14) operatively coupled to and extending away from the receptacle portion (12). The skirt portion (14) has skirt sides (28) defining a second periphery (27) that is larger than the first periphery (15). The second periphery (27) is configured to receive at least portion of a receptacle portion (12) of a second rack (10a).

Description

STACKABLE CHIP RACK AND RELATED METHODSCross Reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Application Serial No. 63 / 516,135 filed July 27, 2023 (pending), the disclosure of which is incorporated by reference herein in its entirety.Technical Field

[0002] This invention relates generally to racks and methods for storing and transporting chips, and more particularly, to stackable racks and related methods, where the stackable racks are configured to be stackable with, and without, chips being placed inside of them.Background

[0003] Gaming chips, such as poker chips, are commonly used in various gaming environments, ranging from casual home games to professional tournaments. To facilitate the handling and storage of these chips, specialized chip racks have been developed.

[0004] Chip racks (hereafter “racks”) are typically designed to hold a specific number of chips in a neat and organized manner. For example, U.S. Patent Number 3,306,462 discloses a rack that uses ribs to hold the chips in place when stored within the rack. The ribs allow the chips to be stored in either a vertical or horizontal position, thereby making the chips more accessible to users.

[0005] To use the chips in the rack, or to store the chips in the rack after use, a user will typically hold the bottom of the rack and move the rack to a desired location, such as a card table, a gaming table, a storage closet, or the like. In manysituations, such as in casinos where a large number of racks are used, it may be advantageous to stack multiple racks on top of each other when transporting and / or storing the racks, whether empty or filled with chips.

[0006] With conventional racks, it is difficult and / or unsafe to stack multiple racks on top of each other. In some convention rack designs, two racks may be stacked by having the bottom of an upper rack simply resting along the tops of chips that are present in a lower rack. However, without any additional support between the two connecting racks, the chips themselves provide insufficient stability when storing and / or transporting the racks as the two racks are not positively engaged with one another. As such, the racks lack the necessary structural support to securely stack the chips, leaving the chips susceptible to being misplaced or stolen during transportation and / or storage. Furthermore, conventional racks that are empty are not designed to be securely stacked. Instead, the conventional racks merely sit one on top of the other, but are easily topple because they are not positively engaged with one another.

[0007] Accordingly, there is a need for a rack that addresses the limitations of the existing designs. Specifically, there is a need for racks that may be secured stacked regardless of whether the racks are holding chips or empty. Such racks would offer enhanced versatility, improved chip safety during transportation, and allow for more efficient storage and transportation of the chips.Summary of the Invention

[0008] In an aspect of the invention, a rack for holding a plurality of chips is provided. The rack includes a receptacle portion having receptacle sides defining a first periphery. The receptacle portion also has a plurality of chip cradles that areconfigured to hold the plurality of chips. The rack further includes a skirt portion operatively coupled to and extending away from the receptacle portion. The skirt portion has skirt sides defining a second periphery that is larger than the first periphery. The second periphery is configured to receive at least portion of a receptacle portion of a second rack.

[0009] In an embodiment of the invention, each of the chip cradles has a curved surface for supporting the plurality of chips. In another embodiment of the invention, the curved surface is recessed relative to a top edge surface of the receptacle portion, and the curved surface does not extend below a bottom of the receptacle portion. In another embodiment of the invention, the rack has a longitudinal axis, and each chip cradle extends transverse to the longitudinal axis.

[0010] In another embodiment of the invention, the receptacle sides have a height Hi and the skirt sides have a height H2 that is greater than Hi. In another embodiment of the invention, the skirt portion is operatively coupled to the receptacle portion such that the skirt sides form a rim around and extend away from a bottom of the first periphery of the receptacle portion.

[0011] In another embodiment of the invention, the second periphery is configured to receive the receptacle portion of the second rack such that when the second rack holds another plurality of chips, a bottom of the skirt sides of the rack is a distance Di from a top of skirt sides of the second rack, and such that when the second rack is not holding the other plurality of chips, the bottom of the skirt sides of the rack is a distance D2 from the top of the skirt sides of the second rack. The distance D2 may be less than the distance Di. In another embodiment of the invention, the distanceD2 may be zero.

[0012] In another embodiment of the invention, the first periphery is configured to receive a skirt portion of a third rack such that when the rack holds the plurality of chips, the top of the skirt sides of the rack is a distance Di from a bottom of skirt sides of the third rack, and such that when the rack is not holding the plurality of chips, the top of the skirt sides of the rack is a distance D2 from the bottom of the skirt sides of the third rack. The distance D2 may be less than the distance Di. In another embodiment of the invention, the distance D2 may be zero.

[0013] In another aspect of the invention, a plurality of racks for holding a plurality of chips is provided. The plurality of racks includes at least a first rack and a second rack. Each respective rack includes a receptacle portion having receptacle sides defining a first periphery. The receptacle portion also has a plurality of chip cradles that are configured to hold the plurality of chips. Each respective rack further includes a skirt portion operatively coupled to and extending away from the receptacle portion. The skirt portion has skirt sides defining a second periphery that is larger than the first periphery. The second periphery of the first rack is configured to receive at least a portion of the receptacle portion of the second rack.

[0014] In an embodiment of the invention, each of the first and second racks has a longitudinal axis, and each chip cradle extends transverse to the longitudinal axis of the respective first and second racks. In another embodiment of the invention, each chip cradle has a curved surface for supporting the plurality of chips. In another embodiment of the invention, the receptacle sides of respective ones of the first and second racks have a height Hi and the skirt sides of respective ones of the first and second racks have a height H2 that is greater than Hi.

[0015] In another embodiment of the invention, the second periphery of the first rack is configured to receive the receptacle portion of the second rack such thatwhen the second rack holds the plurality of chips, a bottom of the skirt sides of the first rack is a distance Di from a top of the skirt sides of the second rack, and such that when the second rack is not holding the plurality of chips, the bottom of the skirt sides of the first rack is a distance D2 from the top of the skirt sides of the second rack, the distance D2 being less than the distance Di.

[0016] In another embodiment of the invention, the plurality of racks further includes a third rack. The first periphery of the first rack is configured to receive a skirt portion of the third rack such that when the first rack holds the plurality of chips, the top of the skirt sides of the first rack is a distance Di from a bottom of skirt sides of the skirt portion of the third rack, and such that when the first rack is not holding the plurality of chips, the top of the skirt sides of the first rack is a distance D2 from the bottom of the skirt sides of the third rack. The distance D2 may be less than the distance Di.

[0017] In another aspect of the invention, a method for holding a plurality of chips with one or more racks is provided. The method includes providing a plurality of racks including at least a first rack and a second rack. Each rack includes a receptacle portion having receptacle sides defining a first periphery. The receptacle portion also has a plurality of chip cradles that are configured to hold the plurality of chips. Each rack further includes a skirt portion operatively coupled to and extending away from the receptacle portion. The skirt portion has skirt sides defining a second periphery that is larger than the first periphery. The method further includes placing at least a portion of the receptacle portion of the second rack through the second periphery of the first rack and into the skirt portion of the first rack.

[0018] In an embodiment of the invention, when placing the second rack under the first rack includes placing the second rack under the first rack such that when thesecond rack holds the plurality of chips, a bottom of the skirt sides of the first rack is a distance Di from a top of the skirt sides of the second rack, and such that when the second rack is not holding the plurality of chips, the bottom of the skirt sides of the first rack is a distance D2 from the top of the skirt sides of the second rack. The distance D2 may be less than the distance Di.

[0019] In another embodiment of the invention, the plurality of racks further includes a third rack and the method further includes placing the third rack on top of the first rack such that the second periphery of the third rack receives at least a portion of the receptacle portion of the first rack.

[0020] In another embodiment of the invention, when placing the third rack on top of the first rack includes placing the third rack on top of the first rack such that when the first rack holds the plurality of chips, a bottom of the skirt sides of the third rack is a distance Di from a top of the skirt sides of the first rack, and such that when the first rack is not holding the plurality of chips, the bottom of the skirt sides of the third rack is a distance D2 from and the top of the skirt sides of the first rack. The distance D2 may be less than the distance D2.

[0021] Other aspects, features, benefits, and advantages of the present invention will become apparent to a person of skill in the art from the detailed description of various embodiments with reference to the accompanying drawing figures, all of which comprise part of the disclosure.Brief Description of the Drawings

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with ageneral description of the invention given above, and the detailed description given below, serve to explain the invention.

[0023] Fig. 1 is a front perspective view of a rack according to one embodiment of the invention.

[0024] Fig. 2 is a front perspective view of the rack of Fig. 1 holding chips.

[0025] Fig. 3 is a front perspective view of the rack of Fig. 1 stacked onto a second( / '.e., bottom) rack.

[0026] Fig. 4 is a cross-sectional view of the rack of Fig. 1 taken along line 4-4.

[0027] Fig. 5 is a cross-sectional view of the rack of Fig. 4, taken on line 5-5.

[0028] Fig. 6 is a cross-sectional view of the racks of Fig. 3 taken along line 6-6, with a plurality of chips stored inside the second rack.

[0029] Fig. 7 is a cross-sectional view of the rack of Fig. 1 stacked onto a second( / '.e., bottom) rack, with no chips stored inside the second rack.

[0030] Fig. 8 is a cross-sectional view of the racks in Fig. 6 taken along line 8-8.

[0031] Fig. 9 is a cross-sectional view of the racks in Fig. 7 taken along line 9-9.

[0032] Fig. 10 is a cross-sectional view of the rack holding chips, with a cover placed on top of the rack.

[0033] Fig. 11 is a front perspective view of a rack according to another embodiment of the invention that includes a corner legged portion.

[0034] Fig. 12 is a front perspective view of a rack according to another embodiment of the invention that includes base portion without corners.Detailed Description

[0035] With reference to the drawing figures, this section describes particular embodiments and their detailed construction and operation. Throughout thespecification, reference to “one embodiment,” “an embodiment,” or “some embodiments” means that a particular described feature, structure, or characteristic may be included in at least one embodiment. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” or “in some embodiments” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the described features, structures, and characteristics may be combined in any suitable manner in one or more embodiments. In view of the disclosure herein, those skilled in the art will recognize that the various embodiments can be practiced without one or more of the specific details or with other methods, components, materials, or the like. In some instances, well-known structures, materials, or operations are not shown or not described in detail to avoid obscuring aspects of the embodiments.

[0036] As used herein, the term “chips” may refer to casino chips, poker chips, gaming chips for games other than poker (e.g., blackjack, roulette, craps, etc.), custom designed chips, a combination of different types of chips, and / or any other disk-shaped or round object. As used herein, the term “rack” is to refer to any structure or apparatus capable of being used to store, hold, and / or transport chips.

[0037] Fig. 1 illustrates a front perspective view of a rack 10 according to one aspect of the invention. The rack 10 may be stacked upon another rack 10a such that the two stacked racks 10, 10a are not readily dislodged from one another when they are acted upon by a transverse load, for example. The rack 10 may be stacked upon another rack 10a whether the other rack 10a is holding chips or the other rack 10a is empty. In either condition (holding chips or empty), one rack 10 may be stacked onto another rack 10a. The stacked racks 10, 10a may be characterized as “nesting” where a top portion of a bottom rack 10a is at least partially surrounded bya lower portion of a top rack 10. The nesting feature allows chips to be more securely transported and the racks 10, 10a to be more efficiently stored, whether filled with chips or empty.

[0038] In an embodiment, the rack 10 may be made using a polycarbonate material. In other embodiments, the rack 10 may be made using an acrylic material or another material known in the art. In some embodiments, the material of the rack 10 may be transparent. In some embodiments, the material of the rack 10 may be semi-transparent. For example, the material may be tinted using a particular color so as to distinguish that rack 10 from other racks 10 that are completely transparent or tinted using a different color.

[0039] In some embodiments, the dimensions of the rack 10 may be selected such that the rack 10 may hold a predetermined number of chips. In some embodiments, one or more dimensions of the rack 10 may be based on the number of chip cradles included in the rack 10. In some embodiments, the rack 10 may have a length between 168 millimeters (mm) and 268 mm, a width between 31 and 131 mm, and a height between 20 mm and 130 mm. That is to say, the rack 10 may have a length between 168 millimeters (mm) and 268 mm, a width between 31 and 131 mm, and a height between 25 and 75 mm. To provide a specific example, the dimensions of rack 10 may be 218.6 mm x 81 .43 mm x 47.5 mm. To provide another specific example, the dimensions of rack 10 may be 208.67 mm x 80.45 mm x 47.5 mm. It is to be understood that these dimensional ranges and specific dimensions are provided by way of example. In practice, any number of different dimensions may be used.

[0040] With continued reference to Fig. 1 , the rack 10 includes a receptable portion12 and a skirt portion 14. The receptable portion 12 includes receptacle sides 16that define a first or receptacle periphery 15. The receptacle periphery 15 represents a boundary outlined by the bottom edges of the receptacle sides 16. In some embodiments, such as that shown in Fig. 1 , the receptacle sides 16 may include a front side 16a, a rear side 16b (not visible in Fig. 1 ), a right side 16c, and a left side 16d (not visible in Fig. 1 ).

[0041] In some embodiments, receptacle periphery 15 may be generally rectangular such that opposing front and rear receptacle sides 16a, 16b have a first length, and opposing right and left receptacle sides 16c, 16d have a second length that is different than the first length. In the example shown in Fig. 1 , the first length of the front and rear receptacle sides 16a, 16b is shorter than the second length of the left and right receptacle sides 16c, 16d.

[0042] The receptacle portion 12 includes a plurality of chip cradles 18 for holding chips. The plurality of chip cradles 18 may be arrayed along the receptacle portion 12. In some embodiments, such as that shown in Fig. 1 , the plurality of chip cradles 18 may include an array of five chip cradles 18. It is to be understood that this is provided by way of example, and that in practice, the plurality of chip cradles may include an array of less than five chip cradles 18 or more than five chip cradles 18.

[0043] Each respective chip cradle 18 may include a curved or concave surface 20 that extends transverse to a longitudinal axis 22 of the rack 10. The curved or concave surface 20 is configured to receive chips placed inside each respective chip cradle 18. In some embodiments, the radius of the curved or concave surface 20 closely matches the radius of the chip placed in the chip cradle 18 so that that chip is largely supported around at least a portion of its circumference. The curved or concave surface 20 of each chip cradle 18 is recessed relative to a top edge surface 24 of the receptacle portion 12. Each respective chip cradle 18 may further include apair of opposing end surfaces 26 disposed adjacent to the right and left receptacle sides 16c, 16d. In Fig. 1 , only one of the two opposing end surfaces 26 is visible for each respective chip cradle 18.

[0044] The skirt portion 14 includes skirt sides 28 defining a skirt periphery 27 (also referred to as a second periphery 27) that is larger than the receptacle periphery 15. The skirt periphery 27 represents a boundary outlined by the bottom edges of the skirt sides 28.

[0045] In some embodiments, such as that shown in Fig. 1 , the skirt sides 28 include a front side 28a, a rear side 28b (not visible in Fig. 1), a right side 28c, and a left side 28d (not visible in Fig. 1). In some embodiments, skirt periphery 27 may be generally rectangular such that opposing front and rear skirt sides 28a, 28b have a first length, and opposing right and left skirt sides 28c, 28d have a second length that is different than the first length. In the example shown in Fig. 1 , the first length of the front and rear skirt sides 28a, 28b is shorter than the second length of the left and right skirt sides 28c, 28d.

[0046] The skirt portion 14 may be operatively coupled to the receptacle portion 12. In one embodiment, the skirt portion 14 may be integrally formed with the receptacle portion 12 such as shown in Fig. 1. In other embodiments, the skirt portion 14 may be removably attached to the receptacle portion 12. The rack 10 may be constructed using a molding technique or another technique known in the art. In some embodiments, the rack 10 may be constructed such that a rim or ledge 30 is formed at a position where the receptacle portion 12 and the skirt portion 14 connect. The rim 30 permits a second rack 10a to be stacked on top of the rack 10 such that a skirt portion of the second rack 10a rests upon or near the rim 30.

[0047] The receptacle sides 16 have a height Hi and the skirt sides 28 have a height H2. In some embodiments, the height H2 is greater than Hi. For example, the receptacle sides 16 may have a height a height Hi between 10 mm and 25 mm, and the skirt sides 28 may have a height H2 between 24 mm and 36 mm. To provide a specific example, the receptacle sides 16 may have a height Hi of 16.75 mm and the skirt sides 28 may have a height H2 of 30.75 mm.

[0048] The rack 10 may include an inner cavity 31 defined by at least the skirt portion 14. The inner cavity 31 of the rack 10 is configured so that at least part of the receptacle portion 12 of another (i.e., bottom) rack 10a may be received inside the inner cavity 31 the rack 10. For example, the receptable portion 12 of another rack 10a may be inserted into the inner cavity of the rack 10 such that chips stored within the other rack 10a are encapsulated within the inner cavity by at least portions of the skirt sides 28 of the rack 10. The encapsulation improves the security of the chips during transport as the chips may not be readily accessed.

[0049] Fig. 2 illustrates a front perspective view of the rack 10 holding a plurality of chips 32. In the embodiment shown in Fig. 2, each chip cradle 18 may hold twenty chips 32, such that the rack 10 holds one hundred chips 32. As can be appreciated by a person of ordinary skill in the art, a variable number of chips 32 may be held by each chip cradle 18 and the rack 10 overall, depending on the width of the rack 10, the number of chip cradles 18, the size of the chips 32, etc.

[0050] Fig. 3 illustrates a front perspective view of the rack 10 stacked on top of a second rack 10a. The skirt periphery 27 of rack 10 is configured to receive the receptacle portion 12 of the second rack 10a. For example, the receptacle periphery 15 of the other (bottom) rack 10a is smaller than the skirt periphery 27 of the (top) rack 10 allowing a user to place the (top) rack 10 onto the second (bottom) rack 10a,such that the skirt sides 28 of the (top) rack 10 receives at least a portion of the receptacle portion 12 of the second (bottom) rack 10a.

[0051] Fig. 4 illustrates a cross-sectional view of the rack 10. As described above, the curved surface 20 of respective chip cradles 18 is recessed relative to the top edge surface 24 of the receptacle portion 12.

[0052] In some embodiments, such as that shown in Fig. 4, a depth of the recession of the curved surface 20 is such that the recession does not extend below the rim 30. In some embodiments, the height H2 of the skirt sides 28 may be greater than the height Hi of the receptacle sides 16.

[0053] Fig. 5 illustrates a cross-sectional view of the rack 10. In some embodiments, the rack 10 may include one or more support beams 36 disposed in the inner cavity 31 to provide additional support and stability to the rack 10. In some embodiments, the rack 10 may include spaced-apart support beams 36 extending between adjacent chip cradles 18 as shown in Fig. 4. In some embodiments, the rack 10 may include spaced-apart support beams 36 that extend between the end chip cradle 18 and the front and rear skirt sides 28a, 28b as shown in Fig. 5.

[0054] Fig. 6 illustrates a cross-sectional of the rack 10 stacked on top of the second rack 10a, with a plurality of chips 32 stored inside the second rack 10a. When the rack 10 is stacked onto the second rack 10a, there is a distance Di between the bottom of the skirt sides 28 of the rack 10 and the top of the skirt sides of the second rack 10a. The distance Di may vary depending on the dimensions of each respective rack 10. However, the distance Di should be small enough such that the chips 32 remain encapsulated inside of the stacked racks 10, 10a.

[0055] Fig. 7 illustrates a cross-sectional view of the rack 10 stacked onto the second rack 10a, with no chips stored inside the second rack 10a. When the rack 10is stacked onto the second rack 10a, there is a second distance D2 between the bottom of the skirt sides 28 of the rack 10 and the top of the skirt sides of the second rack 10a. The distance D2 may vary depending on the dimensions of each respective rack 10, but is less than the distance Di shown in Fig. 6. In some embodiments, the distance D2 may be zero or nearly zero, such that the bottom of the skirt sides 28 of rack 10 contacts or nearly contacts the top of the skirt sides 28 of the second rack 10a. For example, the distance D2 shown in Fig. 7 is zero as the bottom of the skirt sides 28 of rack 10 is contacting the top of the skirt sides of the second rack 34.

[0056] Fig. 8 illustrates a cross-sectional view of the rack 10 stacked on top of the second rack 10a, with chips 32 stored inside the second rack 10a. Fig. 9 illustrates a cross-sectional view of the rack 10 stacked on top of the second rack 10a, with no chips 32 stored inside the second rack 10a.

[0057] Fig. 10 illustrates a cross-sectional view of the rack 10 holding the plurality of chips 32, with a cover 40 placed onto the rack 10. The cover 40 may be configured to encapsulate the chips 32, such that the chips 32 are secured and protected during storage and / or transportation. The cover 40 may be used in situations where the rack 10 is not stacked with other racks (e.g., rack 10a, etc.), and in situations where the rack 10 is the top rack in a stack of other racks 10, 10a.

[0058] In some embodiments, the cover 40 may be a rectangular shape, such as is shown in Fig. 10. In other embodiments, the cover 40 may be another shape, so long as the cover 40 secures the chips 32 in the rack 10. In some embodiments, the cover 40 may be made using polycarbonate. In other embodiments, the cover 40 may be made using acrylic or another material known in the art. In some embodiments, the material of the cover 40 may be transparent or translucent. Insome embodiments, the material of the cover 40 may be opaque or a solid material, so as to hide or obscure the chips 32 stored inside the rack 10. In some embodiments, the material of the cover 40 may be polycarbonate with a tinted color.

[0059] The disclosure also contemplates a method for holding a plurality of chips. The method may include providing a plurality of racks including at least a first rack, such as rack 10, and a second rack, such as rack 10a (Step 1 ). Each of the first and second racks 10, 10a may include the receptacle portion 12 having receptacle sides 16 that define the first periphery 15. The receptacle portion 12 also has the plurality of chip cradles 18 that are configured to hold the plurality of chips 32.

[0060] The method further includes placing the receptacle portion 12 of the second rack 10a into the receptacle portion 12 of the first rack 10 such that at least a portion of the second rack 10a nests inside the rack 10. (Step 2). In some embodiments, the method includes placing the second rack 10a under the first rack 10 such that when the second rack 10a holds the plurality of chips 32, there is the distance Di between a bottom of the skirt sides 28 of the first rack 10 and a top of the skirt sides 28 of the second rack 10a, and such that when the second rack 10a is not holding the plurality of chips 32, there is the distance D2 between the bottom of the skirt sides 28 of the first rack 10 and the top of the skirt sides 28 of the second rack 10a, the distance D2 being less than the distance Di.

[0061] In some embodiments, the plurality of racks may further include a third rack 10a. In these embodiments, the method may further include placing the receptacle portion 12 of the third rack 10a into the receptacle portion 12 of the first rack 10a such that at least a portion of the third rack 10a nests inside the second rack 10a(Step 3). In some embodiments, the method may include placing the third rack 10a onto the first rack 10a such that when the first rack 10a holds the plurality ofchips 32, there is a distance Di between a bottom of the skirt sides 28 of the third rack 10a and a top of the skirt sides 28 of the first rack 10a, and such that when the first rack is not holding the plurality of chips, there is the distance D2 between the bottom of the skirt sides 28 of the third rack 10a and the top of the skirt sides 28 of the first rack 10a, the distance D2 being less than the distance Di. As can be appreciated by a person of ordinary skill in the art, this is provided by way of example. In practice, any number of racks may be stacked together using the method described herein.

[0062] In some embodiments, a depth of the recession of the curved surface 20 is such that the recession does not extend below the rim 30. Furthermore, in some embodiments, the height H2 of the skirt sides 28 may be greater than the height Hi of the receptacle sides 16. For example, the height H2 of the skirt sides 28 may be greater than the height Hi of the receptacle sides 16 such that when the rack 10 is stacked with other racks 10 (e.g., rack 10a, etc.), the chips 32 stored inside of the racks 10 will not contact the bottom surface of the chip cradles 18. This prevents wear and tear on the chips 32 relative to configurations where the chips contact a bottom surface of a top rack 10.

[0063] Fig. 11 is a front perspective view of a rack 10b according to another aspect of the invention. In this embodiment, the rack 10b may include a corner legged portion 42, rather than the skirt portion 14. The legged portion 42 may include a set of legs 44. Dimensions of the legs 44 may vary depending on the embodiment.

[0064] Fig. 12 is a front perspective view of a rack 10c according to another aspect of the invention. In this embodiment, the rack 10c may include a base portion 46, rather than the skirt portion 14 or the legged portion 42. The base portion 46 may include wall portions 48 along each side of the rack 10c that extend along a bottomedge of the receptacle portion 12 of the rack 10c. The wall portions 48 do not extend along corner regions of the base portion 46.

[0065] In the embodiments described in both Figs. 11 and 12, the racks 10b, 10c are still configured to be stacked with one or more other racks (e.g., rack 10, 10a, 10b, 10c, etc.). For example, the racks 10b, 10c in these embodiments may be configured to nest with another rack 10a, 10b, 10c such that the racks 10b, 10c engage with one another to resist transverse force. As can be appreciated by a person of ordinary skill in the art, other structural configurations may be implemented so long as the configurations (e.g., racks 10, 10a, 10b, 10c) do not disrupt the rack from stacking / nesting in the manner described herein.

[0066] In this way, the racks 10, 10a described herein are configured to efficiently and securely store chips, and are configured such that multiple racks 10, 10a may be stacked regardless of whether chips 32 are stored inside them. For example, the chips are securely stored because the racks 10, 10a are not readily dislodged from one another when acted upon by a transverse load.

[0067] The foregoing disclosure provides illustration and description but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments.

[0068] No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items and may be used interchangeably with “one or more.” Furthermore, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.), and may be used interchangeablywith “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Also, as used herein, the terms “has,” “have,” “having,” or the like are intended to be open-ended terms. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise.

[0069] While one or more embodiments of the present invention have been described in detail, it should be apparent that modifications and variations thereto are possible, all of which fall within the true spirit and scope of the invention. Therefore, the foregoing is intended only to be illustrative of the principles of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not intended to limit the invention to the exact construction and operation shown and described. Accordingly, all suitable modifications and equivalents may be included and considered to fall within the scope of the invention, defined by the following claim or claims.

Claims

WHAT IS CLAIMED IS:1 . A rack for holding a plurality of chips, comprising: a receptacle portion having receptacle sides defining a first periphery, the receptacle portion also having a plurality of chip cradles that are configured to hold the plurality of chips; and a skirt portion operatively coupled to and extending away from the receptacle portion, the skirt portion having skirt sides defining a second periphery that is larger than the first periphery, wherein the second periphery is configured to receive at least a portion of a receptacle portion of a second rack.

2. The rack of claim 1 , wherein each of the chip cradles has a curved surface for supporting the plurality of chips.

3. The rack of claim 2, wherein the curved surface is recessed relative to a top edge surface of the receptacle portion, and wherein the curved surface does not extend below a bottom of the receptacle portion.

4. The rack of any of the preceding claims, wherein the rack has a longitudinal axis, and wherein each chip cradle extends transverse to the longitudinal axis.

5. The rack of any of the preceding claims, wherein the receptacle sides have a height Hi and the skirt sides have a height H2 that is greater than Hi.

6. The rack of any of the preceding claims, wherein the skirt portion is operatively coupled to the receptacle portion such that the skirt sides form a rim around and extend away from a bottom of the first periphery of the receptacle portion.7 The rack of claim 1 , wherein the second periphery is configured to receive the receptacle portion of the second rack such that when the second rack holds another plurality of chips, a bottom of the skirt sides of the rack is a distance Di from a top of skirt sides of the second rack, and such that when the second rack is not holding the other plurality of chips, the bottom of the skirt sides of the rack is a distance D2 from the top of the skirt sides of the second rack, the distance D2 being less than the distance Di.

8. The rack of claim 7, wherein the distance D2is zero.9 The rack of claim 1 , wherein the first periphery is configured to receive a skirt portion of a third rack such that when the rack holds the plurality of chips, the top of the skirt sides of the rack is a distance Di from a bottom of skirt sides of the third rack, and such that when the rack is not holding the plurality of chips, the top of the skirt sides of the rack is a distance D2 from the bottom of the skirt sides of the third rack, the distance D2 being less than the distance Di.

10. The rack of claim 9, wherein the distance D2 is zero.

11. A plurality of racks for holding a plurality of chips, comprising: at least a first rack and a second rack, wherein each respective rack includes: a receptacle portion having receptacle sides defining a first periphery, the receptacle portion also having a plurality of chip cradles that are configured to hold the plurality of chips, and a skirt portion operatively coupled to and extending away from the receptacle portion, the skirt portion having skirt sides defining a second periphery that is larger than the first periphery, wherein the second periphery of the first rack is configured to receive at least a portion of the receptacle portion of the second rack.

12. The plurality of racks of claim 1 1 , wherein each of the first and second racks has a longitudinal axis, and wherein each chip cradle extends transverse to the longitudinal axis of the respective first and second racks.

13. The plurality of racks of any claims 11 or 12, wherein each chip cradle has a curved surface for supporting the plurality of chips.

14. The plurality of racks of any claims 11 -13, wherein the receptacle sides of respective ones of the first and second racks have a height Hi and wherein the skirt sides of respective ones of the first and second racks have a height H2 that is greater than Hi.

15. The plurality of racks of claim 1 1 , wherein the second periphery of the first rack is configured to receive the receptacle portion of the second rack such thatwhen the second rack holds the plurality of chips, a bottom of the skirt sides of the first rack is a distance Di from a top of the skirt sides of the second rack, and such that when the second rack is not holding the plurality of chips, the bottom of the skirt sides of the first rack is a distance D2 from the top of the skirt sides of the second rack, the distance D2 being less than the distance Di.

16. The plurality of racks of claim 11 , further comprising a third rack, wherein the first periphery of the first rack is configured to receive a skirt portion of the third rack such that when the first rack holds the plurality of chips, the top of the skirt sides of the first rack is a distance Di from a bottom of skirt sides of the skirt portion of the third rack, and such that when the first rack is not holding the plurality of chips, the top of the skirt sides of the first rack is a distance D2 from the bottom of the skirt sides of the third rack, the distance D2 being less than the distance Di.

17. A method for holding a plurality of chips with one or more racks, comprising: providing a plurality of racks including at least a first rack and a second rack, wherein each rack includes: a receptacle portion having receptacle sides defining a first periphery, the receptacle portion also having a plurality of chip cradles that are configured to hold the plurality of chips, and a skirt portion operatively coupled to and extending away from the receptacle portion, the skirt portion having skirt sides defining a second periphery that is larger than the first periphery; and placing at least a portion of the receptacle portion of the second rack through the second periphery of the first rack and into the skirt portion of the first rack.

18. The method of claim 17, wherein placing the second rack under the first rack comprises: placing the second rack under the first rack such that when the second rack holds the plurality of chips, a bottom of the skirt sides of the first rack is a distance Di from a top of the skirt sides of the second rack, and such that when the second rack is not holding the plurality of chips, the bottom of the skirt sides of the first rack is a distance D2 from the top of the skirt sides of the second rack, the distance D2 being less than the distance Di.

19. The method of 17, wherein the plurality of racks further comprises a third rack; and where the method further comprises: placing the third rack on top of the first rack such that the second periphery of the third rack receives at least a portion of the receptacle portion of the first rack.

20. The method of claim 19, wherein placing the third rack on top of the first rack comprises: placing the third rack on top of the first rack such that when the first rack holds the plurality of chips, a bottom of the skirt sides of the third rack is a distance Di from a top of the skirt sides of the first rack, and such that when the first rack is not holding the plurality of chips, the bottom of the skirt sides of the third rack is a distance D2 from and the top of the skirt sides of the first rack, the distance D2 being less than the distance D2.

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