All-glass stacked packaging structure and preparation method therefor

Abstract

An all-glass stacked packaging structure and a preparation method therefor. The preparation method for the all-glass stacked packaging structure comprises the following steps: S1, providing an embedded chip fan-out packaging structure and a glass metallized circuit structure that are each provided with a glass substrate, and aligning and bonding metal bumps of the embedded chip fan-out packaging structure to a second redistribution layer of the glass metallized circuit structure, and fixing the two together by welding; and S2, filling a gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure with an inorganic silicate or an alkali-metal-free silicon compound, and sintering to obtain the all-glass stacked packaging structure.

Description

All-glass stacked packaging structure and preparation method thereof

[0001] This application claims priority to Chinese patent application filed on August 1, 2023, with application number 202310959645.7, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the technical field of integrated circuit packaging, for example, to an all-glass stacked packaging structure and a preparation method thereof. Background Art

[0003] In the related art, for a semiconductor stack component, a plurality of semiconductor chips are usually stacked together by bonding materials, and then the stacked semiconductor chips are encapsulated with molding materials or bottom filling materials to form a semiconductor stack packaging structure.

[0004] Related art discloses a three-dimensional fan-out packaging structure and its preparation method, which involves digging grooves on a carrier board, preparing a metal wiring layer in the grooves and around them, then mounting a core particle, and leading some of the core particle's pins to the front of the carrier board through the metal wiring layer. After plastic sealing, conductive columns are prepared on the plastic sealing layer to lead out some of the pins, and then a first redistribution layer and a first dielectric layer are prepared on the plastic sealing layer to complete the front packaging; then the back of the carrier board is thinned to the metal wiring layer, exposing another part of the core particle's pins, and then a second redistribution layer and a second dielectric layer are prepared to complete the preparation of a double-sided fan-out fan-out packaging unit, and the fan-out packaging units are stacked as needed and connected using solder balls to obtain a three-dimensional fan-out packaging structure.

[0005] In the related art, fan-out package units are stacked and connected using solder balls. When subjected to external forces, the fan-out package units are easily misaligned, resulting in poor connection stability between the fan-out package units.

[0006] Summary of the Invention

[0007] The present application provides a method for preparing an all-glass stacked packaging structure, which can effectively improve the connection stability between the embedded chip fan-out packaging structure and the glass metallization circuit structure.

[0008] On the one hand, an embodiment of the present application provides a method for preparing an all-glass stacked package structure, comprising:

[0009] S1. Provide an embedded chip fan-out package structure and a glass metallization circuit structure, both with a glass substrate, and butt-bond the metal bumps of the embedded chip fan-out package structure to the second redistribution layer of the glass metallization circuit structure and weld them together;

[0010] S2. Filling a connection material into the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure and sintering to obtain an all-glass stacked packaging structure, wherein the connection material is an inorganic silicate or a compound not containing alkali metals.

[0011] The present application, after butting and laminating an embedded chip fan-out packaging structure and a glass metallized circuit structure, first welds and secures the metal bumps of the embedded chip fan-out packaging structure to the redistribution layer of the glass metallized circuit structure, then fills the gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure with a connecting material, and then sinters the structure to securely connect the embedded chip fan-out packaging structure to the glass substrate of the glass metallized circuit structure through sintering of the connecting material. Using the connecting material for sintering and securing further improves the electrical connection stability between the embedded chip fan-out packaging structure and the glass metallized circuit structure, thereby producing a more structurally stable all-glass stacked packaging structure.

[0012] This application utilizes the characteristics of glass, such as good rigidity, high flatness, and excellent dielectric properties, and adopts glass substrate embedded installation of chips and production of circuit structures, which has high application value and prospects in the fields of high-density substrates and radio frequency.

[0013] In one embodiment, in step S2, when the connecting material is an inorganic silicate, the sintering is performed at 160-300° C. for 0.5-4 h; when the connecting material is a compound not containing an alkali metal, the sintering is performed at 100-200° C. for 0.5-2 h;

[0014] Wherein, the inorganic silicate is Na2O·nSiO2, where n=0.1-5, and the compound not containing alkali metal is silica gel, resin or PI.

[0015] Among them, the common Na2O·nSiO2 solid products are: ① solid block, ② solid powder, ③ instant sodium silicate, ④ sodium metasilicate zero water, ⑤ sodium metasilicate pentahydrate, ⑥ sodium orthosilicate.

[0016] In one embodiment, as a first solution of a method for preparing an all-glass stacked package structure, in step S1, a method for preparing an embedded chip fan-out package structure includes the following steps:

[0017] S10, providing a first glass substrate, and forming a plurality of embedding grooves on the first glass substrate, each of which is larger than the chip size;

[0018] S20, attaching the first surface of the first glass substrate to a temporary adhesive film, and attaching the chip to the embedding groove;

[0019] S30, preparing dielectric layers on the first surface and the second surface of the first glass substrate respectively, and processing the dielectric layers to expose the I / O ports of the chip to obtain a chip package;

[0020] S40, performing a hole-forming process on the chip package to form a plurality of through holes penetrating the chip package;

[0021] S50 , electrically leading the I / O ports of the chip out from both sides of the chip package through the through holes synchronously to obtain an embedded chip fan-out package structure.

[0022] In one embodiment, in step S20, the I / O port of the chip protrudes from the surface of the chip. After the chip is placed in the embedding slot with the front side facing upward, step S30 specifically includes the following steps:

[0023] S30a, preparing a first dielectric layer on the second surface of the first glass substrate;

[0024] S30b, grinding and thinning the first dielectric layer to expose the I / O port of the chip;

[0025] S30c, removing the temporary adhesive film;

[0026] S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

[0027] In one embodiment, in step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed in the embedding slot with the front side facing upward. Then, step S30 specifically includes the following steps:

[0028] S30a, preparing a first dielectric layer on the second surface of the first glass substrate;

[0029] S30b, performing laser drilling processing on the first dielectric layer to expose the I / O port of the chip;

[0030] S30c, removing the temporary adhesive film;

[0031] S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

[0032] In one embodiment, in step S20, when the I / O port of the chip is flush with the surface of the chip and the chip is placed face down in the embedding slot, step S30 specifically includes the following steps:

[0033] S30a, preparing a first dielectric layer on the second surface of the first glass substrate;

[0034] S30b, removing the temporary adhesive film;

[0035] S30c, preparing a second dielectric layer on the first surface of the first glass substrate;

[0036] S30d, performing laser drilling processing on the second dielectric layer to expose the I / O port of the chip to obtain a chip package.

[0037] In one embodiment, step S50 specifically includes the following steps:

[0038] S50a, forming a seed layer on the surface of the chip package and the inner wall of the through hole;

[0039] S50b, attaching a photosensitive film to the seed layer on the surface of the chip package, and forming a patterned window after exposure and development;

[0040] S50c, preparing a first redistribution layer in the patterned window and on the inner wall of the through hole;

[0041] S50d, removing the remaining photosensitive film and etching away the exposed seed layer;

[0042] S50e, preparing solder resist layers in the through hole and on both sides of the chip package having the first redistribution layer, and exposing the pad area of ​​the first redistribution layer;

[0043] S50f, preparing a nickel-palladium-gold layer in the pad area of ​​the first redistribution layer, and implanting metal bumps in the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure.

[0044] In one embodiment, as a second solution of the method for preparing an all-glass stacked package structure, in step S1, the method for preparing an embedded chip fan-out package structure includes the following steps:

[0045] S10, providing a first glass substrate, and forming a plurality of first through holes and a plurality of embedding grooves designed to be larger than the chip size on the first glass substrate;

[0046] S20, attaching the first surface of the first glass substrate to a temporary adhesive film, and attaching the chip to the embedding groove;

[0047] S30, preparing dielectric layers on the first surface and the second surface of the first glass substrate respectively, and filling the first through-hole and the gap between the chip and the first glass substrate with the dielectric layers, processing the dielectric layers to expose the I / O ports of the chip, and manufacturing a chip package;

[0048] S40, opening a second through hole in the dielectric layer filled in the first through hole;

[0049] S50 , electrically leading the I / O ports of the chip out from both sides of the chip package simultaneously through the second through holes to obtain an embedded chip fan-out package structure.

[0050] In one embodiment, in step S20, the I / O port of the chip protrudes from the surface of the chip. After the chip is placed in the embedding slot with the front side facing upward, step S30 specifically includes the following steps:

[0051] S30a, preparing a first dielectric layer on the second surface of the first glass substrate;

[0052] S30b, grinding and thinning the first dielectric layer to expose the I / O port of the chip;

[0053] S30c, removing the temporary adhesive film;

[0054] S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

[0055] In one embodiment, in step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed in the embedding slot with the front side facing upward. Then, step S30 specifically includes the following steps:

[0056] S30a, preparing a first dielectric layer on the second surface of the first glass substrate;

[0057] S30b, performing laser drilling processing on the first dielectric layer to expose the I / O port of the chip;

[0058] S30c, removing the temporary adhesive film;

[0059] S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

[0060] In one embodiment, in step S20, when the I / O port of the chip is flush with the surface of the chip and the chip is placed face down in the embedding slot, step S30 specifically includes the following steps:

[0061] S30a, preparing a first dielectric layer on the second surface of the first glass substrate;

[0062] S30b, removing the temporary adhesive film;

[0063] S30c, preparing a second dielectric layer on the first surface of the first glass substrate;

[0064] S30d, performing laser drilling processing on the second dielectric layer to expose the I / O port of the chip to obtain a chip package.

[0065] In one embodiment, step S50 specifically includes the following steps:

[0066] S50a, forming a seed layer on the surface of the chip package and the inner wall of the second through hole;

[0067] S50b, attaching a photosensitive film to the seed layer on the surface of the chip package, and forming a patterned window after exposure and development;

[0068] S50c, preparing a first redistribution layer in the patterned window and on the inner wall of the second through hole;

[0069] S50d, removing the remaining photosensitive film and etching away the exposed seed layer;

[0070] S50e, preparing solder resist layers in the second through hole and on both sides of the chip package having the first redistribution layer, and exposing the pad area of ​​the first redistribution layer;

[0071] S50f, preparing a nickel-palladium-gold layer in the pad area of ​​the first redistribution layer, and implanting metal bumps in the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure.

[0072] In one embodiment, in step S40 , a laser is used to open a second through hole in the dielectric layer filled in the first through hole.

[0073] In one embodiment, as a third solution of the method for preparing an all-glass stacked package structure, the method for preparing a glass metallized circuit structure includes the following steps:

[0074] S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate;

[0075] S200, pressing a photosensitive film on both sides of a second glass substrate, and performing exposure and development processing to form a first patterned window, and exposing the laser-modified area of ​​the second glass substrate to the first patterned window;

[0076] S300, etching the second glass substrate to form a through hole in the laser-modified area and an embedded circuit groove in the non-laser-modified area of ​​the first patterned window;

[0077] S400, removing the remaining photosensitive film and forming a seed layer on the surface of the embedded circuit groove and the inner wall of the through hole;

[0078] S500, pressing a photosensitive film on the surface of the second glass substrate and the seed layer on the surface of the embedded circuit groove, and performing exposure and development processing on the photosensitive film to form a second patterned window;

[0079] S600, forming a conductive pillar in the through hole and simultaneously forming a second redistribution layer electrically connected to the conductive pillar in the second patterned window, and making the surface of the second redistribution layer flush with the surface of the second glass substrate;

[0080] S700, removing the remaining photosensitive film and performing flash etching on the exposed seed layer;

[0081] S800 , preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the surface of the corresponding second redistribution layer, to obtain a glass metallization circuit structure.

[0082] In one embodiment, as a fourth solution of the method for preparing an all-glass stacked package structure, the method for preparing a glass metallized circuit structure includes the following steps:

[0083] S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate;

[0084] S200, pressing a photosensitive film on both sides of a second glass substrate, and performing exposure and development processing to form a first patterned window, and exposing the laser-modified area of ​​the second glass substrate to the first patterned window;

[0085] S300, etching the second glass substrate to form a through hole in the laser-modified area and an embedded circuit groove in the non-laser-modified area of ​​the first patterned window;

[0086] S400, removing the remaining photosensitive film and forming a seed layer on the surface of the embedded circuit groove and the inner wall of the through hole;

[0087] S500, pressing a photosensitive film on the surface of the second glass substrate and the seed layer on the surface of the embedded circuit groove, and performing exposure and development processing on the photosensitive film to form a second patterned window;

[0088] S600, forming a conductive pillar in the through hole and simultaneously forming a second redistribution layer electrically connected to the conductive pillar in the second patterned window, and making the surface of the second redistribution layer flush with the surface of the second glass substrate;

[0089] S700, removing the remaining photosensitive film and performing a flash etching process on the exposed seed layer; preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the surface of the corresponding second redistribution layer;

[0090] S800, producing m+1 first substrate structures according to steps S100-S700, where m is a positive integer, opening holes in the solder resist layers of the m first substrate structures to expose pad regions of the second redistribution layers of the first substrate structures, and implanting metal bumps in the pad regions to produce a second substrate structure that can serve as an intermediate.

[0091] S900, dip the metal bumps of one of the second substrate structures with nano-metal paste, connect them to the exposed second redistribution layer of the first substrate structure, and then sinter and fix them; then dip the metal bumps of another second substrate structure with nano-metal paste, connect them to the exposed second redistribution layer of the second substrate structure, and then sinter and fix them, and fix all the second substrate structures in this way, and finally fill the connection material between the first substrate structure and the second substrate structure and between every two adjacent second substrate structures and sinter them to obtain a glass metallized circuit structure.

[0092] Optionally, the nano metal paste may be nano copper paste, nano silver paste, or the like.

[0093] In one embodiment, in step S300 , the etching rate ratio between the laser-modified region and the non-laser-modified region of the second glass substrate is 20:1.

[0094] In one embodiment, in step S400b, after the second patterned window is formed, the photosensitive film remaining in the second patterned window is etched away using plasma.

[0095] In one embodiment, as a fifth solution of the method for preparing the all-glass stacked package structure, the method for preparing the glass metallization circuit structure includes the following steps:

[0096] S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate;

[0097] S200, etching the second glass substrate to form a through hole in the laser-modified area;

[0098] S300, forming a seed layer on the inner wall of the through hole and on both sides of the second glass substrate;

[0099] S400, pressing a photosensitive film on the seed layers on both sides of the second glass substrate, and exposing and developing the film to form a patterned window;

[0100] S500, fabricating a second redistribution layer in the patterned window and filling copper pillars in the through holes;

[0101] S600, removing the remaining photosensitive film and performing flash etching on the exposed seed layer;

[0102] S700 , preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the surface of the corresponding second redistribution layer, to obtain a glass metallization circuit structure.

[0103] In one embodiment, as a sixth solution of the method for preparing an all-glass stacked package structure, the method for preparing a glass metallized circuit structure includes the following steps:

[0104] S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate;

[0105] S200, etching the second glass substrate to form a through hole in the laser-modified area;

[0106] S300, forming a seed layer on the inner wall of the through hole and on both sides of the second glass substrate;

[0107] S400, pressing a photosensitive film on the seed layers on both sides of the second glass substrate, and exposing and developing the film to form a patterned window;

[0108] S500, fabricating a second redistribution layer in the patterned window and filling a copper column connected to the second redistribution layer in the through hole;

[0109] S600, removing the remaining photosensitive film and performing flash etching on the exposed seed layer;

[0110] S700, preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the corresponding surface of the second redistribution layer;

[0111] S800, producing m+1 first substrate structures according to steps S100-S700, where m is a positive integer, opening holes in the solder resist layers of the m first substrate structures to expose pad regions of the second redistribution layers of the first substrate structures, and implanting metal bumps in the pad regions to produce a second substrate structure that can serve as an intermediate.

[0112] S900, dip the metal bumps of one of the second substrate structures with nano-metal paste, connect them to the exposed second redistribution layer of the first substrate structure, and then sinter and fix them; then dip the metal bumps of another second substrate structure with nano-metal paste, connect them to the exposed second redistribution layer of the second substrate structure, and then sinter and fix them, and fix all the second substrate structures in this way, and finally fill the connection material between the first substrate structure and the second substrate structure and between two adjacent second substrate structures and sinter them to obtain a glass metallized circuit structure.

[0113] Optionally, the nano metal paste in the present application may be nano copper paste, nano silver paste, etc.

[0114] Optionally, the metal bumps in the present application may be solder balls or conductive pillars, etc.

[0115] On the other hand, the present application also provides a full-glass stacked packaging structure prepared by the preparation method, comprising an embedded chip fan-out packaging structure and a glass metallization circuit structure stacked up and down, the metal bumps of the embedded chip fan-out packaging structure are connected to the exposed second redistribution layer of the glass metallization circuit structure, and the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure is filled with a connection layer formed by sintering a connecting material.

[0116] The beneficial effects of the present application are as follows: After the embedded chip fan-out packaging structure and the glass metallized circuit structure are butt-jointed, the metal bumps of the embedded chip fan-out packaging structure are first welded to the redistribution layer of the glass metallized circuit structure, and then a connecting material is filled into the gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure. The gaps are then sintered to secure the embedded chip fan-out packaging structure to the glass substrate of the glass metallized circuit structure through the sintering of the connecting material. The use of the connecting material for sintering can further improve the electrical connection stability between the embedded chip fan-out packaging structure and the glass metallized circuit structure, thereby producing a more stable all-glass stacked packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0117] FIG1.1 is a cross-sectional schematic diagram of the chip described in Example 1 of the present application embedded in the embedding groove of the first glass substrate.

[0118] Figure 1.2 is a schematic cross-sectional view of the first dielectric layer after being pressed as described in Example 1 of the present application.

[0119] FIG1.3 is a schematic cross-sectional view of the chip package described in Example 1 of the present application after a through hole is opened.

[0120] Figure 1.4 is a cross-sectional schematic diagram after preparing the first redistribution layer as described in Example 1 of the present application.

[0121] Figure 1.5 is a cross-sectional schematic diagram after brushing green oil as described in Example 1 of the present application.

[0122] Figure 1.6 is a schematic cross-sectional view of the nickel-palladium-gold coating described in Example 1 of the present application.

[0123] FIG1.7 is a schematic cross-sectional view of the nickel-palladium-gold layer after metal bumps are implanted as described in Example 1 of the present application.

[0124] Figure 1.8 is a schematic cross-sectional view of the second glass substrate described in Example 1 of the present application.

[0125] Figure 1.9 is a schematic diagram of the center line of the laser-modified area on the second glass substrate described in Example 1 of the present application.

[0126] Figure 1.10 is a cross-sectional schematic diagram of the second glass substrate after the first photosensitive film is pressed on both sides as described in Example 1 of the present application.

[0127] Figure 1.11 is a schematic cross-sectional view of the photosensitive film described in Example 1 of the present application after exposure and development.

[0128] Figure 1.12 is a schematic cross-sectional view of the second glass substrate after etching described in Example 1 of the present application.

[0129] Figure 1.13 is a cross-sectional schematic diagram after removing the residual photosensitive film as described in Example 1 of the present application.

[0130] Figure 1.14 is a cross-sectional schematic diagram after the preparation of the copper pillar and the second redistribution layer as described in Example 1 of the present application.

[0131] Figure 1.15 is a cross-sectional schematic diagram of the glass metallization circuit structure described in Example 1 of the present application.

[0132] Figure 1.16 is a cross-sectional schematic diagram of the embedded chip fan-out packaging structure and the glass metallization circuit structure described in Example 1 of the present application after docking, bonding and welding.

[0133] Figure 1.17 is a cross-sectional schematic diagram of the all-glass stacked packaging structure described in Example 1 of the present application.

[0134] FIG2.1 is a schematic cross-sectional view of the second glass substrate after etching as described in Example 2 of the present application.

[0135] Figure 2.2 is a cross-sectional schematic diagram of the photosensitive film after being attached as described in Example 2 of the present application.

[0136] Figure 2.3 is a schematic cross-sectional view of the photosensitive film described in Example 2 of the present application after exposure and development.

[0137] Figure 2.4 is a cross-sectional schematic diagram after the preparation of the copper pillar and the second redistribution layer as described in Example 2 of the present application.

[0138] Figure 2.5 is a cross-sectional schematic diagram of the glass metallization circuit structure described in Example 2 of the present application.

[0139] FIG3.1 is a cross-sectional schematic diagram of the chip described in Example 3 of the present application embedded in the embedding groove of the first glass substrate.

[0140] Figure 3.2 is a schematic cross-sectional view of the first dielectric layer after being pressed as described in Example 3 of the present application.

[0141] FIG3.3 is a schematic cross-sectional view of the chip package described in Example 3 of the present application after a through hole is opened.

[0142] Figure 3.4 is a cross-sectional schematic diagram after the preparation of the redistribution layer described in Example 3 of the present application.

[0143] Figure 3.5 is a cross-sectional schematic diagram after brushing green oil as described in Example 3 of the present application.

[0144] Figure 3.6 is a schematic cross-sectional view of the nickel-palladium-gold coating described in Example 3 of the present application.

[0145] FIG3.7 is a schematic cross-sectional view of the nickel-palladium-gold layer after metal bumps are implanted as described in Example 3 of the present application.

[0146] Figure 3.8 is a cross-sectional schematic diagram of the second substrate structure described in Example 3 of the present application.

[0147] Figure 3.9 is a cross-sectional schematic diagram of the glass metallization circuit structure described in Example 3 of the present application.

[0148] Figure 3.10 is a cross-sectional schematic diagram of the embedded chip fan-out packaging structure and the glass metallization circuit structure after docking, bonding and welding as described in Example 3 of the present application.

[0149] Figure 3.11 is a cross-sectional schematic diagram of the all-glass stacked packaging structure described in Example 3 of the present application.

[0150] FIG4.1 is a cross-sectional schematic diagram of the chip described in Example 4 of the present application embedded in the embedding groove of the first glass substrate.

[0151] Figure 4.2 is a schematic cross-sectional view of the first dielectric layer after being pressed as described in Example 4 of the present application.

[0152] FIG4.3 is a schematic cross-sectional view of the chip package described in Example 4 of the present application after a through hole is opened.

[0153] Figure 4.4 is a cross-sectional schematic diagram after preparing the first redistribution layer as described in Example 4 of the present application.

[0154] Figure 4.5 is a cross-sectional schematic diagram after brushing green oil as described in Example 4 of the present application.

[0155] Figure 4.6 is a schematic cross-sectional view of the nickel-palladium-gold coating described in Example 4 of the present application.

[0156] Figure 4.7 is a cross-sectional schematic diagram of the nickel palladium gold layer after metal bumps are implanted as described in Example 4 of the present application.

[0157] Figure 4.8 is a cross-sectional schematic diagram of the embedded chip fan-out packaging structure and the glass metallization circuit structure after docking, bonding and welding as described in Example 4 of the present application.

[0158] Figure 4.9 is a cross-sectional schematic diagram of the all-glass stacked packaging structure described in Example 4 of the present application.

[0159] FIG5.1 is a cross-sectional schematic diagram of the chip described in Example 6 of the present application embedded in the embedding groove of the first glass substrate.

[0160] Figure 5.2 is a schematic cross-sectional view of the first dielectric layer and the second dielectric layer after being pressed as described in Example 6 of the present application.

[0161] FIG5.3 is a schematic cross-sectional view of the chip package according to Example 6 of the present application after a second through hole is formed.

[0162] Figure 5.4 is a cross-sectional schematic diagram after preparing the first redistribution layer as described in Example 6 of the present application.

[0163] Figure 5.5 is a cross-sectional schematic diagram after brushing green oil as described in Example 6 of the present application.

[0164] Figure 5.6 is a schematic cross-sectional view of the nickel-palladium-gold coating described in Example 6 of the present application.

[0165] FIG5.7 is a schematic cross-sectional view of the nickel-palladium-gold layer after metal bumps are implanted as described in Example 6 of the present application.

[0166] Figure 5.8 is a cross-sectional schematic diagram of the second substrate structure described in Example 6 of the present application.

[0167] Figure 5.9 is a cross-sectional schematic diagram of the glass metallization circuit structure described in Example 6 of the present application.

[0168] Figure 5.10 is a cross-sectional schematic diagram of the embedded chip fan-out packaging structure and the glass metallized circuit structure after docking, bonding and welding as described in Example 6 of the present application.

[0169] Figure 5.11 is a cross-sectional schematic diagram of the all-glass stacked packaging structure described in Example 6 of the present application. DETAILED DESCRIPTION

[0170] The technical solution of this application is further explained below through specific implementation methods.

[0171] Unless otherwise specified, the various raw materials of the present application can be purchased commercially or prepared according to conventional methods in the art.

[0172] The fan-out packaging structure with double-sided fan-out in this application can effectively reduce the interconnection distance, facilitate three-dimensional stacking, and has great advantages in electrical interconnection performance, with lower loss and higher efficiency, greatly reducing the difficulty of the packaging process and reducing the packaging cost.

[0173] Example 1

[0174] The preparation method of the all-glass stack package structure of this embodiment is as follows:

[0175] 1. Preparation of embedded chip fan-out packaging structure:

[0176] 1. Provide a first glass substrate 1, and open a plurality of embedding grooves 1a (through-hole form) on the first glass substrate 1, the design size of which is larger than the size of the chip 2;

[0177] 2. Attach the lower surface (first surface) of the first glass substrate 1 to a temporary adhesive film 3;

[0178] 3. Provide several chips 2 with their I / O ports protruding from the surface (bump pillar). Place the chips 2 facing up (i.e., with their I / O ports facing up) on the temporary adhesive film 3 embedded in the slot 1a, as shown in Figure 1.1.

[0179] 4. Press a first dielectric layer 4a onto the upper surface (second surface) of the first glass substrate 1, filling the gap between the chip 2 and the first glass substrate 1 with the first dielectric layer 4a. Grind and thin the first dielectric layer 4a to expose the I / O port of the chip 2, as shown in Figure 1.2.

[0180] 5. Removing the temporary adhesive film 3 on the first surface of the first glass substrate 1;

[0181] 6. Pressing a second dielectric layer 4b on the first surface of the first glass substrate 1 to obtain a chip package;

[0182] 7. Use mechanical drilling to open through holes in the chip package to form several through holes 1b on the chip package, as shown in Figure 1.3;

[0183] 8. Simultaneously prepare a seed layer on the inner wall of the through hole 1 b and the side of the first dielectric layer 4 a away from the first glass substrate 1 and the side of the second dielectric layer 4 b away from the first glass substrate 1 by vacuum sputtering;

[0184] 9. A photosensitive film is applied to the seed layer on the first dielectric layer 4a and the seed layer on the second dielectric layer 4b, and then subjected to exposure and development treatment to form a patterned window that exposes part of the seed layer;

[0185] 10. Synchronously fabricate the first redistribution layer 5 by electroplating on the surface of the seed layer on the inner wall of the through hole 1b and in the patterned window, as shown in FIG1.4;

[0186] 11. Remove the remaining photosensitive film to expose part of the seed layer, and etch the exposed seed layer;

[0187] 12. Apply green oil inside the through hole 1b where the seed layer and the first redistribution layer 5 are prepared, and on the surfaces of the first dielectric layer 4a, the second dielectric layer 4b, and the first redistribution layer 5. After the green oil is cured, it is exposed and developed to form a solder resist layer 6 that exposes the pad area of ​​the first redistribution layer 5, as shown in Figure 1.5. The first dielectric layer 4a and the second dielectric layer 4b constitute the dielectric layer.

[0188] 13. Nickel-palladium-gold is deposited on the pad area of ​​the first redistribution layer 5 to form a nickel-palladium-gold layer 7, as shown in FIG1.6;

[0189] 14. Metal bumps 8 are implanted into the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure, as shown in Figure 1.7.

[0190] 2. Preparation of glass metallized circuit structure:

[0191] 1. Provide a second glass substrate 10 as shown in FIG1.8, and perform laser modification on a portion of the second glass substrate 10 (target area); specifically, define the area of ​​the second glass substrate 10 where a hole is to be opened as the target area (centerline area, FIG1.9), then place the second glass substrate 10 under a titanium sapphire femtosecond laser with a pulse energy of 2 uJ and a laser scanning speed of 0.35 mm / s, and perform circular irradiation on the target area to modify the second glass substrate 10 in the target area;

[0192] 2. As shown in 1.10, the photosensitive film 20 is pressed on both sides of the second glass substrate 10, and then subjected to exposure and development treatment to form a first patterned window as shown in FIG. 1.11, and the laser-modified area of ​​the second glass substrate 10 is exposed in the first patterned window;

[0193] 3. Etching the second glass substrate 10, controlling the etching rate ratio between the laser-modified and non-laser-modified regions of the second glass substrate 10 to be 20:1, forming a through hole 10a in the laser-modified region and an embedded wiring trench 10b in the non-laser-modified region at the first patterned window, with the through hole 10a communicating with the embedded wiring trench 10b, as shown in FIG1.12. Specifically, the second glass substrate 10 is sprayed with an etching solution (hydrofluoric acid + additives) at 30°C for 30 minutes, causing the glass in the laser-modified region to fall off, forming the through hole 10a, and also causing the region surrounding the through hole, exposed to the photosensitive film 20, to fall off, forming the embedded wiring trench 10b.

[0194] 4. Remove the remaining photosensitive film 20 ( FIG. 1.13 ) and form a seed layer on the surface of the embedded circuit groove 10 b and the inner wall of the through hole 10 a ;

[0195] 5. Pressing a photosensitive film again on the surface of the second glass substrate 10 and the seed layer on the surface of the embedded circuit groove 10b, and performing exposure and development processing on the photosensitive film to form a second patterned window;

[0196] 6. Use plasma to etch away the remaining photosensitive film 20 in the second patterned window;

[0197] 7. Depositing copper pillars 30a in the through-holes 10a by electroplating and simultaneously forming a second redistribution layer 30b electrically connected to the copper pillars 30a in the second patterned window, and making the surface of the second redistribution layer 30b flush with the surface of the second glass substrate 10;

[0198] 8. Remove the remaining second photosensitive film and perform flash etching on the exposed seed layer. As shown in FIG1.14 , the surface of the second redistribution layer 30 b is flush with the surface of the second glass substrate 10 ;

[0199] 9. Brush green oil on one side of the second glass substrate 10 and the surface of the corresponding second redistribution layer 30b. After curing, a solder resist layer 40 covering the second glass substrate 10 and the second redistribution layer 30b is formed to obtain a glass metallization circuit structure as shown in Figure 1.15.

[0200] 3. Stacking welding, filling with Na2O·SiO2 and sintering:

[0201] 1. Align the metal bumps 8 of the embedded chip fan-out package structure with the second redistribution layer 30b of the glass metallization circuit structure and weld them together, as shown in Figure 1.16;

[0202] 2. Fill the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure with Na2O·SiO2, and then sinter at 180°C for 3 hours to obtain the full glass stacked packaging structure shown in Figure 1.17.

[0203] As shown in FIG1.17 , the all-glass stacked package structure of this embodiment includes an embedded chip fan-out package structure and a glass metallization circuit structure stacked one above the other. The metal bumps 8 of the embedded chip fan-out package structure are connected to the second redistribution layer 30 b of the glass metallization circuit structure, and the gap between the embedded chip fan-out package structure and the glass metallization circuit structure is filled with a connection layer 100 sintered with Na2O·SiO2.

[0204] As shown in Figure 1.7, the embedded chip fan-out package structure includes:

[0205] A first glass substrate 1, wherein the first glass substrate 1 is provided with a plurality of embedding grooves 1a and a plurality of through holes 1b;

[0206] Several chips 2 are fixed in the embedding grooves 1a via a first dielectric layer 4a above the first glass substrate 1 and a second dielectric layer 4b below the first glass substrate 1, with the I / O ports of the chips 2 protruding from the surface of the chips 2 and exposed on the first dielectric layer 4a. The I / O ports of the chips 2 are flush with the surface of the first dielectric layer 4a, and the first dielectric layer 4a and the second dielectric layer 4b are respectively partially embedded in the gap between the chips 2 and the embedding grooves 1a.

[0207] a seed layer located on the inner wall of the through hole 1b and the surface of the first dielectric layer 4a and the surface of the second dielectric layer 4b and electrically connected to the I / O port of the chip 2. In one embodiment, the seed layer is located on the inner wall of the through hole 1b and the upper surface of the first dielectric layer 4a and the lower surface of the second dielectric layer 4b;

[0208] A first redistribution layer 5 is located on the seed layer. In one embodiment, the first redistribution layer 5 is located on the surface of the seed layer on the inner wall of the through hole 1b and on the surfaces of the seed layer on both sides of the chip package.

[0209] a solder resist layer 6 filling the through hole 1 b and covering the first redistribution layer 5 , the first dielectric layer 4 a and the second dielectric layer 4 b , with the pad area of ​​the first redistribution layer 5 exposed on the solder resist layer 6 ;

[0210] A nickel-palladium-gold layer 7 and a metal bump 8 , wherein the nickel-palladium-gold layer 7 is located in the pad region of the first redistribution layer 5 and is electrically connected to the metal bump 8 .

[0211] As shown in Figure 1.15, the glass metallization circuit structure includes:

[0212] A second glass substrate 10 made of glass, the second glass substrate 10 having a through hole 10a and embedded circuit grooves 10b located on both sides of the second glass substrate 10, the embedded circuit grooves 10b being connected to the through hole 10a;

[0213] An embedded circuit, comprising a conductive post embedded in the through hole 10a and a circuit layer embedded in the embedded circuit groove 10b, wherein the conductive post is electrically connected to the circuit layer, and the surface of the circuit layer is flush with the surface of the second glass substrate 10;

[0214] The conductive pillar includes a first seed layer covering the inner wall of the through hole 10a and a copper pillar 30a filled in the through hole 10a and connected to the first seed layer. The circuit layer includes a second seed layer located in the embedded circuit groove 10b and a second redistribution layer 30b (copper layer) located on the surface of the second seed layer. The second redistribution layer 30b is electrically connected to the copper pillar 30a.

[0215] The solder resist layer 40 covers one side of the second glass substrate 10 and the second redistribution layer 30 b located on the side.

[0216] The first seed layer and the second seed layer constitute a seed layer, which is integrally formed by vacuum sputtering;

[0217] The copper pillar 30a and the second redistribution layer 30b are integrally formed by electroplating deposition.

[0218] In one embodiment, the second glass substrate 10 of the glass metallization circuit structure is connected to the embedded chip fan-out packaging structure through a connection layer 100 formed by sintering Na2O·SiO2.

[0219] Example 2

[0220] The preparation method of the all-glass stack package structure of this embodiment is as follows:

[0221] 1. Preparation of embedded chip fan-out packaging structure:

[0222] The preparation method of the embedded chip fan-out packaging structure of this embodiment is basically the same as that of the above-mentioned embodiment 1 (refer to the drawings of the above-mentioned embodiment 1, and the same component names are marked with the same drawings). The difference is that the I / O port of the chip 2 is flush with the surface of the chip 2 (ubm), and the chip 2 is attached to the temporary adhesive film 3 in the embedding groove 1a with the front side facing up (i.e., the I / O port is facing up); the first dielectric layer 4a is pressed on the upper surface (second side) of the first glass substrate 1, and the first dielectric layer 4a is laser drilled in alignment with the I / O port of the chip 2 to expose the I / O port of the chip 2; the temporary adhesive film 3 on the first side of the first glass substrate 1 is removed; the second dielectric layer 4b is pressed on the first side of the first glass substrate 1 to obtain a chip package. The subsequent steps are exactly the same as those in embodiment 1, and the obtained embedded chip fan-out packaging structure is also basically the same as that in embodiment 1, and the details are not repeated here.

[0223] 2. Preparation of glass metallized circuit structure:

[0224] S10, providing a second glass substrate 10 as shown in FIG1.8, and performing laser modification on a portion of the second glass substrate 10, specifically: demarcating the area of ​​the second glass substrate 10 where a hole is to be opened as a target area (centerline area, FIG1.9), then placing the second glass substrate 10 under a titanium sapphire femtosecond laser with a pulse energy of 2 uJ and a laser scanning speed of 0.35 mm / s, and performing circular irradiation on the target area to modify the substrate in the target area;

[0225] S20, etching the second glass substrate 10 to form a through hole 10a in the laser-modified area as shown in FIG2.1. Specifically, the second glass substrate 10 is sprayed with an etching solution (hydrofluoric acid + additives) at 30°C for 30 minutes to cause the glass in the laser-modified area to fall off to form the through hole 10a.

[0226] S30, forming a seed layer (not shown in the figure) on the inner wall of the through hole 10a and the double sides of the second glass substrate 10 by vacuum sputtering, wherein the seed layer is made of Ti / Cu alloy;

[0227] S40, pressing a photosensitive film 20 ( FIG. 2.2 ) on the seed layer on both sides of the second glass substrate 10, and exposing and developing the photosensitive film 20 to form a patterned window ( FIG. 2.3 ), with a portion of the seed layer exposed on the photosensitive film 20;

[0228] S50, filling the through hole 10a with a copper pillar 30a and forming a second redistribution layer 30b (copper layer) electrically connected to the copper pillar 30a in the patterned window;

[0229] S60, removing the remaining photosensitive film 20 and performing a flash etching process on the seed layer exposed on the second redistribution layer 30b, as shown in FIG2.4;

[0230] S70, brush green oil on one side of the second glass substrate 10 and the surface of the corresponding second redistribution layer 30b, and after curing, form a solder resist layer 40 covering the second glass substrate 10 and the second redistribution layer 30b, to obtain a glass metallization circuit structure as shown in Figure 2.5.

[0231] 3. Stacking welding, filling with Na2O·1.5SiO2 and sintering:

[0232] 1. The metal bumps 8 of the embedded chip fan-out package structure are butted against the second redistribution layer 30b of the glass metallization circuit structure and fixed by welding;

[0233] 2. Filling Na2O·1.5SiO2 into the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure, and then sintering at 200° C. for 2 hours to obtain a full glass stacked packaging structure.

[0234] The all-glass stacked package structure of this embodiment includes an embedded chip fan-out package structure and a glass metallization circuit structure stacked on top of each other. The metal bumps 8 of the embedded chip fan-out package structure are connected to the second redistribution layer 30b of the glass metallization circuit structure, and the gap between the embedded chip fan-out package structure and the glass metallization circuit structure is filled with a connection layer 100 sintered with Na2O·1.5SiO2.

[0235] Among them, the embedded chip fan-out packaging structure is basically the same as the above-mentioned embodiment 1, and the details are not repeated here.

[0236] As shown in FIG2.5 , the glass substrate metallization structure of this embodiment includes:

[0237] A second glass substrate 10 made of glass, wherein the second glass substrate 10 is provided with a through hole 10a;

[0238] The conductive pillar includes a first seed layer and a copper pillar 30a, wherein the first seed layer covers the inner wall of the through hole 10a; the copper pillar 30a is filled in the through hole 10a whose inner wall is covered with the first seed layer;

[0239] The circuit layer includes a second seed layer and a second redistribution layer 30b, wherein the second seed layer is located on both sides of the second glass substrate 10 and is electrically connected to the first seed layer respectively; the second redistribution layer 30b is located on the second seed layer and the copper pillars 30a on both sides of the second glass substrate 10 and is electrically connected to the copper pillars 30a;

[0240] The solder resist layer 40 covers one side of the second glass substrate 10 and the second redistribution layer 30 b located on the side.

[0241] The first seed layer and the second seed layer constitute a seed layer and are integrally formed by sputtering, and the copper pillar 30 a and the second redistribution layer 30 b are integrally formed by electroplating deposition.

[0242] In one embodiment, the glass substrate of the glass metallization circuit structure is connected to the embedded chip fan-out packaging structure through a connection layer 100 formed by sintering Na2O·1.5SiO2.

[0243] Example 3

[0244] The preparation method of the all-glass stack package structure of this embodiment is as follows:

[0245] 1. Preparation of embedded chip fan-out packaging structure:

[0246] 1. Provide a first glass substrate 1, and open a plurality of embedding grooves 1a (through-hole form) on the first glass substrate 1, the design size of which is larger than the size of the chip 2;

[0247] 2. Attach the lower surface (first surface) of the first glass substrate 1 to a temporary adhesive film 3;

[0248] 3. Make sure the I / O port of chip 2 is flush with the surface of chip 2 (ubm). Place chip 2 face down (i.e., I / O port facing down) on the temporary adhesive film 3 in the embedding slot 1a, as shown in Figure 3.1.

[0249] 4. Press a first dielectric layer 4a on the upper surface (second surface) of the first glass substrate 1 and embed the first dielectric layer 4a into the gap between the chip 2 and the embedding groove 1a, as shown in FIG3.2;

[0250] 5. Removing the temporary adhesive film 3 on the first surface of the first glass substrate 1;

[0251] 6. Flip the first glass substrate 1 and press a second dielectric layer 4 b on the first surface of the first glass substrate 1 . Perform laser drilling on the second dielectric layer 4 b to expose the I / O port of the chip 2 , thereby obtaining a chip package.

[0252] 7. Use mechanical drilling to open through holes in the chip package to form several through holes 1b on the chip package, as shown in Figure 3.3;

[0253] 8. Simultaneously prepare a seed layer on the inner wall of the through hole 1 b and the side of the first dielectric layer 4 a away from the first glass substrate 1 and the side of the second dielectric layer 4 b away from the first glass substrate 1 by vacuum sputtering;

[0254] 9. A photosensitive film is applied to the seed layer on the first dielectric layer 4a and the seed layer on the second dielectric layer 4b, and then subjected to exposure and development treatment to form a patterned window that exposes part of the seed layer;

[0255] 10. Synchronously fabricate the first redistribution layer 5 by electroplating on the surface of the seed layer on the inner wall of the through hole 1b and in the patterned window, as shown in FIG3.4;

[0256] 11. Remove the remaining photosensitive film to expose part of the seed layer, and etch the exposed seed layer;

[0257] 12. Apply green oil inside the through hole 1b where the seed layer and the first redistribution layer 5 are prepared, as well as on the surfaces of the first dielectric layer 4a, the second dielectric layer 4b, and the first redistribution layer 5. After the green oil is cured, it is exposed and developed to form a solder resist layer 6 that exposes the pad area of ​​the first redistribution layer 5, as shown in Figure 3.5;

[0258] 13. Nickel-palladium-gold is deposited on the pad area of ​​the first redistribution layer 5 to form a nickel-palladium-gold layer 7, as shown in FIG3.6;

[0259] 14. Metal bumps 8 are implanted into the nickel-palladium-gold layer 7 to obtain the embedded chip fan-out packaging structure shown in Figure 3.7.

[0260] 2. Preparation of glass metallized circuit structure:

[0261] The glass metallized circuit structure in this embodiment is formed by connecting a first substrate structure and a second substrate structure, wherein the preparation method of the first substrate structure is exactly the same as steps 1-9 in the preparation method of the glass metallized circuit structure in the above embodiment 1.

[0262] After two first substrate structures are prepared (see FIG. 1.15 ), one of the first substrate structures is used to prepare a second substrate structure, which specifically includes the following steps:

[0263] The solder resist layer 40 of the first substrate structure is opened to expose the pad area of ​​the second redistribution layer 30b of the first substrate structure, and metal bumps 50 are implanted in the pad area to obtain a second substrate structure that can be used as an intermediate, as shown in FIG3.8.

[0264] The connection between the first substrate structure and the second substrate structure is specifically as follows:

[0265] The metal bumps 50 of the second substrate structure are dipped in nano-copper paste and connected to the exposed second redistribution layer 30b of the first substrate structure and then sintered and fixed; the connection material described in Example 1 is filled between the first substrate structure and the second substrate structure and between two adjacent second substrate structures and sintered and fixed according to the sintering method in Example 1 to obtain the glass metallization circuit structure shown in Figure 3.9.

[0266] 3. Stacking welding, filling with silicone sintering:

[0267] 1. As shown in FIG3.10, the metal bump 8 of the embedded chip fan-out package structure is butted against the second redistribution layer 30b of the glass metallization circuit structure and then fixed by welding;

[0268] 2. Fill the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure with silica gel, and then sinter at 160°C for 4 hours to form a connecting layer 100, thereby obtaining the full-glass stacked packaging structure shown in FIG3.11.

[0269] As shown in FIG3.11, the all-glass stacked package structure of this embodiment includes an embedded chip fan-out package structure and a glass metallization circuit structure stacked on top of each other. The metal bumps 8 of the embedded chip fan-out package structure are connected to the second redistribution layer 30b of the glass metallization circuit structure, and the gap between the embedded chip fan-out package structure and the glass metallization circuit structure is filled with a connection layer 100 formed by sintering silicone rubber.

[0270] Among them, the embedded chip fan-out packaging structure includes:

[0271] A first glass substrate 1, wherein the first glass substrate 1 is provided with a plurality of embedding grooves 1a and a plurality of through holes 1b;

[0272] Several chips 2 are fixed in the embedding grooves 1a via a first dielectric layer 4a above the first glass substrate 1 and a second dielectric layer 4b below the first glass substrate 1, with the I / O ports of the chips 2 flush with the surface of the chips 2 and exposed in the second dielectric layer 4b (the second dielectric layer 4b has a hole structure for exposing the I / O ports of the chips 2). The first dielectric layer 4a and the second dielectric layer 4b are each partially embedded in the gap between the chip 2 and the embedding grooves 1a; the first dielectric layer 4a and the second dielectric layer 4b constitute a dielectric layer;

[0273] a seed layer located on the inner wall of the through hole 1b and the surface of the first dielectric layer 4a and electrically connected to the I / O port of the chip 2. In one embodiment, the seed layer is located on the inner wall of the through hole 1b, the upper surface of the first dielectric layer 4a, the lower surface of the second dielectric layer 4b, and within the hole structure thereof;

[0274] A first redistribution layer 5 is located on the seed layer. In one embodiment, the first redistribution layer 5 is located on the surface of the seed layer on the inner wall of the through hole 1b and on the surfaces of the seed layer on both sides of the chip package.

[0275] a solder resist layer 6 filling the through hole 1 b and the first redistribution layer 5 , the surface of the first dielectric layer 4 a , and the surface of the second dielectric layer 4 b , with the pad area of ​​the first redistribution layer 5 exposed on the solder resist layer 6 ;

[0276] A nickel-palladium-gold layer 7 and a metal bump 8 , wherein the nickel-palladium-gold layer 7 is located in the pad region of the first redistribution layer 5 and is electrically connected to the metal bump 8 .

[0277] The glass substrate metallization structure includes a first substrate structure, a second substrate structure, and a connection layer filled between the first substrate structure and the second substrate structure;

[0278] Wherein, the first substrate structure includes:

[0279] A second glass substrate 10 made of glass, wherein the second glass substrate 10 is provided with a through hole 10a;

[0280] The conductive pillar includes a first seed layer and a copper pillar 30a, wherein the first seed layer covers the inner wall of the through hole 10a; the copper pillar 30a is filled in the through hole 10a whose inner wall is covered with the first seed layer;

[0281] The circuit layer includes a second seed layer and a second redistribution layer 30b, wherein the second seed layer is located on both sides of the second glass substrate 10 and is electrically connected to the first seed layer respectively; the second redistribution layer 30b is located on the second seed layer and the copper pillars 30a on both sides of the second glass substrate 10 and is electrically connected to the copper pillars 30a;

[0282] a solder resist layer 40 covering one side of the second glass substrate 10 and the second redistribution layer 30 b located on the side;

[0283] The second substrate structure is substantially the same as the first substrate structure, except that the solder resist layer 40 is provided with a hole structure for exposing the pad area of ​​the second redistribution layer 30b and a metal bump 50 soldered and fixed to the pad area of ​​the second redistribution layer 30b.

[0284] The metal bumps 50 of the second substrate structure are electrically connected to the second redistribution layer 30 b of the first substrate structure via a connection portion formed by sintering the nano-copper paste.

[0285] In one embodiment, the second glass substrate 10 of the glass metallization circuit structure is connected to the embedded chip fan-out packaging structure through a connection layer 100 formed after silicone sintering.

[0286] In other embodiments, after the metal bumps of the first substrate structure and the second substrate structure are sintered and fixed, they are then welded and fixed to the metal bumps of the embedded chip fan-out packaging structure. Finally, the gap between the first substrate structure and the second substrate structure and the gap between the second substrate structure and the embedded chip fan-out packaging structure are simultaneously filled with connecting material and then sintered and fixed.

[0287] Example 4

[0288] The preparation method of the all-glass stack package structure of this embodiment is as follows:

[0289] 1. Preparation of embedded chip fan-out packaging structure:

[0290] 1. Provide a first glass substrate 1, and open a plurality of first through holes 1b and a plurality of embedding grooves 1a (actually in the form of through holes) with a design size larger than the size of the chip 2 on the first glass substrate 1;

[0291] 2. Attach the lower surface (first surface) of the first glass substrate 1 to a temporary adhesive film 3;

[0292] 3. Provide several chips 2 with their I / O ports protruding from the surface (bump pillar). Place the chips 2 with their front faces facing up (i.e., their I / O ports facing up) on the temporary adhesive film 3 embedded in the slots 1a, as shown in Figure 4.1.

[0293] 4. Press a first dielectric layer 4a onto the upper surface (second surface) of the first glass substrate 1, filling the gap between the chip 2 and the first glass substrate 1 and the first through-hole 1b with the first dielectric layer 4a. Grind and thin the first dielectric layer 4a to expose the I / O port of the chip 2, as shown in Figure 4.2.

[0294] 5. Removing the temporary adhesive film 3 on the first surface of the first glass substrate 1;

[0295] 6. Pressing a second dielectric layer 4b on the first surface of the first glass substrate 1 to obtain a chip package;

[0296] 7. A second through hole 1c is opened in the first dielectric layer 4a filled in the first through hole 1b and the corresponding second dielectric layer 4b by laser drilling, as shown in FIG4.3;

[0297] 8. Simultaneously prepare a seed layer on the inner wall of the second through hole 1 c and the side of the first dielectric layer 4 a away from the first glass substrate 1 and the side of the second dielectric layer 4 b away from the first glass substrate 1 by vacuum sputtering;

[0298] 9. A photosensitive film is applied to the seed layer on the first dielectric layer 4a and the seed layer on the second dielectric layer 4b, and then subjected to exposure and development treatment to form a patterned window that exposes part of the seed layer;

[0299] 10. Synchronously fabricate the first redistribution layer 5 by electroplating the surface of the seed layer on the inner wall of the second through hole 1c and in the patterned window, as shown in FIG4.4 ;

[0300] 11. Remove the remaining photosensitive film to expose part of the seed layer, and etch the exposed seed layer;

[0301] 12. Apply green oil to the inside of the second through hole 1c where the seed layer and the first redistribution layer 5 are prepared, as well as to the surfaces of the first dielectric layer 4a, the second dielectric layer 4b, and the first redistribution layer 5. After the green oil is cured, it is exposed and developed to form a solder resist layer 6 that exposes the pad area of ​​the first redistribution layer 5, as shown in Figure 4.5. The first dielectric layer 4a and the second dielectric layer 4b constitute the dielectric layer.

[0302] 13. Nickel palladium gold is deposited on the pad area of ​​the first redistribution layer 5 to form a nickel palladium gold layer 7, as shown in FIG4.6;

[0303] 14. Metal bumps 8 are implanted into the nickel-palladium-gold layer 7 to obtain the embedded chip fan-out packaging structure shown in Figure 4.7.

[0304] 2. Preparation of glass metallized circuit structure:

[0305] It is exactly the same as Example 2 and will not be described in detail.

[0306] 3. Stacking welding, filling PI sintering:

[0307] 1. As shown in Figure 4.8, the metal bumps of the embedded chip fan-out package structure are butted and welded to the redistribution layer of the glass metallization circuit structure.

[0308] 2. Fill PI into the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure, and then sinter at 100°C for 2 hours to obtain the full glass stacked packaging structure shown in Figure 4.9.

[0309] As shown in FIG4.9, the all-glass stacked package structure of this embodiment includes an embedded chip fan-out package structure and a glass metallization circuit structure stacked on top of each other. The metal bumps 8 of the embedded chip fan-out package structure are connected to the second redistribution layer 30b of the glass metallization circuit structure, and the gap between the embedded chip fan-out package structure and the glass metallization circuit structure is filled with a connection layer 100 formed by PI sintering.

[0310] As shown in Figure 4.9, the embedded chip fan-out package structure includes:

[0311] A first glass substrate 1, wherein the first glass substrate 1 is provided with a plurality of embedding grooves 1a and a plurality of first through holes 1b;

[0312] Several chips 2 are located in the embedding grooves 1a. The gaps between the chips 2 and the embedding grooves 1a and the first through holes 1b are filled with a dielectric layer. The I / O ports of the chips 2 are exposed in the dielectric layer. A second through hole 1c is opened in the dielectric layer of the first through hole 1b.

[0313] a seed layer, located on the inner wall of the second through hole 1 c and the surface of the dielectric layer and electrically connected to the I / O port of the chip 2;

[0314] A first redistribution layer 5, located on the seed layer;

[0315] a solder resist layer 6 filling the second through hole 1c and the first redistribution layer 5 and the surface of the dielectric layer, with the pad area of ​​the first redistribution layer 5 exposed on the solder resist layer 6;

[0316] A nickel-palladium-gold layer 7 and a metal bump 8 , wherein the nickel-palladium-gold layer 7 is located in the pad region of the first redistribution layer 5 and is electrically connected to the metal bump 8 .

[0317] In one embodiment, the dielectric layer comprises a first dielectric layer 4a and a second dielectric layer 4b. The first dielectric layer 4a fills the gap between the chip 2 and the embedded slot 1a and the first through hole 1b. The first dielectric layer 4a covers the second surface (upper surface) of the first glass substrate 1, and the second dielectric layer 4b covers the first surface (lower surface) of the first glass substrate 1.

[0318] A seed layer is provided on the surfaces of the first dielectric layer 4a and the second dielectric layer 4b.

[0319] The structure of the glass metallization circuit is the same as that of Example 2, and will not be described in detail.

[0320] The second glass substrate 10 of the glass metallization circuit structure is further fixedly connected to the embedded chip fan-out packaging structure through a connection layer 100 formed after PI sintering.

[0321] Example 5

[0322] The preparation method of the all-glass stack package structure of this embodiment is as follows:

[0323] 1. Preparation of embedded chip fan-out packaging structure:

[0324] The preparation method of the embedded chip fan-out packaging structure of this embodiment is basically the same as that of the above-mentioned embodiment 4 (refer to the drawings of the above-mentioned embodiment 4, and the same component names are marked with the same drawings). The difference is that the I / O port of the chip 2 is flush with the surface of the chip 2 (ubm), and the chip 2 is attached to the temporary adhesive film 3 in the embedding groove 1a with the front side facing up (i.e., the I / O port is facing up); the first dielectric layer 4a is pressed on the upper surface (second side) of the first glass substrate 1, and the first dielectric layer 4a is laser drilled in alignment with the I / O port of the chip 2 to expose the I / O port of the chip 2; the temporary adhesive film 3 on the first side of the first glass substrate 1 is removed; the second dielectric layer 4b is pressed on the first side of the first glass substrate 1 to obtain a chip package. The subsequent steps are exactly the same as those in embodiment 4, and the obtained embedded chip fan-out packaging structure is also basically the same as that in embodiment 4, and the details are not repeated here.

[0325] 2. Preparation of glass metallized circuit structure:

[0326] It is exactly the same as Example 2 and will not be described in detail.

[0327] 3. Stacking welding, filling with Na2O·2SiO2 and sintering:

[0328] 1. The metal bumps 8 of the embedded chip fan-out package structure are butted against the second redistribution layer 30b of the glass metallization circuit structure and fixed by welding;

[0329] 2. Filling Na2O·2SiO2 into the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure, and then sintering at 250° C. for 1.5 hours to obtain a full glass stacked packaging structure.

[0330] The all-glass stacked package structure of this embodiment includes an embedded chip fan-out package structure and a glass metallization circuit structure stacked on top of each other. The metal bumps 8 of the embedded chip fan-out package structure are connected to the second redistribution layer 30b of the glass metallization circuit structure, and the gap between the embedded chip fan-out package structure and the glass metallization circuit structure is filled with a connection layer 100 sintered by Na2O·2SiO2.

[0331] Among them, the embedded chip fan-out packaging structure is basically the same as the above-mentioned embodiment 4, and the details are not repeated here.

[0332] The glass metallization circuit structure is exactly the same as that of the above-mentioned embodiment 2, and will not be described in detail.

[0333] The second glass substrate 10 of the glass metallization circuit structure is connected to the embedded chip fan-out packaging structure through a connection layer 100 formed by sintering Na2O·2SiO2.

[0334] Example 6

[0335] 1. Preparation of embedded chip fan-out packaging structure:

[0336] The preparation method of the embedded chip fan-out packaging structure of this embodiment (Figures 5.1-5.7) is basically the same as that of the above-mentioned embodiment 4, except that the I / O port of the chip 2 is flush with the surface of the chip 2 (ubm), and the chip 2 is attached to the temporary adhesive film 3 in the embedding groove 1a with the front side facing down (that is, the I / O port facing up), and the first dielectric layer 4a is pressed on the upper surface (second side) of the first glass substrate 1, and the first dielectric layer 4a is filled in the gap between the chip 2 and the first glass substrate 1 and in the first through hole 1b; the temporary adhesive film 3 on the first side of the first glass substrate 1 is removed; the second dielectric layer 4b is pressed on the first side of the first glass substrate 1, and the second dielectric layer 4b is laser-opened to expose the I / O port of the chip 2 to obtain a chip package. The subsequent steps are exactly the same as those in embodiment 4, and the obtained embedded chip fan-out packaging structure is also basically the same as that in embodiment 4, and the details are not repeated here.

[0337] 2. Preparation of glass metallized circuit structure:

[0338] The glass metallization circuit structure in this embodiment is formed by connecting a first substrate structure and two second substrate structures, and specifically includes the following steps:

[0339] S10, providing a second glass substrate 10, and performing laser modification on a portion of the second glass substrate 10 (same as in Example 2);

[0340] S20, etching the second glass substrate 10 to form a through hole 10a in the laser modified area;

[0341] S30, forming a seed layer on the inner wall of the through hole 10a and on both sides of the second glass substrate 10;

[0342] S40, pressing a photosensitive film 20 on the seed layers on both sides of the second glass substrate 10, and exposing and developing the same to form a patterned window;

[0343] S50, forming a second redistribution layer 30b in the patterned window and filling a copper pillar 30a connected to the second redistribution layer in the through hole;

[0344] S60, removing the remaining photosensitive film 20 and performing flash etching on the exposed seed layer;

[0345] S70: Apply green paint on one side of the second glass substrate 10 and the corresponding surface of the second redistribution layer 30b. After curing, a solder resist layer 40 covering the second glass substrate 10 and the second redistribution layer 30b is formed. Three first substrate structures are manufactured according to the above steps (see FIG. 2.5 ).

[0346] S80. Take two first substrate structures, open holes in the solder resist layer 40 of each first substrate structure to expose the pad area of ​​the second redistribution layer 30b of the first substrate structure; implant metal bumps 50 in the pad area to obtain two second substrate structures as intermediate bodies as shown in FIG5.8.

[0347] S90, dip the metal bump 50 of one of the second substrate structures with nano-silver paste, connect it with the exposed second redistribution layer 30b of the first substrate structure, and then sinter and fix it; then dip the metal bump 50 of the second substrate structure with nano-silver paste, connect it with the exposed second redistribution layer 30b of another second substrate structure, and then sinter and fix it; finally, fill Na2O·2SiO2 (connecting material) between the first substrate structure and the second substrate structure and between two adjacent second substrate structures and sinter them at 280℃ for 1h. After the Na2O·2SiO2 (connecting material) is sintered and fixed, a connecting layer 100 is formed to obtain a glass metallized circuit structure (Figure 5.9).

[0348] 3. Stacking welding, filling with Na2O·3.5SiO2 and sintering:

[0349] 1. As shown in FIG5.10, the metal bumps 8 of the embedded chip fan-out package structure are butted against the second redistribution layer 30b of the glass metallization circuit structure and fixed by welding;

[0350] 2. Fill the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure with Na2O·3.5SiO2, and then sinter at 280°C for 1 hour to obtain the full glass stacked packaging structure shown in Figure 5.11.

[0351] The all-glass stacked package structure of this embodiment includes an embedded chip fan-out package structure and a glass metallization circuit structure stacked on top of each other. The metal bumps 8 of the embedded chip fan-out package structure are connected to the second redistribution layer 30b of the glass metallization circuit structure, and the gap between the embedded chip fan-out package structure and the glass metallization circuit structure is filled with a connection layer 100 sintered by Na2O·3.5SiO2.

[0352] Among them, the embedded chip fan-out packaging structure is basically the same as the above-mentioned embodiment 4, and the details are not repeated here.

[0353] As shown in FIG5.11 , the glass metallization circuit structure of this embodiment includes a first substrate structure and two second substrate structures.

[0354] Wherein, the first substrate structure includes:

[0355] A second glass substrate 10, wherein the second glass substrate 10 is provided with a through hole 10a;

[0356] The conductive pillar includes a first seed layer and a copper pillar 30a, wherein the first seed layer covers the inner wall of the through hole 10a; the copper pillar 30a is filled in the through hole 10a whose inner wall is covered with the first seed layer;

[0357] The circuit layer includes a second seed layer and a second redistribution layer 30b. The second seed layer is located on both sides of the second glass substrate 10 and is electrically connected to the first seed layer respectively; the second redistribution layer 30b is located on the second seed layer and the copper pillar 30a on both sides of the second glass substrate 10 and is electrically connected to the copper pillar 30a.

[0358] The first seed layer and the second seed layer constitute a seed layer and are integrally formed by sputtering, and the copper pillar 30a and the second redistribution layer 30b are integrally formed by electroplating deposition;

[0359] The solder resist layer 40 covers one side of the second glass substrate 10 and the second redistribution layer 30 b located on the side.

[0360] The second substrate structure is substantially the same as the first substrate structure, except that the solder resist layer 40 has a hole structure for exposing the pad area of ​​the second redistribution layer 30b and a metal bump 50 welded and fixed to the pad area of ​​the second redistribution layer 30b.

[0361] The metal bumps 50 of the second substrate structure are electrically connected to the second redistribution layer 30 b of the first substrate structure via a connection portion formed by sintering the nano-metal paste.

[0362] In one embodiment, a connection layer 100 formed by sintering Na 2 O·3.5SiO 2 is filled between two adjacent second substrate structures of the glass metallization circuit structure and between the first substrate structure and the second substrate structure.

[0363] The second glass substrate 10 of the glass metallization circuit structure is connected to the embedded chip fan-out packaging structure through a connection layer 100 formed by sintering Na2O·3.5SiO2.

Claims

1. A method for preparing an all-glass stacked packaging structure, comprising the following steps: S1. Provide an embedded chip fan-out packaging structure and a glass metallization circuit structure, both of which have a glass substrate, and butt-join and weld the metal bumps of the embedded chip fan-out packaging structure to the exposed second redistribution layer of the glass metallization circuit structure; S2. Filling a connection material into the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure and sintering to obtain a full glass stack packaging structure, wherein the connection material is an inorganic silicate or a compound not containing alkali metals.

2. The method for preparing the all-glass stacked package structure according to claim 1, characterized in that: In step S2, when the connecting material is an inorganic silicate, sintering is performed at 160-300° C. for 0.5-4 h; when the connecting material is a compound not containing alkali metals, sintering is performed at 100-200° C. for 0.5-2 h; Wherein, the inorganic silicate is Na2O·nSiO2, n=0.1-5, and the compound not containing alkali metal is silica gel, resin or PI.

3. The method for preparing the all-glass stacked package structure according to claim 1, characterized in that: In step S1, the method for preparing the embedded chip fan-out packaging structure includes the following steps: S10, providing a first glass substrate, and opening a plurality of embedding grooves with a design size larger than the chip size on the first glass substrate; S20, attaching the first surface of the first glass substrate to the temporary adhesive film, and attaching the chip to the embedding groove; S30, preparing dielectric layers on the first surface and the second surface of the first glass substrate respectively, and processing the dielectric layers to expose the I / O ports of the chip to obtain a chip package; S40, performing hole-opening processing on the chip package to form a plurality of through holes penetrating the chip package; S50, electrically leading the I / O ports of the chip out from both sides of the chip package synchronously through the through holes to obtain an embedded chip fan-out packaging structure.

4. The method for preparing the all-glass stacked package structure according to claim 3, wherein: In step S20, the I / O port of the chip protrudes from the surface of the chip, and the chip is attached to the embedding groove with the front side facing upward. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the first glass substrate; S30b, grinding and thinning the first dielectric layer to expose the I / O port of the chip; S30c, removing the temporary adhesive film; S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

5. The method for preparing the all-glass stacked package structure according to claim 3, wherein: In step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed in the embedding slot with the front side facing upward. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the first glass substrate; S30b, performing laser opening processing on the first dielectric layer to expose the I / O port of the chip; S30c, removing the temporary adhesive film; S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

6. The method for preparing the all-glass stacked package structure according to claim 3, wherein: In step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed face down in the embedding slot. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the first glass substrate; S30b, removing the temporary adhesive film; S30c, preparing a second dielectric layer on the first surface of the first glass substrate; S30d, performing laser hole opening processing on the second dielectric layer to expose the I / O port of the chip to obtain a chip package.

7. The method for preparing the all-glass stacked package structure according to claim 3, wherein: Step S50 includes the following steps: S50a, forming a seed layer on the surface of the chip package and the inner wall of the through hole; S50b, attaching a photosensitive film to the seed layer on the surface of the chip package, and forming a patterned window after exposure and development; S50c, preparing a first redistribution layer in the patterned window and on the inner wall of the through hole; S50d, removing the remaining photosensitive film and etching away the exposed seed layer; S50e, preparing solder resist layers in the through hole and on both sides of the chip package having the first redistribution layer, and exposing the pad area of ​​the first redistribution layer; S50f, preparing a nickel-palladium-gold layer in the pad area of ​​the first redistribution layer, and implanting metal bumps in the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure.

8. The method for preparing the all-glass stacked package structure according to claim 1, wherein: In step S1, the method for preparing the embedded chip fan-out packaging structure includes the following steps: S10, providing a first glass substrate, and opening a plurality of first through holes and a plurality of embedding grooves with a design size larger than a chip size on the first glass substrate; S20, attaching the first surface of the first glass substrate to the temporary adhesive film, and attaching the chip to the embedding groove; S30, preparing dielectric layers on the first surface and the second surface of the first glass substrate respectively, and filling the first through hole and the gap between the chip and the first glass substrate with the dielectric layers, processing the dielectric layers, and making the chip The I / O port of the chip is exposed to obtain a chip package; S40, opening a second through hole in the dielectric layer filled in the first through hole; S50, electrically leading the I / O port of the chip out from both sides of the chip package synchronously through the second through hole to obtain an embedded chip fan-out packaging structure.

9. The method for preparing the all-glass stacked package structure according to claim 8, wherein: In step S20, the I / O port of the chip protrudes from the surface of the chip, and the chip is attached to the embedding groove with the front side facing upward. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the first glass substrate; S30b, grinding and thinning the first dielectric layer to expose the I / O port of the chip; S30c, removing the temporary adhesive film; S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

10. The method for preparing the all-glass stacked package structure according to claim 8, wherein: In step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed in the embedding slot with the front side facing upward. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the first glass substrate; S30b, performing laser opening processing on the first dielectric layer to expose the I / O port of the chip; S30c, removing the temporary adhesive film; S30d, preparing a second dielectric layer on the first surface of the first glass substrate to obtain a chip package.

11. The method for preparing the all-glass stack package structure according to claim 8, wherein: In step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed face down in the embedding slot. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the first glass substrate; S30b, removing the temporary adhesive film; S30c, preparing a second dielectric layer on the first surface of the first glass substrate; S30d, performing laser hole opening processing on the second dielectric layer to expose the I / O port of the chip to obtain a chip package.

12. The method for preparing the all-glass stacked package structure according to claim 8, wherein: Step S50 specifically includes the following steps: S50a, forming a seed layer on the surface of the chip package and the inner wall of the second through hole; S50b, attaching a photosensitive film to the seed layer on the surface of the chip package, and forming a patterned window after exposure and development; S50c, preparing a first redistribution layer in the patterned window and on the inner wall of the second through hole; S50d, removing the remaining photosensitive film and etching away the exposed seed layer; S50e, preparing solder resist layers in the second through hole and on both sides of the chip package having the first redistribution layer, and exposing the pad area of ​​the first redistribution layer; S50f, preparing a nickel-palladium-gold layer in the pad area of ​​the first redistribution layer, and implanting metal bumps in the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure.

13. The method for preparing the all-glass stacked package structure according to any one of claims 8 to 12, wherein: In step S40, a second through hole is opened in the dielectric layer filled in the first through hole by using a laser.

14. The method for preparing the all-glass stacked package structure according to claim 2, wherein: The method for preparing the glass metallization circuit structure comprises the following steps: S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate; S200, pressing a photosensitive film on both sides of the second glass substrate, and performing exposure and development processing to form a first patterned window, and making the laser modified area of ​​the second glass substrate exposed in the first patterned window; S300, etching the second glass substrate to form a through hole in the laser modified area and an embedded circuit groove in the non-laser modified area at the first patterned window; S400, removing the remaining photosensitive film, and forming a seed layer on the surface of the embedded circuit groove and the inner wall of the through hole; S500, pressing a photosensitive film on the surface of the second glass substrate and the seed layer on the surface of the embedded circuit groove, and performing exposure and development processing on the photosensitive film to form a second patterned window; S600, forming a conductive column in the through hole and simultaneously forming a second redistribution layer electrically connected to the conductive column in the second patterned window, and making the surface of the second redistribution layer flush with the surface of the second glass substrate; S700, removing the remaining photosensitive film and performing flash etching on the exposed seed layer; S800, preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the surface of the corresponding second redistribution layer, so as to obtain a glass metallization circuit structure.

15. The method for preparing the all-glass stacked package structure according to claim 2, wherein: The method for preparing the glass metallization circuit structure comprises the following steps: S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate; S200, pressing a photosensitive film on both sides of the second glass substrate, and performing exposure and development processing to form a first patterned window, and making the laser modified area of ​​the second glass substrate exposed in the first patterned window; S300, etching the second glass substrate to form a through hole in the laser modified area and an embedded circuit groove in the non-laser modified area at the first patterned window; S400, removing the remaining photosensitive film, and forming a seed layer on the surface of the embedded circuit groove and the inner wall of the through hole; S500, pressing a photosensitive film on the surface of the second glass substrate and the seed layer on the surface of the embedded circuit groove, and performing exposure and development processing on the photosensitive film to form a second patterned window; S600, forming a conductive column in the through hole and simultaneously forming a second redistribution layer electrically connected to the conductive column in the second patterned window, and making the surface of the second redistribution layer flush with the surface of the second glass substrate; S700, removing the remaining photosensitive film and performing flash etching on the exposed seed layer; preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the surface of the corresponding second redistribution layer; S800, according to steps S100-S700, m+1 first substrate structures are obtained, where m is a positive integer, holes are opened in the solder resist layers of the m first substrate structures to expose the pad regions of the second redistribution layers of the first substrate structures, and metal bumps are implanted in the pad regions to obtain a second substrate structure that can be used as an intermediate; S900, dip the metal bump of one of the second substrate structures into nano-metal paste, connect it with the exposed second redistribution layer of the first substrate structure, and then sinter it to fix it; then dip the metal bump of another second substrate structure into nano-metal paste, connect it with the exposed second redistribution layer of the second substrate structure, and then sinter it to fix it, and fix all the second substrate structures in this way, and finally fill the connection material between the first substrate structure and the second substrate structure and between every two adjacent second substrate structures and sinter them to obtain a glass metallization circuit structure.

16. The method for preparing the all-glass stacked package structure according to claim 14 or 15, wherein: In step S300 , the etching rate ratio between the laser modified region and the non-laser modified region of the second glass substrate is 20:

1.

17. The method for preparing the all-glass stacked package structure according to claim 1 or 2, wherein: The method for preparing the glass metallization circuit structure comprises the following steps: S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate; S200, etching the second glass substrate to form a through hole in the laser modified area; S300, forming a seed layer on the inner wall of the through hole and on both sides of the second glass substrate; S400, pressing photosensitive films on the seed layers on both sides of the second glass substrate, and exposing and developing the layers to form patterned windows; S500, manufacturing a second redistribution layer in the patterned window and filling a copper column connected to the second redistribution layer in the through hole; S600, removing the remaining photosensitive film and performing flash etching on the exposed seed layer; S700, preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the surface of the corresponding second redistribution layer, so as to obtain a glass metallization circuit structure.

18. The method for preparing the all-glass stacked package structure according to claim 1 or 2, wherein: The method for preparing the glass metallization circuit structure comprises the following steps: S100, providing a second glass substrate, and performing laser modification on a partial area of ​​the second glass substrate; S200, etching the second glass substrate to form a through hole in the laser modified area; S300, forming a seed layer on the inner wall of the through hole and on both sides of the second glass substrate; S400, pressing photosensitive films on the seed layers on both sides of the second glass substrate, and exposing and developing the layers to form patterned windows; S500, manufacturing a second redistribution layer in the patterned window and filling a copper column connected to the second redistribution layer in the through hole; S600, removing the remaining photosensitive film and performing flash etching on the exposed seed layer; S700, preparing a solder resist layer covering the second glass substrate and the second redistribution layer on one side of the second glass substrate and the surface of the corresponding second redistribution layer; S800, according to steps S100-S700, m+1 first substrate structures are obtained, where m is a positive integer, holes are opened in the solder resist layers of the m first substrate structures to expose the pad regions of the second redistribution layers of the first substrate structures, and metal bumps are implanted in the pad regions to obtain a second substrate structure as an intermediate; S900, dip the metal bump of one of the second substrate structures into nano-metal paste, connect it with the exposed second redistribution layer of the first substrate structure, and then sinter it to fix it; then dip the metal bump of another second substrate structure into nano-metal paste, connect it with the exposed second redistribution layer of the second substrate structure, and then sinter it to fix it, and fix all the second substrate structures in this way, and finally fill the connection material between the first substrate structure and the second substrate structure and between two adjacent second substrate structures and sinter them to obtain a glass metallization circuit structure.

19. An all-glass stacked packaging structure made by the preparation method described in any one of claims 1 to 18, comprising an embedded chip fan-out packaging structure and a glass metallization circuit structure stacked up and down, the metal bumps of the embedded chip fan-out packaging structure are connected to the exposed second redistribution layer of the glass metallization circuit structure, and the gap between the embedded chip fan-out packaging structure and the glass metallization circuit structure is filled with a connection layer formed by sintering a connection material.

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