Embedded fan-out chip packaging structure and preparation method therefor

Abstract

The present application relates to the technical field of integrated circuit packaging. Disclosed are an embedded fan-out chip packaging structure and a preparation method therefor. The preparation method for the embedded fan-out chip packaging structure comprises the following steps: S10, providing a substrate, and providing in the substrate several embedding recesses, each of which has a design size greater than the size of each chip; S20, affixing a first surface of the substrate to a temporary adhesive film, and affixing the chips into the embedding recesses; S30, preparing a dielectric layer on each of the first surface and a second surface of the substrate, and processing the dielectric layer to expose an I / O port of each chip, thus obtaining a chip packaging body; S40, making holes in the chip packaging body to form several through holes running through the chip packaging body; and S50, synchronously and electrically leading out the I / O ports of the chips from two surfaces of the chip packaging body via the through holes to obtain an embedded fan-out chip packaging structure. Using the preparation method can effectively improve the strength of the embedded fan-out chip packaging structure, thereby solving the problem of a large chip packaging structure being fragile.

Description

Embedded chip fan-out packaging structure and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 1, 2023, with application number 202310959644.2, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of integrated circuit packaging, and in particular to an embedded chip fan-out packaging structure and a preparation method thereof. Background Art

[0003] The traditional method for preparing a fan-out chip packaging structure is as follows: providing a temporary carrier, attaching the chip to the temporary carrier through temporary bonding glue; plastic-sealing the chip to form a plastic layer; performing hole-opening and / or grinding on the plastic layer to expose the I / O port of the chip, and at the same time making TMV through-holes that penetrate the plastic layer; making a first circuit layer on the surface of the plastic layer and in the TMV through-holes; debonding, that is, removing the temporary carrier; and making a second circuit layer electrically connected to the first circuit layer on the other side of the plastic layer to obtain a double-sided fan-out chip packaging structure.

[0004] The above-mentioned manufacturing method is only applicable to a single chip or chipset (containing only a few chips). However, some customers require large-scale chip packaging structures (dozens, hundreds, or even more chips simultaneously packaged in a fan-out format). When using the above-mentioned manufacturing method, the resulting product is fragile.

[0005] Summary of the Invention

[0006] One of the purposes of the present application is to provide a method for preparing an embedded chip fan-out packaging structure, which can effectively improve the strength of the embedded chip fan-out packaging structure and solve the problem of the fragility of large-chip packaging structures.

[0007] A method for preparing an embedded chip fan-out packaging structure is provided, comprising the following steps:

[0008] S10, providing a substrate, and forming a plurality of embedding grooves on the substrate, each of which is larger than the chip size;

[0009] S20, attaching the first surface of the substrate to a temporary adhesive film, and attaching the chip to the embedding groove;

[0010] S30, preparing dielectric layers on the first surface and the second surface of the substrate respectively, and processing the dielectric layers to expose the I / O ports of the chip to obtain a chip package;

[0011] S40, performing a hole-forming process on the chip package to form a plurality of through holes penetrating the chip package;

[0012] S50 , electrically leading the I / O ports of the chip out from both sides of the chip package through the through holes synchronously to obtain an embedded chip fan-out package structure.

[0013] Compared with related technologies, this solution eliminates the use of a temporary carrier and instead uses a substrate as a reinforcement plate. The chip is directly embedded in the reinforcement plate, and the chip's I / O ports are then electrically and synchronously led out from both sides to produce a high-strength embedded chip fan-out packaging structure, solving the problem of fragility of large-scale chip packaging structures.

[0014] As one of the solutions for the method of preparing an embedded chip fan-out package structure, in step S20, the I / O port of the chip protrudes from the surface of the chip, and the chip is placed in the embedding groove with the front side facing up. Step S30 specifically includes the following steps:

[0015] S30a, preparing a first dielectric layer on the second surface of the substrate;

[0016] S30b, grinding and thinning the first dielectric layer to expose the I / O port of the chip;

[0017] S30c, removing the temporary adhesive film;

[0018] S30d, preparing a second dielectric layer on the first surface of the substrate to obtain a chip package.

[0019] As a second method for preparing an embedded chip fan-out package structure, in step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed face up in the embedding groove. Step S30 specifically includes the following steps:

[0020] S30a, preparing a first dielectric layer on the second surface of the substrate;

[0021] S30b, performing laser drilling processing on the first dielectric layer to expose the I / O port of the chip;

[0022] S30c, removing the temporary adhesive film;

[0023] S30d, preparing a second dielectric layer on the first surface of the substrate to obtain a chip package.

[0024] As a third solution of the method for preparing an embedded chip fan-out package structure, in step S20, when the I / O port of the chip is flush with the surface of the chip and the chip is placed face down in the embedding groove, step S30 specifically includes the following steps:

[0025] S30a, preparing a first dielectric layer on the second surface of the substrate;

[0026] S30b, removing the temporary adhesive film;

[0027] S30c, preparing a second dielectric layer on the first surface of the substrate;

[0028] S30d, performing laser drilling processing on the second dielectric layer to expose the I / O port of the chip to obtain a chip package.

[0029] Furthermore, step S50 specifically includes the following steps:

[0030] S50a, forming a seed layer on the surface of the chip package and the inner wall of the through hole;

[0031] S50b, attaching a photosensitive film to the seed layer on the surface of the chip package, and forming a patterned window after exposure and development;

[0032] S50c, preparing a redistribution layer in the patterned window and on the inner wall of the through hole;

[0033] S50d, removing the remaining photosensitive film and etching away the exposed seed layer;

[0034] S50e, preparing solder resist layers in the through hole and on both sides of the chip package with the redistribution layer, and exposing the pad area of ​​the redistribution layer;

[0035] S50f, preparing a nickel-palladium-gold layer in the pad area of ​​the redistribution layer, and implanting metal bumps in the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure.

[0036] Wherein, the substrate is BT board, stainless steel board, glass material or FR-3 material.

[0037] The second purpose of the present application is to provide an embedded chip fan-out packaging structure manufactured using the above-mentioned preparation method, wherein the embedded chip fan-out packaging structure has high strength and is not easy to break.

[0038] The embedded chip fan-out packaging structure includes:

[0039] A substrate having a plurality of embedding grooves and a plurality of through holes;

[0040] A plurality of chips are fixed in the embedding grooves through a dielectric layer, and the I / O ports of the chips are exposed on the dielectric layer;

[0041] a seed layer, located on the inner wall of the through hole and the surface of the dielectric layer and electrically connected to the I / O port of the chip;

[0042] a redistribution layer, located on the seed layer;

[0043] The solder resist layer is filled in the through hole and covers the redistribution layer and the surface of the dielectric layer, and the pad area of ​​the redistribution layer is exposed on the solder resist layer.

[0044] As a solution of the embedded chip fan-out packaging structure, it also includes a nickel-palladium-gold layer and a metal bump. The nickel-palladium-gold layer is located in the pad area of ​​the redistribution layer and is electrically connected to the metal bump.

[0045] Effects of this application: This application creates an embedding groove and a through-hole on the substrate, embeds the chip into the embedding groove, and secures it via a dielectric layer. Furthermore, by simultaneously forming a circuit layer on the inner wall of the through-hole and the surface of the dielectric layer, the chip's I / O port can be electrically connected from both sides. Compared to related technologies, this application effectively increases the strength of the embedded chip fan-out package structure by introducing a substrate as a reinforcement plate for chip mounting, thus solving the problem of fragility of large-chip chip packaging structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a cross-sectional view of a chip according to Example 1 of the present application embedded in an embedding groove of a substrate;

[0047] FIG2 is a schematic cross-sectional view of the first dielectric layer after being pressed according to Example 1 of the present application;

[0048] FIG3 is a cross-sectional view of the chip package according to Example 1 of the present application after a through hole is formed;

[0049] FIG4 is a schematic cross-sectional view of the preparation of the redistribution layer according to Example 1 of the present application;

[0050] FIG5 is a cross-sectional view of Example 1 of the present application after applying green oil;

[0051] FIG6 is a cross-sectional view of the nickel-palladium-gold coating according to Example 1 of the present application;

[0052] FIG7 is a cross-sectional view of the nickel-palladium-gold layer after metal bumps are implanted according to Example 1 of the present application;

[0053] FIG8 is a cross-sectional view of a chip according to Example 3 of the present application embedded in an embedding groove of a substrate;

[0054] FIG9 is a schematic cross-sectional view of the first dielectric layer after being pressed according to Example 3 of the present application;

[0055] FIG10 is a schematic cross-sectional view of the chip package according to Example 3 of the present application after a through hole is formed;

[0056] FIG11 is a cross-sectional view of the preparation of the redistribution layer according to Example 3 of the present application;

[0057] FIG12 is a cross-sectional view of Example 3 of the present application after applying green oil;

[0058] FIG13 is a cross-sectional view of the nickel-palladium-gold coating according to Example 3 of the present application;

[0059] FIG14 is a cross-sectional schematic diagram of the nickel palladium gold layer after metal bumps are implanted as described in Example 3 of the present application. DETAILED DESCRIPTION

[0060] The technical solution of this application is further explained below through specific implementation methods.

[0061] Unless otherwise specified, the various raw materials of the present application can be purchased commercially or prepared according to conventional methods in the art.

[0062] Example 1

[0063] The preparation method of the embedded chip fan-out packaging structure of this embodiment is as follows:

[0064] 1. Use BT board as substrate 1, and open several embedding grooves 1a (through-hole form) on the substrate 1 with a design size larger than the size of the chip 2;

[0065] 2. Attach the lower surface (first surface) of the substrate 1 to a temporary adhesive film 3;

[0066] 3. Provide several chips 2, with their I / O ports protruding from the surface (bump pillar). Place the chips 2 facing up (i.e., with their I / O ports facing up) on the temporary adhesive film 3 embedded in the slot 1a, as shown in Figure 1.

[0067] 4. Press a first dielectric layer 4a on the upper surface (second surface) of the substrate 1 so that the first dielectric layer 4a fills the gap between the chip 2 and the substrate 1. Grind and thin the first dielectric layer 4a to expose the I / O port of the chip 2, as shown in Figure 2.

[0068] 5. Remove the temporary adhesive film 3 on the first side of the substrate 1;

[0069] 6. Pressing a second dielectric layer 4b on the first surface of the substrate 1 to obtain a chip package;

[0070] 7. Use mechanical drilling to open through holes in the chip package to form a plurality of through holes 1b on the chip package, as shown in FIG3 ;

[0071] 8. Simultaneously prepare a seed layer on the inner wall of the through hole 1 b and the side of the first dielectric layer 4 a away from the substrate 1 and the side of the second dielectric layer 4 b away from the substrate 1 by vacuum sputtering;

[0072] 9. A photosensitive film is applied to the seed layer on the first dielectric layer 4a and the seed layer on the second dielectric layer 4b, and then subjected to exposure and development treatment to form a patterned window that exposes part of the seed layer;

[0073] 10. Synchronously fabricate a redistribution layer 5 by electroplating on the surface of the seed layer on the inner wall of the through hole 1b and in the patterned window, as shown in FIG4 ;

[0074] 11. Remove the remaining photosensitive film to expose part of the seed layer, and etch the exposed seed layer;

[0075] 12. Green oil is applied to the inside of the through hole 1b where the seed layer and the redistribution layer 5 are prepared, and to the surfaces of the first dielectric layer 4a, the second dielectric layer 4b, and the redistribution layer 5. After the green oil is cured, it is exposed and developed to form a solder resist layer 6 that exposes the pad area of ​​the redistribution layer 5, as shown in FIG5 ; the first dielectric layer 4a and the second dielectric layer 4b constitute a dielectric layer;

[0076] 13. Nickel palladium gold is formed on the pad area of ​​the redistribution layer 5 to obtain a nickel palladium gold layer 7, as shown in FIG6 ;

[0077] 14. Implant metal bumps 8 in the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure, as shown in FIG7. As shown in FIG7, the embedded chip fan-out packaging structure obtained by the above preparation method includes:

[0078] A substrate 1 is provided with a plurality of embedding grooves 1a and a plurality of through holes 1b;

[0079] Several chips 2 are fixed in the embedding grooves 1a via a first dielectric layer 4a above the substrate 1 and a second dielectric layer 4b below the substrate 1, with the I / O ports of the chips 2 protruding from the surface of the chips 2 and exposed on the first dielectric layer 4a. The I / O ports of the chips 2 are flush with the surface of the first dielectric layer 4a, wherein the first dielectric layer 4a and the second dielectric layer 4b are respectively partially embedded in the gap between the chips 2 and the embedding grooves 1a.

[0080] a seed layer located on the inner wall of the through hole 1b and the surface of the first dielectric layer 4a and the surface of the second dielectric layer 4b and electrically connected to the I / O port of the chip 2; specifically, the seed layer is located on the inner wall of the through hole 1b and the upper surface of the first dielectric layer 4a and the lower surface of the second dielectric layer 4b;

[0081] The redistribution layer 5 is located on the seed layer, specifically, on the surface of the seed layer on the inner wall of the through hole 1b and on the surfaces of the seed layer on both sides of the chip package;

[0082] a solder resist layer 6 filling the through hole 1 b and covering the surfaces of the redistribution layer 5 , the first dielectric layer 4 a and the second dielectric layer 4 b , with the pad area of ​​the redistribution layer 5 exposed on the solder resist layer 6 ;

[0083] A nickel-palladium-gold layer 7 and a metal bump 8 , wherein the nickel-palladium-gold layer 7 is located in the pad area of ​​the redistribution layer 5 and is electrically connected to the metal bump 8 .

[0084] Example 2

[0085] This embodiment is substantially the same as the above-mentioned embodiment 1 (refer to the drawings of the above-mentioned embodiment 1, and the same reference numerals are used for the same components). Specifically, the method for preparing the embedded chip fan-out package structure of this embodiment is as follows:

[0086] 1. Select a stainless steel plate as the substrate 1, and open a number of embedding grooves 1a (through-hole form) on the substrate 1 with a design size larger than the size of the chip 2;

[0087] 2. Attach the lower surface (first surface) of the substrate 1 to a temporary adhesive film 3;

[0088] 3. Provide several chips 2, with the I / O ports of the chips 2 flush with the surface of the chips 2 (ubm), and attach the chips 2 with the front side facing up (i.e., the I / O ports facing up) to the temporary adhesive film 3 embedded in the slot 1a;

[0089] 4. Press a first dielectric layer 4a on the upper surface (second surface) of the substrate 1, and perform laser drilling on the first dielectric layer 4a aligned with the I / O port of the chip 2 to expose the I / O port of the chip 2;

[0090] 5. Remove the temporary adhesive film 3 on the first side of the substrate 1;

[0091] 6. Pressing a second dielectric layer 4b on the first surface of the substrate 1 to obtain a chip package;

[0092] 7. Use mechanical drilling to open through holes in the chip package to form a number of through holes 1b on the chip package;

[0093] 8. A seed layer is simultaneously formed on the inner wall of the through hole 1b and on the side of the first dielectric layer 4a and the side of the second dielectric layer 4b away from the substrate 1 by vacuum sputtering. The seed layer extends to the I / O port of the chip 2 and is electrically connected to the I / O port of the chip;

[0094] 9. A photosensitive film is applied to the seed layer on the first dielectric layer 4a and the seed layer on the second dielectric layer 4b, and then subjected to exposure and development treatment to form a patterned window that exposes part of the seed layer;

[0095] 10. Synchronously forming a redistribution layer 5 by electroplating on the surface of the seed layer on the inner wall of the through hole 1b and in the patterned window;

[0096] 11. Remove the remaining photosensitive film to expose part of the seed layer, and etch the exposed seed layer;

[0097] 12. Apply green oil inside the through hole 1b where the seed layer and the redistribution layer 5 are prepared, and on the surfaces of the first dielectric layer 4a, the second dielectric layer 4b, and the redistribution layer 5. After the green oil is cured, it is exposed and developed to form a solder resist layer 6 that exposes the pad area of ​​the redistribution layer 5. The first dielectric layer 4a and the second dielectric layer 4b constitute a dielectric layer.

[0098] 13. Nickel palladium gold is formed on the pad area of ​​the redistribution layer 5 to obtain a nickel palladium gold layer 7;

[0099] 14. Implant metal bumps 8 into the nickel-palladium-gold layer 7 to obtain an embedded chip fan-out packaging structure.

[0100] The embedded chip fan-out packaging structure prepared by the above preparation method includes:

[0101] A substrate 1 is provided with a plurality of embedding grooves 1a and a plurality of through holes 1b;

[0102] Several chips 2 are fixed in the embedding grooves 1a via a first dielectric layer 4a above the substrate 1 and a second dielectric layer 4b below the substrate 1, with the I / O ports of the chips 2 flush with the surface of the chips 2. The first dielectric layer 4a has a hole structure that exposes the I / O ports of the chips 2. The first dielectric layer 4a and the second dielectric layer 4b are each partially embedded in the gap between the chips 2 and the embedding grooves 1a.

[0103] A seed layer is located on the inner wall of the through hole 1b and the surface of the first dielectric layer 4a, the surface of the second dielectric layer 4b, and the hole structure of the first dielectric layer 4a. The seed layer is electrically connected to the I / O port of the chip 2. Specifically, the seed layer is located on the inner wall of the through hole 1b and the upper surface of the first dielectric layer 4a and the lower surface of the second dielectric layer 4b.

[0104] The redistribution layer 5 is located on the seed layer, specifically, on the surface of the seed layer on the inner wall of the through hole 1b and on the surfaces of the seed layer on both sides of the chip package;

[0105] A solder resist layer 6 is filled in the through hole 1b and the surface of the redistribution layer 5 and the dielectric layer, and the pad area of ​​the redistribution layer 5 is exposed on the solder resist layer 6;

[0106] A nickel-palladium-gold layer 7 and a metal bump 8 , wherein the nickel-palladium-gold layer 7 is located in the pad area of ​​the redistribution layer 5 and is electrically connected to the metal bump 8 .

[0107] Example 3

[0108] The preparation method of the embedded chip fan-out packaging structure of this embodiment is as follows:

[0109] 1. Use BT board as substrate 1, and open several embedding slots 1a (through-hole form) on the substrate 1 with a design size larger than the size of the chip 2;

[0110] 2. Attach the lower surface (first surface) of the substrate 1 to a temporary adhesive film 3;

[0111] 3. Provide several chips 2, with the I / O ports of the chips 2 flush with the surface of the chips 2 (ubm). Place the chips 2 face down (i.e., the I / O ports face down) on the temporary adhesive film 3 embedded in the slot 1a, as shown in Figure 8;

[0112] 4. Pressing a first dielectric layer 4a on the upper surface (second surface) of the substrate 1 and embedding the first dielectric layer 4a into the gap between the chip 2 and the embedding groove 1a, as shown in FIG9 ;

[0113] 5. Remove the temporary adhesive film 3 on the first side of the substrate 1;

[0114] 6. Press a second dielectric layer 4b on the first surface of the substrate 1, and perform laser drilling on the second dielectric layer 4b aligned with the I / O port of the chip to expose the I / O port of the chip 2, thereby obtaining a chip package;

[0115] 7. Use mechanical drilling to open through holes in the chip package to form a plurality of through holes 1b on the chip package, as shown in FIG10 ;

[0116] 8. A seed layer is simultaneously formed on the inner wall of the through hole 1b and on the side of the first dielectric layer 4a and the side of the second dielectric layer 4b away from the substrate 1 by vacuum sputtering. The seed layer extends to the I / O port of the chip 2 and is electrically connected to the I / O port of the chip 2.

[0117] 9. A photosensitive film is applied to the seed layer on the first dielectric layer 4a and the seed layer on the second dielectric layer 4b, and then subjected to exposure and development treatment to form a patterned window that exposes part of the seed layer;

[0118] 10. Synchronously forming a redistribution layer 5 by electroplating on the surface of the seed layer on the inner wall of the through hole 1b and in the patterned window;

[0119] 11. Remove the remaining photosensitive film to expose part of the seed layer, and then etch the exposed seed layer, as shown in Figure 11;

[0120] 12. Green oil is applied to the inside of the through hole 1b where the seed layer and the redistribution layer 5 are prepared, and to the surfaces of the first dielectric layer 4a, the second dielectric layer 4b, and the redistribution layer 5. After the green oil is cured, it is exposed and developed to form a solder resist layer 6 that exposes the pad area of ​​the redistribution layer 5, as shown in FIG12 ; the first dielectric layer 4a and the second dielectric layer 4b constitute a dielectric layer;

[0121] 13. As shown in FIG13 , nickel-palladium-gold is formed on the pad area of ​​the redistribution layer 5 to form a nickel-palladium-gold layer 7;

[0122] 14. Metal bumps 8 are implanted into the nickel-palladium-gold layer 7 to obtain the embedded chip fan-out packaging structure shown in FIG. 14 .

[0123] The embedded chip fan-out packaging structure of this embodiment includes:

[0124] A substrate 1 is provided with a plurality of embedding grooves 1a and a plurality of through holes 1b;

[0125] Several chips are fixed in the embedding groove 1a by a first dielectric layer 4a above the substrate 1 and a second dielectric layer 4b below the substrate 1, with the I / O port of each chip 2 flush with the surface of the chip 2, and the second dielectric layer 4b has a hole structure that exposes the I / O port of the chip 2, wherein the first dielectric layer 4a and the second dielectric layer 4b are respectively partially embedded in the gap between the chip 2 and the embedding groove 1a;

[0126] A seed layer is located on the inner wall of the through hole 1b and the surface of the first dielectric layer 4a, the surface of the second dielectric layer 4b, and the hole structure of the first dielectric layer 4a. The seed layer is electrically connected to the I / O port of the chip 2. Specifically, the seed layer is located on the inner wall of the through hole 1b and the upper surface of the first dielectric layer 4a and the lower surface of the second dielectric layer 4b.

[0127] The redistribution layer 5 is located on the seed layer, specifically, on the surface of the seed layer on the inner wall of the through hole 1b and on the surfaces of the seed layer on both sides of the chip package;

[0128] A solder resist layer 6 is filled in the through hole 1b and the surface of the redistribution layer 5 and the dielectric layer, and the pad area of ​​the redistribution layer 5 is exposed on the solder resist layer 6;

[0129] A nickel-palladium-gold layer 7 and a metal bump 8 , wherein the nickel-palladium-gold layer 7 is located in the pad area of ​​the redistribution layer 5 and is electrically connected to the metal bump 8 .

Claims

1. A method for preparing an embedded chip fan-out packaging structure, comprising the following steps: S10, providing a substrate, and opening a plurality of embedding grooves on the substrate, the designed size of which is larger than the size of the chip; S20, attaching the first surface of the substrate to the temporary adhesive film, and attaching the chip to the embedding groove; S30, preparing dielectric layers on the first surface and the second surface of the substrate respectively, and processing the dielectric layers to expose the I / O ports of the chip to obtain a chip package; S40, performing hole-opening processing on the chip package to form a plurality of through holes penetrating the chip package; S50, electrically leading the I / O ports of the chip out from both sides of the chip package synchronously through the through holes to obtain an embedded chip fan-out packaging structure.

2. The method for preparing an embedded chip fan-out packaging structure according to claim 1, wherein: In step S20, the I / O port of the chip protrudes from the surface of the chip, and the chip is attached to the embedding groove with the front side facing upward. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the substrate; S30b, grinding and thinning the first dielectric layer to expose the I / O port of the chip; S30c, removing the temporary adhesive film; S30d, preparing a second dielectric layer on the first surface of the substrate to obtain a chip package.

3. The method for preparing an embedded chip fan-out packaging structure according to claim 1, wherein: In step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed in the embedding slot with the front side facing upward. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the substrate; S30b, performing laser opening processing on the first dielectric layer to expose the I / O port of the chip; S30c, removing the temporary adhesive film; S30d, preparing a second dielectric layer on the first surface of the substrate to obtain a chip package.

4. The method for preparing an embedded chip fan-out packaging structure according to claim 1, wherein: In step S20, the I / O port of the chip is flush with the surface of the chip, and the chip is placed face down in the embedding slot. Step S30 specifically includes the following steps: S30a, preparing a first dielectric layer on the second surface of the substrate; S30b, removing the temporary adhesive film; S30c, preparing a second dielectric layer on the first surface of the substrate; S30d, performing laser hole opening processing on the second dielectric layer to expose the I / O port of the chip, Get a chip package.

5. The method for preparing an embedded chip fan-out packaging structure according to claim 1, wherein: Step S50 specifically includes the following steps: S50a, forming a seed layer on the surface of the chip package and the inner wall of the through hole; S50b, attaching a photosensitive film to the seed layer on the surface of the chip package, and forming a patterned window after exposure and development; S50c, preparing a redistribution layer in the patterned window and on the inner wall of the through hole; S50d, removing the remaining photosensitive film and etching away the exposed seed layer; S50e, preparing solder resist layers in the through hole and on both sides of the chip package having the redistribution layer, and exposing the pad area of ​​the redistribution layer; S50f, preparing a nickel-palladium-gold layer in the pad area of ​​the redistribution layer, and implanting metal bumps in the nickel-palladium-gold layer to obtain an embedded chip fan-out packaging structure.

6. The method for preparing an embedded chip fan-out packaging structure according to any one of claims 1 to 5, wherein: The substrate is made of BT board, stainless steel board, glass material or FR-3 material.

7. An embedded chip fan-out packaging structure prepared by the preparation method according to any one of claims 1 to 6, comprising: A substrate, wherein the substrate is provided with a plurality of embedding grooves and a plurality of through holes; A plurality of chips are fixed in the embedding grooves through a dielectric layer, and the I / O ports of the chips are exposed on the dielectric layer; A seed layer, located on the inner wall of the through hole and the surface of the dielectric layer and electrically connected to the I / O port of the chip; a redistribution layer, located on the seed layer; The solder resist layer is filled in the through hole and covers the redistribution layer and the surface of the dielectric layer, and the pad area of ​​the redistribution layer is exposed on the solder resist layer. 8 . The embedded chip fan-out packaging structure according to claim 7 , further comprising a nickel-palladium-gold layer and a metal bump, wherein the nickel-palladium-gold layer is located in the pad area of ​​the redistribution layer and is electrically connected to the metal bump.

Images