Chip packaging structure with fuse

Abstract

According to the chip packaging structure with the fuse, the fuse is arranged in the first metal layer, and the first chip and the second chip are arranged on the fifth metal layer and the sixth metal layer respectively, so that the area of the first chip and the area of the second chip are not affected by existence of the fuse; the size of the chip in the packaging structure provided by the utility model can be consistent with the size of the chip without the fuse in the packaging structure in the prior art.

Description

Technical Field

[0001] Embodiments of the present application belong to the field of semiconductor technology, and in particular, relate to a chip packaging structure with a fuse. Background Art

[0002] Transient voltage and surge are important factors leading to damage of electronic products. However, during daily use and manufacturing of electronic products, they are often subject to transient voltage, DC voltage greater than the operating voltage, and surge impact. Therefore, it is essential to use a transient voltage suppressor on electronic products. In traditional transient voltage suppressors, once the surge or DC voltage exceeds the capacity of the transient voltage suppressor, it will cause the transient voltage suppressor to short-circuit. After the device short-circuits, the current flowing through the device will increase instantaneously. When the current exceeds the range that the wire bonding of the transient voltage suppressor can withstand, it will cause the transient voltage suppressor to open-circuit to the ground. After the transient voltage suppressor opens-circuit, the surge or DC voltage will directly act on the backend chip, resulting in damage to the backend circuit. Therefore, a transient voltage suppressor with a fuse is proposed. When the surge or abnormal DC voltage is greater than the breakdown voltage of the transient voltage suppressor, the current is discharged through the transient voltage suppressor. When the energy exceeds the capacity of the transient voltage suppressor, the transient voltage suppressor chip short-circuits, the current increases instantaneously, and the fuse is blown. After the fuse is blown, the surge or DC voltage cannot act on the backend, effectively protecting the backend system. Since the transient voltage suppressor with a fuse integrates a fuse in the package, the chip area is limited and the protection ability becomes weak. Therefore, a new packaging structure for a transient voltage suppressor with a fuse is proposed, and the chip size of the new packaging structure can be made the same as that of a traditional chip without a fuse. Summary of the Invention

[0003] To solve or alleviate the problems in the prior art, the chip size in the packaging structure provided by the present application can be the same as that of a chip without a fuse in the packaging structure in the prior art.

[0004] The present application provides a chip packaging structure with a fuse, including: a first insulating layer, a second insulating layer, a first chip, and a second chip;

[0005] A first metal layer and a second metal layer are arranged at intervals on one side of the first insulating layer, and a third metal layer and a fourth metal layer are arranged at positions corresponding to the first metal layer and the second metal layer on the other side of the first insulating layer. The first metal layer and the third metal layer are connected through a first conductive connection layer in the first insulating layer, and the second metal layer and the fourth metal layer are connected through a second conductive connection layer in the first insulating layer. Electrodes of the first chip and the second chip are led out through the third metal layer and the fourth metal layer;

[0006] The side of the first metal layer away from the first insulating layer is connected to the fifth metal layer through a third conductive connection layer. The side of the second metal layer away from the first insulating layer is connected to the sixth metal layer through a fourth conductive connection layer, and the fifth metal layer and the sixth metal layer are arranged at intervals.

[0007] A first chip is arranged on the side of the fifth metal layer away from the third conductive connection layer, and a second chip is arranged on the side of the sixth metal layer away from the fourth conductive connection layer, and the first chip and the second chip are arranged at intervals.

[0008] The first chip is connected to the seventh metal layer through a fifth conductive connection layer, and the second chip is connected to the seventh metal layer through a sixth conductive connection layer. The seventh metal layer is used to connect the first chip and the second chip.

[0009] Among them, the first metal layer, the second metal layer, the fifth metal layer, the sixth metal layer, the seventh metal layer, the third conductive connection layer, the fourth conductive connection layer, the fifth conductive connection layer, the sixth conductive connection layer, the first chip, and the second chip above one side of the first insulating layer are all arranged in the second insulating layer.

[0010] The first metal layer has a fuse, and the fuse material is copper.

[0011] As a preferred embodiment of the present application, both between the side of the fifth metal layer away from the third conductive connection layer and the first chip and between the side of the sixth metal layer away from the fourth conductive connection layer and the second chip are connected through conductive glue.

[0012] As a preferred embodiment of the present application, the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, the sixth metal layer, the seventh metal layer, the first conductive connection layer, the second conductive connection layer, the third conductive connection layer, the fourth conductive connection layer, the fifth conductive connection layer, and the sixth conductive connection layer are all copper.

[0013] The present application provides a chip packaging structure with a fuse. In the present application, the fuse is arranged in the first metal layer, and the first chip and the second chip are respectively arranged on the fifth metal layer and the sixth metal layer. This structural arrangement can enable the areas of the first chip and the second chip not to be affected by the presence of the fuse. The chip size in the packaging structure provided by the present application can be the same as the chip size without a fuse in the existing packaging structure. Description of the Drawings

[0014] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. Some specific embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings in an exemplary rather than restrictive manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0015] Figure 1 is a schematic cross-sectional view of the Vin position of a chip package structure with a fuse provided by the prior art;

[0016] Figure 2 is a schematic cross-sectional view of the Vout position of a chip package structure with a fuse provided by the prior art;

[0017] Figure 3 is a schematic top view structure of different layers of a chip package structure with a fuse provided by the prior art;

[0018] Figure 4 is a schematic cross-sectional view of the Vin position of a chip package structure with a fuse provided by the present application;

[0019] Figure 5 is a schematic cross-sectional view of the Vout position of a chip package structure with a fuse provided by the present application;

[0020] Figure 6 is a schematic top view structure of different layers of a chip package structure with a fuse provided by the present application; Detailed Description of the Embodiments

[0021] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0022] As Figure 1 and Figure 2 shown, Figure 1 is Figure 3 a cross-sectional view from the voltage input terminal Vin to the ground terminal Gnd in Figure 2 is Figure 3Cross-sectional view from the voltage output terminal Vout to the ground terminal Gnd. The first metal layer 03 is provided with a fuse 20, and the first chip 13 and the second chip 14 are directly disposed corresponding to the first metal layer 03 and the second metal layer 06 respectively through conductive adhesives, and the first metal layer 03 and the second metal layer 06 belong to the same layer. This causes a technical problem that the transient voltage suppressor with a fuse has a limited chip area due to the integration of the fuse in the package, resulting in a weakened protection ability.

[0023] To solve the technical problem in the prior art that the chip with a fuse has a relatively small actual effective area (the surge protection ability is related to the chip area of the transient voltage suppression device) due to the need to integrate the fuse, resulting in a weak protection ability, a new package structure of the present application is proposed. The equivalent wire diameter of the fuse in the chip package structure of the present application and the prior art is smaller than the wire diameter of the connection line between the chips. At the same time, the surge overcurrent capacity of the fuse is greater than the surge resistance ability of the chip itself.

[0024] As Figure 4 and Figure 5 shown, Figure 4 For Figure 6 the cross-sectional view from the voltage input terminal Vin to the ground terminal Gnd in Figure 5 For Figure 6 the cross-sectional view from the voltage output terminal Vout to the ground terminal Gnd in Figure 4 in

[0025] The first metal layer 03 and the fifth metal layer 11 are isolated by an insulating layer 21.

[0026] On one side of the first insulating layer 07, the first metal layer 03 and the second metal layer 06 are disposed at intervals. On the other side of the first insulating layer 07, the third metal layer 01 and the fourth metal layer 04 are disposed at positions corresponding to the first metal layer 03 and the second metal layer 06 respectively. The first metal layer 03 and the third metal layer 01 are connected through a first conductive connection layer 02 in the first insulating layer 07, and the second metal layer 06 and the fourth metal layer 04 are connected through a second conductive connection layer 05 in the first insulating layer 07. The electrodes of the first chip 13 and the second chip 14 are led out through the third metal layer 01 and the fourth metal layer 04;

[0027] On one side of the fifth metal layer 11 away from the third conductive connection layer 09, a first chip 13 is provided. On one side of the sixth metal layer 12 away from the fourth conductive connection layer 10, a second chip 14 is provided, and the first chip 13 and the second chip 14 are arranged at intervals.

[0028] The first chip 13 is connected to the seventh metal layer 17 through a fifth conductive connection layer 15, and the second chip 14 is connected to the seventh metal layer 17 through a sixth conductive connection layer 16. The seventh metal layer 17 is used to connect the first chip 13 and the second chip 14.

[0029] Among them, the first metal layer 03, the second metal layer 06, the fifth metal layer 11, the sixth metal layer 12, the seventh metal layer 17, the third conductive connection layer 09, the fourth conductive connection layer 10, the fifth conductive connection layer 15, the sixth conductive connection layer 16, the first chip 13, and the second chip 14 above one side of the first insulating layer 07 are all arranged in the second insulating layer 08.

[0030] A fuse 20 is arranged in the first metal layer 03.

[0031] In this embodiment, it mainly includes a voltage input terminal Vin, a voltage output terminal Vout, and a ground terminal Gnd. In the embodiment of the present application, the voltage input terminal Vin is the Vin terminal of the third metal layer 01, the voltage output terminal Vout is the Vout terminal of the third metal layer 01, and the ground terminal Gnd is the fourth metal layer 04.

[0032] It should be noted that in actual application, the normal current passes through the voltage input terminal Vin, through the fuse 20, to the voltage output terminal Vout and directly acts on the subsequent circuit, without flowing through the chip of the transient voltage suppression device. When a surge occurs, after the current passes through the fuse 20 from the voltage input terminal Vin to the output terminal Vout, the transient voltage suppression device chip is turned on, and the current is discharged through the chip of the transient voltage suppression device, and the voltage between the voltage output terminal Vout and the ground terminal Gnd is clamped and decreased.

[0033] As a preferred embodiment of the present application, between the side of the fifth metal layer 11 away from the third conductive connection layer 09 and the first chip 13, and between the side of the sixth metal layer 12 away from the fourth conductive connection layer 10 and the second chip 14, they are both connected by conductive adhesive.

[0034] As a preferred embodiment of the present application, the first metal layer 03, the second metal layer 06, the third metal layer 01, the fourth metal layer 04, the fifth metal layer 11, the sixth metal layer 12, the seventh metal layer 17, the first conductive connection layer 02, the second conductive connection layer 05, the third conductive connection layer 09, the fourth conductive connection layer 10, the fifth conductive connection layer 15, and the sixth conductive connection layer 16 are all made of copper.

[0035] A fuse chip packaging structure provided by the present application. A fuse 20 is provided in the first metal layer 03, and a third conductive connection layer 09 and a fifth metal layer 11 are further provided between the first chip 13 and the first metal layer 03. A fourth conductive connection layer 10 and a sixth metal layer 12 are further provided between the second chip 14 and the second metal layer 06. That is to say, between the first chip 13 and the first metal layer 03, and between the second chip 14 and the second metal layer 06, they are not directly connected but indirectly connected. This structural setting can enable the areas of the first chip 13 and the second chip 14 not to be affected by the presence of the fuse. The chip size in the packaging structure provided by the present application can be the same as the chip size of the fuse-free chip in the existing packaging structure.

[0036] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A fuse chip package structure, characterized in that Including: A first insulating layer, a second insulating layer, a first chip, and a second chip; On one side of the first insulating layer, a first metal layer and a second metal layer are arranged at intervals. On the other side of the first insulating layer, a third metal layer and a fourth metal layer are arranged at positions corresponding to the first metal layer and the second metal layer respectively. The first metal layer and the third metal layer are connected through a first conductive connection layer in the first insulating layer, and the second metal layer and the fourth metal layer are connected through a second conductive connection layer in the first insulating layer. Electrodes of the first chip and the second chip are led out through the third metal layer and the fourth metal layer; The side of the first metal layer away from the first insulating layer is connected to a fifth metal layer through a third conductive connection layer, and the side of the second metal layer away from the first insulating layer is connected to a sixth metal layer through a fourth conductive connection layer, and the fifth metal layer and the sixth metal layer are arranged at intervals; A first chip is arranged on the side of the fifth metal layer away from the third conductive connection layer, and a second chip is arranged on the side of the sixth metal layer away from the fourth conductive connection layer, and the first chip and the second chip are arranged at intervals; The first chip is connected to a seventh metal layer through a fifth conductive connection layer, and the second chip is connected to the seventh metal layer through a sixth conductive connection layer, and the seventh metal layer is used to connect the first chip and the second chip; Among them, the first metal layer, the second metal layer, the fifth metal layer, the sixth metal layer, the seventh metal layer, the third conductive connection layer, the fourth conductive connection layer, the fifth conductive connection layer, the sixth conductive connection layer, the first chip, and the second chip above one side of the first insulating layer are all arranged in the second insulating layer; A fuse is arranged in the first metal layer, and the fuse material is copper.

2. The fuse chip package structure according to claim 1, characterized in that, Both between the side of the fifth metal layer away from the third conductive connection layer and the first chip and between the side of the sixth metal layer away from the fourth conductive connection layer and the second chip are connected through conductive adhesive.

3. A fuse chip package structure as claimed in claim 1, wherein, The first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, the sixth metal layer, the seventh metal layer, the first conductive connection layer, the second conductive connection layer, the third conductive connection layer, the fourth conductive connection layer, the fifth conductive connection layer, and the sixth conductive connection layer are all copper.

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