Gate drive circuit and display panel

Abstract

The present invention relates to the field of display panels. Provided are a gate drive circuit and a display panel. The gate drive circuit comprises a plurality of stages of shift register units and a timing controller, wherein the shift register unit at each stage comprises 12 or 13 transistors and three capacitors, and the timing controller comprises three timing control signal lines. By means of the gate drive circuit and the display panel of the present invention, a new 12T3C or 13T3C circuit of shift register units is provided, such that the output stability of the shift register units is improved, and the number of components of the shift register units is reduced, thereby reducing the width of a frame of the display panel.

Description

Gate drive circuit and display panel Technical Field

[0001] The present invention relates to the field of frame design of display panels, and in particular to a gate drive circuit and a display panel. Background Art

[0002] The display panel includes multiple pixel circuits arranged in an array within the display area and a gate driver circuit located in the edge area. The gate driver circuit includes a multi-stage shift register and is used to provide corresponding scan drive signals to the corresponding pixel circuits. Because the gate driver circuit is located in the edge area of ​​the display panel, the number of shift register components and the arrangement of the gate driver circuit determine the width of the display panel's border.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field.

[0004] Summary of the Invention

[0005] In view of this, the present invention provides a gate driving circuit and a display panel.

[0006] One aspect of the present invention provides a gate drive circuit, comprising a multi-stage shift register unit, wherein the shift register unit comprises a control module, a reset module and an output setting module;

[0007] The control module includes:

[0008] a third transistor, wherein a first electrode of the third transistor is connected to the first power supply, a second electrode is connected to the third node, and a gate is connected to the first timing control terminal;

[0009] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode of the fourth transistor is connected to the second timing control terminal, and a gate of the fourth transistor is connected to the fourth node;

[0010] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the third timing control terminal, a second electrode of the fifth transistor is connected to the first node, and a gate of the fifth transistor is connected to the third node;

[0011] an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the first power supply, a second electrode is connected to the third node, and a gate is connected to the third timing control terminal;

[0012] The reset module includes:

[0013] a second transistor, wherein a first electrode of the second transistor is connected to the first power supply, a second electrode is connected to the fourth node, and a gate is connected to the first timing control terminal;

[0014] a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first node, a second electrode of the tenth transistor is connected to the second power supply, and a gate of the tenth transistor is connected to the third timing control terminal;

[0015] a twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the third timing control terminal, a second electrode of the twelfth transistor is connected to the first node, and a gate of the twelfth transistor is connected to the fourth node;

[0016] The output setting module includes:

[0017] a first transistor, wherein a first electrode of the first transistor is connected to the fourth node, a second electrode of the first transistor is connected to the signal input terminal, and a gate of the first transistor is connected to the third timing control terminal;

[0018] a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node;

[0019] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the second timing control terminal, and a gate of the eighth transistor is connected to the second node;

[0020] a ninth transistor, wherein a first electrode of the ninth transistor is connected to the fourth node, a second electrode of the ninth transistor is connected to the second node, and a gate of the ninth transistor is connected to the second power supply;

[0021] The shift register unit further includes:

[0022] a first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node;

[0023] a second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode of the second capacitor is connected to the signal output terminal;

[0024] A third capacitor, wherein a first electrode of the third capacitor is connected to the first power supply, and a second electrode of the third capacitor is connected to the third node.

[0025] In some embodiments,

[0026] The reset module further includes:

[0027] A sixth transistor, wherein a first electrode of the sixth transistor is connected to the first node, a second electrode is connected to the second power supply, and a gate is connected to the first timing control terminal.

[0028] In some embodiments,

[0029] The reset module further includes:

[0030] a sixth transistor, wherein a second electrode of the sixth transistor is connected to the second node, and a gate of the sixth transistor is connected to the first node;

[0031] A thirteenth transistor, wherein a first electrode of the thirteenth transistor is connected to the first power supply, a second electrode is connected to the first electrode of the sixth transistor, and a gate is connected to the second timing control end.

[0032] In some embodiments, a timing controller is further included, and the timing controller includes a first timing control signal line, a second timing control signal line, and a third timing control signal line.

[0033] In some embodiments, the first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal; and the third timing control signal line is used to output a third timing control signal.

[0034] In some embodiments, the shift register unit is used to delay the signal received from the signal input end under the control of the first timing control signal, the second timing control signal and the third timing control signal, and the processed signal is output by the signal output end.

[0035] In some embodiments, the shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

[0036] In some embodiments, in the 3N-2 stage shift register unit, the first timing control terminal is connected to the first timing control signal line, the second timing control terminal is connected to the second timing control signal line, and the third timing control terminal is connected to the third timing control signal line, where N is a positive integer.

[0037] In some embodiments, in the 3N-1th level shift register unit, the first timing control terminal is connected to the third timing control signal line, the second timing control terminal is connected to the first timing control signal line, and the third timing control terminal is connected to the second timing control signal line, where N is a positive integer.

[0038] In some embodiments, in the 3N-th level shift register unit, the first timing control terminal is connected to the second timing control signal line, the second timing control terminal is connected to the third timing control signal line, and the third timing control terminal is connected to the first timing control signal line, where N is a positive integer.

[0039] In some embodiments, the first to thirteenth transistors are all P-type MOS transistors.

[0040] Another aspect of the present invention further provides a display panel, characterized by comprising any one of the above-mentioned gate driving circuits.

[0041] The beneficial effects of the present invention compared with the prior art include at least:

[0042] The gate drive circuit and display panel of the present invention improve the output stability of the shift register unit and reduce the number of components of the shift register unit by providing a new 12T3C or 13T3C shift register unit circuit, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0045] FIG1 is a schematic diagram showing a display panel of the present invention;

[0046] FIG2 shows a schematic diagram of a cascade connection of a gate drive circuit according to the present invention;

[0047] FIG3 shows a circuit diagram of a shift register unit according to a first embodiment of the present invention;

[0048] FIG4 shows a waveform diagram of the shift register unit shown in FIG3 when it is working;

[0049] FIG5 is a schematic diagram showing the conduction state of the shift register unit at stage t11 in FIG4 ;

[0050] FIG6 is a schematic diagram showing the conduction state of the shift register unit at stage t12 in FIG4 ;

[0051] FIG7 is a schematic diagram showing the conduction state of the shift register unit at stage t13 in FIG4 ;

[0052] FIG8 is a schematic diagram showing the conduction state of the shift register unit at stage t14 in FIG4 ;

[0053] FIG9 is a schematic diagram showing the conduction state of the shift register unit at stage t15 in FIG4 ;

[0054] FIG10 shows a circuit diagram of a shift register unit according to a second embodiment of the present invention;

[0055] FIG11 shows a waveform diagram of the shift register unit shown in FIG10 when it is working;

[0056] FIG12 is a schematic diagram showing the conduction state of the shift register unit at stage t21 in FIG11 ;

[0057] FIG13 is a schematic diagram showing the conduction state of the shift register unit at stage t22 in FIG11 ;

[0058] FIG14 is a schematic diagram showing the conduction state of the shift register unit at stage t23 in FIG11 ;

[0059] FIG15 is a schematic diagram showing the conduction state of the shift register unit at stage t24 in FIG11 ;

[0060] FIG. 16 is a schematic diagram showing the conduction state of the shift register unit at stage t25 in FIG. 11 .

[0061] Reference Signs: 10 display panel 11 display area 20 timing controller 30 gate driving circuit CKV1 first timing control signal line CKV2 second timing control signal line CKV3 third timing control signal line c1 first timing control terminal c2 second timing control terminal c3 third timing control terminal IN signal input terminal Gout signal output terminal T1 first transistor T2 second transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor T8 eighth transistor T9 ninth transistor T10 tenth transistor T11 eleventh transistor T12 twelfth transistor T13 thirteenth transistor C1 first capacitor C2 second capacitor C3 third capacitor VDD first power supply VEE second power supply N1 first node N2 second node N3 third node N4 fourth node DETAILED DESCRIPTION

[0062] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the figures represent identical or similar structures, and thus a repeated description thereof will be omitted.

[0063] The terms "first," "second," and similar terms used in the specific description do not denote any order, quantity, or importance, but are simply used to distinguish different components. Furthermore, in the description of the present invention, the terms "upper," "lower," and similar terms indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely for ease of description and do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0064] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0065] Through careful and in-depth research, the inventors of this case have provided a solution to the problems existing in the prior art. As shown in Figures 1, 2, 3 and 10, Figure 1 shows a schematic diagram of the display panel of the present invention; Figure 2 shows a schematic diagram of the gate drive circuit of the present invention; Figure 3 shows a circuit diagram of the shift register unit of the first embodiment of the present invention; and Figure 10 shows a circuit diagram of the shift register unit of the second embodiment of the present invention. The embodiment of the present invention discloses a gate drive circuit 30 and a display panel 10, wherein the gate drive circuit 30 includes a multi-stage shift register unit and a timing controller, wherein each stage of the shift register unit includes 12 or 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout and three timing control terminals, and the timing controller 20 includes three timing control signal lines. The gate drive circuit and display panel of the present invention improve the output stability of the shift register unit and reduce the number of components of the shift register unit through a new 12T3C or 13T3C shift register unit circuit, thereby reducing the border width of the display panel.

[0066] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0067] As shown in FIG1 , one aspect of the present invention provides a display panel 10 comprising a display area 11 and a non-display area. A gate driver circuit 30, a data driver, and a light-emission control circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the gate driver circuit 30, the data driver, the light-emission control circuit, and the pixel circuits.

[0068] As shown in FIG. 1 and FIG. 2 , the present invention further provides a gate driving circuit 30 , which includes a multi-stage shift register unit and a timing controller 20 .

[0069] In some embodiments, the shift register unit includes a control module, a reset module, and an output set module. Specifically, it includes 12 or 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2, and a third timing control terminal c3. Each level of the shift register unit outputs a scan signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive the pixels in that row to emit light. The previous level of the shift register unit simultaneously outputs the scan signal to the signal input terminal IN of the next level of the shift register unit as a start signal. Since the last level of the shift register unit does not have a next level, the scan signal output is only input to the pixel circuit in that row.

[0070] Specifically, in FIG2 , five cascaded shift register units are used as an example. The signal input terminal IN1 of the first-stage shift register unit S1 inputs a start pulse signal STV as an input signal. The signal output terminal Gout1 of the first-stage shift register unit S1 outputs a scan signal as an input signal for the second-stage shift register unit S2. The signal output terminal Gout1 of the first-stage shift register unit S1 is connected to the signal input terminal IN2 of the second-stage shift register unit S2. The signal output terminal Gout2 of the second-stage shift register unit S2 outputs a scan signal as an input signal for the third-stage shift register unit S3. The signal output terminal Gout2 of the second-stage shift register unit S2 is connected to the signal input terminal IN3 of the third-stage shift register unit S3. The signal output terminal Gout3 of the third-stage shift register unit S3 outputs a scan signal as an input signal for the fourth-stage shift register unit S4. The signal output terminal Gout3 of the third-stage shift register unit S3 is connected to the signal input terminal IN4 of the fourth-stage shift register unit S4. The signal output terminal Gout4 of the fourth-stage shift register unit S4 outputs the scanning signal as the input signal of the fifth-stage shift register unit S5. The signal output terminal Gout4 of the fourth-stage shift register unit S4 is connected to the signal input terminal IN5 of the fifth-stage shift register unit S5. The subsequent-stage shift register units are repeated in this way to form a gate drive circuit 30.

[0071] In some embodiments, as shown in FIG2 , the timing controller 20 includes a first timing control signal line CKV1, a second timing control signal line CKV2, and a third timing control signal line CKV3. The first timing control signal line CKV1 is used to output a first timing control signal. The second timing control signal line CKV2 is used to output a second timing control signal. The third timing control signal line CKV3 is used to output a third timing control signal. The first, second, and third timing control signals are square wave signals with the same output frequency and a low potential that repeats continuously.

[0072] In some preferred embodiments, with continued reference to FIG2 , further, in the 3N-2 stage shift register unit, the first timing control terminal c1 is connected to the first timing control signal line CKV1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKV2 for receiving the second timing control signal. The third timing control terminal c3 is connected to the third timing control signal line CKV3 for receiving the third timing control signal. Wherein, N is a positive integer. In the 3N-1 stage shift register unit, the first timing control terminal c1 is connected to the third timing control signal line CKV3 for receiving the third timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKV1 for receiving the first timing control signal. The third timing control terminal c3 is connected to the second timing control signal line CKV2 for receiving the second timing control signal. Wherein, N is a positive integer. In the 3N-stage shift register unit, the first timing control terminal c1 is connected to the second timing control signal line CKV2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the third timing control signal line CKV3 for receiving the third timing control signal. The third timing control terminal c3 is connected to the first timing control signal line CKV1 for receiving the first timing control signal. Where N is a positive integer. Each stage of the shift register unit in the gate drive circuit 30 receives the three timing control signals according to the above rule.

[0073] In some embodiments, the shift register unit is used to delay the signal received from the signal input terminal IN under the control of the first timing control signal, the second timing control signal and the third timing control signal. The processed signal is output by the signal output terminal Gout, and the signal is output as a scanning signal to the display area 11 or input to the signal input terminal IN of the next-level shift register unit.

[0074] Figures 1 to 9 show a first embodiment of the present invention, wherein Figure 4 shows a waveform diagram of the shift register unit shown in Figure 3 when it is working; Figure 5 shows a schematic diagram of the conduction state of the shift register unit in stage t11 of Figure 4; Figure 6 shows a schematic diagram of the conduction state of the shift register unit in stage t12 of Figure 4; Figure 7 shows a schematic diagram of the conduction state of the shift register unit in stage t13 of Figure 4; Figure 8 shows a schematic diagram of the conduction state of the shift register unit in stage t14 of Figure 4; and Figure 9 shows a schematic diagram of the conduction state of the shift register unit in stage t15 of Figure 4.

[0075] As shown in Figure 3, the shift register unit of the first embodiment of the present invention includes a control module, a reset module and an output set module. Specifically, it includes 12 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2 and a third timing control terminal c3.

[0076] In this embodiment, as shown in FIG3 , the control module includes: a third transistor T3, a fourth transistor T4, a fifth transistor T5, and an eleventh transistor T11. The third transistor T3 has a first electrode connected to the first power supply VDD, a second electrode connected to the third node N3, and a gate connected to the first timing control terminal c1. The fourth transistor T4 has a first electrode connected to the third node N3, a second electrode connected to the second timing control terminal c2, and a gate connected to the fourth node N4. The fifth transistor T5 has a first electrode connected to the third timing control terminal c3, a second electrode connected to the first node N1, and a gate connected to the third node N3. The eleventh transistor T11 has a first electrode connected to the first power supply VDD, a second electrode connected to the third node N3, and a gate connected to the third timing control terminal c3.

[0077] In this embodiment, as shown in FIG3 , the reset module includes a second transistor T2, a tenth transistor T10, and a twelfth transistor T12. The second transistor T2 has a first electrode connected to the first power supply VDD, a second electrode connected to the fourth node N4, and a gate connected to the first timing control terminal c1. The tenth transistor T10 has a first electrode connected to the first node N1, a second electrode connected to the second power supply VEE, and a gate connected to the third timing control terminal c3. The twelfth transistor T12 has a first electrode connected to the third timing control terminal c3, a second electrode connected to the first node N1, and a gate connected to the fourth node N4. Specifically, the reset module further includes a sixth transistor T6. The sixth transistor T6 has a first electrode connected to the first node N1, a second electrode connected to the second power supply VEE, and a gate connected to the first timing control terminal c1.

[0078] In this embodiment, as shown in FIG3 , the output set module includes: a first transistor T1, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The first transistor T1 has a first electrode connected to the fourth node N4, a second electrode connected to the signal input terminal IN, and a gate connected to the third timing control terminal c3. The seventh transistor T7 has a first electrode connected to the first power supply VDD, a second electrode connected to the signal output terminal Gout, and a gate connected to the first node N1. The eighth transistor T8 has a first electrode connected to the signal output terminal Gout, a second electrode connected to the second timing control terminal c2, and a gate connected to the second node N2. The ninth transistor T9 has a first electrode connected to the fourth node N4, a second electrode connected to the second node N2, and a gate connected to the second power supply VEE.

[0079] In this embodiment, as shown in FIG3 , the shift register unit further includes: a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first electrode of the first capacitor C1 is connected to the first power supply VDD, and the second electrode is connected to the first node N1. The first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the signal output terminal Gout. The first electrode of the third capacitor C3 is connected to the first power supply VDD, and the second electrode is connected to the third node N3. The first power supply VDD provides a positive voltage signal, and the second power supply VEE provides a negative voltage signal.

[0080] In this embodiment, the first transistor M1 to the twelfth transistor M12 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source. The on-level of the PMOS transistor is a low level, and the off-level is a high level. In other embodiments, those skilled in the art will readily appreciate that the shift register unit provided by the present invention can be easily modified to include all N-type MOS transistors. Alternatively, the shift register unit provided by the present invention can also be easily modified to include CMOS transistors, etc.

[0081] In this embodiment, referring to FIG4 , the waveform diagram shown in FIG4 includes five processes: t11, t12, t13, t14, and t15. In these five processes, the output signal of the signal output terminal Gout of the shift register unit completes a process from set to reset. It should be noted that, for ease of understanding, the high-level signal is represented by "H" and the low-level signal is represented by "L" in the accompanying drawings. The relationship between the input and output of the shift register unit in the above five processes is analyzed below in conjunction with the waveform diagram of FIG4 and the circuit diagram of FIG3 :

[0082] In this embodiment, referring to Figures 4 and 5, during process t11, a low level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a high level is input to the second timing control signal line CKV2, and a low level is input to the third timing control signal line CKV3. At this time, the first transistor T1, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off. Specifically, the first transistor T1 and the tenth transistor T10 are turned on by the low potential of the third timing control signal line CKV3. The second node N2 and the first node N1 are respectively written with the low potential of the signal input terminal IN and the second power supply VEE. Simultaneously, the fourth transistor T4 and the twelfth transistor T12 are turned on by the low potential of the second node N2. The first node N1 is written with the low potential of the third timing control signal line CKV3. The third node N3 is written with a high potential due to the turning on of the fourth transistor T4. The fifth transistor T5 is turned off. The first node N1 and the second node N2 are low potentials. As a result, the seventh transistor T7 and the eighth transistor T8 are both turned on. Finally, the signal output terminal Gout outputs the high potential of the first power supply VDD and the second timing control signal line CKV2.

[0083] In this embodiment, referring to Figures 4 and 6, during process t12, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a low level is input to the second timing control signal line CKV2, and a high level is input to the third timing control signal line CKV3. At this time, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 are turned on, while the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 are turned off. Specifically, the first transistor T1 is turned off due to the high level of the third timing control signal line CKV3, the second node N2 maintains the low level at the previous moment, the eighth transistor T8 remains on, the fourth transistor T4 and the twelfth transistor T12 remain on due to the low level of the second node N2, the low level of the second timing control signal line CKV2 is written to the third node N3, the fifth transistor T5 is turned on, the first node N1 is simultaneously written to a high level by the fifth transistor T5 and the twelfth transistor T12, and the seventh transistor T7 is turned off. Finally, the signal output terminal Gout outputs the low potential of the second timing control signal line CKV2.

[0084] In this embodiment, referring to Figures 4 and 7, during process t13, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKV1, a high level is input to the second timing control signal line CKV2, and a high level is input to the third timing control signal line CKV3. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned off. Specifically, the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned on by the low potential of the first timing control signal line CKV1. The second node N2 is written to a high potential due to the turning on of the second transistor T2. The fourth transistor T4, the eighth transistor T8, and the twelfth transistor T12 are turned off. The third node N3 is written to a high potential of the first power supply VDD due to the turning on of the third transistor T3. The fifth transistor T5 is turned off. The first node N1 is written to a low potential of the second power supply VEE due to the turning on of the sixth transistor T6. The seventh transistor T7 is turned on. Ultimately, the signal output terminal Gout outputs a high potential of the first power supply VDD.

[0085] In this embodiment, referring to Figures 4 and 8, during process t14, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a high level is input to the second timing control signal line CKV2, and a low level is input to the third timing control signal line CKV3. At this time, the first transistor T1, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the twelfth transistor T12 are turned off. Specifically, the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned on by the low potential of the third timing control signal line CKV3, the high potential of the signal input terminal IN is written to the second node N2, the fourth transistor T4, the eighth transistor T8, and the twelfth transistor T12 remain turned off, the high potential of the first power supply VDD is written to the third node N3 due to the turning on of the eleventh transistor T11, the fifth transistor T5 remains turned off, the low potential of the second power supply VEE is written to the first node N1 due to the turning on of the tenth transistor T10, and the seventh transistor T7 remains turned on. Ultimately, the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0086] In this embodiment, referring to Figures 4 and 9, during process t15, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a low level is input to the second timing control signal line CKV2, and a high level is input to the third timing control signal line CKV3. At this time, the seventh transistor T7 and the ninth transistor T9 are turned on, while the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned off. Specifically, the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned off due to the high level of the third timing control signal line CKV3. The third node N3 maintains the high level at the previous moment, the fifth transistor T5 is turned off, the second node N2 maintains the high level at the previous moment, the eighth transistor T8 is turned off, the first node N1 maintains the low level at the previous moment, and the seventh transistor T7 remains on. Ultimately, the signal output terminal Gout outputs the high level of the first power supply VDD.

[0087] The shift register unit repeats the process from t13 to t15 after t15, until the next frame begins to be displayed, the start pulse signal STV or the signal input terminal IN inputs a low potential, and re-enters the next round t11 process.

[0088] In this embodiment, the relationship between the input and output of the shift register unit is as follows: if the start pulse signal STV or the signal input terminal IN is at a low level in a certain process, then under the action of the first timing control signal line CKV1, the second timing control signal line CKV2, and the third timing control signal line CKV3, the signal output terminal Gout also outputs a low level in the next process. In other processes, the start pulse signal STV or the signal input terminal IN and the signal output terminal Gout both maintain a high level until the start pulse signal STV or the signal input terminal IN inputs a low level again, at which point the signal output terminal Gout outputs a low level again. This is equivalent to the shift register unit delaying the low level signal from the start pulse signal STV or the signal input terminal IN and outputting it from the signal output terminal Gout.

[0089] In the second embodiment of the present invention, referring to Figures 1 to 2 and Figures 10 to 16, Figure 11 shows a waveform diagram of the shift register unit shown in Figure 10 when it is working; Figure 12 shows a schematic diagram of the conduction state of the shift register unit at the t21 stage in Figure 11; Figure 13 shows a schematic diagram of the conduction state of the shift register unit at the t22 stage in Figure 11; Figure 14 shows a schematic diagram of the conduction state of the shift register unit at the t23 stage in Figure 11; Figure 15 shows a schematic diagram of the conduction state of the shift register unit at the t24 stage in Figure 11; and Figure 16 shows a schematic diagram of the conduction state of the shift register unit at the t25 stage in Figure 11.

[0090] As shown in Figure 3, the shift register unit of the second embodiment of the present invention includes a control module, a reset module and an output set module. Specifically, it includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2 and a third timing control terminal c3.

[0091] In this embodiment, as shown in Figure 3, the settings and connection methods of the transistors and three capacitors of the control module and the output setting module are the same as those of the first embodiment and are not described in detail here. The reset module of this embodiment includes: a second transistor T2, a tenth transistor T10 and a twelfth transistor T12, and their connection methods are also the same as those of the first embodiment and are not described in detail here. In particular, the reset module of this embodiment also includes: a sixth transistor T6 and a thirteenth transistor T13. Among them, the second electrode of the sixth transistor T6 is connected to the second node N2, and the gate is connected to the first node N1. The first electrode of the thirteenth transistor T13 is connected to the first power supply VDD, the second electrode is connected to the first electrode of the sixth transistor T6, and the gate is connected to the second timing control terminal c2.

[0092] In this embodiment, the first transistor M1 to the thirteenth transistor M13 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source. The on-level of the PMOS transistor is a low level, and the off-level is a high level. In other embodiments, those skilled in the art will readily appreciate that the shift register unit provided by the present invention can be easily modified to include all N-type MOS transistors. Alternatively, the shift register unit provided by the present invention can also be easily modified to include CMOS transistors, etc.

[0093] In this embodiment, referring to FIG11, the waveform diagram shown in FIG11 includes five processes: t21, t22, t23, t24, and t25. In these five processes, the output signal of the signal output terminal Gout of the shift register unit completes a process from set to reset. It should be noted that, for ease of understanding, the high-level signal is represented by "H" and the low-level signal is represented by "L". The relationship between the input and output of the shift register unit in the above five processes is analyzed below in conjunction with the waveform diagram of FIG11 and the circuit diagram of FIG10:

[0094] In this embodiment, referring to Figures 11 and 12, during process t21, a low level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a high level is input to the second timing control signal line CKV2, and a low level is input to the third timing control signal line CKV3. At this time, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, and the thirteenth transistor T13 are turned off. Specifically, the first transistor T1 and the tenth transistor T10 are turned on by the low potential of the third timing control signal line CKV3. The second node N2 and the first node N1 are respectively written with the low potential of the signal input terminal IN and the second power supply VEE. Simultaneously, the fourth transistor T4 and the twelfth transistor T12 are turned on by the low potential of the second node N2. The first node N1 is written with the low potential of the third timing control signal line CKV3. The third node N3 is written with a high potential due to the turning on of the fourth transistor T4. The fifth transistor T5 is turned off. The first node N1 and the second node N2 are low potentials. As a result, the seventh transistor T7 and the eighth transistor T8 are both turned on. Finally, the signal output terminal Gout outputs the high potential of the first power supply VDD and the second timing control signal line CKV2.

[0095] In this embodiment, referring to Figures 11 and 13, during process t22, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a low level is input to the second timing control signal line CKV2, and a high level is input to the third timing control signal line CKV3. At this time, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 are turned off. Specifically, the first transistor T1 is turned off by the high level of the third timing control signal line CKV3, the second node N2 maintains the low potential at the previous moment, the eighth transistor T8 remains on, the fourth transistor T4 and the twelfth transistor T12 remain on by the low potential of the second node N2, the third node N3 is written with the low potential of the second timing control signal line CKV2 due to the turning on of the fourth transistor T4, the fifth transistor T5 is turned on, and the first node N1 is simultaneously written with the high potential of the third timing control signal line CKV3 by the fifth transistor T5 and the twelfth transistor T12, and the seventh transistor T7 is turned off. Ultimately, the signal output terminal Gout outputs the low potential of the second timing control signal line CKV2.

[0096] In this embodiment, referring to Figures 11 and 14, during process t23, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKV1, a high level is input to the second timing control signal line CKV2, and a high level is input to the third timing control signal line CKV3. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off. Specifically, the second transistor T2 and the third transistor T3 are turned on by the low potential of the first timing control signal line CKV1. The second node N2 is written with the high potential of the first power supply VDD due to the turning on of the second transistor T2. The fourth transistor T4, the eighth transistor T8, and the twelfth transistor T12 are turned off. The third node N3 is written with the high potential of the first power supply VDD due to the turning on of the third transistor T3. The fifth transistor T5 is turned off. The first node N1 maintains the low potential at the previous moment. The seventh transistor T7 is turned on. Ultimately, the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0097] In this embodiment, referring to Figures 11 and 15, during process t24, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a high level is input to the second timing control signal line CKV2, and a low level is input to the third timing control signal line CKV3. At this time, the first transistor T1, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are turned off. Specifically, the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned on by the low potential of the third timing control signal line CKV3, the high potential of the signal input terminal IN is written to the second node N2, the fourth transistor T4, the eighth transistor T8, and the twelfth transistor T12 remain turned off, the high potential of the first power supply VDD is written to the third node N3 due to the turning on of the eleventh transistor T11, the fifth transistor T5 remains turned off, the low potential of the second power supply VEE is written to the first node N1 due to the turning on of the tenth transistor T10, and the seventh transistor T7 remains turned on. Ultimately, the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0098] In this embodiment, referring to Figures 11 and 16, during process t25, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKV1, a low level is input to the second timing control signal line CKV2, and a high level is input to the third timing control signal line CKV3. At this time, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the thirteenth transistor T13 are turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned off. Specifically, the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned off due to the high potential of the third timing control signal line CKV3. The third node N3 maintains the high potential at the previous moment. The fifth transistor T5 is turned off, while the first node N1 maintains the low potential at the previous moment. The second node N2 is written with the high potential of the first power supply VDD due to the low potential of the second timing control signal line CKV2 and the first node N1, which causes the sixth transistor T6 and the thirteenth transistor T13 to turn on. The eighth transistor T8 is turned off, and the seventh transistor T7 is turned on due to the low potential of the first node N1. Ultimately, the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0099] The shift register unit repeats the process from t23 to t25 after t25 until the next frame begins to be displayed, and the start pulse signal STV or the signal input terminal IN inputs a low potential, and re-enters the next round t21 process.

[0100] In this embodiment, the relationship between the input and output of the shift register unit is as follows: if the start pulse signal STV or the signal input terminal IN is at a low level in a certain process, then under the action of the first timing control signal line CKV1, the second timing control signal line CKV2, and the third timing control signal line CKV3, the signal output terminal Gout also outputs a low level in the next process. In other processes, the start pulse signal STV or the signal input terminal IN and the signal output terminal Gout both maintain a high level until the start pulse signal STV or the signal input terminal IN inputs a low level again, at which point the signal output terminal Gout outputs a low level again. This is equivalent to the shift register unit delaying the low level signal from the start pulse signal STV or the signal input terminal IN and outputting it from the signal output terminal Gout.

[0101] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel 10 described above. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The implementation of the display device can be referenced to the embodiments of the display panel 10 described above, and any repetitive details will not be repeated here.

[0102] In summary, the gate drive circuit and display panel of the present invention improve the output stability of the shift register unit and reduce the number of components of the shift register unit by providing a new 12T3C or 13T3C shift register unit circuit, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0103] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A gate drive circuit, characterized in that: It comprises a multi-stage shift register unit, wherein the shift register unit comprises a control module, a reset module and an output setting module; The control module comprises: a third transistor, wherein a first electrode of the third transistor is connected to the first power supply, a second electrode of the third transistor is connected to the third node, and a gate of the third transistor is connected to the first timing control terminal; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode of the fourth transistor is connected to the second timing control terminal, and a gate of the fourth transistor is connected to the fourth node; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the third timing control terminal, a second electrode of the fifth transistor is connected to the first node, and a gate of the fifth transistor is connected to the third node; an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the first power supply, a second electrode of the eleventh transistor is connected to the third node, and a gate of the eleventh transistor is connected to the third timing control terminal; The reset module comprises: a second transistor, wherein a first electrode of the second transistor is connected to the first power supply, a second electrode of the second transistor is connected to the fourth node, and a gate of the second transistor is connected to the first timing control terminal; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first node, a second electrode of the tenth transistor is connected to the second power supply, and a gate of the tenth transistor is connected to the third timing control terminal; a twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the third timing control terminal, a second electrode of the twelfth transistor is connected to the first node, and a gate of the twelfth transistor is connected to the fourth node; The output setting module comprises: A first transistor, wherein a first electrode of the first transistor is connected to the fourth node, a second electrode of the first transistor is connected to the signal input terminal, and a gate of the first transistor is connected to the third timing control terminal; a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node; an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the second timing control terminal, and a gate of the eighth transistor is connected to the second node; a ninth transistor, wherein a first electrode of the ninth transistor is connected to the fourth node, a second electrode of the ninth transistor is connected to the second node, and a gate of the ninth transistor is connected to the second power supply; The shift register unit also includes: A first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node; a second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode of the second capacitor is connected to the signal output terminal; A third capacitor, wherein a first electrode of the third capacitor is connected to the first power supply, and a second electrode of the third capacitor is connected to the third node.

2. The gate driving circuit according to claim 1, characterized in that: The reset module also includes: A sixth transistor, wherein a first electrode of the sixth transistor is connected to the first node, a second electrode of the sixth transistor is connected to the second power supply, and a gate of the sixth transistor is connected to the first timing control terminal.

3. The gate driving circuit according to claim 1, characterized in that: The reset module also includes: a sixth transistor, wherein a second electrode of the sixth transistor is connected to the second node, and a gate of the sixth transistor is connected to the first node; A thirteenth transistor, wherein a first electrode of the thirteenth transistor is connected to the first power supply, a second electrode of the thirteenth transistor is connected to the first electrode of the sixth transistor, and a gate electrode is connected to the second timing control terminal.

4. The gate drive circuit according to claim 2 or 3, characterized in that: The system also includes a timing controller, which includes a first timing control signal line, a second timing control signal line and a third timing control signal line.

5. The gate driving circuit according to claim 4, characterized in that: The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal; and the third timing control signal line is used to output a third timing control signal.

6. The gate driving circuit according to claim 5, characterized in that: The shift register unit is used to perform delay processing on the signal received from the signal input end under the control of the first timing control signal, the second timing control signal and the third timing control signal, and the processed signal is output from the signal output end.

7. The gate drive circuit according to claim 2 or 3, characterized in that: The shift register unit of the previous stage outputs a scan signal to the shift register unit of the next stage, and the shift register unit of the last stage outputs a scan signal.

8. The gate driving circuit according to claim 4, characterized in that: In the 3N-2th level shift register unit, the first timing control terminal is connected to the first timing control signal line, the second timing control terminal is connected to the second timing control signal line, and the third timing control terminal is connected to the third timing control signal line, wherein N is a positive integer.

9. The gate driving circuit according to claim 8, characterized in that: In the 3N-1th level shift register unit, the first timing control terminal is connected to the third timing control signal line, the second timing control terminal is connected to the first timing control signal line, and the third timing control terminal is connected to the second timing control signal line, wherein N is a positive integer.

10. The gate driving circuit according to claim 9, characterized in that: In the 3Nth-level shift register unit, the first timing control terminal is connected to the second timing control signal line, the second timing control terminal is connected to the third timing control signal line, and the third timing control terminal is connected to the first timing control signal line, wherein N is a positive integer.

11. The gate driving circuit according to claim 2 or 3, characterized in that: The first transistor to the thirteenth transistor are all P-type MOS transistors.

12. A display panel, characterized in that: The invention comprises a gate driving circuit according to any one of claims 1 to 11.

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