Memory and data operation method therefor, and electronic device

Abstract

Provided in the present disclosure are a memory and a data operation method therefor, and an electronic device. Each memory cell of the memory comprises write transistors and read transistors, wherein first source / drain electrodes of the write transistors are connected to gate electrodes of the read transistors, each first bit line is connected to second source / drain electrodes of a row of write transistors, and each second bit line is connected to first source / drain electrodes of a row of read transistors; and gate electrodes of an anterior column of write transistors and second source / drain electrodes of a posterior column of read transistors share the same word line.

Description

Memory and data operation method thereof, and electronic device

[0001] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on August 2, 2023, with application number 202310976027.3 and application name “Memory and data operation method thereof, electronic device”, the entire contents of which are incorporated by reference in this disclosure. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a memory, a data operation method thereof, and an electronic device. Background Art

[0003] With the development of semiconductor technology, memory, especially dynamic random access memory (DRAM), has been widely used in various electronic devices due to its high storage density and fast read and write speeds. DRAM consists of multiple memory cells, each of which typically includes a transistor and a capacitor, forming a 1T1C (1 transistor 1 capacitor) structure.

[0004] In the aforementioned memory cell with a 1T1C structure, the manufacturing process for the capacitor occupies a large area, which is not conducive to size reduction. To this end, the memory cell can also adopt a 2T0C (2 Transistor 0 Capacitor) structure, that is, the memory cell includes two transistors, where the first source and drain of one transistor are connected to the gate of the other transistor, thereby eliminating the capacitor. However, in a memory cell with a 2T0C structure, the other electrodes of the two transistors require leads (word lines or bit lines) to connect, making the dynamic random access memory structure complex and inconvenient for the arrangement (array) of the memory cells.

[0005] Summary of the Invention

[0006] In view of the above problems, embodiments of the present disclosure provide a memory and a data operation method thereof, and an electronic device to simplify the structure of the memory.

[0007] According to some embodiments, the present disclosure provides a first aspect of a memory, comprising:

[0008] A plurality of memory cells arranged in an array, each memory cell comprising a write transistor and a read transistor, wherein a first source and a drain of the write transistor are connected to a gate of the read transistor;

[0009] a plurality of first bit lines, each of the first bit lines correspondingly connected to the second source and drain of the write transistor of a row of the memory cells;

[0010] a plurality of second bit lines, each of the second bit lines correspondingly connected to the first source and drain of the read transistor of a row of the memory cells;

[0011] A plurality of word lines are provided, each word line being electrically coupled to a plurality of the memory cells arranged in columns, wherein in two adjacent columns of the memory cells, the gate of the write transistor in the previous column and the second source and drain of the read transistor in the next column are coupled to the same word line.

[0012] The memory in the disclosed embodiment includes a plurality of memory cells arranged in an array, a plurality of first bit lines, a plurality of second bit lines, and a plurality of word lines, each word line being electrically coupled to a plurality of memory cells arranged in columns. Specifically, in two adjacent columns of memory cells, the gate of the write transistor in the preceding column and the second source and drain of the read transistor in the following column are coupled to the same word line, so that the word line serves as both a write word line for the connected write transistors and a read word line for the connected read transistors. By having two adjacent columns of memory cells share a single word line, the number of word lines is reduced, the memory architecture is simplified, and the complexity of the memory cell array manufacturing process is reduced.

[0013] According to some embodiments, the second aspect of the present disclosure provides an electronic device, including the memory as described above, which at least has the advantages of simplified memory architecture and simple manufacturing process. The specific effects are referred to above and will not be repeated here.

[0014] According to some embodiments, a third aspect of the present disclosure provides a memory data operation method, which is applied to the memory as described above, and the data operation method includes:

[0015] A data writing operation or a data reading operation is performed on a column of the memory cells.

[0016] In some possible examples, performing the data writing operation on a column of the storage cells includes:

[0017] Applying a first voltage to a word line coupled to the gates of the write transistors in the memory cells in the column, and applying data signals to the first bit lines respectively, so as to turn on the write transistors in the memory cells in the column and write the data signals into the gates of the read transistors in the memory cells in the column; and

[0018] A first reference voltage is applied to the word lines other than the word lines to which the gates of the write transistors in the memory cells in the column are coupled, and complementary signals of the data signals are respectively applied to multiple second bit lines to cut off the write transistors in the memory cells in the columns other than the memory cells in the column and to cut off the read transistors in the memory cells in each column.

[0019] In summary, the data operation method in the embodiment of the present disclosure is applied to the above-mentioned memory to implement data writing operation or data reading operation on a column of storage cells in the above-mentioned memory, thereby simplifying the memory architecture and reducing complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a schematic diagram of a storage unit in the related art;

[0021] FIG2 is a schematic diagram of a memory in an embodiment of the present disclosure;

[0022] FIG3 is a schematic diagram of a data writing operation of a memory in an embodiment of the present disclosure;

[0023] FIG4 is a specific process diagram of a data writing operation of a memory in an embodiment of the present disclosure;

[0024] FIG5 is a schematic diagram of a data reading operation of a memory in an embodiment of the present disclosure;

[0025] FIG6 is a detailed process diagram of a data reading operation of a memory in an embodiment of the present disclosure.

[0026] Explanation of reference numerals: 10 - memory; 11 - memory cell; 12 - write transistor; 13 - read transistor; 14 - word line; 15 - first bit line; 16 - second bit line; 17 - sense amplifier. DETAILED DESCRIPTION

[0027] The related art has a problem of complex memory structure. The inventors have discovered that the reason is as follows: Referring to Figure 1, the memory cell 11 includes a read transistor 13 and a write transistor 12. Among them, the first source and drain of the write transistor 12 are connected to the gate of the read transistor 13, the first source and drain of the write transistor 12 are connected to the write bit line (WBL), and the gate of the write transistor 12 is connected to the write word line (WWL). The first source and drain of the read transistor 13 are connected to the read bit line (RBL), and the second source and drain of the read transistor 13 are connected to the read word line (RWL). Each memory cell 11 requires four leads (write bit line, write word line, read bit line, and read word line), and the memory structure is complex.

[0028] An embodiment of the present disclosure provides a memory in which two adjacent columns of memory cells share a word line, wherein the gate of the write transistor in the previous column and the second source and drain of the read transistor in the next column are coupled to the same word line, so that the word line serves as both a write word line for the connected write transistors and a read word line for the connected read transistors, thereby reducing the number of word lines, simplifying the memory architecture, and reducing the complexity of the memory cell array manufacturing process.

[0029] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0030] 2 , an embodiment of the present disclosure provides a memory 10 comprising a plurality of memory cells 11 arranged in an array. Exemplarily, the plurality of memory cells 11 are spaced apart and arranged in multiple rows and columns, with the rows being horizontal as shown in FIG2 , and the columns being vertical as shown in FIG1 .

[0031] As shown in Figure 2, each memory cell 11 includes a write transistor 12 and a read transistor 13. The first source and drain of write transistor 12 are connected to the gate of read transistor 13. The gate of read transistor 13 serves as a storage node to store data, such as data "1" or data "0." Memory cell 11 is a 2T0C memory cell 11, which reduces the size of memory cell 11 and improves storage density.

[0032] The memory 10 further includes a plurality of first bit lines 15 and a plurality of second bit lines 16. The plurality of first bit lines 15 are spaced apart, and each first bit line 15 is connected to the second source and drain of the write transistor 12 of a row of memory cells 11. The plurality of second bit lines 16 are spaced apart, and each second bit line 16 is connected to the first source and drain of the read transistor 13 of a row of memory cells 11. Data is written to the storage node via the write transistor 12, and data is read from the storage node via the read transistor 13.

[0033] The plurality of first bit lines 15 and the plurality of second bit lines 16 extend along the row direction (horizontal direction as shown in FIG2 ) of the array formed by the plurality of memory cells 11. The first bit lines 15 and the second bit lines 16 are respectively located on either side of a row of memory cells 11 and are connected to a corresponding row of memory cells 11. The first bit lines 15 serve as write bit lines for the connected write transistors 12, and the second bit lines 16 serve as read bit lines for the connected read transistors 13.

[0034] The memory 10 also includes a plurality of word lines 14, each word line 14 being electrically coupled to a plurality of memory cells 11 arranged in columns. In two adjacent columns of memory cells 11, the gate of the write transistor 12 in the preceding column and the second source and drain of the read transistor 13 in the succeeding column are coupled to the same word line 14. The front-to-back direction is the left-to-right direction as shown in FIG2 , where the preceding column is the left column and the succeeding column is the right column.

[0035] The conduction or cutoff of the write transistor 12 and the read transistor 13 is controlled by the word line 14, and two adjacent memory cells 11 share one word line 14, that is, one word line 14 is used as both a write word line for the connected write transistor 12 and a read word line for the connected read transistor 13, thereby reducing the number of word lines 14, simplifying the architecture of the memory 10, and reducing the complexity of the memory cell 11 array manufacturing process.

[0036] By controlling the voltages of each word line 14, each first bit line 15, and each second bit line 16, it is possible to control the conduction or cutoff of each write transistor 12, and the conduction or cutoff of each read transistor 13, thereby writing data to or reading data from the storage node. Each word line 14 can be used to write data to or read data from a column of data cells, writing data from each first bit line 15 to the corresponding storage node, or reading data from the storage node to the corresponding second bit line 16.

[0037] The gate of each read transistor 13 in the memory cell 11 is a storage node, and the read transistor 13 and the write transistor 12 are of the same type, for example, both the read transistor 13 and the write transistor 12 are N-type transistors, or both the read transistor 13 and the write transistor 12 are P-type transistors. When both the read transistor 13 and the write transistor 12 are N-type transistors, the voltages on each word line 14, each first bit line 15, and each second bit line 16 are adapted to the N-type transistors to turn on or off each read transistor 13 and the write transistor 12. When both the read transistor 13 and the write transistor 12 are P-type transistors, the voltages on each word line 14, each first bit line 15, and each second bit line 16 are adapted to the P-type transistors to turn on or off each read transistor 13 and the write transistor 12.

[0038] In some examples, the plurality of word lines 14 include a plurality of first word lines and two second word lines, where each first word line is connected to the gate of the write transistor 12 of the memory cell 11 in the first column and the second source and drain of the read transistor 13 of the memory cell 11 in the second column in two adjacent columns of memory cells 11. The two second word lines are connected to the second source and drain of the read transistor 13 of the memory cell 11 in the first column and the gate of the write transistor 12 of the memory cell 11 in the second column in the two outermost columns of memory cells 11.

[0039] The word line 14 between two adjacent columns of memory cells 11 is a first word line, meaning that two adjacent columns of memory cells 11 can share a single word line 14. The read transistors 13 or write transistors 12 in the two outermost columns of memory cells 11 require a separate connection to a word line 14, which is a second word line. As shown in Figure 2 , the read transistor 13 in the leftmost column of memory cells 11 and the write transistor 12 in the rightmost column of memory cells 11 are each connected to a second word line.

[0040] The second word line connected to the read transistor 13 of the front-column memory cell 11 is used as the read word line of the connected read transistor 13 , and the second word line connected to the write transistor 12 of the rear-column memory cell 11 is used as the write word line of the connected write transistor 12 .

[0041] In some examples, the memory 10 further includes a plurality of sense amplifiers 17 (SA), each of which is connected between a first bit line 15 and a second bit line 16 corresponding to a row of memory cells 11. The sense amplifier 17 is configured to sense and amplify a voltage difference between the corresponding first bit line 15 and the second bit line 16 during a data read operation, so as to facilitate reading data stored in the memory cell 11 from the second bit line 16.

[0042] A sense amplifier 17 is connected between the corresponding first and second bit lines 15, 16, and is used to sense and amplify the voltage difference between the first and second bit lines 15, 16. During a data read operation, the voltages on the corresponding first and second bit lines 15, 16 differ, and the sense amplifier 17 senses and amplifies the voltage difference. For example, when the voltage on the second bit line 16 is lower than the voltage on the first bit line 15, the voltage on the second bit line 16 is lowered and / or the voltage on the first bit line 15 is raised, making the voltage on the second bit line 16 even lower than the voltage on the first bit line 15. When the voltage on the second bit line 16 is higher than the voltage on the first bit line 15, the voltage on the second bit line 16 is higher than the voltage on the first bit line 15 by raising the voltage on the second bit line 16 and / or lowering the voltage on the first bit line 15. This facilitates reading data stored in the memory cell 11 from the second bit line 16.

[0043] In summary, the memory 10 in the disclosed embodiment includes a plurality of memory cells 11 arranged in an array, a plurality of first bit lines 15, a plurality of second bit lines 16, and a plurality of word lines 14. Each word line 14 is electrically coupled to a plurality of memory cells 11 arranged in columns. In two adjacent columns of memory cells 11, the gate of the write transistor 12 in the preceding column and the second source and drain of the read transistor 13 in the succeeding column are coupled to the same word line 14, so that the word line 14 serves as both a write word line for the connected write transistor 12 and a read word line for the connected read transistor 13. By sharing a single word line 14 between two adjacent columns of memory cells 11, the number of word lines 14 is reduced, the architecture of the memory 10 is simplified, and the complexity of the memory cell 11 array fabrication process is reduced.

[0044] It should be noted that in this disclosure, the concepts of "row" and "column" are relative, that is, "row" and "column" are interchangeable. In addition, in this disclosure, the positive and negative signs are considered when comparing the magnitudes of voltages.

[0045] The embodiment of the present disclosure also provides an electronic device, which can be a computer or a server, etc., which includes the above-mentioned memory 10 (see Figure 2), and thus has at least the advantages of simplified memory 10 architecture and simple manufacturing process. The specific effects are referred to above and will not be repeated here.

[0046] The electronic device may further include at least one processor to execute computer-executable instructions stored in the memory 10. The processor may be a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic devices.

[0047] For example, the electronic device includes but is not limited to a server, a printer, a scanner, a tablet computer, a smart phone, a driving recorder, a navigation device, a wearable device, etc.

[0048] The embodiment of the present disclosure also provides a data operation method for a memory, referring to Figures 3 to 6, which is applied to the above-mentioned memory 10. The data operation method includes: performing a data write operation or a data read operation on a column of memory cells 11 to store data in the gate of the read transistor 13 of the column of memory cells 11, or reading out the data stored in the gate of the read transistor 13 of the column of memory cells 11.

[0049] In some examples, referring to Figure 3, a data write operation is performed on a column of memory cells 11, including: applying a first voltage to a word line 14 coupled to the gate of a write transistor 12 in the column of memory cells 11, and applying data signals to multiple first bit lines 15 respectively to turn on the write transistor 12 in the column of memory cells 11, and write the data signal into the gate of the read transistor 13 in the column of memory cells 11.

[0050] Among them, the first voltage can be recorded as V wlw , the first voltage can turn on all write transistors 12 in the column of storage cells 11. The data signal can be a first high-level signal or a first low-level signal, that is, it can be one of the first high-level signal and the first low-level signal. The voltages of the first high-level signal and the first low-level signal are respectively denoted as V H1 and V L1 For example, when the data signal is a first high-level signal, data “1” is stored in the storage node through the conductive write transistor 12, and when the data signal is a first low-level signal, data “0” is stored in the storage node through the conductive write transistor 12; or, when the data signal is a first high-level signal, data “0” is stored in the storage node through the conductive write transistor 12, and when the data signal is a first low-level signal, data “1” is stored in the storage node through the conductive write transistor 12.

[0051] Performing a data writing operation on a column of memory cells 11 also includes: applying a first reference voltage to other word lines 14 except the word line 14 coupled to the gate of the write transistor 12 in the column of memory cells 11, and applying complementary signals of the data signal to multiple second bit lines 16 to turn off the write transistors 12 in other columns of memory cells 11 except the column of memory cells 11 and turn off the read transistors 13 in each column of memory cells 11.

[0052] Among them, the first reference voltage can be recorded as V ref1 , the first reference voltage turns off the write transistors 12 in the other columns of memory cells 11. The complementary signal is complementary to the data signal, and the complementary signal and the data signal are respectively a first high-level signal and a first low-level signal, that is, the data signal is one of the first high-level signal and the first low-level signal, and the complementary signal is the other of the first high-level signal and the first low-level signal.

[0053] In some possible implementations, the read transistor 13 and the write transistor 12 are both N-type transistors, and the difference between the first voltage and the voltage of the data signal (including the first high-level signal and the first low-level signal) is greater than the threshold voltage of the write transistor 12, thereby turning on the write transistor 12 coupled to the word line 14 to which the first voltage is applied. The difference between the first reference voltage and the voltage of the data signal (including the first high-level signal and the first low-level signal) is less than the threshold voltage of the write transistor 12, thereby turning off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied.

[0054] The threshold voltage of the write transistor 12 is V tw , the threshold voltage of the read transistor 13 is recorded as V tr The difference refers to the value of the former minus the latter. The difference between the first voltage and the voltage of the data signal is equal to the first voltage minus the voltage of the data signal. The difference in the following text refers to the meaning here.

[0055] When both the read transistor 13 and the write transistor 12 are N-type transistors, the threshold voltage of the write transistor 12 and the threshold voltage of the read transistor 13 are both greater than zero. The difference between the first voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor 12, turning on the write transistor 12 coupled to the word line 14 to which the first voltage is applied, thereby writing the data on the first bit line 15 to the storage node. The difference between the first reference voltage and the voltage of the data signal is less than the threshold voltage of the write transistor 12, turning off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied, i.e., no data write operation is performed on the other columns of memory cells 11.

[0056] The data signal is one of a first high level signal or a first low level signal, and the voltage of the first high level signal is greater than the voltage of the first low level signal. When the difference between the first voltage and the voltage of the first high level signal is greater than the threshold voltage of the write transistor 12, that is, V wlw -V H1 >V tw When the difference between the first reference voltage and the voltage of the first low level signal is less than the threshold voltage of the write transistor 12, that is, V ref1 -V L1 <V tw When , the column write transistors 12 coupled to the word line 14 applying the first reference voltage are all turned off.

[0057] When data is written to a column of memory cells 11, all read transistors 13 are turned off. That is, when the write transistor 12 coupled to the word line 14 applied with the first voltage is turned on and the write transistor 12 coupled to the word line 14 applied with the first reference voltage is turned off, all read transistors 13 are turned off. For example, the difference between the voltage of the first high-level signal and the first low-level signal is less than the threshold voltage of the read transistor 13, and the difference between the voltage of the first high-level signal and the first reference voltage is less than the threshold voltage of the read transistor 13, so that all read transistors 13 are turned off. That is, V H1 -V L1 <V tr , V H1 -V ref1 <V tr , ensuring that each read transistor 13 is turned off. The first reference voltage may be between the voltage of the first high level signal and the voltage of the first low level signal, that is, the first reference voltage is less than the voltage of the first high level signal and greater than the voltage of the first low level signal.

[0058] For example, referring to FIG4 , the threshold voltage of the write transistor 12 is X (X>0), the voltage of the read transistor 13 is 1.5X, the first voltage is 2.5X, the first reference voltage is 0.5X, the voltage of the first high-level signal is X, and the voltage of the first low-level signal is 0, that is, V tw =X,V tr =1.5X, V wlw =2.5X, V ref1 =0.5X, V H1 =X,V L1 = 0. At this time, the first high level signal or the first low level signal on the first bit line 15 is written into the corresponding memory cell 11 in a column of memory cells 11 coupled to the word line 14 to which the first voltage is applied. It should be noted that the embodiments of the present disclosure include but are not limited to this.

[0059] In some possible implementations, both the read transistor 13 and the write transistor 12 are P-type transistors. The difference between the first voltage and the voltage of the data signal is less than the threshold voltage of the write transistor 12, thereby turning on the write transistor 12 coupled to the word line 14 to which the first voltage is applied. The difference between the first reference voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor 12, thereby turning off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied.

[0060] Furthermore, the data signal is one of the first high-level signal and the first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltages of the first low-level signal and the first high-level signal is greater than the threshold voltage of the read transistor 13, and the difference between the voltage of the first low-level signal and the first reference voltage is greater than the threshold voltage of the read transistor 13, so as to cut off each read transistor 13.

[0061] When both the read transistor 13 and the write transistor 12 are P-type transistors, the threshold voltage of the write transistor 12 and the threshold voltage of the read transistor 13 are both less than zero. The difference between the first voltage and the voltage of the data signal is less than the threshold voltage of the write transistor 12, thereby turning on the write transistor 12 coupled to the word line 14 to which the first voltage is applied, thereby writing the data on the first bit line 15 to the storage node. The difference between the first reference voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor 12, thereby turning off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied, i.e., no data write operation is performed on the other columns of memory cells 11.

[0062] When the difference between the first voltage and the voltage of the first high level signal is less than the threshold voltage of the write transistor 12, that is, V wlw –V H1 <V tw , the column of write transistors 12 coupled to the word line 14 applying the first voltage are all turned on. When the difference between the first reference voltage and the voltage of the first high level signal is greater than the threshold voltage of the write transistor 12, that is, V ref1 -V H1 >V tw , the column write transistors 12 coupled to the word line 14 applying the first reference voltage are all turned off.

[0063] When data is written to a column of memory cells 11, all read transistors 13 are turned off. The difference between the voltage of the first low-level signal and the first high-level signal is greater than the threshold voltage of the read transistor 13, and the difference between the voltage of the first low-level signal and the first reference voltage is greater than the threshold voltage of the read transistor 13, so that all read transistors 13 are turned off. That is, V L1 -V H1 >V tr , V L1 -V ref1 >V tr , ensuring that each read transistor 13 is turned off. The first reference voltage can be between the voltage of the first high level signal and the voltage of the first low level signal. Therefore, when V L1 -V H1 <V tr When V L1 -V ref1 <V tr .

[0064] In some possible exemplary embodiments, referring to Figure 5, a data reading operation is performed on a column of memory cells 11, including: precharging multiple second bit lines 16 to a second reference voltage; applying a second voltage to the word line 14 coupled to the first source and drain of the read transistor 13 in the column of memory cells 11, and turning on or off the read transistor 13 in the column of memory cells 11 according to the storage signal of the gate of the read transistor 13 in the column of memory cells 11, so as to read the storage signal of the read transistor 13 in the column of memory cells 11 to the connected second bit line 16.

[0065] Among them, the second reference voltage can be recorded as V ref2 , the second voltage can be recorded as V wlr The second voltage turns on all the read transistors 13 in the column of memory cells 11. The storage signal at the gate of the read transistor 13 includes a second high-level signal and a second low-level signal, which are respectively denoted as V H2 and V L2 When the storage signal at the gate of the read transistor 13 is the second high-level signal, the gate of the read transistor 13 stores data “1”; when the storage signal at the gate of the read transistor 13 is the second low-level signal, the gate of the read transistor 13 stores data “0”; or, when the storage signal at the gate of the read transistor 13 is the second high-level signal, the gate of the read transistor 13 stores data “0”; when the storage signal at the gate of the read transistor 13 is the second low-level signal, the gate of the read transistor 13 stores data “1”.

[0066] Read transistor 13 is turned on or off based on the comparison of the voltage of the stored signal at the gate of read transistor 13 with the second reference voltage. For example, if read transistor 13 is an N-type transistor, when the stored signal at the gate of read transistor 13 is a second high-level signal, read transistor 13 is turned on to read the second high-level signal. When the stored signal at the gate of read transistor 13 is a second low-level signal, read transistor 13 is turned off, and the voltage on second bit line 16 remains unchanged to read the second low-level signal.

[0067] Performing a data reading operation on a column of memory cells 11 also includes: applying a third reference voltage to other word lines 14 except the word line 14 coupled to the gate of the read transistor 13 in the column of memory cells 11, and applying a fourth reference voltage to each of the plurality of first bit lines 15 to turn off the read transistors 13 in the other columns of memory cells 11 except the column of memory cells 11 and to turn off the write transistors 12 in each column of memory cells 11.

[0068] The third reference voltage can be recorded as V ref3 , the fourth reference voltage can be recorded as V ref4, the other column read transistors 13 are turned off, and all write transistors 12 are turned off. In some possible implementations, the read transistors 13 and the write transistors 12 are both N-type transistors. The storage signal includes a second high-level signal and a second low-level signal, and the difference between the voltage of the second high-level signal and the second reference voltage is less than the threshold voltage of each read transistor 13, that is, V H2 -V ref2 <V tr , to turn off each read transistor 13 after pre-charging.

[0069] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the read transistor 13, that is, V H2 -V wlr >V tr , the read transistor 13 whose storage signal is the second high level signal is turned on. The voltage of the second bit line 16 connected to the turned-on read transistor 13 changes from the second reference voltage to the second voltage.

[0070] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second low level signal, the difference between the voltage of the second low level signal and the second voltage is less than the threshold voltage of the read transistor, that is, V L2 -V wlr <V tr The read transistor 13 whose storage signal is the second low level signal is turned off, and the voltage of the second bit line 16 connected to the turned-off read transistor 13 maintains the second reference voltage.

[0071] The difference between the voltage of the second high level signal and the third reference voltage is less than the threshold voltage of the read transistor 13, that is, V H2 -V ref3 <V tr When V H2 -V ref3 <V tr When V L2 -V ref3 <V H2 -V ref3 <V tr , no matter the storage signals of other column read transistors 13 are the second high level signals or the second low level signals, they remain cut off.

[0072] The difference between the third reference voltage and the voltage of the second low level signal is less than the threshold voltage of the write transistor 12, and the difference between the third reference voltage and the fourth reference voltage is less than the threshold voltage of the write transistor 12, that is, V ref3 -V L2 <V tw , and V ref3 -Vref4 <V tw , to turn off each write transistor 12.

[0073] For example, referring to FIG6 , the threshold voltage of the write transistor 12 is X (X>0), the voltage of the read transistor 13 is 1.5X, the voltage of the first high-level signal is X, the voltage of the first low-level signal is 0, the second voltage can be -X, the second reference voltage can be X, and the third reference voltage and the fourth reference voltage are both 0.5X, that is, V tw =X,V tr =1.5X, V wlr =-X, V ref2 =1X, V ref3 =V ref4 =0.5X, V H2 =X,V L2 = 0. At this time, the storage signal in the storage unit 11 is read out to the connected second bit line 16. It should be noted that the embodiments of the present disclosure include but are not limited to the above.

[0074] In some other possible implementations, the read transistor 13 and the write transistor 12 are both P-type transistors, the storage signal includes a second high-level signal and a second low-level signal, and the difference between the voltage of the second low-level signal and the second reference voltage is greater than the threshold voltage of each read transistor 13, that is, V L2 -V ref2 >V tr , to turn off each read transistor 13 after pre-charging.

[0075] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second high level signal, the difference between the voltage of the second low level signal and the second voltage is smaller than the threshold voltage of the read transistor 13, V L2 -V wlr <V tr , by turning on the read transistor 13 whose storage signal is the second low level signal, the voltage of the second bit line 16 connected to the turned-on read transistor 13 changes from the second reference voltage to the second voltage.

[0076] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the read transistor, that is, V H2 -V wlr <V tr The read transistor 13 whose storage signal is the second high level signal is turned off, and the voltage of the second bit line 16 connected to the turned-off read transistor 13 maintains the second reference voltage.

[0077] The difference between the voltage of the second low level signal and the third reference voltage is greater than the threshold voltage of the read transistor 13, that is, VL2 -V ref3 >V tr Furthermore, due to V H2 -V ref3 >V L2 -V ref3 >V tr , no matter the storage signals of other column read transistors 13 are the second high level signals or the second low level signals, they remain cut off.

[0078] The difference between the third reference voltage and the voltage of the second high level signal is greater than the threshold voltage of the write transistor 12, and the difference between the third reference voltage and the fourth reference voltage is greater than the threshold voltage of the write transistor 12, that is, V ref3 -V H2 >V tw , and V ref3 -V ref4 >V tw , to turn off each write transistor 12.

[0079] In some possible examples, the third reference voltage and the fourth reference voltage are half of the difference between the voltages of the second high-level signal and the second low-level signal. The voltage of the second high-level signal may be the same as the voltage of the first high-level signal, and the voltage of the second low-level signal may be the same as the voltage of the first low-level signal.

[0080] In summary, the data operation method in the embodiment of the present disclosure is applied to the above-mentioned memory 10 to implement data writing operation or data reading operation on a column of storage cells 11 in the above-mentioned storage, thereby simplifying the architecture of the memory 10 and reducing complexity.

[0081] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory (10), comprising: A plurality of memory cells (11) arranged in an array, each of the memory cells (11) comprising a write transistor (12) and a read transistor (13), a first source and drain of the write transistor (12) being connected to a gate of the read transistor (13); A plurality of first bit lines (15), each of the first bit lines (15) correspondingly connected to the second source and drain of the write transistor (12) of a row of the storage cells (11); A plurality of second bit lines (16), each of the second bit lines (16) correspondingly connected to the first source and drain of the read transistor (13) of a row of the storage cells (11); A plurality of word lines (14), each of the word lines (14) being electrically coupled to a plurality of the memory cells (11) arranged in columns, wherein in two adjacent columns of the memory cells (11), the gate of the write transistor (12) in the previous column and the second source and drain of the read transistor (13) in the next column are coupled to the same word line (14).

2. The memory (10) according to claim 1, wherein: The plurality of word lines (14) include a plurality of first word lines and two second word lines, each of the first word lines correspondingly connecting the gate of the write transistor (12) of the memory cell (11) in the first column and the second source and drain of the read transistor (13) of the memory cell (11) in the second column of two adjacent columns of the memory cells (11); The two second word lines are respectively connected to the second source and drain of the read transistor (13) of the front memory cell (11) in the two outermost memory cell (11) columns, and the gate of the write transistor (12) of the rear memory cell (11).

3. The memory (10) according to claim 1 or 2, wherein: The memory (10) further comprises a plurality of sense amplifiers (17), each of the sense amplifiers (17) being connected between the first bit line and the second bit line corresponding to a row of the storage cells (11); The sense amplifier (17) is configured to sense and amplify the voltage difference between the first bit line and the second bit line when performing a data reading operation, so as to read the data stored in the storage unit (11) from the second bit line.

4. The memory (10) according to any one of claims 1 to 3, wherein: The gate of the read transistor (13) is a storage node, and the read transistor (13) and the write transistor (12) are both N-type transistors, or the read transistor (13) and the write transistor (12) are both P-type transistors.

5. An electronic device, comprising the memory (10) according to any one of claims 1 to 4.

6. A data operation method of a memory (10), applied to the memory (10) according to any one of claims 1 to 4, the data operation method comprising: A data writing operation or a data reading operation is performed on a column of the storage units (11).

7. The data operation method according to claim 6, wherein: Performing the data writing operation on a column of the storage units (11) comprises: Applying a first voltage to a word line (14) coupled to the gate of a write transistor (12) in the memory cell (11) in the column, and applying data signals to a plurality of first bit lines (15) respectively, so as to turn on the write transistor (12) in the memory cell (11) in the column, and write the data signal into the gate of a read transistor (13) in the memory cell (11) in the column; and, A first reference voltage is applied to the word lines (14) other than the word lines (14) coupled to the gates of the write transistors (12) in the memory cells (11) in the column, and complementary signals of the data signals are applied to a plurality of second bit lines (16) respectively, so as to turn off the write transistors (12) in the memory cells (11) in the columns other than the memory cells (11) in the column, and to turn off the read transistors (13) in the memory cells (11) in each column.

8. The data operation method according to claim 7, wherein: The read transistor (13) and the write transistor (12) are both N-type transistors, and the difference between the first voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor (12), so as to turn on the write transistor (12) coupled to the word line (14) to which the first voltage is applied; The difference between the first reference voltage and the voltage of the data signal is smaller than the threshold voltage of the write transistor (12), so as to turn off the write transistor (12) coupled to the word line (14) to which the first reference voltage is applied; The data signal is one of a first high-level signal and a first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltages of the first high-level signal and the first low-level signal is smaller than the threshold voltage of the read transistor (13), and the difference between the voltage of the first high-level signal and the first reference voltage is smaller than the threshold voltage of the read transistor (13) so as to cut off each of the read transistors (13).

9. The data operation method according to claim 7 or 8, wherein: The read transistor (13) and the write transistor (12) are both P-type transistors, and the difference between the first voltage and the voltage of the data signal is smaller than the threshold voltage of the write transistor (12), so as to turn on the write transistor (12) coupled to the word line (14) to which the first voltage is applied; The difference between the first reference voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor (12), so as to turn off the write transistor (12) coupled to the word line (14) to which the first reference voltage is applied; The data signal is one of a first high-level signal and a first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltage of the first low-level signal and the first high-level signal is greater than the threshold voltage of the read transistor (13), and the difference between the voltage of the first low-level signal and the first reference voltage is greater than the threshold voltage of the read transistor (13) to cut off each of the read transistors (13).

10. The data operation method according to any one of claims 7 to 9, wherein: Performing the data reading operation on a column of the storage units (11) comprises: Precharging the plurality of second bit lines (16) to a second reference voltage; Applying a second voltage to the word line (14) coupled to the first source and drain of the read transistor (13) in the memory cell (11) in the column, and turning on or off the read transistor (13) in the memory cell (11) in the column according to the storage signal of the gate of the read transistor (13) in the memory cell (11) in the column, so as to read out the storage signal of the read transistor (13) in the memory cell (11) in the column to the connected second bit line (16); and, A third reference voltage is applied to the word lines (14) other than the word lines (14) coupled to the gates of the read transistors (13) in the memory cells (11) in the column, and a fourth reference voltage is applied to each of the plurality of first bit lines (15) to turn off the read transistors (13) in the memory cells (11) in the columns other than the memory cells (11) in the column, and to turn off the write transistors (12) in the memory cells (11) in each column.

11. The data operation method according to claim 10, wherein: The read transistor (13) and the write transistor (12) are both N-type transistors; The storage signal comprises a second high level signal and a second low level signal, the difference between the voltage of the second high level signal and the second reference voltage is smaller than the threshold voltage of each of the read transistors (13), so as to turn off each of the read transistors (13) after precharging; When the storage signal of the gate of the read transistor (13) in the storage unit (11) of the column is a second high level signal, the voltage of the second high level signal is equal to the voltage of the second voltage. The difference is greater than the threshold voltage of the read transistor (13), so as to turn on the read transistor (13) whose storage signal is a second high level signal, and the voltage of the second bit line (16) connected to the turned-on read transistor (13) changes from the second reference voltage to the second voltage; When the storage signal at the gate of the read transistor (13) in the storage unit (11) of the column is a second low level signal, the difference between the voltage of the second low level signal and the second voltage is smaller than the threshold voltage of the transistor being read, so that the read transistor (13) whose storage signal is the second low level signal is turned off, and the voltage of the second bit line (16) connected to the turned-off read transistor (13) is maintained at the second reference voltage.

12. The data operation method according to claim 11, wherein: The difference between the voltage of the second high level signal and the third reference voltage is smaller than the threshold voltage of the read transistor (13), so as to turn off the read transistors (13) in other columns; The difference between the third reference voltage and the voltage of the second low level signal is smaller than the threshold voltage of the write transistor (12), and the difference between the third reference voltage and the fourth reference voltage is smaller than the threshold voltage of the write transistor (12), so that each of the write transistors (12) is turned off.

13. The data operation method according to any one of claims 10 to 12, wherein: The read transistor (13) and the write transistor (12) are both P-type transistors; The storage signal comprises a second high level signal and a second low level signal, the difference between the voltage of the second low level signal and the second reference voltage is greater than the threshold voltage of each of the read transistors (13), so as to turn off each of the read transistors (13) after precharging; When the storage signal of the gate of the read transistor (13) in the storage unit (11) of the column is a second low-level signal, the difference between the voltage of the second low-level signal and the second voltage is smaller than the threshold voltage of the read transistor (13), so that the read transistor (13) whose storage signal is the second low-level signal is turned on, and the voltage of the second bit line (16) connected to the turned-on read transistor (13) changes from the second reference voltage to the second voltage; When the storage signal at the gate of the read transistor (13) in the storage unit (11) of the column is a second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the transistor being read, so that the read transistor (13) whose storage signal is the second high level signal is turned off, and the voltage of the second bit line (16) connected to the turned-off read transistor (13) is maintained at the second reference voltage.

14. The data operation method according to claim 13, wherein: The difference between the voltage of the second low level signal and the third reference voltage is greater than the threshold voltage of the read transistor (13), so as to turn off the read transistors (13) in other columns; The difference between the third reference voltage and the voltage of the second high level signal is greater than the threshold voltage of the write transistor (12), and the difference between the third reference voltage and the fourth reference voltage is greater than the threshold voltage of the write transistor (12), so that each of the write transistors (12) is turned off.

15. The data operation method according to any one of claims 11 to 14, wherein: The third reference voltage and the fourth reference voltage are half of a difference between a voltage of the second high level signal and a voltage of the second low level signal.

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