Method and apparatus for generating fault locating information, electronic device, and storage medium

Abstract

Embodiments of the present application relate to the technical field of generation of fault locating information, and provide a method and apparatus for generating fault locating information, an electronic device, and a storage medium. The method comprises: configuring a first operating system for a coprocessor, and configuring a second operating system for a main processor, the first operating system and the second operating system being different operating systems; when a fault signal for a server is acquired by means of the main processor, sending the fault signal to the first operating system by means of the second operating system; and generating fault locating information for the server by means of the first operating system on the basis of the fault signal. Excessively occupying the main processor when the server is subjected to fault locating is effectively avoided, improving the data processing efficiency of the processor.

Description

Fault location information generation method, device, electronic device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 28, 2023, with application number 202310944736.3 and titled “Fault Location Information Generation Method, Device, Electronic Device and Storage Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of fault location information generation, and in particular to a fault location information generation method, a fault location information generation device, an electronic device, and a computer non-volatile readable storage medium. Background Art

[0004] With the rapid development of Internet technology, servers have become an indispensable and important part of modern society. However, during the operation of the server, various faults may occur, among which IERR fault is a relatively common fault. IERR (Internal Error) refers to an internal error, which is usually caused by hardware failures such as the CPU or motherboard power supply. Hardware failures occur frequently. If the IERR fault cannot be accurately detected and handled, it will cause the server to crash, affecting the normal operation of the business and having a great impact on the stability and reliability of the server operation. Therefore, how to improve the efficiency of locating server IERR faults has become a technical problem that technicians in this field need to overcome.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a method, device, electronic device, and computer non-volatile readable storage medium for generating fault location information to solve the problem of improving the efficiency of locating server IERR faults.

[0007] The present application discloses a method for generating fault location information. The method is applied to a baseboard management controller (BMC). The BMC is configured on a server. The BMC includes a main processor and a coprocessor. The main processor and the coprocessor exchange data via a shared memory. The method includes:

[0008] Configuring a first operating system for the coprocessor and configuring a second operating system for the main processor; the first operating system and the second operating system are different operating systems;

[0009] When a fault signal for the server is obtained through the main processor, the fault signal is sent to the first operating system through the second operating system;

[0010] Fault locating information for the server is generated based on the fault signal by the first operating system.

[0011] Optionally, the first operating system is a microcontroller real-time operating system, and the second operating system is a Linux operating system.

[0012] Optionally, it also includes:

[0013] Integrate a file parsing library into a microcontroller real-time operating system.

[0014] Optionally, it also includes:

[0015] During the power-on phase of the baseboard management controller, initialization and enabling operations are performed on the coprocessor.

[0016] Optionally, the coprocessor includes a coprocessor control register, an instruction memory address limit register, a data memory address limit register, a cache function control register, and a cacheable area declaration register, and the steps of performing initialization and enabling operations on the coprocessor include:

[0017] Initialization operations and enable operations are performed on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register, and the cacheable area declaration register.

[0018] Optionally, the coprocessor has a corresponding flash memory, the flash memory is configured with a corresponding first pin control register, a second pin control register, and a pin address decoding range register, and further includes:

[0019] Serial peripheral interface configuration parameters for a first pin control register, a second pin control register, and a pin address decode range register are determined.

[0020] Optionally, a corresponding asynchronous receiver / transmitter serial port is provided between the baseboard management controller and the coprocessor, and the microcontroller real-time operating system has a corresponding entry function, further comprising:

[0021] The asynchronous receiver / transmitter serial port is initialized to determine the initial configuration parameters of the data receiving and transmitting registers corresponding to the asynchronous receiver / transmitter serial port using an entry function.

[0022] Optionally, it also includes:

[0023] Determine the initialization operation functions for the main processor and the coprocessor;

[0024] The interactive link for the shared memory is determined by the initialization operation function.

[0025] Optionally, it also includes:

[0026] A microcontroller real-time operating system is used to create a data receiving task for the fault signal.

[0027] Optionally, the step of generating fault location information for the server based on the fault signal by the microcontroller real-time operating system includes:

[0028] When the microcontroller real-time operating system receives the first interrupt signal sent by the second operating system, a fault location and solution task for the fault signal is created by the microcontroller real-time operating system;

[0029] Unlock the shared memory and receive the fault signal using the receive data task through the microcontroller real-time operating system;

[0030] The fault location solving task is adopted by the real-time operating system of the microcontroller to generate the fault location information for the server based on the fault signal.

[0031] Optionally, it also includes:

[0032] generating a fault detection process for the fault signal;

[0033] Build dual-core communication driver writing functions for the main processor and coprocessor;

[0034] Determine asset information for the server;

[0035] The fault detection process calls the dual-core communication driver write function to store the asset information in the shared memory.

[0036] Optionally, the baseboard management controller is configured with a corresponding complex programmable logic device and a platform environment control interface link; the complex programmable logic device is used to obtain a fault signal, and the steps of sending the fault signal to the microcontroller real-time operating system include:

[0037] In response to monitoring a fault signal, register information for expressing the fault signal is acquired through a platform environment control interface link, and the register information is stored in a file parsing library.

[0038] Optionally, the method is characterized in that it further comprises:

[0039] When it is detected that register information exists in the file parsing library, the register information is stored in the shared memory.

[0040] Optionally, it also includes:

[0041] When it is detected that the file parsing library has register information and the file parsing library has historical register information, the historical register information is deleted.

[0042] Optionally, it also includes:

[0043] Generate a start instruction for the fault location and solution task;

[0044] The fault detection process calls the dual-core communication driver write function to send the start execution instruction to the microcontroller real-time operating system;

[0045] Optionally, the steps of generating fault location information for the server based on the fault signal by using a fault location solution task in a microcontroller real-time operating system include:

[0046] In response to the start execution instruction, the microcontroller real-time operating system is used to generate fault location information for the server based on the register information through a fault location solution task.

[0047] Optionally, the microcontroller real-time operating system is further configured to generate a fault diagnosis result for the fault location information, and send the fault diagnosis result to the shared memory after sending the second interrupt signal to the second operating system.

[0048] Optionally, it also includes:

[0049] When the second operating system receives the second interrupt signal, it reads the fault diagnosis result from the shared memory and generates log alarm information for the fault diagnosis result.

[0050] The present application also discloses a fault location information generating device, which is applied to a baseboard management controller. The baseboard management controller is configured on a server. The baseboard management controller includes a main processor and a coprocessor. The main processor and the coprocessor exchange data through a shared memory, including:

[0051] A microcontroller real-time operating system configuration module is used to configure a first operating system for the coprocessor and a second operating system for the main processor; the first operating system and the second operating system are different operating systems;

[0052] a fault signal sending module, configured to send the fault signal to the first operating system via the second operating system when a fault signal for the server is obtained via the main processor;

[0053] The fault location information generating module is configured to generate fault location information for the server based on the fault signal through the first operating system.

[0054] Optionally, the first operating system is a microcontroller real-time operating system, and the second operating system is a Linux operating system.

[0055] Optionally, it also includes:

[0056] The file parsing library integration module is used to integrate the file parsing library into the microcontroller real-time operating system.

[0057] Optionally, it also includes:

[0058] The initialization operation and enabling operation execution module is used to execute the initialization operation and enabling operation on the coprocessor during the power-on phase of the baseboard management controller.

[0059] Optionally, the coprocessor includes a coprocessor control register, an instruction memory address limit register, a data memory address limit register, a cache function control register, and a cacheable area declaration register, and the initialization operation and enable operation execution module includes:

[0060] The initialization and enable execution submodule is used to perform initialization operations and enable operations on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register, and the cacheable area declaration register.

[0061] Optionally, the coprocessor has a corresponding flash memory, the flash memory is configured with a corresponding first pin control register, a second pin control register, and a pin address decoding range register, and further includes:

[0062] The serial peripheral interface configuration parameter determination submodule is used to determine serial peripheral interface configuration parameters for the first pin control register, the second pin control register, and the pin address decoding range register.

[0063] Optionally, a corresponding asynchronous receiver / transmitter serial port is provided between the baseboard management controller and the coprocessor, and the microcontroller real-time operating system has a corresponding entry function, further comprising:

[0064] The initial configuration parameter determination submodule is used to initialize the serial port of the asynchronous transceiver transmitter, so as to determine the initial configuration parameters of the data receiving and sending registers corresponding to the serial port of the asynchronous transceiver transmitter by using an entry function.

[0065] Optionally, it also includes:

[0066] An initialization operation function determination submodule, used to determine the initialization operation functions for the main processor and the coprocessor;

[0067] The interactive link determination submodule is used to determine the interactive link for the shared memory through an initialization operation function.

[0068] Optionally, it also includes:

[0069] The receiving data task creation submodule is used to create a receiving data task for a fault signal by using a microcontroller real-time operating system.

[0070] Optionally, the fault location information generating module includes:

[0071] a fault location and solution task creation submodule, configured to create a fault location and solution task for the fault signal through the microcontroller real-time operating system when the microcontroller real-time operating system receives a first interrupt signal sent by the second operating system;

[0072] A fault signal receiving submodule is used to unlock the shared memory and receive the fault signal by using a receive data task through the real-time operating system of the microcontroller;

[0073] The fault location information generation submodule is used to generate fault location information for the server based on the fault signal by adopting the fault location solution task through the real-time operating system of the microcontroller.

[0074] Optionally, it also includes:

[0075] A fault detection process generation submodule is used to generate a fault detection process for a fault signal;

[0076] A dual-core communication driver write function construction submodule is used to construct a dual-core communication driver write function for the main processor and the coprocessor;

[0077] An asset information determination submodule, used to determine asset information for the server;

[0078] The asset information storage submodule is used to store asset information in shared memory by calling the dual-core communication driver write function through the fault detection process.

[0079] Optionally, the baseboard management controller is configured with a corresponding complex programmable logic device and a platform environment control interface link; the complex programmable logic device is used to obtain a fault signal, and the steps of sending the fault signal to the microcontroller real-time operating system include:

[0080] The fault signal sending submodule is used to obtain register information used to express the fault signal through the platform environment control interface link in response to monitoring the fault signal, and store the register information in the file parsing library.

[0081] Optionally, it also includes:

[0082] The register information storage submodule is used to store the register information in the shared memory when detecting that the file parsing library has register information.

[0083] Optionally, it also includes:

[0084] The historical register information deletion submodule is used to delete the historical register information when it is detected that the file parsing library has register information and the file parsing library has historical register information.

[0085] Optionally, it also includes:

[0086] The start execution instruction generation submodule is used to generate the start execution instruction for the fault location and solution task;

[0087] The start execution instruction sending submodule is used to call the dual-core communication driver write function through the fault detection process to send the start execution instruction to the microcontroller real-time operating system;

[0088] The fault location information generation submodule includes:

[0089] The fault location information generating unit is used to generate fault location information for the server based on register information by using a microcontroller real-time operating system through a fault location solving task in response to a start execution instruction.

[0090] Optionally, the microcontroller real-time operating system is further configured to generate a fault diagnosis result for the fault location information, and send the fault diagnosis result to the shared memory after sending the second interrupt signal to the second operating system.

[0091] Optionally, it also includes:

[0092] The fault diagnosis result reading submodule is used to read the fault diagnosis result from the shared memory when the second operating system receives the second interrupt signal, and generate log alarm information for the fault diagnosis result.

[0093] An embodiment of the present application also discloses a server, which is configured with a baseboard management controller. The baseboard management controller includes a main processor and a coprocessor. The main processor and the coprocessor exchange data through shared memory. The baseboard management controller is used to configure a first operating system for the coprocessor and a second operating system for the main processor; the first operating system and the second operating system are different operating systems; when a fault signal for the server is obtained by the main processor, the fault signal is sent to the first operating system through the second operating system; and fault location information for the server is generated by the first operating system based on the fault signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] FIG1 is a flowchart of a method for generating fault location information provided in an embodiment of the present application;

[0095] FIG2 is a schematic diagram of the structure of a server provided in an embodiment of the present application;

[0096] FIG3 is a schematic diagram of a structure of a register provided in an embodiment of the present application;

[0097] FIG4 is a schematic diagram of an execution flow for a FreeRTOS system provided in an embodiment of the present application;

[0098] FIG5 is a schematic diagram of an execution flow for a Linux system provided in an embodiment of the present application;

[0099] FIG6 is a schematic diagram of the structure of a baseboard management controller and a server central processing unit provided in an embodiment of the present application;

[0100] FIG7 is a data flow timing diagram provided in an embodiment of the present application;

[0101] FIG8 is a structural block diagram of a fault location information generating device provided in an embodiment of the present application;

[0102] FIG9 is a hardware structure block diagram of an electronic device provided in an embodiment of the present application;

[0103] FIG10 is a schematic diagram of a computer-readable medium provided in an embodiment of the present application. Specific embodiments

[0104] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0105] In order to enable those skilled in the art to better understand the embodiments of the present application, some technical terms involved in the embodiments of the present application are explained below.

[0106] A BMC (Board Management Controller) is a specialized service processor that uses sensors to monitor the status of a computer, network server, or other hardware device and communicates with the system administrator via independent connections. The BMC is part of the Intelligent Platform Management Interface (IPMI) and is typically contained within the motherboard or main circuit board of the monitored device. The BMC's sensors measure internal physical variables such as temperature, humidity, power supply voltage, fan speed, communication parameters, and operating system (OS) function. If any of these variables exceed established limits, the BMC notifies the administrator, who can then take corrective action using remote control. The monitored device can be power-cycled or restarted when necessary. This allows a single administrator to remotely control numerous servers and other devices simultaneously, reducing overall network costs and ensuring reliability.

[0107] JSON (JavaScript Object Notation) is a lightweight, text-based, readable format. Based on a subset of ECMAScript (the European Computer Manufacturers Association's JS specification), it uses a text format that is completely independent of the programming language to store and represent data. Its simplicity and clear hierarchical structure make JSON an ideal data exchange language. It's easy for humans to read and write, as well as for machines to parse and generate, and significantly improves network transmission efficiency.

[0108] FreeRTOS: A real-time operating system for microcontrollers. FreeRTOS is a mini real-time operating system kernel. As a lightweight operating system, its features include task management, time management, semaphores, message queues, memory management, logging, software timers, and coroutines, and can generally meet the needs of smaller systems.

[0109] AST2600: A new generation of BMC.

[0110] IERR: Internal error.

[0111] Linux, full name GNU / Linux, is a free to use and free to disseminate UNIX-like operating system. It is mainly inspired by Minix and Unix ideas. It is a POSIX-based multi-user, multi-tasking, multi-threaded and multi-CPU operating system.

[0112] The CPU (Central Processing Unit) serves as the computing and control core of a computer system and is the ultimate execution unit for information processing and program execution. Since its inception, the CPU has achieved significant advancements in logical structure, operational efficiency, and functional extension.

[0113] Currently, related technologies implement fault detection through the server motherboard's Baseboard Management (BMC). This BMC, powered by a Linux system, performs IEER fault detection. While this method can effectively detect hardware faults, it only provides basic hardware monitoring capabilities and cannot meet the requirements of high-end servers. Therefore, improving the accuracy and real-time performance of server IEER fault detection has become a hot topic of research.

[0114] The server IERR fault location algorithm is highly complex and requires a large amount of data, resulting in high CPU usage. This can also affect other programs and even cause system lags, impacting system stability and responsiveness. Therefore, mitigating the CPU usage caused by the large number of BMC algorithm executions is a challenge.

[0115] To this end, this application proposes a server IERR fault precision location algorithm based on a coprocessor equipped with Freertos. This method can be based on the AST2600 hardware platform, and utilizes the coprocessor, low power consumption, safety and reliability, flexibility and ease of use, and the lightweight, high real-time and good stability characteristics of the freertos operating system. Freertos is run on the coprocessor to complete the development of the server IERR fault precision location algorithm. At the same time, in view of the high performance and high processing power of the main processor and the complex functions of the linxu system, the linxu system is run on the main processor to complete the collection of auxiliary CPU registers and the alarm processing of fault results. This method can effectively improve the accuracy and real-time performance of server IEER fault detection. At the same time, the server IERR fault precision location algorithm is completed by the coprocessor, which can greatly reduce the occupancy rate of the main processor and improve the data processing efficiency of the processor.

[0116] 1 , a flowchart of a method for generating fault location information provided in an embodiment of the present application is shown, which may specifically include the following steps:

[0117] Step 101: configure a first operating system for the coprocessor and a second operating system for the main processor; the first operating system and the second operating system are different operating systems;

[0118] Step 102: When a fault signal for the server is obtained through the main processor, the fault signal is sent to the first operating system through the second operating system;

[0119] Step 103: Generate fault location information for the server based on the fault signal through the first operating system.

[0120] In a specific implementation, the embodiment of the present application can be applied to a baseboard management controller in a server. For example, the baseboard management controller of the embodiment of the present application can be a baseboard management controller equipped with AST2600.

[0121] Referring to Figure 2, which is a schematic diagram of the structure of a server provided in an embodiment of the present application, the server may include a main processor and a coprocessor. For example, the main processor may be a Cortex A7, and the coprocessor may be a Cortex M3, which may be a 32-bit processor core. The internal data path is 32-bit, the registers are 32-bit, and the memory interface is also 32-bit. The CM3 adopts a Harvard architecture with independent instruction and data buses, allowing instruction fetches and data access to proceed in parallel.

[0122] Of course, the above examples are only examples, and those skilled in the art may adopt any other central processing unit (CPU) as the main processor or coprocessor according to actual needs, and the embodiments of the present application do not limit this.

[0123] The main processor of the embodiment of the present application can exchange data with the coprocessor through the shared memory based on the data bus bus.

[0124] In the embodiment of the present application, independent operating systems can be installed for the main processor and the coprocessor respectively. Specifically, a first operating system can be configured for the coprocessor, and a second operating system can be configured for the main processor; the first operating system and the second operating system are different operating systems.

[0125] In some embodiments of the present application, the first operating system may install a microcontroller real-time operating system freeRtso for the coprocessor, and the second operating system may be a Linux operating system.

[0126] For example, communication can be established between the main processor Cortex A7 and the coprocessor Cortex M3 of AST2600 through the bus Bus. When an IERR fault occurs in the server, the fault signal caterr is triggered. When the Linux system running on the main processor receives the caterr signal, it directly collects the register information used to express the caterr signal and transmits the register information to the freertos system running on the coprocessor. After the freertos system receives the start execution instruction and the CPU register information, it runs the fault positioning algorithm in real time to detect the fault. After the detection is completed, the detection result is fed back to the Linux system, and the Linux system performs operations such as log alarms, thereby effectively avoiding excessive occupation of the main processor when locating the server fault.

[0127] In an embodiment of the present application, a first operating system is configured for the coprocessor and a second operating system is configured for the main processor; the first operating system and the second operating system are different operating systems; when a fault signal for a server is obtained by the main processor, the fault signal is sent to the first operating system through the second operating system; and the first operating system generates fault location information for the server based on the fault signal, thereby effectively avoiding excessive occupation of the main processor when locating the server fault, thereby improving the data processing efficiency of the processor.

[0128] Based on the above embodiment, a modified embodiment of the above embodiment is proposed. It should be noted that, in order to simplify the description, only the differences from the above embodiment are described in the modified embodiment.

[0129] In some optional embodiments of the present application, the present invention further includes:

[0130] Integrate a file parsing library into a microcontroller real-time operating system.

[0131] In practical applications, the precise fault location algorithm requires the parsing and processing of a large number of JSON files. However, before the Cortex M3 was equipped with the FreeRTOS system, the FreeRTOS system itself did not have a JSON file parsing library.

[0132] Therefore, in the specific implementation, the embodiment of the present application may first need to complete the integration of the third-party json library and the freertso system before the hardware platform is installed. For example, the open source json-c library can be selected to achieve integrated integration into the freertso system.

[0133] In the embodiment of the present application, a file parsing library is integrated into a microcontroller real-time operating system to expand the generation and parsing functions of the FreeRTOS system for JSON data.

[0134] In some optional embodiments of the present application, the present invention further includes:

[0135] During the power-on phase of the baseboard management controller, initialization and enabling operations are performed on the coprocessor.

[0136] In practical applications, initialization can set up the coprocessor, and enabling operation can make the coprocessor available.

[0137] Optionally, the coprocessor includes a coprocessor control register, an instruction memory address limit register, a data memory address limit register, a cache function control register, and a cacheable area declaration register, and the steps of performing initialization and enabling operations on the coprocessor include:

[0138] Initialization operations and enable operations are performed on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register, and the cacheable area declaration register.

[0139] Specifically, the first initial configuration parameter may be an initial configuration parameter for the coprocessor.

[0140] Refer to FIG3 , which is a schematic diagram of a structure of a register provided in an embodiment of the present application.

[0141] In a specific implementation, the initialization and enable operations may involve the parameter configuration of the CM3 coprocessor control register, the CM3 instruction memory address limit register, the CM3 data memory address limit register, the CM3 cache function control register and the CM3 cacheable area declaration register. Specifically, the initialization operation and the enable operation may be performed on the control register, the instruction memory address limit register, the data memory address limit register, the cache function control register and the cacheable area declaration register respectively.

[0142] The embodiment of the present application completes the initialization and enabling of the coprocessor by performing initialization operations and enabling operations on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register, and the cacheable area declaration register, thereby ensuring the stability of the coprocessor during operation, thereby improving the success rate of FreeRTOS system startup.

[0143] Optionally, the coprocessor has a corresponding flash memory, the flash memory is configured with a corresponding first pin control register, a second pin control register, and a pin address decoding range register, and further includes:

[0144] Serial peripheral interface configuration parameters for a first pin control register, a second pin control register, and a pin address decode range register are determined.

[0145] In practical applications, ce is the abbreviation of chip enable, which can be a pin required for reading and writing flash memory.

[0146] The coprocessor of the embodiment of the present application may have a corresponding flash memory FLASH. The embodiment of the present application may configure the serial peripheral interface FSPI of the flash memory before starting the Freetos system.

[0147] Referring to Figure 3, the embodiment of the present application can determine the serial peripheral interface configuration parameters for the CE first pin control register, the CE1 second pin control register, and the CE1 pin address decoding range register, and configure the serial peripheral interface FSPI of the flash memory through the serial peripheral interface configuration parameters.

[0148] In an embodiment of the present application, before starting the real-time operating system of the microcontroller, the serial peripheral interface configuration parameters for the first pin control register, the second pin control register, and the pin address decoding range register are determined, and the serial peripheral interface FSPI of the flash memory is configured through the serial peripheral interface configuration parameters, thereby improving the stability of the flash memory FLASH and thus improving the data interaction efficiency between the main processor and the coprocessor.

[0149] Based on this, the preparation process before the FreeRTOS system is started is completed. The following is a description of the data execution process of the FreeRTOS system after the FreeRTOS system is started.

[0150] In some optional embodiments of the present application, a corresponding asynchronous receiver / transmitter serial port is provided between the baseboard management controller and the coprocessor, and the microcontroller real-time operating system has a corresponding entry function, further comprising:

[0151] An entry function is used to determine initial configuration parameters of data receiving and transmitting registers corresponding to the serial port of the asynchronous receiver and transmitter.

[0152] A Universal Asynchronous Receiver / Transmitter (UART), commonly known as a UART, is an asynchronous receiver / transmitter that is part of server hardware. A corresponding UART may be provided between the baseboard management controller and the coprocessor in the embodiment of the present application, and the UART may be configured with an UART serial port.

[0153] The embodiment of the present application can construct an entry function main for the Freertos system. In a specific implementation, after completing the startup of the Freetos system, the entry function main can be used to determine the initial configuration parameters of the data receiving and transmitting registers corresponding to the serial port of the asynchronous transceiver transmitter, so that the print information of the Freertos system can be normally output to the BMC terminal serial port, thereby improving the efficiency of generating fault location information.

[0154] In some optional embodiments of the present application, the present invention further includes:

[0155] Determine the initialization operation functions for the main processor and the coprocessor;

[0156] The interactive link for the shared memory is determined by the initialization operation function.

[0157] In practical applications, shared memory and inter-core interrupts are the most basic underlying configurations for communication between the main processor and the coprocessor. Therefore, the embodiment of the present application can determine the initialization operation function for the main processor and the coprocessor. The initialization operation function can be used to determine the shared memory for the main processor and the coprocessor, as well as the interactive link for the shared memory, thereby completing the parameter configuration of the shared memory, and completing the configuration and enabling of the registers of the soft interrupt for communication between the master / slave processors, ensuring that the underlying interactive link of the dual processors is correct.

[0158] In some optional embodiments of the present application, the present invention further includes:

[0159] A microcontroller real-time operating system is used to create a data receiving task for the fault signal.

[0160] Exemplarily, an embodiment of the present application can create a data receiving task for communication between a master / slave processor. The data receiving task can be used to be responsible for the FreeRTOS system receiving data information sent by the Linux system and performing corresponding processing based on the data information.

[0161] In some optional embodiments of the present application, the step of generating fault location information for the server based on the fault signal by the microcontroller real-time operating system includes:

[0162] When the microcontroller real-time operating system receives the first interrupt signal sent by the second operating system, a fault location and solution task for the fault signal is created by the microcontroller real-time operating system;

[0163] Unlock the shared memory and receive the fault signal using the receive data task through the microcontroller real-time operating system;

[0164] The fault location solving task is adopted by the real-time operating system of the microcontroller to generate the fault location information for the server based on the fault signal.

[0165] In a specific implementation, the embodiment of the present application can use a microcontroller real-time operating system to create a fault location and solution task. After receiving the start execution instruction sent by the Linux system, the microcontroller real-time operating system can execute the fault location and solution task to generate fault location information for the server.

[0166] Based on this, the data execution process of the FreeRTOS system is completed. The following is a description of the data execution process of the Linux system after the Linux system is started.

[0167] Optionally, it also includes:

[0168] generating a fault detection process for the fault signal;

[0169] Build dual-core communication driver writing functions for the main processor and coprocessor;

[0170] Determine asset information for the server;

[0171] The fault detection process calls the dual-core communication driver write function to store the asset information in the shared memory.

[0172] In a specific implementation, the present invention can generate a fault detection process for fault signals and construct a dual-core communication driver write function for the main processor and coprocessor. The present invention can also determine asset information for the server and store the asset information in a file parsing library, so that the fault detection process can call the dual-core communication driver write function to store the asset information in shared memory.

[0173] For example, after the BOIS (Basic Input Output System) is started, the asset information of devices such as the CPU, memory, high-speed serial computer expansion bus PCIE required for fault detection can be sent to the BMC, and the BMC can store it in a designated location in JSON format. Specifically, the fault detection process starts normally, and the fault detection process can be used to call the dual-core communication driver write function to write the asset information and other information required for precise fault detection into the preset designation of the shared memory. Optionally, the designated area can be set in advance.

[0174] In some optional embodiments of the present application, the baseboard management controller is configured with a corresponding complex programmable logic device and a platform environment control interface link; the complex programmable logic device is used to obtain a fault signal, and the steps of sending the fault signal to the microcontroller real-time operating system include:

[0175] In response to monitoring a fault signal, register information for expressing the fault signal is acquired through a platform environment control interface link, and the register information is stored in a file parsing library.

[0176] Exemplarily, the baseboard management controller is configured with a corresponding complex programmable logic device (CPLD) and a platform environment control interface link. When an IEER fault occurs in the server, a fault signal (CATERR) can be triggered. The CATERR signal can be captured by the complex programmable logic device (CPLD), and the BMC detects the signal in real time. When the BMC detects the signal, it can trigger an application for automatic register collection. The application can directly collect the CPU register information through the platform environment control interface link (PECI) and store it in JSON format, thereby realizing that asset information, CPU register information, etc. between the Linux system and the FreeRTOS system can be transmitted based on the JSON file format, thereby improving the efficiency of fault location.

[0177] In some optional embodiments of the present application, the present invention further includes:

[0178] When it is detected that register information exists in the file parsing library, the register information is stored in the shared memory.

[0179] When it is detected that the file parsing library has register information and the file parsing library has historical register information, the historical register information is deleted.

[0180] For example, when the IEER fault detection thread in the fault diagnosis process detects the existence of a json file of the CPU register, it will clear the file information of the previous IEER fault detection and then store the CPU register information in json format into the shared memory.

[0181] In an embodiment of the present application, when register information is detected in the file parsing library, the register information is stored in the shared memory; when register information is detected in the file parsing library and historical register information is present in the file parsing library, the historical register information is deleted, thereby avoiding register information redundancy.

[0182] In some optional embodiments of the present application, the present invention further includes:

[0183] Generate a start instruction for the fault location and solution task;

[0184] The fault detection process calls the dual-core communication driver write function to send the start execution instruction to the microcontroller real-time operating system.

[0185] Optionally, the steps of generating fault location information for the server based on the fault signal by using a fault location solution task in a microcontroller real-time operating system include:

[0186] In response to the start execution instruction, the microcontroller real-time operating system is used to generate fault location information for the server based on the register information through a fault location solution task.

[0187] For example, the Linux system can generate a start execution instruction for the fault location and solution task, and call the dual-core communication driver write function through the fault detection process to send the start execution instruction to the microcontroller real-time operating system FreeRTOS. After the fault location and solution task of the FreeRTOS system determines that it has received the start precise positioning instruction, it can call the fault precise positioning entry function to perform fault detection to locate the faulty firmware.

[0188] Optionally, the microcontroller real-time operating system is further configured to generate a fault diagnosis result for the fault location information, and send the fault diagnosis result to the shared memory after sending the second interrupt signal to the second operating system.

[0189] In a specific implementation, the FreeRTOS system can also organize the fault diagnosis results and write them into the free channels in the shared memory, thereby creating conditions for the main processor to read the fault diagnosis results through the shared memory based on the Linux system.

[0190] Optionally, it also includes:

[0191] When the second operating system receives the second interrupt signal, it reads the fault diagnosis result from the shared memory and generates log alarm information for the fault diagnosis result.

[0192] In a specific implementation, the main processor of the embodiment of the present application can generate log alarm information for the fault diagnosis result after reading the fault diagnosis result through shared memory based on the Linux system to facilitate maintenance by technical personnel.

[0193] In order to enable those skilled in the art to better understand the embodiments of the present application, a complete example is used below to illustrate the embodiments of the present application.

[0194] Refer to FIG6 , which is a schematic structural diagram of a baseboard management controller and a server central processing unit provided in an embodiment of the present application.

[0195] The baseboard management controller may include a main processor and a coprocessor, and the main processor and the coprocessor may exchange data via a shared memory based on a data bus (the first sub-bus is an M bus, the second sub-bus is an AHB bus, and the third sub-bus is an APB bus).

[0196] Refer to Figure 7, which is a data flow timing diagram provided in an embodiment of the present application.

[0197] By establishing communication between the main processor Cortex A7 and the coprocessor Cortex M3 of AST2600, when an IERR fault occurs in the server and triggers the caterr signal, the main processor Linux system directly collects the CPU register information and transmits it to the coprocessor FreeRTOS system after receiving the signal. After receiving the fault precise location instruction and CPU register information, the FreeRTOS system runs the fault precise location algorithm in real time to perform fault detection. After the detection is completed, the detection results are fed back to the Linu system, and the Linux system performs log alarm and other operations.

[0198] Specifically, before Cortex M3 is equipped with the FreeRTOS system, considering that the fault location algorithm involves the parsing of a large number of JSON files, and the FreeRTOS system itself does not have a JSON file parsing library, before the hardware platform is installed, it is necessary to first complete the integration of the third-party JSON library and the FreeRTOS system. The open source JSON-C library can be selected to achieve integrated integration, thereby completing the expansion of the FreeRTOS system's JSON data generation and parsing functions;

[0199] BMC is powered on and started, and Cortex A7 starts the diskless boot read-only memory interface bootrom boot program. In the SPL (Secondary Program Loader) stage, the Cortex M3 is initialized and enabled. The initialization and enabling involve the parameter configuration of the CM3 coprocessor control register, CM3 instruction memory address limit register, CM3 data memory address limit register, CM3 cache function control register, and CM3 cacheable area declaration register. After the configuration is completed, the Cortex M3 is enabled. At the same time, the FLASH chip select configuration is also required in this stage. The configuration involves the parameter configuration of the CE first pin control register, the CE1 second pin control register, and the CE1 pin address decoding range register. After the configuration is successful, the Cortex M3 successfully loads the FreeRTOS system. As a lightweight operating system, FreeRTOS can achieve a fast startup at the millisecond level. At the same time, the Cortex A7 loads the Linux system.

[0200] Based on this, the preparation process before the FreeRTOS system is started is completed. The following is a description of the data execution process of the FreeRTOS system after the FreeRTOS system is started;

[0201] Refer to FIG4 , which is a schematic diagram of an execution flow for a FreeRTOS system provided in an embodiment of the present application;

[0202] The first step of the FreeRTOS entry function main is to configure the BCM's UART serial port data receiving and sending registers, so that the FreeRTOS system's print information can be normally output to the BMC terminal serial port, which is convenient for debugging and problem analysis.

[0203] Shared memory and inter-core interrupts are the most basic low-level configuration for communication between the main processor and the coprocessor. Therefore, the second step is to execute the dual-core communication initialization operation function. This function mainly completes the parameter configuration of the dual-core shared memory and the register configuration and enablement of the dual-core communication soft interrupt to ensure the correct low-level interaction link between the two processors.

[0204] The third step is to create a dual-core communication data receiving task, which is responsible for the FreeRTOS system to receive the data information sent by the Linux system and perform corresponding processing based on the data information;

[0205] The fourth step is to create a task to start fault location and solution; this task is executed after receiving the start fault location instruction sent by the Linux system.

[0206] In the fault location and solution task of FreeRTOS, after receiving the start location instruction, it starts to call the fault location entry function to perform fault detection; after a series of complex process judgments, the IEER fault detection will locate the faulty firmware, and at the same time organize the fault diagnosis results and write them into the shared memory idle channel, and send a soft interrupt signal to the main processor.

[0207] Based on this, the data execution process of the FreeRTOS system is completed. The following is a description of the data execution process of the Linux system after the Linux system is started.

[0208] Refer to FIG5 , which is a schematic diagram of an execution flow for a Linux system provided in an embodiment of the present application;

[0209] After the Linux operating system is started, the overall software process includes:

[0210] After BOIS is started, the asset information of CPU, memory, PCIe devices, etc. required for fault detection is sent to BMC. BMC stores it in the specified location in JSON format. The fault detection process starts normally. The fault detection process calls the dual-core communication driver write function to write the asset information and other information required for accurate fault detection and positioning into the specified area of ​​shared memory. The specified area can be pre-set.

[0211] When an IEER failure occurs on a server, a caterr signal is triggered. This signal is captured by cpld and the BMC detects the signal in real time. When the BMC detects the signal, it triggers the automatic register collection application. This application directly collects CPU register information through the peci link and stores it in json format.

[0212] When the IEER fault detection thread in the fault diagnosis process detects the existence of the json file of the CPU register, it will clean up the file information of the previous IEER fault detection and then store the CPU register information in json format into the shared memory;

[0213] This thread calls the write function of the dual-core communication driver to send the start execution fault precise positioning instruction to the FreeRTOS system.

[0214] The main processor Linux system performs read and write operations for dual-core communication by registering a callback processing function, and uses the SIGUSER1 semaphore as the interrupt semaphore. When a soft interrupt signal sent by FreeRTOS is received, the signal callback function is triggered. The callback function reads the fault diagnosis result from the shared memory. The fault diagnosis result is finally generated by Linux as a log alarm information for easy maintenance.

[0215] Through the above method, server IERR failures can be detected quickly and accurately, the impact of failures on the system can be avoided from spreading, and the impact of system failures on users can be reduced, thereby reducing the time and cost of troubleshooting, improving user satisfaction and the stability and reliability of the server, while ensuring the real-time and stability of the system. This is of great significance for server operation and maintenance, greatly facilitates the efficient fault location of operation and maintenance personnel, lays the foundation for the product to win customer reputation, and provides strong technical support for subsequent market and customer expansion. The brand competitiveness of the product is effectively improved and has broad application prospects.

[0216] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0217] 8 , a block diagram of a fault location information generating device provided in an embodiment of the present application is shown, which may include the following modules:

[0218] A microcontroller real-time operating system configuration module 601 is configured to configure a first operating system for the coprocessor and a second operating system for the main processor; the first operating system and the second operating system are different operating systems;

[0219] A fault signal sending module 602 is configured to send the fault signal to the first operating system via the second operating system when a fault signal for the server is obtained via the main processor;

[0220] The fault location information generating module 603 is configured to generate fault location information for the server based on the fault signal through the first operating system.

[0221] Optionally, the first operating system is a microcontroller real-time operating system, and the second operating system is a Linux operating system.

[0222] Optionally, it also includes:

[0223] The file parsing library integration module is used to integrate the file parsing library into the microcontroller real-time operating system.

[0224] Optionally, it also includes:

[0225] The initialization operation and enabling operation execution module is used to execute the initialization operation and enabling operation on the coprocessor during the power-on phase of the baseboard management controller.

[0226] Optionally, the coprocessor includes a coprocessor control register, an instruction memory address limit register, a data memory address limit register, a cache function control register, and a cacheable area declaration register, and the initialization operation and enable operation execution module includes:

[0227] The initialization and enable execution submodule is used to perform initialization operations and enable operations on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register, and the cacheable area declaration register.

[0228] Optionally, the coprocessor has a corresponding flash memory, the flash memory is configured with a corresponding first pin control register, a second pin control register, and a pin address decoding range register, and further includes:

[0229] The serial peripheral interface configuration parameter determination submodule is used to determine serial peripheral interface configuration parameters for the first pin control register, the second pin control register, and the pin address decoding range register.

[0230] Optionally, a corresponding asynchronous receiver / transmitter serial port is provided between the baseboard management controller and the coprocessor, and the microcontroller real-time operating system has a corresponding entry function, further comprising:

[0231] The initial configuration parameter determination submodule is used to initialize the serial port of the asynchronous transceiver transmitter, so as to determine the initial configuration parameters of the data receiving and sending registers corresponding to the serial port of the asynchronous transceiver transmitter by using an entry function.

[0232] Optionally, it also includes:

[0233] An initialization operation function determination submodule, used to determine the initialization operation functions for the main processor and the coprocessor;

[0234] The interactive link determination submodule is used to determine the interactive link for the shared memory through an initialization operation function.

[0235] Optionally, it also includes:

[0236] The receiving data task creation submodule is used to create a receiving data task for a fault signal by using a microcontroller real-time operating system.

[0237] Optionally, the fault location information generating module includes:

[0238] a fault location and solution task creation submodule, configured to create a fault location and solution task for the fault signal through the microcontroller real-time operating system when the microcontroller real-time operating system receives a first interrupt signal sent by the second operating system;

[0239] A fault signal receiving submodule is used to unlock the shared memory and receive the fault signal by using a receive data task through the real-time operating system of the microcontroller;

[0240] The fault location information generation submodule is used to generate fault location information for the server based on the fault signal by adopting the fault location solution task through the real-time operating system of the microcontroller.

[0241] Optionally, it also includes:

[0242] A fault detection process generation submodule is used to generate a fault detection process for a fault signal;

[0243] A dual-core communication driver write function construction submodule is used to construct a dual-core communication driver write function for the main processor and the coprocessor;

[0244] An asset information determination submodule, used to determine asset information for the server;

[0245] The asset information storage submodule is used to store asset information in shared memory by calling the dual-core communication driver write function through the fault detection process.

[0246] Optionally, the baseboard management controller is configured with a corresponding complex programmable logic device and a platform environment control interface link; the complex programmable logic device is used to obtain a fault signal, and the steps of sending the fault signal to the microcontroller real-time operating system include:

[0247] The fault signal sending submodule is used to obtain register information used to express the fault signal through the platform environment control interface link in response to monitoring the fault signal, and store the register information in the file parsing library.

[0248] Optionally, it also includes:

[0249] The register information storage submodule is used to store the register information in the shared memory when detecting that the file parsing library has register information.

[0250] Optionally, it also includes:

[0251] The historical register information deletion submodule is used to delete the historical register information when it is detected that the file parsing library has register information and the file parsing library has historical register information.

[0252] Optionally, it also includes:

[0253] The start execution instruction generation submodule is used to generate the start execution instruction for the fault location and solution task;

[0254] The start execution instruction sending submodule is used to call the dual-core communication driver write function through the fault detection process to send the start execution instruction to the microcontroller real-time operating system;

[0255] The fault location information generation submodule includes:

[0256] The fault location information generating unit is used to generate fault location information for the server based on register information by using a microcontroller real-time operating system through a fault location solving task in response to a start execution instruction.

[0257] Optionally, the microcontroller real-time operating system is further configured to generate a fault diagnosis result for the fault location information, and send the fault diagnosis result to the shared memory after sending the second interrupt signal to the second operating system.

[0258] Optionally, it also includes:

[0259] The fault diagnosis result reading submodule is used to read the fault diagnosis result from the shared memory when the second operating system receives the second interrupt signal, and generate log alarm information for the fault diagnosis result.

[0260] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0261] In addition, an embodiment of the present application also provides an electronic device, including: a processor, a memory, and a computer program stored in the memory and runnable on the processor. When the computer program is executed by the processor, the various processes of the above-mentioned fault location information generation method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0262] The present application also provides a non-volatile computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the various processes of the above-mentioned method for generating fault location information are implemented, and the same technical effects are achieved. To avoid repetition, the details are not described here. The non-volatile computer-readable storage medium may be, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0263] FIG9 is a schematic diagram of the hardware structure of an electronic device implementing various embodiments of the present application.

[0264] The electronic device 900 includes but is not limited to components such as a radio frequency unit 901, a network module 902, an audio output unit 903, an input unit 904, a sensor 905, a display unit 906, a user input unit 907, an interface unit 908, a memory 909, a processor 910, and a power supply 911. Those skilled in the art will appreciate that the electronic device structure shown in FIG7 does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange the components differently. In the embodiments of the present application, the electronic device includes but is not limited to a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted terminal, a wearable device, and a pedometer.

[0265] It should be understood that in the embodiments of the present application, the RF unit 901 may be used to receive and transmit signals during information transmission or calls. Specifically, it receives downlink data from the base station and transmits it to the processor 910 for processing; in addition, it transmits uplink data to the base station. Typically, the RF unit 901 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, and the like. Furthermore, the RF unit 901 may communicate with the network and other devices via a wireless communication system.

[0266] The electronic device provides users with wireless broadband Internet access through the network module 902, such as helping users to send and receive emails, browse web pages, and access streaming media.

[0267] The audio output unit 903 can convert audio data received by the RF unit 901 or the network module 902 or stored in the memory 909 into an audio signal and output it as sound. In addition, the audio output unit 903 can also provide audio output related to a specific function performed by the electronic device 900 (for example, a call signal reception sound, a message reception sound, etc.). The audio output unit 903 includes a speaker, a buzzer, a receiver, etc.

[0268] The input unit 904 is used to receive audio or video signals. The input unit 904 may include a graphics processing unit (GPU) 9041 and a microphone 9042. The graphics processor 9041 processes image data of a still picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The processed image frames can be displayed on the display unit 906. The image frames processed by the graphics processor 9041 can be stored in the memory 909 (or other storage medium) or transmitted via the radio frequency unit 901 or the network module 902. The microphone 9042 can receive sound and can process such sound into audio data. The processed audio data can be converted into a format that can be sent to a mobile communication base station via the radio frequency unit 901 in the case of a telephone call mode.

[0269] The electronic device 900 also includes at least one sensor 905, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 9061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 9061 and / or the backlight when the electronic device 900 is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in all directions (generally three axes), and can detect the magnitude and direction of gravity when stationary. It can be used to identify the posture of the electronic device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; the sensor 905 can also include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be repeated here.

[0270] The display unit 906 is used to display information input by the user or information provided to the user. The display unit 906 may include a display panel 9061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0271] The user input unit 907 can be used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device. Specifically, the user input unit 907 includes a touch panel 9071 and other input devices 9072. The touch panel 9071, also known as a touch screen, can collect user touch operations on or near it (such as operations performed by the user using any suitable object or accessory such as a finger, stylus, etc. on or near the touch panel 9071). The touch panel 9071 may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction and detects the signal caused by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device and converts it into contact point coordinates, which are then sent to the processor 910, which receives the command sent by the processor 910 and executes it. In addition, the touch panel 9071 can be implemented using various types such as resistive, capacitive, infrared and surface acoustic wave. In addition to the touch panel 9071, the user input unit 907 may also include other input devices 9072. Specifically, other input devices 9072 may include but are not limited to a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0272] Furthermore, the touch panel 9071 may be overlaid on the display panel 9061. When the touch panel 9071 detects a touch operation on or near it, it transmits the information to the processor 910 to determine the type of touch event. The processor 910 then provides a corresponding visual output on the display panel 9061 based on the type of touch event. Although in FIG7 , the touch panel 9071 and the display panel 9061 are used as two independent components to implement the input and output functions of the electronic device, in some embodiments, the touch panel 9071 and the display panel 9061 may be integrated to implement the input and output functions of the electronic device, which is not limited to this specific embodiment.

[0273] The interface unit 908 is an interface for connecting external devices to the electronic device 900. For example, the external devices may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, etc. The interface unit 908 may be used to receive input (e.g., data information, power, etc.) from the external device and transmit the received input to one or more elements within the electronic device 900, or may be used to transmit data between the electronic device 900 and the external device.

[0274] Memory 909 can be used to store software programs and various data. Memory 909 may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as a sound playback function or an image playback function); the data storage area may store data generated based on the use of the mobile phone (such as audio data, a phone book, etc.). Furthermore, memory 909 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0275] The processor 910 is the control center of the electronic device. It connects the various components of the electronic device using various interfaces and circuits. By running or executing software programs and / or modules stored in the memory 909 and accessing data stored in the memory 909, it performs various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. The processor 910 may include one or more processing units; preferably, the processor 910 may integrate an application processor and a modem processor, wherein the application processor primarily processes the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into the processor 910.

[0276] The electronic device 900 may also include a power supply 911 (such as a battery) to supply power to each component. Preferably, the power supply 911 may be logically connected to the processor 910 through a power management system, thereby managing functions such as charging, discharging, and power consumption through the power management system.

[0277] In addition, the electronic device 900 includes some functional modules not shown, which will not be described here.

[0278] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0279] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of each embodiment of the present application.

[0280] As shown in FIG10 , in some other embodiments provided in the present application, a computer non-volatile readable storage medium 1001 is further provided, in which instructions are stored. When the instructions are executed on a computer, the computer executes the fault location information generating method in the above-mentioned embodiment.

[0281] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

[0282] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0283] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0284] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0285] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0286] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0287] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0288] The above are only some specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for generating fault location information, characterized in that: The method is applied to a baseboard management controller, the baseboard management controller is configured on a server, the baseboard management controller includes a main processor and a coprocessor, the main processor and the coprocessor perform data exchange through a shared memory, and includes: configuring a first operating system for the coprocessor and configuring a second operating system for the main processor; the first operating system and the second operating system are different operating systems; When a fault signal for the server is acquired through the main processor, the fault signal is sent to the first operating system through the second operating system; The first operating system generates fault location information for the server based on the fault signal.

2. The method according to claim 1, characterized in that The first operating system is a microcontroller real-time operating system, and the second operating system is a Linux operating system.

3. The method according to claim 2, characterized in that Also includes: A file parsing library is integrated into the microcontroller real-time operating system.

4. The method according to claim 3, characterized in that Also includes: During the power-on phase of the baseboard management controller, an initialization operation and an enabling operation are performed on the coprocessor.

5. The method according to claim 4, characterized in that The coprocessor includes a coprocessor control register, an instruction memory address limit register, a data memory address limit register, a cache function control register, and a cacheable area declaration register, and the steps of performing initialization operations and enabling operations on the coprocessor include: Initialization operations and enabling operations are performed on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register, and the cacheable area declaration register.

6. The method according to claim 5, characterized in that The coprocessor has a corresponding flash memory, the flash memory is configured with a corresponding first pin control register, a second pin control register, and a pin address decoding range register, and further includes: Determine serial peripheral interface configuration parameters for the first pin control register, the second pin control register, and the pin address decoding range register.

7. The method according to claim 4, characterized in that There is a corresponding asynchronous transceiver serial port between the baseboard management controller and the coprocessor, and the microcontroller real-time operating system has a corresponding entry function, and also includes: The entry function is used to determine initial configuration parameters of data receiving and transmitting registers corresponding to the serial port of the asynchronous receiver and transmitter.

8. The method according to claim 7, characterized in that Also includes: Determine initialization operation functions for the main processor and the coprocessor; An interactive link for the shared memory is determined through an initialization operation function.

9. The method according to claim 8, characterized in that Also includes: The microcontroller real-time operating system is used to create a data receiving task for the fault signal.

10. The method according to claim 9, characterized in that The step of generating fault location information for the server based on the fault signal by the microcontroller real-time operating system comprises: When the microcontroller real-time operating system receives the first interrupt signal sent by the second operating system, a fault location and solution task for the fault signal is created by the microcontroller real-time operating system; Unlocking the shared memory, and receiving the fault signal by using the receiving data task through the microcontroller real-time operating system; The fault location solving task is adopted by the microcontroller real-time operating system to generate fault location information for the server based on the fault signal.

11. The method according to claim 10, characterized in that Also includes: generating a fault detection process for the fault signal; Constructing a dual-core communication driver write function for the main processor and the coprocessor; determining asset information for the server; The fault detection process calls the dual-core communication driver write function to store the asset information in the shared memory.

12. The method according to claim 11, characterized in that The baseboard management controller is configured with a corresponding complex programmable logic device and a platform environment control interface link; the complex programmable logic device is used to obtain a fault signal, and the step of sending the fault signal to the microcontroller real-time operating system through the second operating system includes: In response to monitoring the fault signal, register information for expressing the fault signal is acquired through the platform environment control interface link, and the register information is stored in the file parsing library.

13. The method according to claim 12, characterized in that Also includes: When it is detected that the file parsing library contains the register information, the register information is stored in the shared memory.

14. The method according to claim 12, characterized in that Also includes: When it is detected that the file parsing library has the register information and the file parsing library has historical register information, the historical register information is deleted.

15. The method according to claim 13 or 14, characterized in that Also includes: Generate a start execution instruction for the fault location and solution task; The dual-core communication driver write function is called through the fault detection process to send the start execution instruction to the microcontroller real-time operating system.

16. The method according to claim 15, characterized in that The step of using the fault location solving task through the microcontroller real-time operating system to generate fault location information for the server based on the fault signal includes: In response to the start execution instruction, the microcontroller real-time operating system is used to generate fault location information for the server based on the register information through the fault location solving task.

17. The method according to claim 16, characterized in that The microcontroller real-time operating system is also used to generate a fault diagnosis result for the fault location information, and after sending a second interrupt signal to the second operating system, send the fault diagnosis result to the shared memory.

18. The method according to claim 17, characterized in that Also includes: When the second operating system receives the second interrupt signal, the fault diagnosis is read from the shared memory. The result is a log warning message generated for the fault diagnosis result.

19. A fault location information generating device, characterized in that: The device is applied to a baseboard management controller, the baseboard management controller is configured on a server, the baseboard management controller includes a main processor and a coprocessor, the main processor and the coprocessor perform data exchange through a shared memory, including: A microcontroller real-time operating system configuration module, configured to configure a first operating system for the coprocessor and a second operating system for the main processor; the first operating system and the second operating system are different operating systems; a fault signal sending module, configured to send the fault signal to the first operating system through the second operating system when a fault signal for the server is acquired through the main processor; A fault location information generating module is used to generate fault location information for the server based on the fault signal through the first operating system.

20. A server, characterized in that: The server is configured with a baseboard management controller, the baseboard management controller includes a main processor and a coprocessor, the main processor and the coprocessor perform data exchange through a shared memory, the baseboard management controller is used to configure a first operating system for the coprocessor and a second operating system for the main processor; the first operating system and the second operating system are different operating systems; When a fault signal for the server is acquired by the main processor, the fault signal is sent to the first operating system by the second operating system; and fault location information for the server is generated by the first operating system based on the fault signal.

21. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; The memory is used to store computer programs; The processor is used to implement the method according to any one of claims 1 to 17 when executing the program stored in the memory.

22. A computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, cause the processors to perform the method according to any one of claims 1 to 17.

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