Satellite navigation baseband processing device optimized by coprocessor

Abstract

The invention relates to a satellite navigation baseband processing device optimized by a coprocessor. A core processing part of the device adopts a realization framework of a main processor and a coprocessor; the coprocessor is used for scheduling hardware acceleration computing resources in real time under exchange control of the main processor, and completing high-real-time processing tasks such as signal capture and tracking loop processing of satellite navigation; an instruction set and an external interface of the coprocessor are subjected to targeted optimization, the bus bit width and the internal storage width of the coprocessor are expanded, and the in-situ width of an ALU and a register of the coprocessor is reserved; performing bus data access and storage by adopting an external port access instruction and an internal memory access instruction which are matched with the expanded bus according to the expansion state; and performing access and storage of single register data by adopting a bus write enable, an access instruction and a storage instruction which are matched with the expanded internal storage width. According to the invention, the function load of the main processor is effectively reduced, and the implementation cost of the baseband processing device is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of system on chip and satellite navigation technology, and in particular relates to a coprocessor-optimized satellite navigation baseband processing device. Background Art

[0002] Satellite navigation receivers (GNSS receivers) can obtain their own position, velocity and time (PVT) information by receiving and processing radio frequency signals broadcast by navigation satellites. The processing process of GNSS receivers receiving navigation signals can be divided into two stages: first, signal capture and tracking processing is performed to detect whether the satellite navigation signal exists, and a tracking channel is allocated to the existing signal for tracking processing. This stage is called satellite navigation signal processing; second, navigation message demodulation and decoding are performed, and the ranging information of the tracked satellite is extracted, and the user PVT information is calculated based on this. The overall scheduling operations such as receiver time correction and allocation of satellites to be captured are performed according to the navigation message and PVT information feedback. This stage is called satellite navigation information processing. The above two stages are collectively referred to as satellite navigation baseband processing, which is implemented by the satellite navigation baseband processing module (referred to as GNSS baseband module) inside the GNSS receiver. This module usually adopts the implementation architecture of dedicated chip (ASIC) or programmable logic (FPGA) + processor (CPU) to meet the miniaturization and integration requirements of user terminals.

[0003] In the GNSS baseband module, the information processing of satellite navigation can usually be implemented by a general-purpose processor with strong performance, while the signal processing of satellite navigation cannot be implemented by a general-purpose processor alone, but requires the processor to schedule the hardware accelerators such as the capture engine and the tracking engine in high real time. At present, in the mainstream GNSS baseband modules, there are implementation architectures that use a powerful main processor to take into account the hardware resource scheduling tasks in information processing and signal processing, and there are also implementation architectures that use a main processor plus a coprocessor. When the implementation architecture of the main processor plus the coprocessor is adopted: the coprocessor can realize the front-end signal processing such as capturing and tracking satellite navigation signals in real time under the exchange control of the main processor; the main processor is only responsible for realizing the overall scheduling and satellite navigation information processing. By introducing a coprocessor into the baseband processing of satellite navigation, the following two problems can be solved: First, the coprocessor shares the high real-time processing tasks of the main processor, reducing the load of the main processor, thereby reducing the processing power requirements of the main processor, and effectively reducing the technical threshold and economic cost of implementing the baseband processing module; second, it effectively reduces the complexity of the software on the main processor, and can support the use of packaging mechanisms such as embedded Linux operating system and custom driver module design, so that users can carry out secondary development of software for specific application scenarios. Therefore, the satellite navigation baseband processing implementation architecture using a main processor plus a coprocessor is an important technical development trend, and the key to supporting the development of this architecture lies in the optimized design of the coprocessor.

[0004] In the engineering practice of GNSS baseband processing module design and implementation, ARM hard-core processors are usually selected as the main processors, and soft-core processors are selected as coprocessors. The soft-core processors available can be roughly divided into two categories: one is non-open source soft-core processors, such as Xilinx's MicroBlaze and other soft-core processors; the other is open source soft-core processors, such as Xilinx's PicoBlaze and PicoRV32 processors based on the RISC-V instruction set. For non-open source soft cores such as MicroBlaze, although they have advantages such as high processing efficiency, complete tool chain, and ease of use, it is difficult to obtain the RTL source code of the processor and cannot be applied to ASIC implementation. Among the open source soft-core processors: the PicoBlaze processor, which consumes less resources and is easy to integrate, is more suitable as a coprocessor for GNSS baseband processing, but its bus width is only 8 bits, the processing efficiency is not high enough, and software development is not very convenient; soft-core processors that comply with the RISC-V specification, such as PicoRV32, have sufficient processing power and a relatively complete software development tool chain, but such processors were originally designed to be used as main processors, require more implementation resources, and are difficult to tailor and integrate according to the needs of GNSS baseband processing.

[0005] In summary, in order to meet the needs of satellite navigation baseband processing using the main processor plus coprocessor architecture, it is necessary to optimize the design of a dedicated coprocessor. Summary of the invention

[0006] In view of the above technical background analysis, the present invention aims to disclose a coprocessor-optimized satellite navigation baseband processing device to solve the above-mentioned coprocessor optimization design problem in satellite navigation baseband processing using a main processor plus coprocessor architecture.

[0007] The present invention discloses a coprocessor-optimized satellite navigation baseband processing device, comprising:

[0008] The main processor + coprocessor implementation architecture is adopted; among them,

[0009] The main processor is used for overall scheduling and satellite navigation information processing and is a wide-bit-width processor;

[0010] The coprocessor is used to schedule hardware accelerated computing resources in real time under the switching control of the main processor, and perform signal acquisition and tracking loop processing for satellite navigation. It is a narrow bit width coprocessor;

[0011] Targeted optimization is performed on the instruction set and external interface of the coprocessor, the bus width and internal storage width of the coprocessor are expanded, and the original width of the coprocessor arithmetic unit (ALU) and general registers are retained; according to the expansion state, external port access and internal storage access instructions that match the widened bus are used to access and store bus data; bus write enable, access instructions and storage instructions that match the widened internal storage width are used to access and store single register data;

[0012] Satellite navigation baseband processing is performed through the cooperation of the optimized processor and the main processor.

[0013] Another aspect of the present invention discloses a satellite navigation receiver, in which the satellite navigation receiver adopts the satellite navigation baseband processing device optimized by the coprocessor as described above to perform satellite navigation baseband processing.

[0014] The present invention can achieve one of the following beneficial effects:

[0015] The present invention utilizes the characteristic that the coprocessor required for satellite navigation baseband signal processing has a stronger requirement on I / O throughput rate than on arithmetic operation. By innovatively modifying the instruction set and implementation mechanism of the disclosed PicoBlaze soft-core processor, the problems of insufficient coprocessor bus access speed and mismatch between the coprocessor bus width and the main processor bus width are solved, thereby forming a type of coprocessor suitable for application in the field of satellite navigation signal processing implementation.

[0016] The optimized coprocessor inherits the advantage of PicoBlaze processor that it occupies less hardware resources, and solves the problem of unequal I / O throughput between the main processor and the coprocessor, so that the coprocessor in the baseband processing device can better exert its control and computing efficiency, and the processing performance fully meets the requirements of completing common tracking, capture scheduling and other processing tasks in GNSS baseband signal processing. In addition, this type of processor is also implemented in RTL code, with a simple external interface, easy to integrate and apply, and convenient to use in ASIC design and domestic FPGA, and can replace more complex non-open source processors such as MicroBlaze.

[0017] By adopting the main processor plus coprocessor implementation architecture of the present invention in a satellite navigation baseband processing device and using the coprocessor with optimized design of the present invention, the functional load of the main processor can be effectively reduced, and the implementation difficulty of the main processor can be significantly reduced, thereby reducing the implementation cost of the baseband processing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0019] Figure 1 A schematic block diagram showing the connection components of a satellite navigation baseband processing device optimized for a coprocessor in an embodiment of the present invention;

[0020] Figure 2 The figure is a schematic block diagram of the internal components and connections of an anti-interference satellite navigation baseband processing device implemented by using a Zynq7035 chip in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0022] Embodiment 1

[0023] An embodiment of the present invention discloses a satellite navigation baseband processing device optimized by a coprocessor, such as Figure 1 As shown, a main processor + coprocessor architecture is adopted; wherein,

[0024] The main processor is used for overall scheduling and satellite navigation information processing. It is a wide-bit-width processor. It mainly processes satellite navigation information processing and signal processing auxiliary calculations with low time requirements. The main processor is usually an ARM architecture processor, and the basic bit width of the bus and data is 32 bits.

[0025] The coprocessor is used to schedule hardware accelerated computing resources in real time under the switching control of the main processor, and perform signal acquisition and tracking loop processing for satellite navigation. It is a narrow bit width coprocessor;

[0026] Targeted optimization of the coprocessor's instruction set and external interface; expansion of the coprocessor bus width and internal storage width, retaining the original width of the coprocessor's arithmetic unit (ALU) and general registers; using external port access and internal storage access instructions that match the widened bus to access and store bus data according to the expansion state; using bus write enable, access instructions, and storage instructions that match the widened internal storage width to access and store single register data;

[0027] Satellite navigation baseband processing is performed through the cooperation of the optimized processor and the main processor.

[0028] The coprocessor includes a coprocessor for capturing and at least one coprocessor for tracking. Each coprocessor is connected to the high-speed bus of the main processor and realizes data exchange with the main processor through the dual-port RAM.

[0029] In this embodiment, as a coprocessor of the main processor inside the GNSS baseband processing device, it can be implemented in ASIC or FPGA, and only needs to independently execute a small segment of program code under the configuration of the main processor, and does not need to have the code loading, memory management and other functions of a complete general-purpose processor.

[0030] Therefore, the purpose of implementing the coprocessor proposed in the embodiment of the present invention is to reduce the hardware resources occupied by the coprocessor as much as possible while meeting the processing performance requirements, and to simplify the external interface of the coprocessor as much as possible to facilitate design and integration.

[0031] In the baseband signal processing of satellite navigation, the most typical processing task is the loop filtering processing of signal tracking. This type of processing task requires the implementation of computational processing such as pseudocode phase discriminator and carrier phase discriminator. It also requires the implementation of a third-order phase-locked loop and a second-order frequency-locked loop based on fixed-point operation. It has the characteristics of more computational processing and hardware access control processing.

[0032] Therefore, when the coprocessor is mainly used to implement satellite navigation capture and tracking processing tasks, a large number of input and output access operations of hardware peripherals and computing acceleration units are required, and the arithmetic operation function of the coprocessor is mainly used in process and state control and some relatively simple calculations, showing a phenomenon of high requirements for I / O throughput but low requirements for arithmetic operations.

[0033] After analyzing the existing KCPSM3 soft-core processor (a type of Xilinx's PicoBlaze series processors) that can be used as a coprocessor, it was found that since the bus and ALU bit width of KCPSM3 are both 8 bits and the processing power is limited, it is difficult to meet the requirements of being used as a satellite signal tracking, scheduling and control coprocessor when using the main processor + coprocessor architecture for GNSS baseband processing. Although there is a practice of using multiple KCPSM3 soft-core processors to share processing tasks in parallel in the GNSS baseband processing coprocessor, the difficulty of processing system construction design and software implementation is very high, which is not conducive to widespread promotion.

[0034] Therefore, when existing soft-core processors such as KCPSM3 are used as coprocessors, problems such as low data throughput and slow processing speed are caused.

[0035] The reason is that most of the various data and parameters for signal processing in the main processor are high-bit-width integer types, while the bus width of the narrow-bit-width coprocessor is low. As a result, the ALU of the narrow-bit-width coprocessor can meet the computing requirements because it is mainly used in process and state control and some relatively simple calculations.

[0036] Based on this, the coprocessor of the embodiment of the present invention optimizes the coprocessors for capture and tracking respectively on the basis of inheriting the advantage of less hardware resources occupied by the PicoBlaze processor;

[0037] In the optimization, the bus width and internal storage width of the coprocessor are expanded, and the original width of the coprocessor ALU and registers are retained;

[0038] The bus width and internal storage width of the coprocessor are expanded to improve its I / O throughput rate. In addition, the original width of the coprocessor ALU and registers is retained to avoid the waste of instruction space and the rapid increase of processor implementation resources caused by the increase of ALU and register width.

[0039] Furthermore, according to the expansion status, external port access and internal memory access instructions that match the widened bus are used to access and store bus data; bus write enable, access instructions and storage instructions that match the widened internal storage width are used to access and store single register data; thus, flexible access and storage of bus data and register data are realized.

[0040] Thus, the problems of insufficient access speed of the coprocessor bus and mismatch between the coprocessor bus width and the main processor bus width are solved, and a type of coprocessor suitable for application in the field of satellite navigation signal processing is formed; while meeting the processing performance requirements, the hardware resources occupied by the coprocessor are reduced as much as possible, and the external interface of the coprocessor is simplified as much as possible to facilitate design and integration.

[0041] In this embodiment, based on the PicoBlaze processor such as KCPSM3, the coprocessor is optimized and improved as follows:

[0042] First, the data bit width of the external bus is changed to twice the bit width of the internal basic register, the bit width of the internal ALU remains the same as the bit width of the register, and the width of the internal storage is also changed to twice the width of the register; accordingly, the actual execution meaning of the two external port access instructions, input and output, and the two internal storage access instructions, fetch and store, are changed to operate on a group of two adjacent registers at the same time, and the execution meaning of other instructions remains unchanged;

[0043] When the data bit width of the external bus is changed to twice the register width, when executing instructions including "Op Sx, kk" and "Op Sx, Sy", where Op is one of Input, Output, Fetch or Store, the accessed registers include Sx and another register Sx' adjacent to Sx. When x is an even number such as 0, 2, 4, x'=x+1; when x is an odd number such as 1, 3, 5, x'=x-1;

[0044] For example: when the input s2 03 instruction is executed, the data with a bit width of twice the register width read from the external port 03 will be written to the two registers s2 and s3; when the output s3 03 instruction is executed, the data with a bit width of twice the register width composed of the two registers {s3, s2} will be written to the external port 03; when the fetch s5 05 instruction is executed, the data at address 05 of the internal memory will be read into the two registers s4 and s5; when the store s6 05 instruction is executed, the data with a bit width of twice the register width composed of the two registers {s7, s6} will be written to address 05 of the internal memory.

[0045] In this way, two registers can be accessed through one instruction, which improves the I / O throughput rate.

[0046] Second, the write enable of the bus outside the processor is changed to high and low 2 bits, and a new external port output instruction outHB is added to the instruction set; it is used to implement data access operations based on a single register; thereby making up for the deficiency that in the first improvement, the execution meaning of the output instruction is modified to operate on two registers, and the data of a single register cannot be output separately.

[0047] The external port output instruction outHB includes two forms: "outHB Sx, kk" and "outHB Sx, Sy". The corresponding meaning is: only output the value of register Sx to the external port with the immediate value kk or the value of register Sy as the address;

[0048] When x is an even number, the data corresponding to the outHB instruction is output to the lower half of the bus of the external port, and the write enable of the lower bit is valid at this time;

[0049] When x is an odd number, the data corresponding to the outHB instruction is output to the high half of the bus of the external port, and the write enable of the high bit is valid at this time;

[0050] When executing an output instruction that operates on a group of two adjacent registers at the same time, both the high and low 2-bit write enables are valid.

[0051] For example: the outHB S0 06 instruction will write the value of register S0 to the lower half of port 06; the outHB S106 instruction will write the value of register S0 to the upper half of port 06.

[0052] Third, in the instruction set, a new internal RAM data storage instruction storeHB is added to store a single register data separately; thereby solving the problem of software programming application caused by the first improvement in which the execution meaning of the store instruction is modified to only store two registers at the same time and cannot store the data of a single register separately.

[0053] The internal RAM data storage instruction storeHB includes two forms: "storeHB Sx, kk" and "storeHB Sx, Sy". The corresponding meaning is: only store the value of register Sx into the internal RAM storage, and the address is determined by the immediate value kk or the value of register Sy.

[0054] When x is an even number, the data corresponding to the storeHB instruction is stored in the lower half of the address of the internal RAM;

[0055] When x is an odd number, the data corresponding to the storeHB instruction is stored in the high half of the address of the internal RAM.

[0056] For example, the storeHB S2 07 instruction will write the value of register S2 to the lower half of the internal memory address 07; the outHB S3 07 instruction will write the value of register S3 to the upper half of the internal memory address 07.

[0057] In a specific solution, a satellite navigation baseband processing device with a 1 main processor + 2 coprocessors architecture is provided;

[0058] Among them, the two coprocessors are the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A;

[0059] The first coprocessor is a capture coprocessor, which is used for front-end signal processing of satellite navigation signal capture and executes the capture program; it is optimized using a PicoBlaze processor with an instruction data bit width of 8 bits, such as a KCPSM3 processor;

[0060] Through optimization, the capture coprocessor keeps the instruction data width at 8 bits and the bus data width is expanded to 16 bits;

[0061] The second coprocessor is a tracking coprocessor, which is used for front-end signal processing of satellite navigation signal tracking and executes tracking programs. It is optimized using a PicoBlaze processor with a 16-bit instruction data width.

[0062] Through optimization, the instruction data width of the tracking coprocessor is extended to 26 bits, and the bus data width is extended to 32 bits.

[0063] After the instruction data bit width and bus data width of the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A are expanded, the coprocessor decoding mode, external port definition and instruction set are optimized, including:

[0064] (1) The first coprocessor WUPSM-3A;

[0065] The instruction width of the first coprocessor is 18 bits, the bus width is 16 bits, and the ALU width is 8 bits. The processor has 16 8-bit registers numbered S0 to SF, the internal memory width is 16 bits, the depth is configurable (the default is 32, and the configurable range is 32, 64, 128, 256), and the program code space is 1024×18 bits;

[0066] A single instruction is Instr[17:0], and the decoding method of each part is:

[0067] Instr[17:14]----instruction main type;

[0068] Instr[13:12]----instruction auxiliary type;

[0069] Instr[11:10]----Whether the jump instruction depends on the Z, NZ, C, NC flags;

[0070] Instr[11:8]----first operand;

[0071] Instr[7:4]----the second operand;

[0072] Instr[7:0]----Immediate value.

[0073] The WUPSM-3A processor implements RTL-level code implementation. The top-level module name is advanced_lite_pb, and the external port definitions are shown in the following table.

[0074]

[0075] (2) Second coprocessor WUPSM-4A;

[0076] The instruction bit width of the second coprocessor is 26 bits (extended from 18 in PicoBlaze to 26), the bus width is 32 bits, and the ALU bit width is 16 bits; the processor has 16 16-bit registers numbered S0 to SF, the internal memory bit width is 32 bits, and the depth is configurable (the default is 32, and the configurable range is 32, 64, 128, 256... up to 65536), and the storage space for program code is 4096×26 bits;

[0077] The single instruction is Instr[25:0], and the decoding method of each part is:

[0078] Instr[25:22]----instruction main type;

[0079] Instr[21:20]----instruction auxiliary type;

[0080] Instr[19:18]----Whether it depends on the Z, NZ, C, NC flags;

[0081] Instr[19:16]----first operand;

[0082] Instr[15:12]----the second operand;

[0083] Instr[15:0]----Immediate value.

[0084] The WUPSM-4A processor implements RTL-level code implementation. The top-level module name is advanced_lite, and the external port definitions are shown in the following table.

[0085]

[0086] (3) Detailed instruction set definition for the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A

[0087] The detailed instruction set definitions of WUPSM-3A and WUPSM-4A can be summarized in the following table.

[0088]

[0089]

[0090]

[0091]

[0092] When the satellite navigation baseband processing device of the present embodiment with the architecture of 1 main processor + 2 coprocessors is used to perform satellite navigation baseband processing,

[0093] The first coprocessor WUPSM-3A is connected to a signal capture hardware accelerator (referred to as capture engine) on its external bus, and is used to configure the capture engine to start executing signal capture processing according to the signal capture instruction initiated by the main processor, and feed back the capture results to the main processor.

[0094] The first coprocessor mainly completes the scheduling and control tasks of the capture engine. It does not need to perform more complex arithmetic calculations. Therefore, it adopts an 18-bit instruction bit width and a 16-bit bus width, combined with an optimized instruction set, to achieve I / O throughput in scheduling and control tasks and improve its I / O throughput rate. It performs calculations through an 8-bit ALU. On the basis of meeting application requirements, it avoids the waste of instruction space caused by the increase in ALU and register bit width and the rapid increase in processor implementation resources.

[0095] The second coprocessor WUPSM-4A is connected to a group of signal tracking channels (referred to as tracking engines) on its external bus, for example, 36 channels; it is used to complete the pseudo-code demodulation and loop filtering processing of a group of signal tracking channels set therein, to ensure that the local carrier and pseudo-code phase of the tracking channel remain consistent with the real signal being tracked, and at the same time transmit the correlation value information obtained after pseudo-code demodulation and secondary code stripping of the signal to the main processor, and then the signal processing module in the main processor performs FFT-based Doppler estimation, bit synchronization, telegram synchronization, telegram decoding and other processing.

[0096] In the second coprocessor, not only the scheduling and control tasks for the tracking engine need to be completed, but also the loop filtering processing of satellite signal tracking needs to be realized. The specific tasks include: realizing the calculation processing of pseudo code phase discriminator, carrier phase discriminator, etc., realizing the third-order phase lock loop and second-order frequency lock loop processing based on fixed-point operation, etc. In the traditional conventional implementation scheme, such tracking coprocessing tasks are realized by large-scale soft-core processors such as MicroBlaze and ARM7 with strong processing capabilities. Therefore, compared with the capture process, the requirements for I / O throughput and arithmetic calculation are higher, and the real-time requirements are also higher; therefore, a 26-bit instruction bit width and a 32-bit bus width are used, combined with an optimized instruction set, to realize the I / O throughput in the scheduling and control tasks, improve its I / O throughput rate, and perform calculations through an ALU with a bit width of 16 bits.

[0097] In summary, the satellite navigation baseband signal processing device of the embodiment of the present invention utilizes the characteristics that the coprocessor required for satellite navigation baseband signal processing has a stronger requirement for I / O throughput than for arithmetic operations. Through the innovative design of the instruction set and its execution mechanism, and through the innovative modification of the instruction set and its implementation mechanism of the public PicoBlaze soft-core processor, the problem of insufficient access speed of the coprocessor bus and the mismatch between the coprocessor bus width and the main processor bus width is solved, so that the coprocessor in the baseband processing device can better exert the control and computing efficiency, and the processing performance fully meets the requirements of completing the common tracking, capture scheduling and other processing tasks in GNSS baseband signal processing. In addition, the designed coprocessor is also implemented using RTL code, with a simple external interface, which is convenient for integrated application, convenient for application in ASIC design and domestic FPGA, and can replace more complex non-open source processors such as MicroBlaze. In this type of baseband processing device, through the use of high-efficiency coprocessing, by effectively reducing the functional load of the main processor, the difficulty of implementing the main processor can be significantly reduced, thereby reducing the implementation cost of the baseband processing device.

[0098] Embodiment 2

[0099] This embodiment discloses that in a low-cost satellite navigation anti-interference terminal FPGA prototype design, the satellite navigation baseband processing device is all implemented on a Xilinx Zynq7035 chip, and the implementation architecture of the main processor plus multiple coprocessors is adopted; Figure 2 As shown,

[0100] Wherein: the main processor of the baseband processing device is a dual-core ARM9 processor of the PS part of the Zynq7035 chip; the first coprocessor and the second coprocessor are implemented in the PL part of the Zynq chip, and both coprocessors realize data exchange with the main processor through dual-port RAM;

[0101] The first coprocessor and the second coprocessor respectively implement the coprocessing scheduling of the acquisition engine and the tracking engine; respectively implement the scheduling control coprocessing of one acquisition channel and 36 tracking channels; receive and process the signals of the Beidou B1 and B3 frequency points and the civil signals of the GPS L1 frequency point;

[0102] Preferably, an anti-interference module is added to the baseband processing device to implement an array anti-interference algorithm based on 4 array elements, and then perform baseband processing of satellite navigation after canceling the interference signal in the received signal, so as to improve the ability of the processing device to adapt to complex interference environments.

[0103] Due to the introduction of the first coprocessor and the second coprocessor, the design minimizes the resources occupied by the baseband processing part, so that the various resources occupied by the baseband processing device other than the anti-interference processing array are shown in the following table:

[0104]

[0105] As can be seen from the table above, in the baseband processing part, after optimization, the receiver with 36 channels only occupies less than 60% of the main processing resources, and a large amount of DSP and BRAM resources are reserved for the implementation of array anti-interference algorithms. Therefore, based on the method of the present invention, the PL part of a single Zynq7035 device can also simultaneously implement array anti-interference processing of 4 array elements, and run stably, realizing the capture, tracking and positioning solution processing of navigation signals in the Zynq chip with limited resources, and realizing anti-interference processing at the same time, realizing satellite navigation positioning with strong anti-interference ability under low-cost conditions.

[0106] Specifically, it also includes a first program code memory;

[0107] The software for implementing the capture engine scheduling and control processing on the first coprocessor WUPSM-3A coprocessor is written in assembly code (the assembler is modified based on the open source assembler that supports PicoBlaze), and the length of the compiled binary program code is 394; an 18bitx512 BRAM is used as the first program code memory to store the program code of the coprocessor. After the synthesis is completed, the path of WUPSM-3A processing in the design is:

[0108] U_DIT_LiteUav / U_gnss_main_proc / inst / U_ae / inst / U_acq_top / U_mcu_acq / U_pb_for_acq

[0109] The resources consumed by this processor include: 78 FLOP_LATCH, 164 LUT, 3 CARRY, and 57 DMEM.

[0110] Specifically, it also includes a second program code memory;

[0111] The software for implementing the scheduling and control processing of the tracking engine on the second coprocessor WUPSM-4A processor is written in assembly code (the assembler is modified based on the open source assembler that supports PicoBlaze), and the length of the compiled binary program code is 1271; a 26bitx2048 BRAM is used as the first program code memory to store the program code of the coprocessor. After the synthesis is completed, the path of WUPSM-4A processing in the design is:

[0112] U_DIT_LiteUav / U_gnss_main_proc / inst / U_TrackCtrlCp / U_mcu_track / U_pb_for_track

[0113] The resources consumed by this processor include: 124 FLOP_LATCH, 227 LUT, 17 CARRY, and 108 DMEM.

[0114] In summary, it can be seen that the coprocessor designed in the present invention does have the advantage of greatly saving resources.

[0115] To further comprehensively demonstrate the features of the coprocessor proposed in the present invention, in this embodiment, the second coprocessor WUPSM-4A processor of the present invention is compared with the mainstream MicroBlaze processor from three aspects: implementation cost, processing efficiency, and convenience of application software development and debugging.

[0116] When the tracking engine uses WUPSM-4A to schedule the tracking engine, the interface control circuit for adapting the tracking engine, the multiplier for accelerating calculation, the inverse tangent lookup table, etc. are all implemented in the tracking engine module (i.e., the U_TrackCtrlCp module), while the MicroBlaze processor only needs to adapt the interface control circuit for the tracking engine to form the tracking engine module U_TrackCtrlCp. Therefore, the comparison can be made by replacing the implementation of the U_TrackCtrlCp module in the design of the entire PL.

[0117] The comparison of resource usage is shown in the following table:

[0118]

[0119] According to the table above, when using WUPSM-4A as a coprocessor, the tracking engine scheduling module uses LUT resources more than MicroBlaze, but the rest of the resources are less than MicroBlaze. Since WUPSM-4A uses assembly code that directly operates hardware, it does not need to use standard C library functions, which effectively reduces the size of program code, thereby reducing 2 36Kbit BRAMs. Since MicroBlaze is configured with 32x32-bit hardware multipliers, the number of standard multipliers consumed is 4. When using the WUPSM-4A processor, 16x32-bit multipliers are optimized according to the characteristics of the tracking coprocessor, thereby reducing the consumption of two standard multipliers.

[0120] The comparison in terms of processing efficiency is as follows:

[0121] Considering that in the tracking engine scheduling process, the most important algorithm that the coprocessor needs to implement is the typical tracking loop processing, including: pseudo code phase discriminator, carrier phase discriminator and loop filtering. By building a simulation test bed based on System Verilog and using front-end simulation tools to simulate, the number of clock cycles required for a loop processing of the two processors is recorded respectively, and the processing efficiency of the two processors can be analyzed and compared, as shown in the following table.

[0122]

[0123] From the table above, we can see that when the working clock frequency is the same as 124MHz, the coprocessor based on MicroBlaze has a relatively high processing speed, but the coprocessor based on WUPSM-4A can reach about 2 / 3 of MicroBlaze. No matter which processor is used, there is enough software processing time margin when scheduling the tracking coprocessor of 36 channels.

[0124] The comparison of the convenience of application software development and debugging is as follows:

[0125] In the tracking coprocessor built on MicroBlaze, its software programming can use C / C++ language. In the SDK software provided by Xilinx, the software is compiled to form a binary program file that needs to be initialized to the program memory. The programming implementation of the application software is relatively convenient, and the maintainability of the software code is also good. However, due to the need to use standard C library functions, there is a problem that the compiled code volume is large. In the tracking coprocessor built on WUPSM-4A, its software programming uses assembly language that can directly operate the registers in the processor. There are certain limitations in software development and implementation and the maintainability of software code. However, the use of assembly language can more directly use the characteristics of the processor architecture and save program space and data space as much as possible. In the specific programming implementation, the function functions implemented by the assembly language on the WUPSM-4A processor and the function functions implemented on the MicroBlaze processor can be compared one by one to speed up the verification of the software function. For example: the tracking data of each signal tracking channel on the MicroBlaze processor is stored in a data structure as follows:

[0126] typedef struct{

[0127] S64 np_filter;

[0128] S64 wp_filter;

[0129] S32 carr_fault_h;

[0130] S32 carr_fault_l;

[0131] S32 code_fault_h;

[0132] S32 code_fault_l;

[0133] S32 carry_fre_int;

[0134] S32 carry_nco_fre_err;

[0135] S32 dither;

[0136] S32 carry_fre_frac;

[0137] S32 code_nco_fre_err;

[0138] S32 fft_fd;

[0139] S32 MessAcc;

[0140] S32 i_amp_mean;

[0141] S32 q_amp_mean;

[0142] S32 square_corr;

[0143] S16 early_Icorr;

[0144] S16 early_Qcorr;

[0145] S16 punct_Icorr;

[0146] S16 punct_Qcorr;

[0147] S16 late_Icorr;

[0148] S16 late_Qcorr;

[0149] U16 FreSel;

[0150] U16 SatNum;

[0151] U16 BrhId;

[0152] U16 RateType;

[0153] U16 wait_syn_en;

[0154] U16 mess_num;

[0155] U16 cnt;

[0156] U16 nav_bit_cnt;

[0157] U16 req_cnt;

[0158] U16 vld_bit;

[0159] U16 fd_vld;

[0160] U16 trackI_th;

[0161] U16 lock_en;

[0162] U16 carry_lock;

[0163] U16 lock_cnt_optimistic;

[0164] U16 lock_cnt_pessimistic;

[0165] U16 State;

[0166] }STrackPara;

[0167] The storage space occupied by the STrackPara structure is 118 bytes.

[0168] Correspondingly, in the WUPSM-4A processor, in its external 32-bit RAM memory, 30 addresses will be allocated for each channel to store the above variables, and they will be arranged in the same order as the variables in the STrackPara structure. Therefore, for the 32-bit wide components of the S32 type in the above structure, the input and output instructions can be used directly for read and write access; for the 64-bit wide components of the S64 type in the above structure, the input and output instructions can be used to read and write access twice; for the 16-bit wide components of the S16 / U16 type in the above structure, the input instruction can be used for read access, but the outHB instruction can be used for write access. The data read into the register by the input instruction can be discarded and not used.

[0169] Another example: The phase discriminator function implemented on MicroBlaze is a C function based on the arc tangent lookup table as follows:

[0170]

[0171]

[0172]

[0173] Accordingly, when implementing the tracking co-processor based on WUPSM-4A, the program segments with equivalent functions are implemented using assembly code as follows:

[0174]

[0175]

[0176]

[0177]

[0178] During development and implementation, simulation and code verification can be used to verify that the functions to be implemented in the above code are consistent with the functions implemented by the C function GetPllDetec, and then other higher-level functions can be developed.

[0179] From the above comparison, we can see that when used to build a coprocessor for satellite navigation signal tracking, the WUPSM-4A processor can reach a level comparable to MicroBlaze in terms of resource usage and processing efficiency. Although the WUPSM-4A processor uses assembler to write software, the complexity of its application software development is also within an acceptable range. In addition, since the WUPSM-4A design is more streamlined and easier to run under high clock frequency conditions, it is more suitable for ASIC design.

[0180] Embodiment 3

[0181] The present invention also discloses a satellite navigation receiver, in which the satellite navigation baseband processing device optimized by the coprocessor as described in the above embodiment is adopted to perform satellite navigation baseband processing.

[0182] The specific technical details and beneficial effects in this embodiment are the same as those in the above embodiments. Please refer to them for details and will not be described in detail here.

[0183] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A coprocessor-optimized satellite navigation baseband processing device, characterized in that: It adopts the main processor + coprocessor architecture; The main processor is used for overall scheduling and satellite navigation information processing and is a wide-bit-width processor; The coprocessor is used to schedule hardware accelerated computing resources in real time under the switching control of the main processor, and to perform signal acquisition and tracking loop processing for satellite navigation. It is a narrow bit width coprocessor; Targeted optimization of the coprocessor's instruction set and external interface; expansion of the coprocessor bus width and internal storage width, retaining the original width of the coprocessor ALU and general registers; using external port access and internal storage access instructions that match the widened bus according to the expansion status to access and store bus data; using bus write enable, access instructions and storage instructions that match the widened internal storage width to access and store single register data; Satellite navigation baseband processing is performed through the cooperation of the optimized processor and the main processor.

2. The coprocessor-optimized satellite navigation baseband processing device according to claim 1, characterized in that: In the optimization of the coprocessor, the data bit width of the external bus is changed to twice the bit width of the internal basic register, the bit width of the internal ALU is kept the same as the bit width of the register, and the width of the internal storage is also changed to twice the width of the register; accordingly, the actual execution meaning of the two external port access instructions, input and output, and the two internal storage access instructions, fetch and store, are changed to operate on a group of two adjacent registers at the same time, and the execution meaning of other instructions remains unchanged; In the "Op Sx, kk" and "Op Sx, Sy" instructions, Op is one of Input, output, fetch, and store, and the operated registers include Sx and another register Sx' adjacent to Sx; when x is an even number, x'=x+1; when x is an odd number, x'=x-1.

3. The coprocessor-optimized satellite navigation baseband processing device according to claim 2, characterized in that: Change the bus write enable of the coprocessor's external bus to high and low 2 bits; add a new external port output instruction outHB in the instruction set; used to implement data access operations based on a single general register; The external port output instruction outHB includes two forms: "outHB Sx, kk" and "outHB Sx, Sy". The corresponding meaning is: only output the value of register Sx to the external port with the immediate value kk or the value of register Sy as the address; When x is an even number, the data corresponding to the outHB instruction is output to the lower half of the bus of the external port, and the write enable of the lower bit is valid at this time; When x is an odd number, the data corresponding to the outHB instruction is output to the high half of the bus of the external port, and the write enable of the high bit is valid at this time; When executing an output instruction that operates on a group of two adjacent registers at the same time, both the high and low 2-bit write enables are valid.

4. The coprocessor-optimized satellite navigation baseband processing device according to claim 3, characterized in that: In the instruction set, a new internal RAM data storage instruction storeHB is added to store single register data separately; The internal RAM data storage instruction storeHB includes two forms: "storeHB Sx, kk" and "storeHB Sx, Sy". The corresponding meaning is: only store the value of register Sx into the internal RAM storage, and the address is determined by the immediate value kk or the value of register Sy. When x is an even number, the data corresponding to the storeHB instruction is stored in the lower half of the address of the internal RAM; When x is an odd number, the data corresponding to the storeHB instruction is stored in the high half of the address of the internal RAM.

5. The coprocessor-optimized satellite navigation baseband processing device according to claim 4, characterized in that: The satellite navigation baseband processing device adopts a 1 main processor + 2 coprocessor architecture; The two coprocessors are the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A; The first coprocessor is a capture coprocessor, which is used for front-end signal processing of satellite navigation signal capture and executes the capture program. It is optimized using a PicoBlaze processor with an instruction data bit width of 8 bits. Through optimization, the capture coprocessor maintains the instruction data bit width of 8 bits and expands the bus data width to 16 bits. The second coprocessor is the tracking coprocessor, which is used for front-end signal processing of satellite navigation signal tracking and executes the tracking program. It is optimized using the PicoBlaze processor with an instruction data bit width of 16 bits. Through optimization, the instruction data bit width of the tracking coprocessor is expanded to 26 bits, and the bus data width is expanded to 32 bits.

6. The coprocessor-optimized satellite navigation baseband processing device according to claim 5, characterized in that: The first coprocessor has an instruction width of 18 bits, a bus width of 16 bits, and an ALU width of 8 bits. The processor has 16 8-bit registers numbered S0 to SF, and an internal memory width of 16 bits, with a depth that is configured based on demand. A single instruction is Instr[17:0], and the decoding method of each part is: Instr[17:14]----instruction main type; Instr[13:12]----instruction auxiliary type; Instr[11:10]----Whether the jump instruction depends on the Z, NZ, C, NC flags; Instr[11:8]----first operand; Instr[7:4]----the second operand; Instr[7:0]----immediate value; The external port of the first coprocessor includes the pin write_strobe[1:0]; the corresponding function and timing are described as follows: Write enable signal of external bus, single cycle, high effective; write_strobe[0] corresponds to writing the lower 8 bits; that is, out_port[7:0]; write_strobe[1] corresponds to writing the upper 8 bits; that is, out_port[15:8].

7. The coprocessor-optimized satellite navigation baseband processing device according to claim 5, characterized in that: The instruction bit width of the second coprocessor is 26 bits, the bus width is 32 bits, and the ALU bit width is 16 bits. The processor has 16 16-bit registers numbered S0 to SF, the internal memory bit width is 32 bits, and the depth is configured according to the requirements. The single instruction is Instr[25:0], and the decoding method of each part is: Instr[25:22]----instruction main type; Instr[21:20]----instruction auxiliary type; Instr[19:18]----Whether it depends on the Z, NZ, C, NC flags; Instr[19:16]----first operand; Instr[15:12]----the second operand; Instr[15:0]----immediate value; The external port of the second coprocessor includes the pin write_strobe[1:0]; the corresponding function and timing are described as follows: Write enable signal of external bus, single cycle, high effective; write_strobe[0] corresponds to writing the lower 16 bits; that is, out_port[15:0]; write_strobe[1] corresponds to writing the upper 16 bits; that is, out_port[31:16].

8. The coprocessor-optimized satellite navigation baseband processing device according to any one of claims 1 to 7, characterized in that: The satellite navigation baseband processing device is implemented on a Xilinx Zynq chip; The main processor of the satellite navigation baseband processing device is a dual-core ARM9 processor in the PS part of the Zynq chip; the first coprocessor and the second coprocessor are implemented in the PL part of the Zynq chip; both coprocessors exchange data with the main processor through dual-port RAM; The first coprocessor and the second coprocessor implement the coprocessing scheduling of the capture engine and the tracking engine respectively; Implement baseband processing of one acquisition channel and 36 tracking channels; Receive and process the Beidou B1 and B3 frequency signals and the GPS L1 frequency civil signal.

9. The coprocessor-optimized satellite navigation baseband processing device according to claim 8, characterized in that: The PL part of a single Zynq device is used to remove the remaining resources occupied by the first coprocessor and the second coprocessor to build an anti-interference module for performing anti-interference on the received satellite navigation signal to achieve array anti-interference processing of 4 array elements.

10. A satellite navigation receiver, characterized in that: The satellite navigation receiver adopts the satellite navigation baseband processing device optimized by the coprocessor as described in any one of claims 1 to 9 to perform satellite navigation baseband processing.

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