Storage array, memory, chip, and electronic device

Abstract

Provided in the embodiments of the present application are a storage array, a memory, a chip, and an electronic device. A storage array, comprising: a substrate; a plurality of word lines, a plurality of bit lines and a plurality of back gate lines, which are disposed on the substrate; and a plurality of storage units distributed in an array, wherein each storage unit is in contact with a word line, a bit line and a back gate line; each storage unit comprises a dual-gate transistor and a capacitor, wherein the dual-gate transistor comprises a first gate electrode, a second gate electrode, a first pole, a second pole and a channel, the channel being made of an oxide semiconductor (OS), and the dual-gate transistor is a planar transistor; and the first gate electrode of each storage unit is connected to the corresponding word line, the second gate electrode thereof is connected to the corresponding back gate line, the first pole thereof is connected to the corresponding bit line, the second pole thereof is connected to one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected to a direct-current bias. By means of implementing the embodiments of the present application, the deviation of a threshold voltage Vt of a prepared OS transistor can be reduced, thereby improving the storage performance.

Description

Storage array, memory, chip and electronic device

[0001] This application claims priority to the Chinese patent application with application number 202310970253.0 filed with the State Intellectual Property Office of China on August 2, 2023, and priority to the Chinese patent application with the invention name “A storage array, memory and electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of memory technology, and in particular to a memory array, a memory, a chip, and an electronic device. Background Art

[0003] Volatile memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM), loses its stored information when the current or voltage is interrupted. DRAM offers advantages such as a simple structure, low manufacturing cost, and high capacity density. With technological advancements, DRAM is becoming increasingly popular.

[0004] Current DRAM is mainly based on a 1-transistor-1-capacitor (1T1C) storage structure. As the process size of DRAM gradually shrinks and to avoid the row-hammer characteristics of front-end transistors, current DRAM often chooses transistors with oxide semiconductor (OS) as the channel material. The OS transistor can be based on the characteristics of being row-hammer free, having extremely low off-state current, and being able to achieve back-end integration. It is very suitable as a transistor in the current DRAM storage structure, so as to further reduce the process size of DRAM. However, for the preparation process of OS transistors, due to the influence of the preparation process temperature during the preparation process, the conductive properties of the channel material will change, thereby causing the threshold voltage V of the OS transistor after preparation to change. t Deviations also occur, thereby reducing the sensing margin of the sense amplifier circuit used to amplify the signal in the DRAM, resulting in a decrease in storage performance.

[0005] Therefore, how to reduce the threshold voltage V of the OS transistor after fabrication? t To reduce the deviation and improve the storage performance of memory chips is a technical problem that needs to be solved urgently.

[0006] Summary of the Invention

[0007] The present invention provides a memory array, a memory, a chip and an electronic device to reduce the threshold voltage V of the prepared OS transistor. t deviation, thereby improving the storage performance of the memory chip.

[0008] In the first aspect, an embodiment of the present application provides a memory array, comprising: a substrate, a plurality of word lines, a plurality of bit lines, a plurality of back gate lines and a plurality of memory cells distributed in an array arranged on the substrate; each of the memory cells is in contact with one of the word lines, one of the bit lines and one of the back gate lines; each of the memory cells comprises a dual-gate transistor and a capacitor, the dual-gate transistor comprises a first gate, a second gate, a first electrode, a second electrode and a channel, the material forming the channel is an oxide semiconductor OS, and the dual-gate transistor is a planar transistor; wherein the first gate in each of the memory cells is connected to the corresponding word line, the second gate is connected to the corresponding back gate line, the first electrode is connected to the corresponding bit line, the second electrode is connected to one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected to a DC bias.

[0009] The OS transistor of the 1T1C memory cell in the current memory array (i.e., the transistor whose channel material is oxide semiconductor OS) is easily affected by the high process temperature during the preparation process, which may cause the conductive properties of the channel of the OS transistor to change, resulting in a threshold voltage V corresponding to the prepared OS transistor. t Deviations (e.g., increases or decreases) occur, thereby reducing the storage performance of the memory array. In this regard, an embodiment of the present application provides a memory array in which the OS transistor of the 1T1C memory cell is a dual-gate transistor. The back gate (i.e., the second gate) of the dual-gate transistor can receive a voltage signal (e.g., a back gate drive voltage). By regulating the voltage applied to the back gate of the dual-gate transistor, the threshold voltage V of the dual-gate transistor is adjusted. t, so that the threshold voltage that has deviated is restored to the preset threshold voltage, thereby improving the sensing margin of the sense amplifier SA in the peripheral circuit and improving the storage performance of the memory array. Specifically, each 1T1C memory cell (i.e., a memory cell including a dual-gate transistor and a capacitor) will be in contact with one of the word lines, one of the bit lines, and one of the back-gate lines. The first gate of the dual-gate transistor can be connected to the corresponding word line, the second gate can be connected to the corresponding back-gate line, the first electrode can be connected to the corresponding bit line, and the second electrode can be connected to an electrode of the capacitor. The first electrode can be a drain, and the corresponding second electrode can be a source; the first electrode can also be a source, and the corresponding second electrode can be a drain. The capacitor includes two electrodes, one of which is connected to the second electrode of the dual-gate transistor, and the other electrode can be grounded or connected to a DC bias. During the storage process, the second gate can receive a back-gate drive voltage through the corresponding back-gate line to adjust the threshold voltage of the dual-gate transistor. Furthermore, the first gate can control the conduction or shutdown of the dual-gate transistor through the voltage signal received from the corresponding word line to achieve data storage. This method of adjusting the threshold voltage of the OS transistor by applying a voltage to the second gate ensures that the threshold voltage of the OS transistor does not deviate during storage, thereby ensuring the storage efficiency of the memory array during the storage process. In addition, because the dual-gate transistor is a planar transistor, it is smaller and easier to integrate than the trench transistors used in some embodiments, and does not suffer from severe row-hammer characteristics, it can reduce the probability of device misoperation, which is conducive to further improving the storage performance of the memory array.

[0010] In a possible implementation, the plurality of back gate lines correspond to the plurality of word lines one by one, and each back gate line is arranged in parallel with each word line, and each back gate line is arranged perpendicular to each bit line.

[0011] In an embodiment of the present application, a simple and efficient arrangement structure is provided, in which multiple back gate lines and multiple word lines in a memory array are arranged in parallel in a one-to-one correspondence, which can better electrically connect with the dual-gate transistors in the memory cells to ensure the storage performance of the memory array.

[0012] In one possible implementation, in a direction perpendicular to the substrate, the multiple back gate lines and the multiple word lines are respectively located on the upper and lower sides of the channel; wherein, a first gate oxide dielectric layer is arranged between each of the back gate lines and the channel, and a second gate oxide dielectric layer is arranged between each of the word lines and the channel.

[0013] In an embodiment of the present application, multiple back gate lines and multiple word lines can be located on the upper and lower sides of the channel, respectively. For example, a back gate line can be located above the channel and a word line can be located below the channel; or a back gate line can be located below the channel and a corresponding word line can be located above the channel. In addition, a first gate oxide dielectric layer is located between each back gate line and the channel, and a second gate oxide dielectric layer is located between each word line and the channel. These layers can isolate the back gate lines and word lines from the channel, preventing leakage and thereby ensuring the storage performance of the memory array.

[0014] In a possible implementation, one end of each of the back gate lines is electrically connected via a back gate control line, the back gate control line is used to receive a back gate driving voltage, and the back gate control line is arranged in parallel with each of the bit lines.

[0015] In an embodiment of the present application, a back-gate control line is connected at the side of the memory array, for example, at one end of multiple back-gate lines, to receive a back-gate drive voltage, thereby adjusting the threshold voltage of the dual-gate transistor. Furthermore, connecting all back-gate lines at the side of the memory array simplifies the manufacturing process and reduces the difficulty of manufacturing the memory array.

[0016] In a possible implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located above the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0017] In an embodiment of the present application, multiple bit lines are located above the channel, and also above multiple back gate lines and multiple word lines. The bit line contact portion of each bit line can electrically connect the bit line to the channel. The bit line contact portion can be regarded as the first electrode of the dual-gate transistor. The material forming the bit line contact portion can be the same as or different from the material of the bit line.

[0018] In a possible implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located below the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0019] In the embodiments of the present application, multiple bit lines are located below the channel, as well as below multiple back-gate lines and multiple word lines. A bit line contact portion of each bit line electrically connects the bit line to the channel. This bit line contact portion can be considered the first electrode of a dual-gate transistor. The material forming the bit line contact portion can be the same as or different from that of the bit line. Furthermore, when the bit line is located below the channel, the structure between the channel and the capacitor can be made smaller, thereby making the memory array smaller and easier to integrate, thereby increasing storage density.

[0020] In a possible implementation, in a direction perpendicular to the substrate, the channel is upwardly connected to the capacitor through a storage node contact SNC.

[0021] In an embodiment of the present application, the channel is connected upward to the capacitor through a storage node contact SNC. The storage node contact SNC can be regarded as the second electrode of the dual-gate transistor. The material forming the storage node contact SNC can be the same as or different from the material of the bit line contact.

[0022] In a possible implementation, the material of the plurality of back gate lines includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu, or aluminum Al.

[0023] In the embodiment of the present application, the material of the back gate line includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu or aluminum Al to facilitate electrical connection of the dual-gate transistor. In addition, the material of the back gate line can be the same as or different from the material of the second gate of the dual-gate transistor.

[0024] In a second aspect, an embodiment of the present application provides a memory, comprising a controller and a storage array as described in any one of the first aspects above, wherein the controller is connected to the storage array, and the controller is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

[0025] In an embodiment of the present application, the memory includes a controller and a memory array connected to the controller, and the controller can be used to send read and write instructions to the memory array to instruct the memory array to perform read and write operations. Among them, the channel in the memory cell of the memory array is an oxide semiconductor. Based on the characteristics of row-hammer free, extremely low off-state current, and the ability to achieve back-end integration, the process size of the memory can be further reduced and the storage performance of the memory can be improved. Moreover, since the transistors in the memory cells of the memory array are dual-gate transistors, they can be adjusted when the threshold voltage deviates to ensure the storage performance of the memory.

[0026] In a possible implementation, the controller includes a back-gate driving circuit; the back-gate driving circuit is configured to output a back-gate driving voltage to all back-gate lines in the memory array through a back-gate control line.

[0027] In an embodiment of the present application, the controller includes a back-gate drive circuit so that during the storage process, the back-gate drive circuit outputs a back-gate drive voltage to all back-gate lines in the storage array through a back-gate control line to adjust the threshold voltage of the dual-gate transistor. Furthermore, the storage unit can control the conduction or shutdown of the dual-gate transistor through the voltage signal received by the corresponding word line to realize data storage.

[0028] In a possible implementation, the back gate driving circuit is disposed below the memory array in a direction perpendicular to a substrate in the memory array.

[0029] In an embodiment of the present application, the back gate drive circuit is arranged below the memory array, for example, it can be arranged between the sensor amplifier circuit and the memory array. This arrangement can realize the voltage adjustment of the second gate when the memory is working without increasing the memory process size, greatly reducing the area overhead of the back gate drive circuit and further improving the storage density.

[0030] In a third aspect, an embodiment of the present application provides a chip, characterized in that it includes a control circuit and a storage array as described in any one of the first aspects above, the control circuit is connected to the storage array, the control circuit is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

[0031] In a fourth aspect, an embodiment of the present application provides an electronic device, characterized in that the electronic device comprises: a circuit board and a memory as described in any one of the items involved in the first aspect above; the circuit board is electrically connected to the memory.

[0032] It should be understood that the chip provided in the third aspect and the electronic device provided in the fourth aspect of this application are consistent with the technical solution of the first aspect of this application. Their specific content and beneficial effects can be referred to the storage array provided in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0034] FIG1 is a schematic diagram of a storage structure of a 1T1C storage unit provided in an embodiment of the present application.

[0035] FIG2 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

[0036] FIG3 is a schematic diagram of the structure of a memory provided in an embodiment of the present application.

[0037] FIG4 is a schematic diagram of a circuit structure of a back gate driving circuit provided in an embodiment of the present application.

[0038] 5A and 5B are schematic structural diagrams of a group of storage arrays provided in an embodiment of the present application.

[0039] FIG6 is a schematic structural diagram of a storage unit provided in an embodiment of the present application.

[0040] FIG7 is a schematic diagram of a method for adjusting a back gate voltage according to an embodiment of the present application.

[0041] FIG8 is a schematic structural diagram of another storage unit provided in an embodiment of the present application.

[0042] 9 and 10 are schematic diagrams of a method for preparing a storage array according to an embodiment of the present application.

[0043] Explanation of the accompanying symbols: 200 electronic device, 205 bus, 210 system on chip, 211 application processor, 212 image processing unit, 213 first random access memory, 220 second random access memory, 230 communication chip, 240 power management chip; 300 memory, 400 storage unit, 310 storage array, 320 controller, 3201 sensor amplifier circuit, 3202 decoder, 3203 word line drive circuit, 3204 back gate drive circuit, 3205 timing controller; one end of the P1 switch tube, the other end of the P2 switch tube; T dual-gate transistor, G1 first gate, G2 second gate, K1 first electrode, K2 second electrode, C capacitor; WL, WL1, WL2 and WL3 word lines, BL, BL1, BL2 and BL3 bit lines, BGL, BGL1, BGL2 and BGL3 back gate lines; 600 substrate, 601 channel, 602 back gate line, 603 word line, 604 first gate oxide dielectric layer, 605 second gate oxide dielectric layer, 606 dielectric material layer, 607 bit line, 608 bit line contact portion, 609 storage node contact portion. DETAILED DESCRIPTION

[0044] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0045] The terms "first," "second," and the like in the specification, claims, and accompanying drawings of this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0046] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0047] For ease of description, embodiments of the present application may use spatial relationship terms such as "under", "below", "below", "below", "above", "on", etc. to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation, in addition to the directions depicted in the drawings. For example, if the device in the drawings is turned over, the direction of the element described as "under" or "below" or "below" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both the up and down directions. The device may also have other orientations (rotated 90 degrees or in other directions), so the spatial relationship descriptors used here should be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more layers between them.

[0048] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0049] First, in order to facilitate understanding of the embodiments of the present application, the technical problems that need to be solved by the embodiments of the present application are analyzed in detail below.

[0050] Memory can be categorized by volatility into volatile memory and non-volatile memory. Volatile memory, for example, loses its stored information when the current or voltage is interrupted. Examples include common dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM has the advantages of a simpler structure, lower manufacturing costs, and higher capacity density. With technological advancements, DRAM is becoming increasingly widely used.

[0051] The memory cells in current DRAM memory arrays are mainly based on a 1-transistor-1-capacitor (1T1C) memory structure, and due to the difference in the channel, this memory structure is often divided into two types. In one memory structure, the transistor of the 1T1C memory cell is a recessed channel, and the channel material is silicon. This memory structure uses a buried word line method to set the word line, wherein the gate of the transistor is connected to the word line, and the drain and source of the transistor are connected to the bottom electrode of the capacitor and the bit line (BL) through a storage node contact (SNC) and a bit line contact (BLC), respectively. However, due to the need to limit the size of the memory, peripheral circuits cannot be placed under the memory array formed by this memory structure, and the array efficiency of the memory cannot be further improved. In addition, the transistors in this memory structure are front-end transistors, which have serious row-hammer characteristics, making the device prone to malfunction.

[0052] In this regard, another storage structure is also provided in some embodiments. Please refer to Figure 1. Figure 1 is a schematic diagram of the storage structure of a 1T1C storage unit provided in an embodiment of the present application. The transistor of the 1T1C storage unit in this storage structure is a back-end transistor, and its channel material is an oxide semiconductor (OS), and the bit line BL and word line WL in the storage structure are respectively located above and below the OS channel. The gate of the transistor is connected to the above-mentioned word line, and the drain and source of the transistor are connected to the bottom electrode and bit line (BL) of the capacitor through a storage node contact (SNC) and a bit line contact (BLC), respectively. Moreover, the transistor is a back-end transistor and does not have a serious Row-hammer characteristic, which can reduce the probability of the device being misoperated. However, the storage array composed of this storage structure is prone to changes in the conductive properties of the oxide semiconductor channel of the prepared transistor due to the presence of a high process temperature (Thermal) during the process preparation, which in turn causes the threshold voltage V t Deviation occurs, which reduces the sensing margin of the sensing amplifier circuit (Sensing Amplifier, SA) used to amplify the signal in the DRAM. That is, due to the threshold voltage V t Deviations may cause the voltage applied to the transistor gate to fail to reach the transistor's turn-on voltage in time during the period when the SA circuit is in the working state under the control of the timing signal, causing the transistor to remain in the off state. The transistor is turned on only after the turn-on voltage is reached, causing the sensor amplifier circuit to receive or read fewer valid electrical signals under the original timing control, and thus unable to amplify the electrical signal well (such as amplifying it to 1 or 0), resulting in storage errors and reduced storage performance.

[0053] In this regard, embodiments of the present application provide a memory array, a memory, and an electronic device. In one embodiment, the OS transistor (wherein the OS transistor is a transistor whose channel material is an oxide semiconductor) of a 1T1C memory cell in a memory array is a dual-gate transistor, and the back gate of the dual-gate transistor can receive a back gate drive voltage when the memory array is operating or detecting, so as to adjust the threshold voltage V of the prepared OS transistor. t , thereby improving the Sensing Margin read by the sense amplifier circuit. This method reduces the threshold voltage V of the OS transistor after fabrication by adjusting the voltage of the back gate in the dual-gate transistor. t The deviation method can improve the storage performance of the memory chip using the memory array. The specific implementation method can also refer to the relevant description of the following embodiments, and the embodiments of this application are not described here.

[0054] Secondly, based on the technical problems raised above and to facilitate understanding of the embodiments of the present application, one of the electronic devices on which the embodiments of the present application are based is described below.

[0055] Please refer to FIG2 , which is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

[0056] As shown in Figure 2, the electronic device 200 can be a terminal device that needs to store data, such as a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer, a vehicle-mounted device, a wearable device, augmented reality (AR) glasses, an AR helmet, virtual reality (VR) glasses or a VR helmet, etc., which need to store data. The embodiments of the present application do not impose any specific restrictions on the specific form of the electronic device.

[0057] The electronic device 200 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205. The SoC 210 may be used to process data, for example, process application data, process image data, and cache temporary data.

[0058] In some embodiments, SoC 210 may include an application processor (AP) 211 for processing application programs, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching data.

[0059] The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (EFlash), etc. The AP 211 , GPU 212 and the first RAM 213 may be integrated into one die or may be separately provided in multiple dies.

[0060] In addition, in some embodiments, the first RAM 213 may include a memory array, which includes: a substrate, a plurality of word lines, a plurality of bit lines, a plurality of back gate lines, and a plurality of memory cells distributed in an array, each memory cell being in contact with a word line, a bit line, and a back gate line; each memory cell includes a dual-gate transistor and a capacitor, the dual-gate transistor including a first gate, a second gate, a first electrode, a second electrode, and a channel, the material forming the channel being an oxide semiconductor OS, and the dual-gate transistor being a planar transistor; wherein the first gate in each memory cell is connected to the corresponding word line, the second gate is connected to the corresponding back gate line, the first electrode is connected to the corresponding bit line, the second electrode is connected to one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected to a DC bias. Implementing the embodiments of the present application can reduce the threshold voltage V of the OS transistor after preparation. t The deviation is reduced to improve the storage performance of the storage array. The specific implementation of the storage array can also refer to the following related embodiments, and the embodiments of the present application are not described here in detail.

[0061] The electronic device 200 may further include a second RAM 220 connected to the SOC 210 via the bus 205. The second RAM 220 may be a dynamic random access memory. The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. Furthermore, the second RAM 220 may also include the storage array mentioned above in the first RAM 213.

[0062] In addition, electronic device 200 may also include a communication chip 230 and a power management chip 240 connected to SOC 210 via bus 205. Communication chip 230 can be used for protocol stack processing, or for amplifying and filtering analog RF signals, or for performing the above functions simultaneously. Power management chip 240 can be used to power other chips.

[0063] The electronic device 200 may further include a printed circuit board (PCB), which is not shown in the figure. The PCB may encapsulate one or more of the above-mentioned packaging structures, such as the SOC 210 and the second RAM 220 , etc. The packaging structure may be electrically connected to the PCB.

[0064] In one embodiment, the SOC 210 and the second RAM 220 can be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve a faster inter-chip data transfer rate. The SOC 210 and the second RAM 220 can also be packaged in different package structures, which is not specifically limited in this embodiment of the present application.

[0065] In another embodiment, the electronic device may further include other discrete components, which is not specifically limited in the embodiment of the present application.

[0066] It should be noted that the structure of the electronic device in FIG. 2 is only an exemplary implementation in the embodiment of the present application. The electronic devices in the embodiment of the present application include but are not limited to the above electronic devices.

[0067] Please refer to FIG3 , which is a schematic diagram of the structure of a memory provided in an embodiment of the present application.

[0068] As shown in Figure 3, the memory 300 may be the first RAM 213 shown in Figure 2, or the second RAM 220 shown in Figure 2. The embodiment of the present application does not limit the application scenario of the memory 300.

[0069] As shown in Figure 3, the memory 300 includes a memory array 310 and a controller 320. The controller 320 may be electrically connected to the memory array 310 and configured to send read and write instructions to the memory array 310. The read and write instructions are configured to instruct the memory array to perform read and write operations.

[0070] In one embodiment, the memory array 310 includes a plurality of memory cells 400 arranged in an array, wherein each memory cell 400 can be used to store 1 bit (bit) or multiple bits of data, and each memory cell includes a dual-gate transistor and a capacitor, and the dual-gate transistor is a planar transistor. In the memory cell of the 1T1C structure, when the capacitor is full of positive charge, it is represented as 1; otherwise, it is 0. The memory array 310 may also include a plurality of word lines (WL), a plurality of bit lines (BL) and a plurality of back gate lines (BGL). Each of the memory cells is in contact with a word line WL, a bit line BL and a back gate line BGL. Different memory cells 400 may also be electrically connected through word lines WL, bit lines BL or back gate lines BGL.

[0071] One or more of the above-mentioned word lines WL and bit lines BL can receive the control level or control signal (equivalent to the read and write instruction) output by the controller 320, select the storage cell 400 to be read and written in the storage array, so as to change the charge on the capacitor in the storage cell 400, thereby realizing the read and write operation of the data. One or more of the above-mentioned back gate lines BGL can be used to adjust the threshold voltage of the transistor in the corresponding storage cell to be read and written by receiving the back gate drive voltage output by the controller 320 to ensure the success rate of the read and write operation. Among them, the specific implementation method of the storage array can also refer to the following related embodiments, and the embodiments of the present application will not be repeated here. In addition, for convenience, the embodiments of the present application refer to the above-mentioned WL, BL and BGL as signal lines.

[0072] The controller 320 can be used to output control levels or control signals to the above-mentioned multiple word lines WL and multiple bit lines BL to control the storage array to read and write data. It can also output back gate drive voltages to the above-mentioned multiple back gate lines BGL to adjust the threshold voltages of transistors in the storage cells to ensure the success rate of read and write operations.

[0073] In one embodiment, the controller 320 may be referred to as a peripheral control circuit and may be disposed around the memory array 310 (as shown in (1) in FIG3 ). The memory array 310 and the controller may be integrated into a single chip or may be integrated into multiple chips.

[0074] As shown in (2) of FIG. 3 , the controller 320 may include one or more circuit structures selected from the group consisting of a sensor amplifier circuit 3201 , a decoder 3202 , a word line driver circuit 3203 , a back gate driver circuit 3204 , and a timing controller 3205 .

[0075] The sensor amplifier (SA) 3201 can be connected to the capacitor in the storage unit 400 and can be used to amplify the electrical signal in the capacitor. For example, it can amplify positive charges to "1" and negative charges to "0" to correspond to the 1 and 0 stored in the storage unit. This sensor amplifier circuit can be located above and / or below the storage array 310.

[0076] The decoder 3202 can be used to decode the address of the storage unit 400. The decoder 3202 is used to decode the received address to determine the storage unit 400 to be accessed.

[0077] The sub word line driver (SWD) 3203 may be used to control the level of the signal line according to the decoding result generated by the decoder 3202 , thereby enabling access to the designated memory cell 400 .

[0078] The back gate driver (BGD) 3204 can be used to output a back gate drive voltage to all back gate lines in the memory array via signal lines, for example, to correct the threshold voltage of a specified memory cell 400 based on the decoding result generated by the decoder 3202 .

[0079] The word line driving circuit 3203 and the back gate driving circuit 3204 may be integrated into one structure, for example, integrated into a driver, or may be integrated into multiple structures respectively, which is not specifically limited in the embodiment of the present application.

[0080] The timing controller 3205 can be used to control the word line driving circuit 3203 and the back gate driving circuit 3204 to drive the signal lines in the memory array 310 to realize data reading and writing.

[0081] The controller 320 may further include an input / output driver (not shown), which may be used to drive transmission signals, for example, to drive received data signals and to drive data signals to be sent, so that the data signals may be transmitted over long distances.

[0082] The controller 320 may also include a buffer (not shown) for caching the read data before reading and writing the data. For example, a FIFO (first-in first-out) buffer may be used. In addition, the timing controller 3205 may also be used to control the timing of the buffer.

[0083] It should be noted that the memory structure in FIG. 3 is only an exemplary implementation in the embodiment of the present application. The memory structure in the embodiment of the present application includes but is not limited to the above memory structure.

[0084] In addition, as shown in (1) of FIG3 , the back gate driver circuit 3204 can be placed below or above the memory array 310, such as between the sensor amplifier circuit 3201 and the memory array 310. Alternatively, the back gate driver circuit 3204 can be placed in the corners around the memory array 310, such as the switch corner (SWC) region shown in the figure.

[0085] In one embodiment, the back-gate driver circuit 3204 can be disposed below the memory array 310 in a direction perpendicular to the substrate of the memory array 310. Furthermore, the back-gate driver circuit 3204 can be disposed below the memory array 310 and above the sensor amplifier circuit 3201. For example, the back-gate driver circuit 3204 can be disposed between the sensor amplifier circuit 3201 and the memory array 310. This arrangement allows for voltage regulation of the second gate during memory operation without increasing the memory process size, significantly reducing the area overhead of the back-gate driver circuit and further improving storage density.

[0086] In another embodiment, please refer to FIG4 , which is a schematic diagram of the circuit structure of a backgate drive circuit provided in an embodiment of the present application. As shown in FIG4 , the backgate drive circuit 3204 may include a switch tube, which includes a control terminal VBGEn. The control terminal VBGEn can be connected to a timing controller 3205 or other control circuit to control the conduction or shutdown of the switch tube. One terminal P1 of the switch tube can be connected to a backgate control line in the memory array 310 to control multiple backgate lines; the other terminal P2 of the switch tube can be connected to a power supply signal VBG, thereby enabling voltage regulation during device testing or operation.

[0087] It should be noted that the switch tube can be an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a P-type MOS tube.

[0088] It should also be noted that one end P1 of the switch tube can be a source, and the other end P2 of the corresponding switch tube can be a drain. Alternatively, one end P1 of the switch tube can be a drain, and the other end P2 of the corresponding switch tube can be a source.

[0089] It should be understood that the storage array involved in the electronic device or memory provided in the embodiments shown in Figures 2 to 4 above is consistent with the storage array involved in the relevant embodiments shown in Figures 5A to 8 below. The specific content and beneficial effects thereof can be referred to the storage array involved in the relevant embodiments shown in Figures 5A to 8 below, and will not be repeated here.

[0090] Based on the electronic device or memory provided in the embodiments shown in FIG. 2 to FIG. 4 , the embodiments of the present application provide an exemplary description of a storage array in the electronic device or memory.

[0091] Please refer to Figures 5A and 5B, which are schematic structural diagrams of a group of storage arrays provided in an embodiment of the present application.

[0092] As shown in FIG5A , the memory array 310 includes: a substrate (not shown) and a plurality of word lines WL, a plurality of bit lines BL, a plurality of back gate lines BGL, and a plurality of memory cells 400 arranged in an array on the substrate. Each memory cell 400 is in contact with a word line WL, a bit line BL, and a back gate line BGL. The memory array 310 may be the memory array 310 mentioned in the above-mentioned related embodiments, and the memory cells 400 may also be the memory cells 400 mentioned in the above-mentioned related embodiments. For example, the plurality of word lines WL include word lines WL1, WL2, and WL3 as shown in FIG5A , the plurality of bit lines BL include bit lines BL1, BL2, and BL3 as shown in FIG5A , and the plurality of back gate lines BGL include back gate lines BGL1, BGL2, and BGL3 as shown in FIG5A .

[0093] In addition, the substrate is used to carry or support a plurality of word lines WL, a plurality of bit lines BL, a plurality of back gate lines BGL and a plurality of memory cells 400 distributed in an array stacked on the substrate, wherein the stacking order between the plurality of word lines WL, the plurality of bit lines BL, the plurality of back gate lines BGL and the plurality of memory cells 400 distributed in an array is not fixed and can be set accordingly. For example, the substrate can be a single-layer structure. In this case, the material constituting the substrate can include semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the material constituting the substrate can include non-conductive materials such as glass, plastic or sapphire, etc. For another example, the above-mentioned substrate can also be a multi-layer structure. Among them, the layer farthest away from the stacked structure on the substrate can be made of the above-mentioned semiconductor material or non-conductive material, and the remaining film layers can be patterned as needed to form other circuit structures.

[0094] It should be noted that the above-mentioned patterning process may include a photolithography process, or a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing and inkjet. The corresponding patterning process can be selected according to the structure formed in the embodiments of this application, and the embodiments of this application do not specifically limit this. The above-mentioned photolithography process refers to a process for forming a pattern using a photoresist, a mask, an exposure machine, etc., including process processes such as film formation, exposure, and development.

[0095] As shown in Figure 5B, each memory cell 400 includes a dual-gate transistor T and a capacitor C. The dual-gate transistor T is a planar transistor, including a first gate G1, a second gate G2, a first electrode K1, a second electrode K2 and a channel (not shown). The material forming the channel is an oxide semiconductor OS. Exemplarily, the oxide semiconductor material can be one of indium gallium zinc oxide IGZO, intergranular oxide IGO, and indium zinc oxide IZO. The embodiment of the present application specifically limits the type of oxide semiconductor material.

[0096] As shown in FIG5B , the first gate G1 in each memory cell 400 is connected to the corresponding word line WL, the second gate G2 is connected to the corresponding back gate line BGL, the first electrode K1 is connected to the corresponding bit line BL, the second electrode K2 is connected to one electrode of the capacitor C, and the other electrode of the capacitor C is grounded or connected to a DC bias. The magnitude of the DC bias can be all or part of the power supply voltage. During the storage process, the first gate G1 can control the conduction or shutdown of the dual-gate transistor T through the voltage signal received by the corresponding word line WL to achieve data storage. At the same time, the second gate G2 can receive the back gate drive voltage through the corresponding back gate line BGL to adjust the threshold voltage of the dual-gate transistor to ensure that the dual-gate transistor T can be normally turned on after the control signal or control voltage is applied to the first gate G1, thereby improving the storage performance of the memory array 310. This method of adjusting the threshold voltage of the OS dual-gate transistor by applying a voltage to the second gate G2 can minimize the deviation between the threshold voltage corresponding to the dual-gate transistor T in the working state and the preset threshold voltage, thereby avoiding the impact of the process preparation process on the performance of the devices in the memory array, thereby improving the storage performance of the memory array 310.

[0097] In addition, since the dual-gate transistor is a planar transistor, it is smaller in size and easier to integrate than the trench transistor in some embodiments, and does not have serious Row-hammer characteristics, it can reduce the probability of device misoperation, which is conducive to further improving the storage performance of the storage array.

[0098] It should be noted that the first electrode K1 of the dual-gate transistor T in each memory cell 400 may be a source electrode, and the corresponding second electrode K2 may be a drain electrode. Alternatively, the first electrode K1 of the dual-gate transistor T in each memory cell 400 may be a drain electrode, and the corresponding second electrode K2 may be a source electrode. In addition, the dual-gate transistor T in each memory cell 400 may be an N-type MOS transistor or a P-type MOS transistor, which is not specifically limited in this embodiment of the present application.

[0099] In other embodiments, the connection relationship between the first gate G1 and the second gate G2 of the dual-gate transistor T in each storage unit 400 can be interchangeable, for example: the first gate G1 is connected to the corresponding back gate line BGL, and the second gate G2 is connected to the corresponding word line WL. This embodiment of the present application does not specifically limit this.

[0100] It should also be noted that the embodiment of the present application does not impose any specific restrictions on the type of capacitor in each storage unit 400. For example, the capacitor may be a stacked capacitor.

[0101] In one implementation, the plurality of back gate lines correspond to the plurality of word lines one by one, and each back gate line is arranged in parallel with each word line, and each back gate line is arranged perpendicularly with each bit line.

[0102] As shown in FIG5A above, the embodiment of the present application provides a simple and efficient arrangement structure, in which the multiple back gate lines BGL and the multiple word lines WL in the memory array 310 are arranged in parallel in a one-to-one correspondence, which can better electrically connect with the dual-gate transistor T in the memory cell 400 to ensure the storage performance of the memory array.

[0103] In one implementation, in a direction perpendicular to the substrate, the multiple back gate lines and the multiple word lines are respectively located on the upper and lower sides of the channel; wherein, a first gate oxide dielectric layer is arranged between each of the back gate lines and the channel, and a second gate oxide dielectric layer is arranged between each of the word lines and the channel.

[0104] Please refer to Figure 6, which is a schematic diagram of the structure of a storage unit provided in an embodiment of the present application. To facilitate the following description, an X, Y, and Z coordinate system is established in Figure 6, which is also applicable to the relevant embodiments of the above or following figures. As shown in Figure 6, the plane where the substrate 600 is located can be an XY plane. Taking the substrate 600 shown in Figure 6 as a rectangle as an example, the X-axis can be the length direction of the substrate 600, the Y-axis can be the width direction of the substrate 600, and the Z-axis is a direction perpendicular to or approximately perpendicular to the substrate 600 within the manufacturing tolerance range.

[0105] As shown in FIG6 , in a direction perpendicular to the substrate 600 (the Z-axis direction), a plurality of back gate lines BGL and a plurality of word lines WL may be located on the upper and lower sides of a channel 601, respectively. For example, a back gate line 602 is located above the channel 601, and a word line 603 is located below the channel 601. A first gate oxide dielectric layer 604 is located between the back gate line 602 and the channel 601, and a second gate oxide dielectric layer 605 is provided between the word line 603 and the channel 601.

[0106] In addition, in other embodiments, the back gate line 602 and the first gate oxide dielectric layer 604 may be located below the channel 601, and the corresponding word line 603 and the second gate oxide dielectric layer 605 may be located above the channel 601. This embodiment of the present application does not make any specific limitations on this.

[0107] Among them, the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 can also be called gate insulating film layers (Gate insulator, GI). The first gate oxide dielectric layer 604 can be used to insulate the back gate line 602 and the channel 601, and the second gate oxide dielectric layer 605 can be used to insulate the word line 603 and the channel 601, isolating the back gate line and the word line from the channel to prevent leakage, so as to ensure the storage performance of the storage array 310.

[0108] It should be noted that the materials of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 may be the same or different. For example, the materials of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 may both be silicon carbon nitride (SiCN), hafnium oxide (HfO2), etc. This embodiment of the present application does not specifically limit this.

[0109] In addition, the thickness of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 in a direction perpendicular to the substrate 600 is not specifically limited in this embodiment of the present application. For example, the thickness of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 can be between 2 and 10 nm. The width of the first gate oxide dielectric layer 604 in a direction parallel to the substrate is consistent with the corresponding back gate line 602 and can be between 40 and 200 nm. This embodiment of the present application does not specifically limit this. The width of the second gate oxide dielectric layer 605 in a direction parallel to the substrate 600 (such as the X-axis direction) is consistent with the corresponding word line 603 and can be between 40 and 200 nm. This embodiment of the present application does not specifically limit this.

[0110] It should also be noted that, in order to better illustrate the structure of the storage unit 400, the channel 601 is a rectangular parallelepiped generally parallel to the surface of the substrate 600 in the figure, but there is an angle with both the X-axis direction and the Y-axis direction. For example, the channel 601 is located on the diagonal line of the substrate in the X-axis direction and the Y-axis direction. The embodiments of the present application do not make specific limitations on this.

[0111] It should also be noted that, in order to better support and isolate the various structures within the memory cell 400, the memory cell 400 further includes a dielectric material layer 606. The dielectric material layer 606 is used to fill the gaps between the various structures within the memory cell 400 and to isolate the various semiconductor structures. The material of the dielectric material layer 606 can be an insulating material, such as silicon oxide.

[0112] In one implementation, one end of each of the back gate lines is electrically connected via a back gate control line, the back gate control line is used to receive a back gate driving voltage, and the back gate control line is arranged in parallel with each of the bit lines.

[0113] As shown in above-mentioned Fig. 5 A, in the side of storage array 310, one end of each described back gate line can be electrically connected by back gate control line, and described back gate control line is used to receive back gate drive voltage, and on the direction (as Y-axis direction) parallel to substrate, is arranged in parallel between described back gate control line and each described bit line.All back gate lines are connected with back gate control line at one end of multiple back gate lines, receive back gate drive voltage, can realize the threshold voltage of regulating this dual-gate transistor.And connect all back gate lines in the side of storage array, can make preparation technology easier, reduce the preparation difficulty of storage array.

[0114] Please refer to Figure 7, which is a schematic diagram of a back-gate voltage adjustment method provided by an embodiment of the present application. As shown in Figure 7, before the back-gate control line receives the back-gate drive voltage, that is, before the back-gate drive voltage is applied to the back-gate line, that is, when BG=0, the threshold voltage of the dual-gate transistor T is V1. After the back-gate control line receives the back-gate drive voltage, that is, after the back-gate drive voltage is applied to the back-gate line, that is, when BG=1, the threshold voltage of the dual-gate transistor T is V2. It can be seen that after the back-gate drive voltage is applied to the back-gate line, the threshold voltage of the dual-gate transistor T can be adjusted to reduce the deviation between the threshold voltage during the storage process and the preset threshold voltage.

[0115] It should be noted that the embodiments of the present application do not impose any specific restrictions on the material and size of the back-gate control line. For example, the material of the back-gate control line can be a material with good conductivity or transmission efficiency, or can be a material consistent with the back-gate line. For another example, the width of the back-gate control line can be less than or equal to the width of the back-gate line.

[0116] In one implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located above the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0117] Multiple bit lines are located above the channel, as well as above multiple back gate lines and multiple word lines. For example, as shown in FIG6 , bit line 607 is located above channel 601, as well as above back gate line 602 and word line 603. Bit line 607 is connected to channel 601 via a bit line contact (BLC) 608. A portion of bit line contact 608 or the contact portion between bit line contact 608 and the channel can serve as the first electrode (not shown) of dual-gate transistor T. Furthermore, the material forming bit line contact 608 can be the same as or different from that of bit line 607. The width of bit line contact 608 in a direction parallel to substrate 600 (e.g., the X-axis) can be 15-100 nm, which is not specifically limited in this embodiment of the present application. The thickness of bit line contact 608 in a direction perpendicular to substrate 600 (the Z-axis) is greater than the sum of the thicknesses of word line 603 and second gate oxide dielectric layer 605.

[0118] In one implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located below the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0119] In an embodiment of the present application, please refer to FIG8 , which is a schematic diagram of the structure of another memory cell provided in an embodiment of the present application. As shown in FIG8 , a bit line 607 is located below the channel 601 and also below the back gate line 602 and word line 603. A bit line contact (BLC) 608 connected to the bit line 607 is connected upwardly to the channel 601. The bit line contact 608 can also be considered the first electrode of the dual-gate transistor. The material forming the bit line contact 608 can be the same as or different from that of the bit line 607. The width of the bit line contact 608 in a direction parallel to the substrate 600 (e.g., the X-axis direction) can be 15-100 nm, which is not specifically limited in this embodiment of the present application. The thickness of the bit line contact 608 in a direction perpendicular to the substrate 600 (the Z-axis direction) is greater than the sum of the thicknesses of the back gate line 602 and the first gate oxide dielectric layer 604. Moreover, when the bit line is located below the channel, the structure between the channel and the capacitor can be made smaller, thereby making the memory array smaller and easier to integrate.

[0120] In one implementation, in a direction perpendicular to the substrate, the channel is upwardly connected to the capacitor through a storage node contact SNC.

[0121] As shown in Figure 6 or Figure 8 above, the channel 601 is upwardly connected to an electrode (e.g., the lower electrode) of the capacitor C through a storage node contact (Storage Node Contact, SNC) 609. A portion of the storage node contact 609 or the contact portion between the storage node contact 609 and the channel can serve as the second electrode of the dual-gate transistor T (not shown). The material forming the storage node contact SNC can be the same as or different from the material of the electrode connected to the capacitor, and the embodiments of the present application do not impose specific limitations on this.

[0122] The width of the storage node contact portion 609 in a direction parallel to the substrate 600 (e.g., the X-axis direction) can be 15-100 nm, which is not specifically limited in the embodiments of the present application. It should be noted that in a direction perpendicular to the substrate 600 (the Z-axis direction), the height of the storage node contact portion SNC of the memory cell shown in FIG8 is shorter than that of the storage node contact portion SNC of the memory cell shown in FIG7 , thereby making the memory array smaller and easier to integrate.

[0123] In one implementation, the material of the plurality of back gate lines includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu, or aluminum Al. Exemplary, the material forming the back gate line can be one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu, or aluminum Al. As shown in FIG6 above, in a direction parallel to the substrate 600 (such as the X-axis direction), the width of each back gate line BGL can be consistent with the width of each word line WL, for example, can be between 40-200 nm. In addition, the material of the back gate line can be the same as or different from the material of the second gate of the dual-gate transistor.

[0124] In summary, in a memory array provided in an embodiment of the present application, the OS transistor of the 1T1C memory cell in the memory array is a dual-gate transistor. During the storage process, the back gate (i.e., the second gate) of the dual-gate transistor can receive a voltage signal (e.g., a back gate drive voltage). By regulating the voltage applied to the back gate of the dual-gate transistor, the threshold voltage V of the dual-gate transistor can be adjusted. t , restoring the deviated threshold voltage to the preset threshold voltage, thereby improving the sensing margin of the sense amplifier SA in the peripheral circuit. This method of adjusting the threshold voltage of the OS transistor by applying a voltage to the second gate ensures that the threshold voltage of the OS transistor does not deviate during storage, thereby ensuring the storage efficiency of the memory array during the storage process.

[0125] Secondly, based on the memory cell structure shown in FIG6 , the following embodiment of the present application exemplarily provides a method for preparing a memory array, which can solve the problem of low storage efficiency caused by the deviation of the threshold voltage of the 1T1C memory cell in the OS channel.

[0126] Please refer to Figures 9 and 10 , which are schematic diagrams of a method for preparing a memory array according to an embodiment of the present application.

[0127] Step 1: As shown in (1) of FIG9 , a back gate line layer and a first gate oxide dielectric layer are sequentially deposited on a substrate 600 by chemical vapor deposition (CVD).

[0128] Step 2: As shown in (2) of FIG9 , a plurality of back gate lines 602 and a plurality of first gate oxide dielectric layers 604 are prepared. The back gate line layer and the first gate oxide dielectric layer are etched to form a plurality of back gate lines 602 and a plurality of first gate oxide dielectric layers 604; then, a dielectric material layer 606 is deposited to fill the gaps between adjacent back gate lines 602 and the first gate oxide dielectric layers 604, and chemical mechanical polishing (CMP) is performed until the plurality of back gate lines 602 and the plurality of first gate oxide dielectric layers 604 are exposed.

[0129] Step 3: As shown in (3) of FIG9 , trenches corresponding to the plurality of memory cells are prepared. The semiconductor structure obtained in step 2 is subjected to atomic layer deposition (ALD) to deposit IGZO to form an oxide semiconductor film layer. The oxide semiconductor film layer is etched to form trenches 601, and a dielectric material layer 606 is deposited at the gaps to fill the gaps.

[0130] Step 4: As shown in (1) of FIG10 , a plurality of word lines 603 and a plurality of second gate oxide dielectric layers 605 are prepared. Chemical vapor deposition is performed on the surface of the semiconductor structure obtained in step 3 above, and etching is performed to form a plurality of word lines 603 and a plurality of second gate oxide dielectric layers 605. A dielectric material layer 606 is then deposited to fill the gaps between adjacent word lines 603 and the second gate oxide dielectric layers 605, and chemical mechanical polishing is performed to smooth the gaps. At this point, the plurality of word lines 603 and the plurality of second gate oxide dielectric layers 605 do not need to be exposed.

[0131] Step 5: As shown in (2) of FIG10 , a plurality of bit lines 607 and bit line contacts 608 are prepared. Bit line contact holes (which may be square) are etched on the surface of the semiconductor structure obtained in step 4 above, wherein the bottom of each bit line contact hole BLC exposes a corresponding channel 601. Conductive material (e.g., tungsten W) is filled into each bit line contact hole BLC until it covers the surface of the semiconductor structure obtained in step 4 above, forming a bit line layer. The bit line layer is etched and a dielectric material layer 606 is deposited to form a plurality of bit lines 607 and bit line contacts 608.

[0132] Step 6: As shown in (3) of FIG10 , a plurality of storage node contacts SNC are prepared. The surface of the semiconductor structure obtained in step 5 is etched to obtain a plurality of storage node contact SNC holes (which may be square). The bottom of each storage node contact SNC hole exposes a corresponding channel 601, and a conductive material (e.g., tungsten W) is filled inside each storage node contact SNC hole.

[0133] Step 7: Based on the semiconductor structure obtained in step 6, a capacitor manufacturing process is performed to finally form the memory array structure shown in FIG. 6 .

[0134] It should be understood that the manufacturing method or electronic device for preparing a storage array provided in the embodiments of the present application is consistent with the storage array involved in the relevant embodiments shown in Figures 2 to 8 above. Its specific content and beneficial effects can be referred to the storage array involved in the relevant embodiments shown in Figures 2 to 8 above, and will not be repeated here.

[0135] Based on the memory cell structure shown in FIG8 , the following embodiment of the present application exemplarily provides another method for manufacturing a memory array, which can solve the problem of low storage efficiency caused by the deviation of the threshold voltage of the 1T1C memory cell in the OS channel.

[0136] Step 1: Prepare multiple bit lines 607 and corresponding bit line contacts 608 on a substrate 600. A bit line layer is deposited on the surface of the substrate 600 and then etched to form multiple bit lines 607 and corresponding bit line contacts 608. A dielectric material layer 606 is then filled in the gaps and chemically mechanically polished until the bit line contacts 608 are exposed.

[0137] Step 2: Prepare multiple back gate lines 602 and multiple first gate oxide dielectric layers 604. The surface of the semiconductor structure obtained in Step 1 is etched to form multiple grooves, with the bottom of each groove not exposing the bit line 607. Chemical vapor deposition is then performed sequentially within each groove, followed by chemical mechanical polishing to form multiple back gate lines 602 and multiple first gate oxide dielectric layers 604.

[0138] Step 3: Prepare channels corresponding to the multiple memory cells. Atomic layer deposition (ALD) is performed on the semiconductor structure obtained in Step 2 to deposit IGZO to form an oxide semiconductor film. This oxide semiconductor film is then etched to form channels 601, and a dielectric material layer 606 is deposited at the gaps to fill the gaps.

[0139] Step 4: Prepare multiple word lines 603 and multiple second gate oxide dielectric layers 605. Chemical vapor deposition is performed on the surface of the semiconductor structure obtained in step 3 above, followed by etching to form multiple word lines 603 and multiple second gate oxide dielectric layers 605. A dielectric material layer 606 is then deposited to fill the gaps between adjacent word lines 603 and the second gate oxide dielectric layers 605, and chemical mechanical polishing is performed to smooth the gaps. At this point, the multiple word lines 603 and the multiple second gate oxide dielectric layers 605 do not need to be exposed.

[0140] Step 5: Prepare multiple storage node contacts (SNC). Etch the surface of the semiconductor structure obtained in step 4 to obtain multiple storage node contact (SNC) holes (which may be square). The bottom of each storage node contact (SNC) hole exposes a corresponding channel 601. Conductive material (e.g., tungsten W) is filled inside each storage node contact (SNC) hole.

[0141] Step 6: Based on the semiconductor structure obtained in step 5, a capacitor manufacturing process is performed to finally form the memory array structure shown in FIG. 8 .

[0142] It should be understood that the manufacturing method for preparing a memory array provided in the embodiment of the present application can also refer to the manufacturing method for preparing a memory array shown in FIG. 9 and FIG. 10 , which will not be described in detail here.

[0143] It should be noted that the above-mentioned method for preparing a storage array is only a simple exemplary method provided in the embodiment of the present application, and the embodiment of the present application does not make any specific limitation thereto.

[0144] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0145] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0147] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, the functional units in the embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0149] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0150] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage array, characterized in that: include: A substrate, a plurality of word lines, a plurality of bit lines, a plurality of back gate lines and a plurality of memory cells distributed in an array arranged on the substrate; each of the memory cells is in contact with one of the word lines, one of the bit lines and one of the back gate lines; Each of the storage cells includes a double-gate transistor and a capacitor, the double-gate transistor includes a first gate, a second gate, a first electrode, a second electrode and a channel, the material forming the channel is an oxide semiconductor OS, and the double-gate transistor is a planar transistor; Among them, the first gate in each of the storage cells is connected to the corresponding word line, the second gate is connected to the corresponding back gate line, the first electrode is connected to the corresponding bit line, the second electrode is connected to one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected to a DC bias.

2. The storage array according to claim 1, characterized in that: The plurality of back gate lines correspond to the plurality of word lines one by one, and each of the back gate lines is arranged in parallel with each of the word lines, and each of the back gate lines is arranged vertically with each of the bit lines.

3. The storage array according to claim 2, characterized in that: In a direction perpendicular to the substrate, the plurality of back gate lines and the plurality of word lines are respectively located at upper and lower sides of the channel; Wherein, a first gate oxide dielectric layer is arranged between each of the back gate lines and the channel, and a second gate oxide dielectric layer is arranged between each of the word lines and the channel.

4. The storage array according to claim 2 or 3, characterized in that: One end of each of the back gate lines is electrically connected via a back gate control line, the back gate control line is used to receive a back gate driving voltage, and the back gate control line is arranged in parallel with each of the bit lines.

5. The storage array according to any one of claims 1 to 4, characterized in that: In a direction perpendicular to the substrate, the plurality of bit lines are located above the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

6. The storage array according to any one of claims 1 to 4, characterized in that: In a direction perpendicular to the substrate, the plurality of bit lines are located below the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

7. The storage array according to any one of claims 1 to 6, characterized in that: In a direction perpendicular to the substrate, the channel is connected upward to the capacitor through a storage node contact SNC.

8. The storage array according to any one of claims 1 to 7, characterized in that: The material of the plurality of back gate lines includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu or aluminum Al.

9. A memory, characterized in that: It comprises a controller and a storage array as described in any one of claims 1 to 8, wherein the controller is connected to the storage array, and the controller is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

10. The memory according to claim 9, characterized in that: The controller comprises a back-gate driving circuit; the back-gate driving circuit is used to output a back-gate driving voltage to all back-gate lines in the storage array through a back-gate control line.

11. The memory according to claim 9, characterized in that: In a direction perpendicular to the substrate in the memory array, the back gate driving circuit is arranged below the memory array.

12. A chip, characterized in that: It comprises a control circuit and a storage array as described in any one of claims 1 to 8, wherein the control circuit is connected to the storage array, and the control circuit is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

13. An electronic device, characterized in that: The electronic device comprises: a circuit board and a memory as described in any one of claims 9 to 11; the circuit board is electrically connected to the memory.

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