Encoding circuit, decoding circuit, encoding method, decoding method, and program

Abstract

This encoding circuit for use in coherent digital signal processing comprises: a series / parallel conversion circuit that performs series / parallel conversion on inputted data to divide the inputted data into d (d is an integer of 2 or more) pieces of divided data; an encoding unit that is provided on a first lane to a (d-1)th lane and performs encoding on (d-1) pieces of divided data, which are outputted from the series / parallel conversion circuit, by using an error correction code; a bit conversion circuit that, by calculating an exclusive OR between one piece of divided data that is not encoded by the encoding unit among the d pieces of divided data outputted from the series / parallel conversion circuit and each of the (d-1) pieces of divided data that has been encoded by the encoding unit, converts a bit sequence into another bit sequence; and a parallel / series conversion circuit that converts the d pieces of divided data outputted from the bit conversion circuit into one piece of data by parallel / serial conversion.　

Description

Encoding circuit, decoding circuit, encoding method, decoding method, and program

[0001] The present invention relates to an encoding circuit, a decoding circuit, an encoding method, a decoding method, and a program.

[0002] In an optical transmission system, it is necessary to design the redundancy (overhead: OH) of forward error correction (FEC) according to system requirements such as signal-to-noise ratio (SNR).

[0003] T. Kakizaki et al., “Low-complexity Channel Polarized Multilevel Coding for Modulation-format-independent Forward Error Correction”, ECOC2021, Th1G.3, (2021).T. Kakizaki et al., “Low-complexity Channel Polarized Multilevel Coding for Probabilistic Amplitude Shaping”, OFC2022, W3H.4, (2022).Xiaodong Li and James A. Ritcey, “Bit-Interleaved Coded Modulation with Iterative Decoding”, IEEE ICC1999, pp858-863, vol. 2(1999).

[0004] However, adopting FEC with different redundancy levels requires encoding and decoding circuits for a plurality of error correcting codes, which results in an increase in the circuit size.

[0005] In view of the above circumstances, an object of the present invention is to provide a technique that can perform encoding or decoding of a plurality of error-correcting codes while suppressing an increase in circuit scale.

[0006] One aspect of the present invention is an encoding circuit used in coherent digital signal processing, comprising: a serial-to-parallel conversion circuit that divides input data into d (d is an integer of 2 or greater) pieces of divided data by serial-to-parallel conversion; an encoding unit provided on a first lane through a (d-1)th lane that encodes the (d-1) pieces of divided data output from the serial-to-parallel conversion circuit using an error correction code; a bit conversion circuit that converts a bit sequence into another bit sequence by taking an exclusive OR between one piece of divided data that has not been encoded by the encoding unit and each of the (d-1) pieces of divided data that have been encoded by the encoding unit, out of the d pieces of divided data output from the serial-to-parallel conversion circuit; and a parallel-to-serial conversion circuit that converts the d pieces of divided data output from the bit conversion circuit into a single piece of data by parallel-to-serial conversion.

[0007] One aspect of the present invention is a decoding circuit used in coherent digital signal processing, comprising: a distributor that distributes decoding metrics obtained by demodulating transmission data transmitted from a transmitting device based on information about noise occurring in a communication channel and a received signal to each of a first lane to a d-th lane (d is an integer of 2 or more); a first likelihood calculation circuit that is provided on the first lane to a (d-1)-th lane and that calculates a first log-likelihood ratio for each of the first lane to the (d-1)-th lane using the decoding metrics distributed by the distributor; and a first likelihood calculation circuit that calculates a first log-likelihood ratio for each of the first lane to the (d-1)-th lane by the first likelihood calculation circuit. The decoding circuit includes: a decoding unit that performs error correction decoding using the calculated first log-likelihood ratio and feeds back the error correction decoding result to the first likelihood calculation circuit; a second likelihood calculation circuit that is provided on a lane other than the lane on which the first likelihood calculation circuit is provided among the first lane to d-th lane, and that calculates a second log-likelihood ratio based on the decoding metric distributed by the distributor and the error correction decoding result fed back by the decoding unit, and makes a hard decision; and a parallel-to-serial conversion circuit that converts the output of the decoding unit and the output of the second likelihood calculation circuit into one piece of data by parallel-to-serial conversion.

[0008] One aspect of the present invention is a decoding circuit used in coherent digital signal processing, comprising: a distributor that distributes decoding metrics obtained by demodulating transmission data transmitted from a transmitting device based on information about noise generated in a communication channel and a received signal to each of a first lane to a dth lane (d is an integer greater than or equal to 2); a first likelihood calculation circuit that is provided on the first lane to the dth lane and that calculates a first log-likelihood ratio for each of the first lane to the dth lane using the decoding metrics distributed by the distributor; a decoding unit that performs error correction decoding using the first log-likelihood ratio calculated for each of the first lane to the dth lane by the first likelihood calculation circuit and feeds back the error correction decoding result to the first likelihood calculation circuit; and a parallel-to-serial conversion circuit that converts the output of the decoding unit into one piece of data by parallel-to-serial conversion.

[0009] One aspect of the present invention is an encoding method used in coherent digital signal processing, which divides input data into d (d is an integer of 2 or greater) pieces of divided data by serial-to-parallel conversion, encodes the (d-1) pieces of divided data output from the first lane to the (d-1)th lane using an error correction code, converts a bit sequence into another bit sequence by taking an exclusive OR between one unencoded piece of divided data out of the d pieces of divided data and each of the (d-1) pieces of encoded divided data, and converts the output d pieces of divided data into a single piece of data by parallel-to-serial conversion.

[0010] One aspect of the present invention is a decoding method used in coherent digital signal processing, which distributes decoding metrics obtained by demodulating transmission data transmitted from a transmitting device based on information about noise generated in a communication channel and a received signal to each of the first to dth lanes (d is an integer greater than or equal to 2), calculates a first log-likelihood ratio for each of the first to (d-1)th lanes using the distributed decoding metrics, performs error correction decoding using the first log-likelihood ratios calculated for each of the first to (d-1)th lanes, feeds back the error correction decoding results, calculates a second log-likelihood ratio based on the distributed decoding metrics and the fed-back error correction decoding results, makes a hard decision, and converts the error correction decoding results and the hard decision results into a single piece of data by parallel-to-serial conversion.

[0011] One aspect of the present invention is a decoding method used in coherent digital signal processing, which distributes decoding metrics obtained by demodulating transmission data transmitted from a transmitting device based on information about noise generated in a communication channel and a received signal to each of the first to dth lanes (d is an integer greater than or equal to 2), calculates a first log-likelihood ratio for each of the first to dth lanes using the distributed decoding metrics, performs error correction decoding using the first log-likelihood ratio calculated for each of the first to dth lanes, feeds back the error correction decoding results, and converts the error correction decoding results for each of the first to dth lanes into a single piece of data by parallel-to-serial conversion.

[0012] One aspect of the present invention is a program for causing a computer to function as an encoding device including the encoding circuit described above.

[0013] One aspect of the present invention is a program for causing a computer to function as a decoding device including the above-described decoding circuit.

[0014] According to the present invention, it is possible to perform encoding or decoding of a plurality of error correction codes while suppressing an increase in circuit scale.

[0015] Fig. 1 is a block diagram showing a configuration example of a transmitting device in a first embodiment. Fig. 2 is a block diagram showing a configuration example of a receiving device in a first embodiment. Fig. 3 is a block diagram showing a configuration example of a transmitting device in a second embodiment. Fig. 4 is a block diagram showing a configuration example of a receiving device in a second embodiment. Fig. 5 is a diagram showing the SNR dependency of the maximum achievable rate. Fig. 6 is a diagram showing an estimate of performance degradation from the Shannon limit when FEC-OH is 15%.

[0016] An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) Fig. 1 is a block diagram showing an example of the configuration of a transmitting device 1 in a first embodiment. The transmitting device 1 is part of a digital coherent communication system and is a transmitting device used to transmit data to be transmitted (hereinafter referred to as "transmission data"). The transmitting device 1 transmits the transmission data to a receiving device connected via a communication path. The communication path is assumed to be, for example, an AWGN (Additive White Gaussian Noise) communication path.

[0017] The transmitting device 1 includes an encoding circuit 10, a symbol mapper 11, and a transmitting unit 12. The encoding circuit 10 is made up of an HD-FEC encoding unit 110, a 1:d converter 120, an SD-FEC encoding unit 130, a bit conversion circuit 140, and a d:1 converter 150.

[0018] Data to be transmitted is input to the HD-FEC encoding unit 110. The HD-FEC encoding unit 110 encodes the input data to be transmitted using HD-FEC (Hard-Decision FEC) technology. The HD-FEC encoding unit 110 outputs the encoded data to be transmitted to the 1:d converter 120.

[0019] The 1:d converter 120 divides the coded transmission target data output from the HD-FEC encoding unit 110 into a predetermined division number d (d is an integer of 2 or more). As a result, the coded transmission target data is divided into d pieces. Hereinafter, the divided coded transmission target data will be referred to as divided data. The 1:d converter 120 outputs the divided data to each of the first lane to the d-th lane. The 1:d converter 120 may have a bit interleaver for bit interleaving. However, the total bit length of the (d-1) lanes from the first lane to the (d-1)th lane is nR ＳＤ (d-1) / d, n represents an arbitrary constant, and R ＳＤ denotes the rate of the SD-FEC code.

[0020] The SD-FEC encoding unit 130 is provided on the first lane to the (d-1)th lane, and performs encoding using an error correction code on the divided data output to each of the first lane to the (d-1)th lane. As such, in the first embodiment, encoding using an error correction code is not performed on the divided data output to the dth lane.

[0021] The bit conversion circuit 140 is a conversion circuit that converts a bit sequence into another bit sequence using an exclusive OR. Specifically, the bit conversion circuit 140 performs an exclusive OR operation on each vector of the data in the d-th lane for each of the first to (d-1)-th lanes. For example, the bit conversion circuit 140 performs an exclusive OR operation on the divided data output from the SD-FEC encoding unit 130 to the first lane and the divided data output from the 1:d converter 120 to the d-th lane. Similarly, the bit conversion circuit 140 performs an exclusive OR operation on the divided data output from the SD-FEC encoding unit 130 to the second lane and the divided data output from the 1:d converter 120 to the d-th lane.

[0022] The bit conversion circuit 140 performs this process on the divided data output to each of the lanes from the first lane to the (d-1)th lane. The bit conversion circuit 140 takes an exclusive OR of the divided data of each of the lanes from the first lane to the (d-1)th lane and the divided data output from the 1:d converter 120 to the dth lane, and outputs the result to the d:1 converter 150. In the dth lane, the bit conversion circuit 140 outputs the input divided data to the d:1 converter 150 as is.

[0023] The d:1 converter 150 converts the divided data transmitted in each of the first to d-th lanes into one-lane series of data by performing parallel-to-serial conversion. The d:1 converter 150 outputs the one-lane series of data to the symbol mapper 11.

[0024] The symbol mapper 11 generates transmission data by assigning gray labeling to the data of the one-lane series output from the d:1 converter 150. The symbol mapper 11 outputs the generated transmission data to the transmitter 12.

[0025] The transmitter 12 transmits the transmission data generated by the symbol mapper 11 .

[0026] 2 is a block diagram showing an example of the configuration of a receiving device 2 according to the first embodiment. The receiving device 2 is a transmitting device used in a digital coherent communication system. The receiving device 2 receives transmission data transmitted from a transmitting device 1 connected via a communication path.

[0027] The receiving device 2 includes a receiving unit 20 , a symbol demapper 21 , and a decoding circuit 22 .

[0028] The receiving unit 20 receives the transmission data transmitted from the transmitting device 1 via a communication path.

[0029] The symbol demapper 21 demodulates the transmission data received by the receiver 20 based on the channel information and the received signal using a demodulation method corresponding to the modulation method, and obtains a decoding metric. The decoding metric is, for example, a log-likelihood ratio (LLR). The channel information represents the distribution of noise in the channel. The channel information can be measured using a spectrum analyzer or the like. The channel information is assumed to be measured in advance and stored in the SD likelihood calculation unit 230, which will be described later.

[0030] The decoding circuit 22 is made up of a distributor 220 , an SD likelihood calculation section 230 , an SD-FEC decoding section 240 , an HD likelihood calculation section 250 , a d:1 converter 260 , and an HD-FEC decoding section 270 .

[0031] The distributor 220 receives the value demapped by the symbol demapper 21. The value demapped by the symbol demapper 21 is used to divide the received signal y ｊ :=(y ｊ １ ,y ｊ ２ ,…,y ｊ ｄ ) The distributor 220 divides the received signal y ｊ is shared among the first lane to the d-th lane. Specifically, the distributor 220 copies the same symbol to all lanes from the first lane to the d-th lane and shares it.

[0032] The SD likelihood calculation unit 230 is provided on the first lane to the (d-1)th lane, and calculates the value (for example, the received signal y ｊ ) for each of the first lane to the (d−1)th lane. Specifically, the SD likelihood calculation unit 230 calculates the log likelihood ratio LLRλ based on the following equation (1): ＩＤ ｉ (k) is calculated for each of the 1st lane to the (d-1)th lane. ｚ ｉ │Ｙ,λ represents the communication channel information, and Y represents the received signal.

[0033]

[0034] The SD likelihood calculation unit 230 calculates the log likelihood ratios LLRλ for each of the first lane to the (d−1)th lane. ＩＤ ｉ (k) is output to the SD-FEC decoder 240 from the first lane to the (d−1)th lane, respectively.

[0035] The SD-FEC decoder 240 calculates the log-likelihood ratios (LLRλ) for the first lane to the (d−1)th lane calculated by the SD likelihood calculator 230. ＩＤ ｉ The SD-FEC decoder 240 performs error correction decoding using (k). The SD-FEC decoder 240 feeds back the decoding results for each of the first lane to the (d−1)th lane to the SD likelihood calculator 230.

[0036] The SD likelihood calculation unit 230 receives the decoding result as feedback from the SD-FEC decoding unit 240 and calculates the log likelihood ratio LLRλ based on the above equation (1) using the decoded value. ＩＤ ｉ The SD likelihood calculation unit 230 calculates the log likelihood ratios LLRλ (k) for each of the first lane to the (d−1)th lane. ＩＤ ｉ (k) from the first lane to the (d-1)th lane, respectively, to the SD-FEC decoding unit 240. The SD likelihood calculation unit 230 and the SD-FEC decoding unit 240 repeat the above process t times (t is an integer greater than or equal to 2). The SD likelihood calculation unit 230 outputs the result of repeating the above process t times (the tth decoding result) to the HD likelihood calculation unit 250. The SD-FEC decoding unit 240 outputs the result of repeating the above process t times (the tth decoding result) to the d:1 converter 260.

[0037] The HD likelihood calculation unit 250 is provided on the d-th lane, and receives as input the decoding results for each of the first lane to the (d−1)-th lane output from the SD likelihood calculation unit 230. Using the received decoding results for each of the first lane to the (d−1)-th lane, the HD likelihood calculation unit 250 calculates the log-likelihood ratio λ ＩＤ ｄ In equation (2), z １represents the bit of the first lane decoded by the SD-FEC decoder 240, and z ｄ－１ represents the bit of the d−1th lane decoded by the SD-FEC decoder 240 .

[0038]

[0039] The HD likelihood calculation unit 250 calculates the log likelihood ratio λ obtained by the above equation (2). ＩＤ ｄ The HD likelihood calculation unit 250 outputs the hard decision result to the d:1 converter 260.

[0040] The d:1 converter 260 converts the values ​​transmitted in each of the first to dth lanes into one-lane series of data by performing parallel-to-serial conversion. The d:1 converter 260 outputs the one-lane series of data to the HD-FEC decoding unit 270.

[0041] The HD-FEC decoder 270 decodes the one-lane series of data output from the d:1 converter 260 using a decoding technique corresponding to the encoding performed by the HD-FEC encoder 110 .

[0042] With the above configuration, the rate can be expressed as the following equation (3), and the overhead can be expressed as the following equation (4).

[0043]

[0044]

[0045] Here, the theory of the first embodiment will be explained. In the conventional CP-MLC system, z ｊ ｉ ,y ｊ ｉ Let Z be the random variable corresponding to ｊ ｉ ,Y ｊ ｉ In the following description, the bit number j will be omitted. In CP-MLC, the inequality shown in the following equation (5) holds for the mutual information vector I.

[0046]

[0047] When two-stage decoding is adopted, each random variable Z in the mutual information on the right side of the above equation (5) ｉ＋１ ,…,Z ｄ Since feedback information corresponding to the above is discarded, degradation occurs as shown in the inequality from the left side of equation (5) to the right side of equation (5). Meanwhile, in bit interleaved coded modulation (BICM), a method is known in which iterative demapping is used to compensate for degradation caused by discarding feedback information and achieve the mutual information on the left side of equation (5) (see, for example, Non-Patent Document 3). When sign(·) is a function that returns positive or negative, the achievable capacity in the first embodiment is given by the following equation (6).

[0048]

[0049] When d is large, the second term I(Z ｄ , sign (Y ｄ )) approaches 1.

[0050] According to the transmitting device 1 configured as above, encoding using error correction codes is not performed in some lanes (for example, the d-th lane), thereby making it possible to reduce overhead.

[0051] (Second embodiment) Fig. 3 is a block diagram showing an example of the configuration of a transmitting device 1a in a second embodiment. The transmitting device 1a is part of a digital coherent communication system and is a transmitting device used to transmit transmission data. The transmitting device 1a transmits the transmission data to a receiving device connected via a communication path. The communication path is assumed to be, for example, an AWGN communication path.

[0052] The transmitting device 1a includes a coding circuit 10a, a symbol mapper 11, and a transmitting unit 12. The coding circuit 10a includes an HD-FEC coding unit 110, an SD-FEC coding unit 130a, a bit conversion circuit 140a, a d:1 converter 150, and a 1:(d-1) converter 160. The coding circuit 10a differs in configuration from the coding circuit 10 in that it includes an SD-FEC coding unit 130a and a bit conversion circuit 140a instead of the SD-FEC coding unit 130 and the bit conversion circuit 140, and in that it includes a 1:(d-1) converter 160 instead of the 1:d converter 120. The remaining configuration of the coding circuit 10a is the same as that of the coding circuit 10. The following description will focus on the differences.

[0053] The 1:(d-1) converter 160 generates divided data by dividing the coded data to be transmitted output from the HD-FEC encoding unit 110 by a predetermined division number (d-1). As a result, the coded data to be transmitted is divided into (d-1) pieces. The 1:(d-1) converter 160 outputs the divided data to each of the second lane to the d-th lane. The 1:(d-1) converter 160 may have a bit interleaver for bit interleaving. However, the total bit length of the (d-1) lanes from the second lane to the d-th lane is nR ＳＤ (d-1) / d.

[0054] The SD-FEC encoding unit 130a is provided on the second lane to the d-th lane, and performs encoding using an error correction code on the divided data output to each of the second lane to the d-th lane.

[0055] The bit conversion circuit 140a is a conversion circuit that converts a bit sequence into another bit sequence using an exclusive OR. A 0 vector is input to the bit conversion circuit 140a via the first lane, and encoded divided data is input via the second to d-th lanes. Specifically, the bit conversion circuit 140a performs an exclusive OR operation on each vector between the 0 vector input via the first lane and the divided data in each of the second to d-th lanes. For example, the bit conversion circuit 140a performs an exclusive OR operation on the divided data output from the SD-FEC encoding unit 130 to the second lane and the 0 vector input to the first lane. Similarly, the bit conversion circuit 140a performs an exclusive OR operation on the divided data output from the SD-FEC encoding unit 130 to the d-th lane and the 0 vector input to the first lane.

[0056] The bit conversion circuit 140a performs this process on the divided data output to each lane from the second lane to the d-th lane. The bit conversion circuit 140a performs an exclusive OR operation on the divided data of each lane from the second lane to the d-th lane and the 0 vector input via the first lane, and outputs the result to the d:1 converter 150.

[0057] 4 is a block diagram showing an example of the configuration of a receiving device 2a according to the second embodiment. The receiving device 2a is a transmitting device used in a digital coherent communication system. The receiving device 2a receives transmission data transmitted from a transmitting device 1a connected via a communication path.

[0058] The receiving device 2a includes a receiving section 20, a symbol demapper 21, and a decoding circuit 22a.

[0059] The decoding circuit 22a is composed of a distributor 220a, an SD likelihood calculation unit 230a, an SD-FEC decoding unit 240, an HD likelihood calculation unit 250, an HD-FEC decoding unit 270, and a d:1 converter 280. The decoding circuit 22a differs in configuration from the decoding circuit 22 in that it includes a distributor 220a and an SD likelihood calculation unit 230a instead of the distributor 220 and the SD likelihood calculation unit 230, and in that it includes a d:1 converter 280 instead of the d:1 converter 260. The other configurations of the decoding circuit 22a are the same as those of the decoding circuit 22. The following description will focus on the differences.

[0060] The distributor 220a receives the value demapped by the symbol demapper 21. The value demapped by the symbol demapper 21 is used to divide the received signal y ｊ :=(y ｊ １ ,y ｊ ２ ,…,y ｊ ｄ The divider 220a divides the received signal y ｊ is shared among the first lane to the d-th lane. Specifically, the distributor 220a copies the same symbol to all lanes from the first lane to the d-th lane and shares it.

[0061] The SD likelihood calculation unit 230a receives the values ​​(for example, the received signal y ｊ ) is input. The SD likelihood calculation unit 230a is provided on the first lane to the d-th lane, and calculates the log-likelihood ratio for each of the first lane to the d-th lane based on the values ​​shared by the first lane to the d-th lane by the distributor 220a. Specifically, the SD likelihood calculation unit 230a calculates the log-likelihood ratio LLRλ based on the following equation (7): ＩＤ ｉ (k) is calculated for each of the first to dth lanes.

[0062]

[0063] The SD likelihood calculation unit 230a calculates the log likelihood ratio LLRλ for each of the first to d-th lanes. ＩＤ ｉ (k) is output to the SD-FEC decoder 240 from the first lane to the d-th lane, respectively.

[0064] The SD-FEC decoder 240 calculates the log-likelihood ratios (LLRλ) for the first to d-th lanes calculated by the SD likelihood calculator 230. ＩＤ ｉ The SD-FEC decoder 240 performs error correction decoding using (k). The SD-FEC decoder 240 feeds back the decoding results for each of the first to d-th lanes to the SD likelihood calculator 230a.

[0065] The SD likelihood calculation unit 230a receives the decoded result as feedback from the SD-FEC decoding unit 240, and calculates the log-likelihood ratio LLRλ based on the above equation (7) using the decoded value and the zero vector. ＩＤ ｉ The SD likelihood calculation unit 230a calculates the log likelihood ratios LLRλ(k) for each of the first to d lanes. ＩＤ ｉ (k) from the first lane to the d-th lane, respectively, to the SD-FEC decoding unit 240. The SD likelihood calculation unit 230a and the SD-FEC decoding unit 240 repeat the above process t times. The SD-FEC decoding unit 240 outputs the result of repeating the above process t times (the t-th decoding result) to the d:1 converter 280.

[0066] The d:1 converter 280 converts the values ​​transmitted in each of the first to dth lanes into one-lane series of data by performing parallel-to-serial conversion. The d:1 converter 280 outputs the one-lane series of data to the HD-FEC decoding unit 270.

[0067] With the above configuration, the rate can be expressed as the following equation (8), and the overhead can be expressed as the following equation (9).

[0068]

[0069]

[0070] Here, the theory of the second embodiment will be explained. In the conventional CP-MLC system, z ｊ ｉ ,y ｊ ｉ Let Z be the random variable corresponding to ｊ ｉ ,Y ｊ ｉ In the following description, the bit number j will be omitted. In CP-MLC, the inequality shown in the above equation (5) below holds for the mutual information vector I.

[0071] When two-stage decoding is adopted, each random variable Z in the mutual information on the right side of the above equation (5) ｉ＋１ ,…,Z ｄSince feedback information corresponding to is discarded, degradation occurs as shown in the inequality from the left side of equation (5) above to the right side of equation (5). On the other hand, in bit-interleaved coded modulation, a method is known in which iterative demapping is used to compensate for degradation caused by discarding feedback information and achieve the mutual information on the left side of equation (5) above (see, for example, Non-Patent Document 3). When sign(·) is a function that returns positive or negative, the achievable capacity in the second embodiment is given by the following equation (10).

[0072]

[0073] When d is large, the first term I(Z １ ; Y １ ,Y ２ ,…,Y ｄ ) becomes small enough.

[0074] According to the transmitter 1a configured as described above, by inputting a zero vector to some lanes (e.g., the first lane), the capacity is reduced to almost zero, and the communication path is not used. This increases overhead. By using TSD and iterative demapping together, it is possible to equalize capacity while reducing degradation.

[0075] (Effects of the First and Second Embodiments) Using the first and second embodiments, the achievable capacity when using an ideal FEC-OH 15% code was calculated using the above formula (6) and formula (10), respectively, and the amount of degradation from the Shannon limit was calculated based on the following.

[0076] Degradation from Shannon limit = Shannon limit - achievable capacity

[0077] Figure 5 shows the SNR dependence of the maximum achievable rate, and Figure 6 shows the estimated performance degradation from the Shannon limit when FEC-OH is 15%. As shown in Figure 6, it can be confirmed that the degradation is less than 0.1 dB in the range of 9-21%.

[0078] (Variation 1 common to the first and second embodiments) In the transmitting device 1 and the transmitting device 1a, if the BER (Bit Error Rate) after SD-FEC decoding is below a threshold, the transmitting device 1 and the transmitting device 1a do not need to include the HD-FEC encoding unit 110.

[0079] (Modification 2 common to the first and second embodiments) The first and second embodiments may be configured in combination. Specifically, the transmitting device 1 in the first embodiment may be configured in combination with the receiving device 2 a in the second embodiment, or the transmitting device 1 a in the second embodiment may be configured in combination with the receiving device 2 in the first embodiment.

[0080] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0081] Some of the functional units (e.g., encoding circuits 10, 10a) of the transmitting devices 1, 1a and some of the functional units (e.g., decoding circuits 22, 22a) of the receiving devices 2, 2a in the above-described embodiments may be implemented by a computer. In this case, a program for implementing these functions may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into and executed by a computer system. Note that the term "computer system" here includes hardware such as an OS and peripheral devices.

[0082] Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into computer systems. Furthermore, "computer-readable recording media" may also include devices that dynamically store programs for a short period of time, such as communication lines used when transmitting programs over networks like the Internet or communication lines like telephone lines, or devices that store programs for a fixed period of time, such as volatile memory within the computer systems that serve as servers or clients. Furthermore, the programs may be designed to realize some of the aforementioned functions, or may be capable of realizing the aforementioned functions in combination with programs already stored in the computer system, or may be realized using programmable logic devices such as FPGAs (Field Programmable Gate Arrays).

[0083] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0084] The present invention is applicable to communication systems that use encoders and decoders.

[0085] REFERENCE SIGNS LIST 1, 1a... transmitting device, 2, 2a... receiving device, 10, 10a... encoding circuit, 11... symbol mapper, 12... transmitting unit, 20... receiving unit, 21... symbol demapper, 22, 22a... decoding circuit, 110... HD-FEC encoding unit, 120... 1:d converter, 130, 130a... SD-FEC encoding unit, 140, 140a... bit conversion circuit, 150... d:1 converter, 160... 1:(d-1) converter, 220, 220a... distributor, 230, 230a... SD likelihood calculation unit, 240... SD-FEC decoding unit, 250... HD likelihood calculation unit, 260... d:1 converter, 270... HD-FEC decoding unit, 280... d:1 converter

Claims

1. A coding circuit used in coherent digital signal processing, comprising: a serial-parallel conversion circuit that divides input data into d (d is an integer of 2 or more) pieces of divided data by serial-to-parallel conversion; a coding unit provided on a first lane to a (d-1)th lane that codes the (d-1) pieces of divided data output from the serial-parallel conversion circuit using an error correction code; a bit conversion circuit that converts a bit sequence into another bit sequence by taking an exclusive OR between one piece of divided data out of the d pieces of divided data output from the serial-parallel conversion circuit that has not been coded by the coding unit and each of the (d-1) pieces of divided data coded by the coding unit; and a parallel-serial conversion circuit that converts the d pieces of divided data output from the bit conversion circuit into one piece of data by parallel-to-serial conversion.

2. A decoding circuit used in coherent digital signal processing, comprising: a distributor that distributes a decoding metric obtained by demodulating transmission data transmitted from a transmitting device based on information on noise occurring in a communication path and a received signal to each of a first lane to a d-th lane (d is an integer of 2 or more); a first likelihood calculation circuit that is provided on the first lane to the (d-1)-th lane and that calculates a first log-likelihood ratio for each of the first lane to the (d-1)-th lane using the decoding metric distributed by the distributor; a decoding unit that performs error correction decoding using the first log-likelihood ratio calculated by the first likelihood calculation circuit for each of the first lane to the (d-1)-th lane and feeds back the error correction decoding result to the first likelihood calculation circuit; and a second likelihood calculation circuit that is provided on a lane among the first lane to the d-th lane that is different from the lane on which the first likelihood calculation circuit is provided and that calculates a second log-likelihood ratio based on the decoding metric distributed by the distributor and the error correction decoding result fed back by the decoding unit, and performs hard decision. a parallel-serial conversion circuit that converts an output of the decoding unit and an output of the second likelihood calculation circuit into one data by performing parallel-serial conversion.

3. A decoding circuit used in coherent digital signal processing, comprising: a distributor that distributes a decoding metric obtained by demodulating transmission data transmitted from a transmitting device based on information about noise generated in a communication path and a received signal to each of a first lane to a dth lane (d is an integer equal to or greater than 2); a first likelihood calculation circuit that is provided on the first lane to the dth lane and calculates a first log-likelihood ratio for each of the first lane to the dth lane using the decoding metric distributed by the distributor; a decoding unit that performs error correction decoding using the first log-likelihood ratio calculated for each of the first lane to the dth lane by the first likelihood calculation circuit and feeds back the error correction decoding result to the first likelihood calculation circuit; and a parallel-serial conversion circuit that converts the output of the decoding unit into one data by parallel-serial conversion.

4. An encoding method used in coherent digital signal processing, comprising the steps of: dividing input data into d (d is an integer of 2 or more) pieces of divided data by serial-to-parallel conversion; encoding the (d-1) pieces of divided data output from the first lane to the (d-1)th lane using an error correction code; converting a bit sequence into another bit sequence by taking an exclusive OR between one piece of unencoded divided data out of the d pieces of divided data and each of the (d-1) pieces of encoded divided data; and converting the output d pieces of divided data into a single piece of data by parallel-to-serial conversion.

5. A decoding method used in coherent digital signal processing, comprising the steps of: distributing a decoding metric obtained by demodulating transmission data transmitted from a transmitting device based on information about noise occurring in a communication path and a received signal to each of a first lane to a d-th lane (d is an integer equal to or greater than 2); calculating a first log-likelihood ratio for each of the first lane to the (d-1)-th lane using the distributed decoding metric; performing error correction decoding using the first log-likelihood ratio calculated for each of the first lane to the (d-1)-th lane and feeding back the error correction decoding result; calculating a second log-likelihood ratio based on the distributed decoding metric and the fed back error correction decoding result, performing hard decision; and converting the error correction decoding result and the hard decision result into a single piece of data by performing parallel-to-serial conversion.

6. A decoding method used in coherent digital signal processing, comprising the steps of: distributing a decoding metric obtained by demodulating transmission data transmitted from a transmitting device based on information about noise generated in a communication path and a received signal, to each of a first lane to a dth lane (d is an integer equal to or greater than 2); calculating a first log-likelihood ratio for each of the first lane to the dth lane using the distributed decoding metric; performing error correction decoding using the first log-likelihood ratio calculated for each of the first lane to the dth lane, feeding back the error correction decoding results; and converting the error correction decoding results for each of the first lane to the dth lane into a single piece of data by parallel-serial conversion.

7. A program for causing a computer to function as an encoding device comprising the encoding circuit according to claim 1.

8. A program for causing a computer to function as any one of the decoding devices comprising the decoding circuit according to claim 2 or 3.

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