Semiconductor device, method for manufacturing semiconductor device, and light detection device

Abstract

This semiconductor device includes: a trench disposed from a first surface of a substrate toward a second surface facing the first surface; a first insulated gate field effect transistor disposed at a lower part in the trench and having a first gate electrode embedded in a trench sidewall with a first gate insulating film interposed therebetween; a sidewall insulator disposed on the trench sidewall at an upper part in the trench and thicker than the first gate insulating film in the same direction; and an electrode embedded in the upper part of the trench with the sidewall insulator interposed therebetween and electrically connected to the first gate electrode.

Description

Semiconductor device, semiconductor device manufacturing method and photodetector

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a photodetector.

[0002] Patent Document 1 discloses a solid-state imaging device. In this solid-state imaging device, a pixel is constructed by a photodiode and a charge readout transistor. The photodiode is formed inside a semiconductor substrate. One terminal of the charge readout transistor is connected to the photodiode. The other terminal is an n-type source / drain region formed on the surface side of the semiconductor substrate. This n-type source / drain region is connected to an amplifier transistor through a floating diffusion. In addition, the gate electrode of the charge readout transistor is formed from the surface toward the interior of the semiconductor substrate.

[0003] Japanese Patent Application Laid-Open No. 2005-223084

[0004] In the solid-state imaging device disclosed in Patent Document 1, in the charge readout transistor, the charge transferred from the photodiode to the floating diffusion is affected by a strong electric field effect from the gate electrode, and therefore it has been desired to effectively suppress or prevent the influence of the electric field effect.

[0005] Therefore, there has been a demand for the development of a semiconductor device, a method for manufacturing a semiconductor device, and a photodetector that can effectively suppress or prevent the influence of the field effect from the gate electrode.

[0006] A semiconductor device according to a first embodiment of the present disclosure includes: a trench extending from a first surface of a substrate toward a second surface opposite the first surface; a first insulated gate field effect transistor disposed in a lower portion of the trench and having a first gate electrode embedded in a sidewall of the trench with a first gate insulating film interposed therebetween; a sidewall insulator disposed in an upper portion of the trench on the sidewall of the trench and having a thickness in the same direction greater than that of the first gate insulating film; and an electrode embedded in an upper portion of the trench with the sidewall insulator interposed therebetween and electrically connected to the first gate electrode.

[0007] A semiconductor device according to a second embodiment of the present disclosure is the semiconductor device according to the first embodiment, further comprising an interlayer insulator disposed on the first surface, a connection hole disposed in the interlayer insulator and leading to the groove opening, and wiring disposed at least within the connection hole, a portion of which serves as an electrode.

[0008] A photodetector according to a third embodiment of the present disclosure includes a groove extending from a first surface of a substrate toward a second surface opposite the first surface, a transfer transistor disposed in a lower portion of the groove and having a first gate electrode embedded in a sidewall of the groove with a first gate insulating film interposed therebetween, a sidewall insulator disposed in an upper portion of the groove on the sidewall of the groove and having a thickness in the same direction greater than that of the first gate insulating film, an electrode embedded in an upper portion of the groove with the sidewall insulator interposed therebetween and electrically connected to the first gate electrode, a photoelectric conversion element disposed in the substrate and electrically connected to one end of the transfer transistor and converting light into electric charges, and a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and the electrode and electrically connected to the other end of the transfer transistor.

[0009] A method for manufacturing a semiconductor device according to a fourth embodiment of the present disclosure includes forming a trench from a first surface of a substrate toward a second surface opposite the first surface, forming a first gate electrode at a lower portion of the trench with a first gate insulating film interposed on a sidewall of the trench, and forming a first insulated-gate field-effect transistor, forming a sidewall insulator at an upper portion of the trench on the sidewall of the trench, the sidewall insulator having a thickness greater in the same direction than that of the first gate insulating film, by self-alignment with the trench, and forming an electrode at an upper portion of the trench electrically connected to the first gate electrode with the sidewall insulator interposed.

[0010] FIG. 1 is a schematic system configuration diagram of a photodetector according to a first embodiment of the present disclosure. FIG. 2 is a schematic exploded plan configuration diagram of the photodetector shown in FIG. 1. FIG. 3 is a circuit configuration diagram of a pixel and pixel circuit of the photodetector shown in FIG. 1. FIG. 4A is a plan configuration diagram of a pixel of the photodetector shown in FIG. 1. FIG. 4B is a plan configuration diagram of a main part of the pixel of the photodetector shown in FIG. 4A when misalignment occurs. FIG. 4C is a plan configuration diagram of a main part of the pixel of the photodetector shown in FIG. 4A when misalignment occurs. FIG. 5 is a cross-sectional configuration diagram of a pixel of the photodetector shown in FIG. 1 (a cross-sectional view taken along the A-A section line shown in FIG. 4A). FIG. 6 is a cross-sectional configuration diagram of a pixel of the photodetector shown in FIG. 1 (a cross-sectional view taken along the B-B section line shown in FIG. 4A). FIG. 7 is a cross-sectional view at a first step illustrating a method for manufacturing a photodetector according to the first embodiment. FIG. 8 is a cross-sectional view at a second step. FIG. 9 is a cross-sectional view at a third step. FIG. 10 is a cross-sectional view at a fourth step. FIG. 11 is a cross-sectional view at a fifth step. FIG. 12 is a cross-sectional view at a sixth step. FIG. 13 is a cross-sectional view at a seventh step. FIG. 14 is a cross-sectional view at an eighth step. FIG. 15 is a cross-sectional view at a ninth step. FIG. 16 is a plan view corresponding to FIG. 4A of a pixel of a photodetector according to a second embodiment of the present disclosure. FIG. 17 is a cross-sectional view of the pixel of the photodetector shown in FIG. 16 (a cross-sectional view taken along the CC cutting line shown in FIG. 16). FIG. 18 is a cross-sectional view at a first step for explaining a method of manufacturing a photodetector according to the second embodiment. FIG. 19 is a cross-sectional view at a second step. FIG. 20 is a cross-sectional view at a third step. FIG. 21 is a cross-sectional view at a fourth step. FIG. 22 is a cross-sectional view at a fifth step. FIG. 23 is a cross-sectional view at a sixth step. FIG. 24 is a cross-sectional view at a seventh step. FIG. 25 is a cross-sectional view at an eighth step. FIG. 26 is a cross-sectional view at a ninth step. FIG. 27 is a cross-sectional view at a tenth step. Fig. 28 is a cross-sectional configuration diagram of a pixel of a photodetector according to a third embodiment of the present disclosure, corresponding to Fig. 5. Fig. 29 is an enlarged planar configuration diagram corresponding to Fig. 4A, in which a main part of a pixel of a photodetector according to a fourth embodiment of the present disclosure is enlarged. Fig. 30 is an enlarged planar configuration diagram corresponding to Fig. 29, in which a main part of a pixel of a photodetector according to a fifth embodiment of the present disclosure is enlarged.FIG. 31 is an enlarged plan view corresponding to FIG. 29 , enlarging a main portion of a pixel of a photodetector according to a sixth embodiment of the present disclosure. FIG. 32 is a plan view corresponding to FIG. 4A of a pixel of a photodetector according to a seventh embodiment of the present disclosure. FIG. 33 is a cross-sectional view (cross-sectional view taken along the D-D section line shown in FIG. 32 ) of the pixel of the photodetector shown in FIG. 32. FIG. 34 is a plan view corresponding to FIG. 4A of a pixel of a photodetector according to an eighth embodiment of the present disclosure. FIG. 35 is a plan view corresponding to FIG. 4A of a pixel of a photodetector according to a ninth embodiment of the present disclosure. FIG. 36 is a cross-sectional view illustrating a first step in a method for manufacturing a photodetector according to a tenth embodiment of the present disclosure. FIG. 37 is a cross-sectional view illustrating a second step. FIG. 38 is a cross-sectional view illustrating a third step. FIG. 39 is a cross-sectional view illustrating a fourth step. FIG. 40 is a cross-sectional view illustrating a fifth step. FIG. 41 is a cross-sectional view illustrating a first step in a method for manufacturing a photodetector according to an eleventh embodiment of the present disclosure. FIG. 42 is a cross-sectional view illustrating a second step. FIG. 43 is a cross-sectional view illustrating a third step. 44 is a cross-sectional view of a fourth process. FIG. 45 is a cross-sectional view of a first process for explaining a manufacturing method of a light detection device according to a twelfth embodiment. FIG. 46 is a cross-sectional view of a second process. FIG. 47 is a cross-sectional view of a third process. FIG. 48 is a cross-sectional view of a fourth process. FIG. 49 is a cross-sectional view of a fifth process. FIG. 50 is a cross-sectional view of a sixth process. FIG. 51 is a cross-sectional view of a seventh process. FIG. 52 is a cross-sectional view of an eighth process. FIG. 53 is a cross-sectional view of a ninth process. FIG. 54 is a cross-sectional view of a tenth process. FIG. 55 is a block diagram showing a configuration of an electronic device according to a thirteenth embodiment of the present disclosure. FIG. 56 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 57 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit. FIG. 58 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 59 is a block diagram showing an example of a functional configuration of a camera head and a CCU.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment will describe a first example in which the present technology is applied to a photodetector. In the present technology, the photodetector is one aspect of a semiconductor device. The first embodiment will describe the overall configuration of the photodetector, the pixel configuration, and the pixel circuit configuration. Furthermore, the first embodiment will describe a method for manufacturing the photodetector. 2. Second Embodiment The second embodiment will describe a second example in which the pixel configuration, pixel circuit configuration, and manufacturing method are changed in the photodetector according to the first embodiment. 3. Third Embodiment The third embodiment will describe a third example in which the pixel configuration is changed in the photodetector according to the first embodiment. 4. Fourth Embodiment The fourth embodiment will describe a fourth example in which the pixel configuration is changed in the photodetector according to the first embodiment. 5. Fifth Embodiment The fifth embodiment will describe a fifth example in which the pixel configuration is changed in the photodetector according to the fourth embodiment. 6. Sixth Embodiment The sixth embodiment will describe a sixth example in which the pixel configuration is changed in the photodetector according to the fifth embodiment. 7. Seventh Embodiment The seventh embodiment describes a seventh example in which the pixel configuration is changed in the photodetector device according to the fifth embodiment. 8. Eighth Embodiment The eighth embodiment describes an eighth example in which the pixel configuration is changed in the photodetector device according to the seventh embodiment. 9. Ninth Embodiment The ninth embodiment describes a ninth example in which the pixel configuration is changed in the photodetector device according to the seventh embodiment. 10. Tenth Embodiment The tenth embodiment describes a tenth example in which the pixel configuration and manufacturing method are changed in the photodetector device according to the first or second embodiment. 11. Eleventh Embodiment The eleventh embodiment describes an eleventh example in which the pixel configuration and manufacturing method are changed in the photodetector device according to the first or second embodiment. 12. Twelfth Embodiment The twelfth embodiment describes a twelfth example in which the manufacturing method is changed in the photodetector device according to the first embodiment. 13. Thirteenth Embodiment The thirteenth embodiment describes a thirteenth example in which the present technology is applied to an electronic device including a photodetector device according to any of the first to twelfth embodiments.14. Application Example to a Mobile Body This application example describes an example in which the present technology is applied to a vehicle control system, which is an example of a mobile body control system. 15. Application Example to an Endoscopic Surgery System This application example describes an example in which the present technology is applied to an endoscopic surgery system. 16. Other Embodiments

[0012] 1. First Embodiment A photodetector 1 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 15. FIG.

[0013] Here, the arrow X direction shown as appropriate in the drawings indicates, for convenience, one planar direction of the photodetector 1 placed on a flat surface. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates an upward direction perpendicular to the arrow X direction and the arrow Y direction. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are shown for convenience to facilitate understanding of the explanation, and do not limit the directions of the present technology.

[0014] [Configuration of Photodetector 1] (1) Overall Configuration of Photodetector 1 Fig. 1 shows an example of a system configuration of a photodetector 1 according to a first embodiment. The photodetector 1 is one type of semiconductor device. Here, the photodetector 1 is constructed as a CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging device. The solid-state imaging device detects light L (see Fig. 5) incident from the outside, converts the detected light L into electric charges, and generates an image such as a still image or a moving image based on the converted electric charges.

[0015] The photodetector 1 includes a pixel region (pixel array section) 100 having a plurality of pixels 10 regularly arranged two-dimensionally within a plane in the directions of arrows X and Y, and peripheral circuits.

[0016] As will be explained later, the pixel 10 includes a photoelectric conversion element PD (see FIG. 3) and a transfer transistor TR (see FIG. 3). The photoelectric conversion element PD is configured by, for example, a photodiode. The photoelectric conversion element PD converts light L into electric charges. The transfer transistor TR transfers the electric charges converted by the photoelectric conversion element PD. In addition, a pixel circuit 20 (see FIG. 3) is electrically connected to the pixel 10. The pixel circuit 20 reads out the electric charges converted in the pixel 10.

[0017] The peripheral circuits are configured to include a vertical drive circuit VD, a column signal processing circuit CS, a horizontal drive circuit HD, an output circuit Out, a control circuit CC, and the like.

[0018] The control circuit CC receives an input clock and data instructing the operation mode, etc., and outputs data such as internal information of the photodetector 1. That is, the control circuit CC generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. These signals are then input to the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, etc.

[0019] The vertical drive circuit VD is configured, for example, by a shift register. The vertical drive circuit VD selects a pixel drive line Ld and supplies a pulse to the selected pixel drive line Ld to drive the pixels 10. The pixels 10 are driven row by row. That is, the vertical drive circuit VD sequentially selects and scans each pixel 10 in the pixel region 100 row by row in the vertical direction. Signal charges generated in the photoelectric conversion elements of each pixel 10 according to the amount of light received are supplied as pixel signals to the column signal processing circuit CS via the vertical signal lines Lv.

[0020] The column signal processing circuit CS is arranged, for example, for each column of pixels 10. The column signal processing circuit CS performs signal processing such as noise removal on signals output from one row of pixels 10 for each pixel column. That is, the column signal processing circuit CS performs signal processing such as CDS (Correlated Double Sampling) that removes fixed pattern noise specific to the pixels 10, signal amplification, and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit CS and the horizontal signal line Lh.

[0021] The horizontal drive circuit HD is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits CS in turn, and outputs pixel signals from each of the column signal processing circuits CS to the horizontal signal line Lh.

[0022] The output circuit Out processes and outputs signals sequentially supplied from each of the column signal processing circuits CS through the horizontal signal line Lh. For example, the output circuit Out may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal In exchanges signals between the photodetector 1 and the outside.

[0023] (2) Device Configuration of Light-Detecting Device 1 FIG. 2 shows an example of a schematic exploded planar configuration of the light-detecting device 1 shown in FIG. 1. The light-detecting device 1 has a three-layer structure in which a first substrate 1A, a second substrate 1B, and a third substrate 1C are stacked and bonded together. Here, the third substrate 1C, the second substrate 1B, and the first substrate 1A are stacked in order in the direction of the arrow Z. Note that in the first embodiment and in embodiments that will be described later based on the first embodiment, the light-detecting device 1 has a three-layer structure. In the second embodiment and in embodiments that will be described later based on the second embodiment, the light-detecting device 1 has a two-layer structure in which the first substrate 1A and the second substrate 1B are combined into a single substrate.

[0024] The first substrate 1A is formed in a rectangular shape when viewed from the direction of the arrow Z (hereinafter simply referred to as "in a plan view"). More specifically, the first substrate 1A is formed in a square shape here. The first substrate 1A includes a semiconductor substrate (see reference numeral 30 in FIGS. 5 and 6 ) made of, for example, single-crystal silicon. A photoelectric conversion element PD and a transfer transistor TR that constitute a pixel 10 are disposed on the semiconductor substrate of the first substrate 1A. A pixel region 100 is disposed over substantially the entire area of ​​the first substrate 1A. As described above, a plurality of pixels 10 are arranged in the pixel region 100. In other words, the first substrate 1A constitutes a photodetection surface as an imaging surface that captures an image. Here, "when viewed from the direction of the arrow Z (in a plan view)" corresponds to "when viewed from the first surface side to the second surface side" according to the present technology.

[0025] The second substrate 1B is formed in a rectangular shape similar to the first substrate 1A in plan view and has the same planar size as the first substrate 1A. Like the first substrate 1A, the second substrate 1B includes a semiconductor substrate made of, for example, single-crystal silicon. A plurality of pixel transistors (not shown) constituting a pixel circuit 20 are arranged on the semiconductor substrate of the second substrate 1B. While the number of pixel transistors is not particularly limited, in the first embodiment, one pixel circuit 20 is arranged for four pixels 10. The pixel transistors constituting the pixel circuit 20 will be described later. The second substrate 1B also includes pixel drive wiring Ld and vertical signal lines Lv that overlap the pixel region 100 in plan view and extend through the pixel region 100 in the X direction and the Y direction, respectively. In the case of a photodetector 1 having a two-layer structure, the pixel circuit 20 is arranged on a substrate that combines the first substrate 1A and the second substrate 1B.

[0026] The third substrate 1C is formed in a rectangular shape in plan view similar to that of the first substrate 1A, and is formed to have the same planar size as that of the first substrate 1A. Like the first substrate 1A, the third substrate 1C includes a semiconductor substrate formed of, for example, single crystal silicon. Peripheral circuits are disposed on the semiconductor substrate of the third substrate 1C. As described above, the peripheral circuits include the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, output circuit Out, control circuit CC, etc.

[0027] In the first embodiment, each circuit in the peripheral circuit is a logic circuit. The logic circuit is constructed to include one or more semiconductor elements selected from a transistor, a capacitor, and a resistor. The transistor is an insulated gate field effect transistor (IGFET). At least one pair of main electrodes of the transistor has a surface coated with CoSi ２ A low resistance layer is formed using a salicide (self-aligned silicide) process of NiSi, etc. For example, the resistance value of the low resistance layer is smaller than the resistance value of the semiconductor layer.

[0028] 3 shows an example of the circuit configuration of the pixels 10 and pixel circuits 20 of the photodetector 1. In the first embodiment, four pixels 10 are electrically connected to one pixel circuit 20, and the four pixels 10 share one pixel circuit 20. In other words, the electric charges converted from light L in each of the four pixels 10 are read out in one pixel circuit 20.

[0029] Each pixel 10 includes a photoelectric conversion element PD and a transfer transistor TR, configured as a series circuit of the two. More specifically, the photoelectric conversion element PD is configured as a photodiode. The photodiode includes an anode region and a cathode region. Meanwhile, the transfer transistor TR is an IGFET. The IGFET includes a pair of main electrodes (a source region and a drain region) and a gate electrode. The anode region of the photoelectric conversion element PD is electrically connected to a reference voltage GND. The cathode region is electrically connected to one main electrode of the transfer transistor TR. The other main electrode of the transfer transistor TR is electrically connected to one end of a floating diffusion FD. A control signal for controlling conduction or non-conduction is input to the gate electrode.

[0030] As described above, four pixels 10 are arranged for one pixel circuit 20, and therefore, the identification numbers 1, 2, 3, and 4 are added to the end of the reference numerals of the components within the pixels 10 to distinguish them from one another. For example, one of the four pixels 10 is configured to include a photoelectric conversion element PD1 and a transfer transistor TR1. Note that, if there is no need to distinguish them from one another, no identification number is added.

[0031] Although a detailed structure will be described later, in the first embodiment, the transfer transistor TR is configured as a vertical transistor. That is, the transfer transistor TR is configured as a vertical IGFET. The transfer transistor TR corresponds to a "transfer transistor" according to the present technology, and corresponds to a "first insulated gate field effect transistor (IGFET)" according to the present technology in the semiconductor device.

[0032] The pixel circuit 20 is constructed of a plurality of pixel transistors. Here, the pixel transistor includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. As will be described in a second embodiment below, each transistor of the pixel transistor is configured by a lateral IGFET. Here, the pixel transistor corresponds to the "pixel transistor" according to the present technology.

[0033] One main electrode of the reset transistor RST is electrically connected to the other end of the floating diffusion FD, and the other main electrode is electrically connected to the power supply voltage VDD. A reset signal is input to the gate electrode. When the reset transistor RST is turned on, it resets the floating diffusion FD to a potential corresponding to the power supply voltage VDD.

[0034] One main electrode of the amplifier transistor AMP is electrically connected to one main electrode of the select transistor SEL, and the other main electrode is electrically connected to the power supply voltage VDD. One main electrode of the reset transistor RST and the other end of the floating diffusion FD are electrically connected to the gate electrode of the amplifier transistor AMP. The amplifier transistor AMP forms a source follower amplifier. In other words, the amplifier transistor AMP generates a pixel signal according to the charge transferred through the floating diffusion FD.

[0035] The other main electrode of the selection transistor SEL is electrically connected to a vertical signal line Lv. A selection signal is input to the gate electrode of the selection transistor SEL. The selection transistor SEL outputs the generated pixel signal to the vertical signal line Lv.

[0036] (4) Device Configuration of Pixel 10 Fig. 4A shows an example of the planar configuration of the pixel 10 of the photodetector 1. Fig. 5 and Fig. 6 each show an example of the cross-sectional configuration of the pixel 10. As described above, the photodetector 1 according to the first embodiment has a three-layer structure. The pixel 10 is disposed on a semiconductor substrate 30 that forms a first base 1A that constitutes the three-layer structure.

[0037] In the first embodiment, some or all of the pixels 10 in the pixel region 100 are configured as phase difference detection pixels. As shown in Fig. 4A , the pixels 10 are configured of a first pixel 10A and a second pixel 10B arranged adjacent to each other in the direction of the arrow X.

[0038] In a plan view, the first pixel 10A is formed in a rectangular shape with its short side aligned in the direction of the arrow X and its long side aligned in the direction of the arrow Y. A pixel isolation region 31 is disposed around the first pixel 10A. Similarly, the second pixel 10B is formed in a rectangular shape with its short side aligned in the direction of the arrow X and its long side aligned in the direction of the arrow Y. A pixel isolation region 31 is disposed around the second pixel 10B.

[0039] The pixel isolation region 31 includes a groove 311 and a filler 312. The groove 311 is formed by digging in the thickness direction of the semiconductor substrate 30 from a surface 30A of the semiconductor substrate 30 toward another surface 30B opposite the surface 30A. Here, the surface 30A corresponds to the "second surface" according to the present technology. On the other hand, the surface 30B corresponds to the "first surface" according to the present technology. The grooves 311 extend in the direction of arrow X and are arranged at regular intervals in the direction of arrow Y, and also extend in the direction of arrow Y and are arranged at regular intervals in the direction of arrow X. That is, in a plan view, the grooves 311 are formed in a lattice shape. Therefore, in the first embodiment, the planar shape of the pixel 10 is formed in a rectangular shape. More specifically, in the first embodiment, the planar shape of the pixel 10 is formed in a square shape. The filler 312 is filled in the grooves 311. The filler 312 is made of, for example, SiO 2 which can optically and electrically separate adjacent pixels 10 . ２ Insulating materials such as

[0040] The first pixel 10A of the pixel 10 includes a photoelectric conversion element PD and a transfer transistor TR. Similarly, the second pixel 10B includes a photoelectric conversion element PD and a transfer transistor TR. The first pixel 10A and the second pixel 10B are each formed in an axisymmetric shape with respect to a center line CL extending in the direction of the arrow Y shown for convenience.

[0041] The pixel 10 configured as a phase difference detection pixel can interpolate light detection information (image information) and can realize autofocus.

[0042] (4-1) Device Configuration of Photoelectric Conversion Element PD Although detailed structural illustration and description are omitted, the photoelectric conversion element PD is disposed inside the semiconductor substrate 30 in an area surrounded by pixel isolation regions 31 in the directions of arrows X and Y. In other words, the pixel 10 is constructed in the area surrounded by the pixel isolation region 31.

[0043] The photoelectric conversion element PD includes a p-type semiconductor region 30p as an anode region and an n-type semiconductor region 30n as a cathode region. A pinning region (not shown) having a higher impurity density than the p-type semiconductor region 30p and the same conductivity type as the p-type semiconductor region 30p is disposed on the surface of the p-type semiconductor region 30p along the pixel isolation region 31.

[0044] (4-2) Device Configuration of Transfer Transistor TR The transfer transistor TR is disposed in the pixel isolation region 31, closer to the photoelectric conversion element PD in the direction of the arrow Y than the photoelectric conversion element PD. In each of the first pixel 10A and the second pixel 10B, the transfer transistor TR is disposed in a similar position. As shown in FIGS. 4A to 6 , the transfer transistor TR includes, as its main components, a channel formation region 30c, a gate insulating film 5, a gate electrode 6, and a pair of main electrodes (source region and drain region).

[0045] The gate insulating film 5 and gate electrode 6 of the transfer transistor TR are disposed in the trench 4. Therefore, a channel formation region 30c is formed in the p-type semiconductor region 30p of the semiconductor substrate 30 along the bottom surface of the trench 4 and the sidewall of the trench lower portion 4A. The trench 4 is disposed from the surface 30B toward the surface 30A of the semiconductor substrate 30. Here, when viewed in the direction of arrow X or the direction of arrow Y (hereinafter simply referred to as "side view"), the cross-sectional shape of the trench 4 is formed as a tapered shape with a bottom dimension smaller than the opening dimension on the surface 30B side. Furthermore, in a plan view, the opening shape of the trench 4 is formed as a rectangle. Note that the cross-sectional shape of the trench 4 may be formed as a rectangle with the opening dimension on the surface 30B side and the bottom dimension equal. Alternatively, the cross-sectional shape of the trench 4 may be formed as an inverted tapered shape with the bottom dimension larger than the opening dimension on the surface 30B side. Furthermore, the opening shape of the trench 4 may be formed as a triangle, a polygon with pentagons or more, a circle, or an ellipse.

[0046] The gate insulating film 5 is disposed along the bottom surface of the trench lower portion 4A and the sidewall of the trench lower portion 4A. The gate insulating film 5 is made of, for example, SiO ２ When this insulating material is used, the gate insulating film 5 is formed to have a thickness t1 in a direction from the sidewall of the trench lower portion 4A toward the center of the trench lower portion 4A, which is, for example, 1 nm or more and 20 nm or less.

[0047] The gate electrode 6 is buried in the trench lower portion 4A with a gate insulating film 5 interposed therebetween. The gate electrode 6 is made of a gate electrode material such as polycrystalline silicon. When polycrystalline silicon is used as the gate electrode material, impurities that reduce the resistance value are added to the polycrystalline silicon.

[0048] One of the pair of main electrodes is electrically connected to the cathode region of the photoelectric conversion element PD. In other words, the cathode region is used as one main electrode of the transfer transistor TR. Meanwhile, the other of the pair of main electrodes is electrically connected to the floating diffusion FD. Similarly, the floating diffusion FD is used as the other main electrode of the transfer transistor TR.

[0049] (4-3) Device Configuration of Floating Diffusion FD Within the region surrounded by the pixel isolation region 31, a floating diffusion FD is disposed in the direction of arrow Y of the photoelectric conversion element PD, with a transfer transistor TR interposed therebetween. The floating diffusion FD is formed by an n-type semiconductor region 30n disposed on the surface 30B side of the semiconductor substrate 30. This n-type semiconductor region 30n is electrically isolated from the p-type semiconductor region 30p by a pn junction. In the first pixel 10A, the floating diffusion FD is disposed at a position offset in the direction of arrow X from the transfer transistor TR. In the second pixel 10B, the floating diffusion FD is disposed at a position offset in the opposite direction from the direction of arrow X from the transfer transistor TR.

[0050] 4A, 5, and 6, the electrode 12A is electrically connected to the gate electrode 6 of the transfer transistor TR. The electrode 12A is embedded in the upper portion 4B of the trench 4 with a sidewall insulator 7 interposed therebetween.

[0051] More specifically, an interlayer insulator 11 is disposed on the surface 30B of the semiconductor substrate 30. A connection hole 11H is formed in the interlayer insulator 11, leading to the opening of the trench 4. A wiring 12 is disposed in this connection hole 11H, and a portion of the wiring 12 extends to form an electrode 12A in the trench 4. In the first embodiment, the wiring 12 is at least a plug wiring disposed in the connection hole 11H, or a connection hole wiring extending from a wiring disposed on the opposite side of the interlayer insulator 11 from the surface 30A. The wiring 12 and the electrode 12A are each formed, for example, from a composite material in which a barrier metal and a refractory metal are laminated. Examples of the barrier metal that can be used include Ti, TiN, or a composite material thereof. Examples of the refractory metal that can be used include W. The wiring 12 is also electrically connected to the floating diffusion FD.

[0052] (4-5) Device Configuration of Sidewall Insulator 7 The sidewall insulator 7 is disposed on the sidewall of the trench 4 in the trench upper portion 4B. The thickness t2 of the sidewall insulator 7 in the same direction is thicker than the thickness t1 of the gate insulating film 5 of the transfer transistor TR. The thickness t2 of the sidewall insulator 7 is set to, for example, 16 nm or more and 80 nm or less. In the first embodiment, the sidewall insulator 7 is formed of a composite material in which a first sidewall insulator 7A and a second sidewall insulator 7B are sequentially stacked from the sidewall of the trench 4. The first sidewall insulator 7A is formed along the sidewall of the trench upper portion 4B. The first sidewall insulator 7A is made of, for example, SiO ２ The first sidewall insulator 7A is formed of an insulating material such as SiN. The thickness of the first sidewall insulator 7A is, for example, 1 nm or more and 30 nm or less. The second sidewall insulator 7B is formed on the sidewall of the upper portion 4B of the trench with the first sidewall insulator 7A interposed therebetween. The second sidewall insulator 7B is formed of an insulating material such as SiN that has an etching selectivity with respect to the first sidewall insulator 7A. The thickness of the second sidewall insulator 7B is, for example, 15 nm or more and 50 nm or less.

[0053] Furthermore, the sidewall insulator 7 is formed in a self-aligned manner with respect to the trench 4. That is, the thickness t2 of the sidewall insulator 7 is a constant value corresponding to the deposited thickness without being affected by misalignment in the manufacturing process. In other words, the distance dimension of the floating diffusion FD, which is separated from the electrode 12A by the sidewall insulator 7, is a constant value without variation. Since the sidewall insulator 7 is formed in a self-aligned manner with respect to the trench 4, the electrode 12A is consequently formed in a self-aligned manner with respect to both the trench 4 and the sidewall insulator 7.

[0054] Furthermore, the depth (depth dimension) h2 of the sidewall insulator 7 from the surface 30B toward the surface 30A is greater than or equal to the depth (depth dimension) h3 of the floating diffusion FD in the same direction (h2≧h3). Depth h3 is the pn junction depth of the n-type semiconductor region 30n. Naturally, the depth (depth dimension) h1 of the groove 4 is greater than the depth h2 (h1>h2≧h3). Depth h1 is, for example, 350 nm or more and 450 nm or less. Depth h2 is, for example, 150 nm or more and 250 nm or less. Depth h3 is, for example, 130 nm or more and 200 nm or less.

[0055] In the first embodiment, the floating diffusion FD is disposed at a position spaced apart from the sidewall insulator 7 or the sidewall of the trench 4. In the present technology, the floating diffusion FD may be disposed in contact with the sidewall insulator 7 or the sidewall of the trench 4. In this case, the floating diffusion FD is formed by self-alignment with the trench 4 and the sidewall insulator 7.

[0056] (5) Configuration of Optical Filter 140 In the pixel 10, an optical filter 140 and an optical lens 150 are sequentially disposed on the surface 30A of the semiconductor substrate 30 with a protective film 130 interposed therebetween. The optical filter 140 is formed, for example, as a red color filter that transmits light L in the red light band, a green color filter that transmits light L in the green light band, or a blue color filter that transmits light L in the blue light band. The optical filter 140 may also be a filter that transmits near-infrared light. The optical filter 140 is formed, for example, from a resin material to which an organic pigment is added. Examples of the resin material that can be used include acrylic resins and styrene-based resins.

[0057] (6) Configuration of Optical Lens 150 In side view, the optical lens 150 is disposed for each pixel 10 or for each set of multiple pixels 10. In side view, the optical lens 150 is formed in a curved shape that protrudes in the direction of the arrow Z. The optical lens 150 is formed, for example, from a light-transmitting resin material. Note that, although not shown in the drawings or in detailed description, an anti-reflection film may be formed on the optical lens 150. The optical lens 150 is connected to other adjacent optical lenses 150, and multiple optical lenses 150 are formed integrally. The optical lens 150 is configured as an on-chip lens.

[0058] It should be noted that illustration and detailed description of the pixel circuit 200 disposed on the second substrate 1B of the photodetector 1 and the peripheral circuit disposed on the third substrate 1C will be omitted.

[0059] 7 to 15 show an example of cross-sectional views of steps in a method for manufacturing the photodetector 1, explaining each step of the method for manufacturing the photodetector 1. The method for manufacturing the photodetector 1 according to the first embodiment is mainly a method for manufacturing the transfer transistor TR of the pixel 10. The method for manufacturing the photodetector 1 is as follows. First, a semiconductor substrate 30 is prepared (see FIG. 7). This semiconductor substrate 30 is in the state of a semiconductor wafer before a dicing step, and has a pixel isolation region 31 and a photoelectric conversion element PD (see FIGS. 4A, 5, and 6) formed thereon.

[0060] Next, a mask 300 is formed on the surface 30B of the semiconductor substrate 30 (see FIG. 7). The mask 300 is formed by sequentially stacking, for example, a mask 301, a mask 302, and a mask 303. The mask 301 is made of, for example, SiO ２ The mask 302 is made of, for example, SiN. The mask 303 is made of, for example, photoresist. An opening is formed in the mask 300 in a region where the gate electrode 6 of the transfer transistor TR is to be formed (see FIG. 7).

[0061] 7, a mask 300 is used to form a trench 4 from the surface 30B toward the surface 30A of the semiconductor substrate 30. Anisotropic etching such as RIE (Reactive Ion Etching) is used to form the trench 4. As shown in FIG. 8, the mask 300 is removed.

[0062] 9, a gate electrode material 6A is formed on the sidewalls and bottom surface of the trench 4 with a gate insulating film 5 interposed therebetween. The gate insulating film 5 is formed by, for example, thermal oxidation. ２ The gate electrode material 6A is formed by using, for example, a CVD (Chemical Vapor Deposition) method, and is made of polycrystalline silicon in this example.

[0063] An etch-back process is performed on the entire surface 30B of the semiconductor substrate 30. For example, anisotropic etching is used for the etch-back process. As a result, a gate electrode 6 is formed from the gate electrode material 6A, as shown in FIG. 10 . The gate electrode 6 is embedded in the lower portion 4A of the trench 4, and is formed on the bottom and sidewalls of the trench 4 with the gate insulating film 5 interposed therebetween.

[0064] 11 , a sidewall insulator 7 is formed on the entire surface 30B side of the semiconductor substrate 30. The sidewall insulator 7 is formed by stacking a first sidewall insulator 7A and a second sidewall insulator 7B having an etching selectivity with respect to the first sidewall insulator 7A. The first sidewall insulator 7A and the second sidewall insulator 7B are each formed by, for example, CVD.

[0065] An etch-back process is performed on the entire surface 30B side of the semiconductor substrate 30. For example, anisotropic etching is used for the etch-back process. As a result, as shown in FIG. 12 , a sidewall insulator 7 is formed on the sidewall of the trench 4 in the upper portion 4B of the trench 4. The sidewall insulator 7 is formed in a self-aligned manner with the trench 4, and therefore has a uniform thickness t2. Here, the sidewall insulator 7 is formed by first etching the second sidewall insulator 7B by the etch-back process, and then removing the first sidewall insulator 7A using the second sidewall insulator 7B as a mask. For example, isotropic etching is used to remove the first sidewall insulator 7A. As a result, the second sidewall insulator 7B can be etched using the first sidewall insulator 7A as an etching stopper.

[0066] 13, a first interlayer insulator 11A is formed over the entire surface 30B side of the semiconductor substrate 30. The first interlayer insulator 11A is made of an insulating material such as SiN. Subsequently, as shown in FIG. 14, a second interlayer insulator 11B is formed on the first interlayer insulator 11A, and the interlayer insulator 11 is formed by stacking the first interlayer insulator 11A and the second interlayer insulator 11B. The second interlayer insulator 11B is made of, for example, SiO ２ Insulating materials such as

[0067] 15, a contact hole 11H is formed in the interlayer insulator 11. When the contact hole 11H is formed, the surface of the gate electrode 6 of the transfer transistor TR can be exposed in the trench 4.

[0068] 4A, 5, and 6, a wiring 12 is formed at least in the connection hole 11H, and an electrode 12A is formed on the upper portion 4B of the groove 4. The electrode 12A is electrically connected to the gate electrode 6 of the transfer transistor TR, and is formed by self-alignment with the groove 4 and the sidewall insulator 7. The wiring 12 and the electrode 12A are formed by, for example, a sputtering method.

[0069] When this series of manufacturing steps is completed, the photodetector 1 according to the first embodiment is completed.

[0070] [Operation and Effect] As shown in FIGS. 4A, 5, and 6, the photodetector (semiconductor device) 1 according to the first embodiment includes a trench 4, a transfer transistor TR as a first IGFET, a sidewall insulator 7, and an electrode 12A. The trench 4 is disposed from the surface 30B of the semiconductor substrate 30 toward the surface 30A opposite the surface 30B. The transfer transistor TR is disposed in a trench lower portion 4A and has a gate electrode 6 as a first gate electrode embedded in the sidewall of the trench 4 with a gate insulating film 5 as a first gate insulating film interposed therebetween. The sidewall insulator 7 is disposed on the sidewall of the trench 4 in the trench upper portion 4B and has a thickness greater than that of the gate insulating film 5 in the same direction. Furthermore, the sidewall insulator 7 is formed in a self-aligned manner with the trench 4. The electrode 12A is embedded in the trench upper portion 4B of the trench 4 with the sidewall insulator 7 interposed therebetween and is electrically connected to the gate electrode 6. In the photodetector 1 configured in this manner, the sidewall insulator 7 is formed around the side surface of the electrode 12A, and the thickness t2 of the sidewall insulator 7 is uniform. This effectively suppresses or prevents the influence of the field effect from the electrode 12A on the semiconductor substrate 30 through the sidewall insulator 7, and also effectively suppresses or prevents variations in the influence of the field effect itself. In the photodetector 1, the floating diffusion FD is disposed close to the periphery of the electrode 12A, effectively suppressing or preventing the influence of the field effect from the electrode 12A on the floating diffusion FD. This stabilizes the transfer efficiency from the photoelectric conversion element PD to the floating diffusion FD by the transfer transistor TR, thereby improving pixel characteristics. The floating diffusion FD can be formed in contact with the sidewall insulator 7 and self-aligned with the sidewall insulator 7. Furthermore, the thickness t2 of the sidewall insulator 7 is made uniform, and there is no margin for misalignment in the distance between the electrode 12A and the floating diffusion FD, so the distance can be reduced, which reduces the area occupied by the pixel 10 and allows the number of pixels 10 to be increased.

[0071] Furthermore, in the photodetector 1, as shown in FIGS. 4A , 5 , and 6 , the electrode 12A is formed in a self-aligned manner with respect to the groove 4 and the sidewall insulator 7. This allows the area occupied by the pixel 10 to be further reduced, and the number of pixels 10 to be further increased. FIGS. 4B and 4C show an example of a planar configuration of the main parts of the photodetector when misalignment occurs. FIG. 4B shows a state in which the electrode 12A is misaligned with respect to the groove 4 in the directions opposite to the arrow X and arrow Y. FIG. 4C shows a state in which the electrode 12A is misaligned with respect to the groove 4 in the directions opposite to the arrow X and arrow Y. In either state, the sidewall insulator 7 is formed in a self-aligned manner with respect to the groove 4, and the electrode 12A is guided to this sidewall insulator 7. As a result, the connection positions of the electrode 12A and the gate electrode 6 are determined in a self-aligned manner with respect to the groove 4.

[0072] 4A, 5, and 6, the photodetector 1 includes an interlayer insulator 11, a connection hole 11H, and wiring 12. The interlayer insulator 11 is disposed on the surface 30B of the semiconductor substrate 30. The connection hole 11H is disposed in the interlayer insulator 11 and communicates with the opening of the groove 4. The wiring 12 is disposed at least within the connection hole 11H, and a portion of the wiring 12 serves as an electrode 12A. With the photodetector 1 configured in this manner, it is not necessary to provide a pad on the electrode 12A that serves as a connection region with the wiring 12 and that has a larger diameter than the electrode 12A. This eliminates the need to further reduce the area occupied by the pixel 10 and further increase the number of pixels 10.

[0073] 5 and 6, in the photodetector 1, the dimension (depth h2) of the sidewall insulator 7 from the surface 30B toward the surface 30A is equal to or greater than the dimension (depth h3) of the floating diffusion FD in the same direction. Therefore, the sidewall insulator 7 is disposed over the entire area between the electrode 12A and the floating diffusion FD, so that the influence of the electric field effect from the electrode 12A to the floating diffusion FD can be more effectively suppressed or prevented.

[0074] 4A, 5, and 6, in the photodetector 1, the side periphery of the gate electrode 6 is larger than the side periphery of the electrode 12A in plan view. This allows the width (gate width or channel width) of the channel formation region 30c of the transfer transistor TR to be increased, thereby further improving the transfer efficiency.

[0075] A manufacturing method of a photodetector 1 (semiconductor device) according to the first embodiment includes the following steps. First, a trench 4 is formed from a surface 30B of a semiconductor substrate 30 toward a surface 30A opposite to the surface 30B. Next, a gate electrode 6 is formed on the sidewalls of the trench 4 in a trench lower portion 4A with a gate insulating film 5 interposed therebetween, thereby forming a transfer transistor TR. Next, a sidewall insulator 7 is formed on the sidewalls of the trench 4 in an upper portion 4B of the trench 4 by self-alignment with the trench 4, with a thickness t2 greater in the same direction than a thickness t1 of the gate insulating film 5. Next, an electrode 12A electrically connected to the gate electrode 6 is formed on the trench upper portion 4B of the trench 4 with the sidewall insulator 7 interposed therebetween. According to the manufacturing method of a photodetector 1 including these steps, a photodetector 1 that can achieve the above-described effects can be easily manufactured.

[0076] 2. Second embodiment A photodetector 1 according to a second embodiment will be described using Figures 16 to 27. In the second embodiment and the following embodiments, components that are the same as or substantially the same as components of the photodetector 1 according to the first embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0077] [Device Configuration of Photodetector 1] Fig. 16 shows an example of the planar configuration of a pixel 10 of the photodetector 1. Fig. 17 shows an example of the cross-sectional configuration of the pixel 10. The photodetector 1 according to the second embodiment has a two-layer structure. The pixel 10 is disposed on a semiconductor substrate 30 having a first base 1A and a second base 1B as shown in Fig. 2 described above as a single base. The basic components are the same as or substantially the same as the components of the photodetector 1 according to the first embodiment. In the photodetector 1, the pixel transistor Tr of the pixel circuit 20 shown in Figs. 2 and 3 described above is disposed on the surface 30B side of the semiconductor substrate 30.

[0078] A pixel transistor Tr is disposed in the first pixel 10A and the second pixel 10B that constitute the pixel 10. The pixel transistor Tr is one or more transistors selected from a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL that constitute the pixel circuit 20.

[0079] The pixel transistor Tr is configured by a lateral IGFET and includes a channel formation region 30c, a gate insulating film 50, a gate electrode 60, and a pair of main electrodes.

[0080] The channel formation region 30c is formed by a p-type semiconductor region 30p on the surface 30B side of the semiconductor substrate 30. A gate insulating film 50 is disposed in the channel formation region 30c. A gate electrode 60 is disposed in the channel formation region 30c with the gate insulating film 50 interposed therebetween. A pair of main electrodes is formed by an n-type semiconductor region 80 disposed on the surface 30B side of the semiconductor substrate 30. Here, the pixel transistor Tr corresponds to a "second IGFET" according to the present technology. The gate insulating film 50 corresponds to a "second gate insulating film" according to the present technology. The gate electrode 60 corresponds to a "second gate electrode" according to the present technology. Furthermore, the n-type semiconductor region 80 serving as a pair of main electrodes is formed as the same conductive layer as the n-type semiconductor region 30n of the floating diffusion FD.

[0081] 18 to 27 show an example of cross-sectional views illustrating each step of the method for manufacturing the photodetector 1. The method for manufacturing the photodetector 1 according to the second embodiment is an example in which a method for manufacturing the pixel transistor Tr of the pixel circuit 20 is added to the method for manufacturing the photodetector 1 according to the first embodiment. The method for manufacturing the photodetector 1 is as follows.

[0082] First, similarly to the manufacturing method of the photodetector 1 according to the first embodiment (hereinafter simply referred to as the "first manufacturing method"), a semiconductor substrate 30 is prepared (see FIG. 18). This semiconductor substrate 30 is in the state of a semiconductor wafer before a dicing process, and has pixel isolation regions 31 and photoelectric conversion elements PD formed thereon.

[0083] Next, similarly to the first manufacturing method, a mask 300 is formed on the surface 30B of the semiconductor substrate 30 (see FIG. 18).

[0084] 7 of the first manufacturing method, grooves 4 are formed from front surface 30B toward front surface 30A of semiconductor substrate 30 using mask 300, as shown in Fig. 18. Thereafter, mask 300 is peeled off, as shown in Fig. 19, as in the step of the first manufacturing method shown in Fig. 8.

[0085] 9 of the first manufacturing method, as shown in Fig. 20, a gate electrode material 6A is formed on the sidewalls and bottom surface of the trench 4 with the gate insulating film 5 interposed therebetween. Then, in the region where the pixel transistor Tr is to be formed, a gate insulating film 50 and the gate electrode material 6A are formed on the surface 30B of the semiconductor substrate 30. The gate insulating film 50 is formed in the same insulating layer as the gate insulating film 5 and is made of the same insulating material. The gate electrode material 6A is in the same conductive layer and is made of the same conductive material both in the trench 4 and on the surface 30B.

[0086] 21, a mask 305 is formed on the gate electrode material 6A in the region where the pixel transistor Tr is to be formed. The mask 305 is made of, for example, photoresist.

[0087] 10 of the first manufacturing method, as shown in FIG. 22, an etch-back process is performed on the entire surface 30B side of the semiconductor substrate 30. As a result, a gate electrode 6 is formed from the gate electrode material 6A in the trench lower portion 4A within the trench 4. The gate electrode 6 is embedded in the trench lower portion 4A of the trench 4, and is formed with a gate insulating film 5 interposed on each of the bottom surface and sidewalls of the trench 4. Furthermore, by the same process, a gate insulating film 50 and a gate electrode 60 are formed in the formation region of the pixel transistor Tr. Thereafter, the mask 305 is peeled off.

[0088] 11 of the first manufacturing method, sidewall insulator 7 is formed on the entire surface of front surface 30B of semiconductor substrate 30, as shown in Fig. 23. Similar to the process shown in Fig. 12 of the first manufacturing method, an etch-back process is performed on the entire surface of front surface 30B of semiconductor substrate 30. As a result, as shown in Fig. 24, sidewall insulator 7 is formed on the sidewall of trench 4 in upper portion 4B of trench 4. Sidewall insulator 7 is formed in self-alignment with trench 4, and therefore has a uniform thickness t2. Furthermore, in the region where pixel transistor Tr is formed, sidewall insulator 7 is formed on the sidewall of gate electrode 60 in self-alignment with gate electrode 60.

[0089] 13 of the first manufacturing method, as shown in Fig. 25, first interlayer insulator 11A is formed on the entire surface of front surface 30B of semiconductor substrate 30. Subsequently, as shown in Fig. 26, second interlayer insulator 11B is formed on first interlayer insulator 11A, and interlayer insulator 11 is formed by stacking first interlayer insulator 11A and second interlayer insulator 11B.

[0090] 15 of the first manufacturing method, a contact hole 11H is formed in the interlayer insulator 11, as shown in Fig. 27. When the contact hole 11H is formed, the surface of the gate electrode 6 of the transfer transistor TR can be exposed in the trench 4. Furthermore, the surface of the gate electrode 60 of the pixel transistor Tr can be exposed.

[0091] 17 , a wiring 12 is formed at least in the connection hole 11H, and an electrode 12A is formed in the groove upper portion 4B of the groove 4. The electrode 12A is electrically connected to the gate electrode 6 of the transfer transistor TR, and is formed in self-alignment with the groove 4 and the sidewall insulator 7. Furthermore, the wiring 12 is electrically connected to the gate electrode 60 of the pixel transistor Tr.

[0092] When this series of manufacturing steps is completed, the photodetector 1 according to the first embodiment is completed.

[0093] [Operational Effects] According to the photodetector 1 and manufacturing method of the second embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 and manufacturing method of the first embodiment.

[0094] 16 and 17, the photodetector 1 also includes a pixel transistor Tr that constitutes a pixel circuit 20 on the surface 30B of the semiconductor substrate 30 in a region different from the transfer transistor TR. The pixel transistor Tr has a gate electrode 60 disposed with a gate insulating film 50 interposed therebetween. In the method for manufacturing the photodetector 1, as shown in FIGS. 20 to 22, the gate insulating film 50 of the pixel transistor Tr is formed in the same insulating layer and from the same insulating material as the gate insulating film 5 of the transfer transistor TR. Similarly, the gate electrode 60 of the pixel transistor Tr is formed in the same conductive layer and from the same conductive material as the gate electrode 6 of the transfer transistor TR. Furthermore, the sidewall insulators 7 are formed in the same process for the transfer transistor TR and the pixel transistor Tr. This allows the number of manufacturing steps to be reduced in the method for manufacturing the photodetector 1.

[0095] 3. Third Embodiment A photodetector 1 according to a third embodiment will be described with reference to FIG.

[0096] 28 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the third embodiment, the side periphery dimension of the gate electrode 6 is substantially the same as the side periphery dimension of the electrode 12A in a plan view.

[0097] Alternatively, the manufacturing method can be expressed as follows: after forming the upper groove portion 4B of the groove 4 and forming the sidewall insulator 7, the lower groove portion 4A is formed using the sidewall insulator 7 as a mask. Then, in the lower groove portion 4A, the gate electrode 6 is formed on the bottom surface and sidewalls of the groove 4 with the gate insulating film 5 interposed therebetween. That is, in the manufacturing method of the photodetector 1 according to the first or second embodiment, the step of forming the gate electrode 6 and the step of forming the sidewall insulator 7 are performed in the reverse order.

[0098] The components of the third embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0099] [Operational Effects] According to the photodetector 1 of the third embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0100] 4. Fourth Embodiment A photodetector 1 according to a fourth embodiment will be described with reference to FIG.

[0101] [Configuration of Photodetector 1] Figure 29 shows an example of a planar configuration in which a main part of a pixel 10 of the photodetector 1 is enlarged. In the photodetector 1 according to the fourth embodiment, a photoelectric conversion element PD and a floating diffusion FD are disposed apart from each other on a diagonal line di of the pixel 10 (first pixel 10A or second pixel 10B) in a planar view. The transfer transistor TR has one gate electrode 6 disposed between the photoelectric conversion element PD and the floating diffusion FD on the diagonal line di. The gate electrode 6 has a polygonal planar shape in this example. More specifically, the gate electrode 6 has an octagonal planar shape.

[0102] The components of the fourth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0103] [Operational Effects] According to the photodetector 1 of the fourth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0104] 5. Fifth Embodiment A photodetector 1 according to a fifth embodiment will be described with reference to FIG.

[0105] 30 shows an example of a planar configuration in which a main part of a pixel 10 of the photodetector 1 is enlarged. In the photodetector 1 according to the fifth embodiment, similar to the photodetector 1 according to the fourth embodiment, the photoelectric conversion element PD and the floating diffusion FD are arranged spaced apart from each other on the diagonal line di of the pixel 10 in a planar view. The transfer transistor TR has a plurality of gate electrodes 6 arranged between the photoelectric conversion element PD and the floating diffusion FD on the diagonal line di. Here, two of the plurality of gate electrodes 6 are arranged in a planar direction intersecting the diagonal line di.

[0106] The components of the fifth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the fourth embodiment.

[0107] [Operational Effects] According to the photodetector 1 of the fifth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the fourth embodiment.

[0108] 30 , in the photodetector 1, the transfer transistor TR has a plurality of gate electrodes 6, so that the gate width dimension or the channel width dimension can be increased, thereby further improving the transfer efficiency of the transfer transistor TR.

[0109] 6. Sixth Embodiment A photodetector 1 according to a sixth embodiment will be described with reference to FIG.

[0110] 31 shows an example of an enlarged planar configuration of a main portion of a pixel 10 of the photodetector 1. In the photodetector 1 according to the sixth embodiment, similar to the photodetector 1 according to the fifth embodiment, the photoelectric conversion element PD and the floating diffusion FD are arranged spaced apart from each other on the diagonal line di of the pixel 10 in a planar view. The transfer transistor TR has a plurality of gate electrodes 6 arranged between the photoelectric conversion element PD and the floating diffusion FD on the diagonal line di. Here, two of the plurality of gate electrodes 6 are arranged in a planar direction intersecting the diagonal line di.

[0111] The gate electrode 6 has a triangular planar shape. More specifically, the gate electrode 6 has an isosceles triangular planar shape. The longest side of the gate electrode 6 faces the diagonal line di.

[0112] The components of the sixth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the fifth embodiment.

[0113] [Operational Effects] According to the photodetector 1 of the sixth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the fifth embodiment.

[0114] 31 , in the photodetector 1, the transfer transistor TR has a plurality of gate electrodes 6, and the long sides of the gate electrodes 6 are arranged along the diagonal line di. This allows the gate width or channel width of the transfer transistor TR to be increased, thereby further improving the transfer efficiency of the transfer transistor TR.

[0115] 7. Seventh Embodiment A photodetector 1 according to a seventh embodiment will be described with reference to FIGS. 32 and 33. FIG.

[0116] [Configuration of Photodetector 1] Fig. 32 shows an example of the planar configuration of a pixel 10 of the photodetector 1. Fig. 33 shows an example of the cross-sectional configuration of the pixel 10. The photodetector 1 according to the seventh embodiment is similar to the photodetector 1 according to the fifth embodiment, and in plan view, the photoelectric conversion element PD and the floating diffusion FD are arranged at a distance from each other in the direction of arrow Y of the pixel 10. The transfer transistor TR has a plurality of gate electrodes 6 arranged between the photoelectric conversion element PD and the floating diffusion FD in the direction of arrow X, which is orthogonal to the direction of arrow Y. Here, two gate electrodes 6 are arranged.

[0117] The components of the seventh embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the fifth embodiment.

[0118] [Operational Effects] According to the photodetector 1 of the seventh embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the fifth embodiment.

[0119] 8. Eighth Embodiment A photodetector 1 according to an eighth embodiment will be described with reference to FIG.

[0120] [Configuration of Photodetector 1] Fig. 34 shows an example of the planar configuration of a pixel 10 of the photodetector 1. The photodetector 1 according to the eighth embodiment is similar to the photodetector 1 according to the seventh embodiment, and in plan view, the transfer transistor TR has a plurality of gate electrodes 6 arranged along the floating diffusion FD. More specifically, the floating diffusion FD is formed in a rectangular shape. The gate electrodes 6 are arranged along each of two adjacent sides of this rectangular shape.

[0121] The components of the eighth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment.

[0122] [Operational Effects] According to the photodetector 1 of the eighth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the seventh embodiment.

[0123] 9. Ninth Embodiment A photodetector 1 according to a ninth embodiment will be described with reference to FIG.

[0124] 35 shows an example of the planar configuration of a pixel 10 of the photodetector 1. The photodetector 1 according to the ninth embodiment is similar to the photodetector 1 according to the seventh embodiment, and in plan view, the photoelectric conversion element PD and the floating diffusion FD are arranged at a distance from each other in the direction of arrow Y of the pixel 10. The transfer transistor TR has one gate electrode 6 arranged between the photoelectric conversion element PD and the floating diffusion FD.

[0125] The components of the ninth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment.

[0126] [Operational Effects] According to the photodetector 1 of the ninth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the seventh embodiment.

[0127] 10. Tenth Embodiment A photodetector 1 according to a tenth embodiment will be described with reference to FIGS.

[0128] 36 to 40 show an example of cross sections illustrating each step in a method for manufacturing the photodetector 1. The method for manufacturing the photodetector 1 according to the tenth embodiment is mainly a method for manufacturing the transfer transistor TR of the pixel 10. The method for manufacturing the photodetector 1 is as follows.

[0129] First, a semiconductor substrate 30 is prepared (see FIG. 36). This semiconductor substrate 30 is in the state of a semiconductor wafer before a dicing process, and has pixel isolation regions 31 and photoelectric conversion elements PD (not shown) (see FIGS. 4A to 6) formed thereon.

[0130] Next, a mask 306 is formed on the surface 30B of the semiconductor substrate 30 (see FIG. 36). The mask 306 is, for example, a SiO 2 buffer layer. ２A laminated film of SiN as a hard mask is used. In the mask 306, an opening is formed by photolithography in a region where the gate electrode 6 of the transfer transistor TR is to be formed (see FIG. 36).

[0131] 36 , a shallow upper portion 4B of the trench is formed from the surface 30B toward the surface 30A of the semiconductor substrate 30 using a mask 306. Anisotropic etching is used to form the upper portion 4B of the trench. Here, the opening dimension of the upper portion 4B of the trench is, for example, 150 nm or more and 250 nm or less. The depth dimension of the upper portion 4B of the trench is, for example, 150 nm or more and 250 nm or less.

[0132] 11 of the first manufacturing method described above, as shown in FIG. 37, a sidewall insulator 7 is formed over the entire surface of the mask 306, including the bottom and sidewalls of the trench upper portion 4B. Here, an insulating material such as TEOS (Tetra Ethoxy Silane) is used for the sidewall insulator 7. The sidewall insulator 7 is formed to a thickness of, for example, 25 nm to 35 nm. As shown in FIG. 38, the sidewall insulator 7 is formed on the sidewall of the trench upper portion 4B. The sidewall insulator 7 is formed using an etch-back method using anisotropic etching. Therefore, the sidewall insulator 7 is formed in self-alignment with the trench upper portion 4B.

[0133] 39, using the mask 306 and the sidewall insulator 7 as a mask, a deeper trench lower portion 4A is formed in the semiconductor substrate 30. Anisotropic etching is used to form the trench lower portion 4A. The depth dimension of the trench lower portion 4A is, for example, 250 nm or more and 350 nm or less. The trench lower portion 4A is formed by self-alignment with the sidewall insulator 7 and the trench upper portion 4B. The trench 4 is formed by the trench lower portion 4A and the trench upper portion 4B.

[0134] Subsequently, a gate insulating film 5 is formed in the trench 4, and a gate electrode material 6A (see, for example, FIG. 9) is formed in the trench 4 with the gate insulating film 5 interposed therebetween (see FIG. 40). The gate electrode material 6A is patterned. As a result, as shown in FIG. 40, a gate electrode 6 is formed in a trench lower portion 4A with the gate insulating film 5 interposed therebetween, and an electrode 12A is formed in a trench upper portion 4B with a sidewall insulator 7 interposed therebetween.

[0135] When this series of manufacturing steps is completed, the photodetector 1 according to the tenth embodiment is completed.

[0136] [Effects] The photodetector 1 according to the tenth embodiment can achieve the same effects as those achieved by the photodetector 1 according to the first or second embodiment. Furthermore, in the photodetector 1, the gate electrode 6 and the electrode 12A are each formed integrally using the same conductive material in the same manufacturing process. This allows the gate electrode 6 and the electrode 12A to be easily constructed.

[0137] 11. Eleventh Embodiment A photodetector 1 according to an eleventh embodiment will be described with reference to FIGS.

[0138] 41 to 44 show an example of cross sections illustrating each step in a method for manufacturing the photodetector 1. The method for manufacturing the photodetector 1 according to the eleventh embodiment is mainly a method for manufacturing the transfer transistor TR of the pixel 10. The method for manufacturing the photodetector 1 is as follows.

[0139] First, a semiconductor substrate 30 is prepared (see FIG. 41). This semiconductor substrate 30 is in the state of a semiconductor wafer before the dicing process, and has pixel isolation regions 31 and photoelectric conversion elements PD (not shown) (see FIGS. 4A to 6) formed thereon.

[0140] Next, a mask 306 is formed on the surface 30B of the semiconductor substrate 30 (see FIG. 41 ). As shown in FIG. 41 , the mask 306 is used to form trenches 4 from the surface 30B of the semiconductor substrate 30 toward the surface 30A. Anisotropic etching is used to form the trenches 4. Here, the opening dimension of the trenches 4 is, for example, 150 nm or more and 250 nm or less. The depth dimension of the trenches 4 is, for example, 450 nm or more and 650 nm or less.

[0141] As shown in Fig. 42, a gate insulating film 5 is formed in a trench lower portion 4A within the trench 4, and a gate electrode 6 is formed in the trench lower portion 4A with the gate insulating film 5 interposed therebetween. Subsequently, similar to the step shown in Fig. 40 of the method for manufacturing the photodetector 1 according to the tenth embodiment, a sidewall insulator 7 is formed in an upper portion 4B of the trench 4 as shown in Fig. 43. The sidewall insulator 7 is formed in self-alignment with the trench upper portion 4B.

[0142] As shown in FIG. 44, an electrode 12A is formed on the upper portion 4B of the trench with a sidewall insulator 7 interposed therebetween.

[0143] When this series of manufacturing steps is completed, the photodetector 1 according to the eleventh embodiment is completed.

[0144] [Effects] The photodetector 1 according to the eleventh embodiment can achieve the same effects as those achieved by the photodetector 1 according to the tenth or second embodiment. Furthermore, in the photodetector 1, the gate electrode 6 and the electrode 12A are formed from different conductive materials. This allows optimization of the gate electrode 6 and the electrode 12A.

[0145] 12. Twelfth Embodiment A photodetector 1 according to a twelfth embodiment will be described with reference to FIGS. 45 to 54. [Method of Manufacturing Photodetector 1] FIGS. 45 to 54 show an example of cross sections illustrating each step of a method of manufacturing the photodetector 1. The method of manufacturing the photodetector 1 according to the twelfth embodiment is mainly a method of manufacturing the transfer transistor TR of the pixel 10. The method of manufacturing the photodetector 1 is as follows. First, a semiconductor substrate 30 is prepared (see FIG. 45). This semiconductor substrate 30 is in the state of a semiconductor wafer before a dicing step, and has pixel isolation regions 31 and photoelectric conversion elements PD (see FIGS. 4A, 5, and 6) formed thereon.

[0146] Next, a mask 300 is formed on the surface 30B of the semiconductor substrate 30 (see FIG. 45). The mask 300 is formed by sequentially stacking, for example, a mask 301, a mask 302, and a mask 303. The mask 301 is made of, for example, SiO ２The mask 302 is made of, for example, SiN. The mask 303 is made of, for example, photoresist. An opening is formed in the mask 300 in a region where the gate electrode 6 of the transfer transistor TR is to be formed (see FIG. 45).

[0147] 45, a mask 300 is used to form upper portions 4B of trenches 4 from the front surface 30B toward the front surface 30A of the semiconductor substrate 30. Anisotropic etching is used to form the trenches 4. As shown in FIG. 46, the mask 300 is removed.

[0148] 47 , a sidewall insulator 7 is formed on the entire surface of the semiconductor substrate 30, including the sidewalls of the trench upper portion 4B and the bottom surface of the trench upper portion 4B. The sidewall insulator 7 is formed by stacking a first sidewall insulator 7A and a second sidewall insulator 7B having an etching selectivity with respect to the first sidewall insulator 7A. The first sidewall insulator 7A and the second sidewall insulator 7B are each formed by, for example, CVD.

[0149] An etch-back process is performed on the entire surface 30B side of the semiconductor substrate 30. For example, anisotropic etching is used for the etch-back process. As a result, sidewall insulators 7 are formed on the sidewalls of the upper portions 4B of the trenches, as shown in FIG. 48 . The sidewall insulators 7 are formed in self-alignment with the upper portions 4B of the trenches, and therefore have a uniform thickness t2.

[0150] 49 , the sidewall insulator 7 is mainly used as a mask 300 to form the trench lower portion 4A from the front surface 30B side toward the front surface 30A side of the semiconductor substrate 30. Anisotropic etching is used to form the trench lower portion 4A. Once the trench lower portion 4A is formed, the trench 4 consisting of the trench lower portion 4A and the trench upper portion 4B is completed.

[0151] 50, a gate insulating film 5 is formed on the bottom surface and sidewalls of the trench lower portion 4A. The gate insulating film 5 is formed by, for example, thermal oxidation. ２ It is formed by

[0152] 51, a gate electrode material 6A filling at least the trench lower portion 4A is formed on the entire surface of the semiconductor substrate 30. The gate electrode material 6A is formed by using, for example, the CVD method, and is made of polycrystalline silicon in this example.

[0153] An etch-back process is performed on the entire surface 30B side of the semiconductor substrate 30. For example, anisotropic etching is used for the etch-back process. As a result, a gate electrode 6 is formed from the gate electrode material 6A, as shown in FIG. 52 . The gate electrode 6 is embedded in the trench lower portion 4A of the trench 4, and is formed on the bottom and sidewalls of the trench lower portion 4A with the gate insulating film 5 interposed therebetween.

[0154] 53, an interlayer insulator 11 is formed by laminating a first interlayer insulator 11A and a second interlayer insulator 11B over the entire surface 30B of a semiconductor substrate 30. The first interlayer insulator 11A is made of an insulating material such as SiN. The second interlayer insulator 11B is made of an insulating material such as SiO. ２ An insulating material such as the above is used. A contact hole 11H is formed in the interlayer insulator 11. When the contact hole 11H is formed, the surface of the gate electrode 6 of the transfer transistor TR can be exposed in the trench 4.

[0155] 54, a wiring 12 is formed at least in the connection hole 11H, and an electrode 12A is formed in the upper portion 4B of the trench 4. The electrode 12A is electrically connected to the gate electrode 6 of the transfer transistor TR, and is formed by self-alignment with the trench 4 and the sidewall insulator 7. The wiring 12 and the electrode 12A are formed by, for example, sputtering.

[0156] When this series of manufacturing steps is completed, the photodetector 1 according to the first embodiment is completed.

[0157] The components of the twelfth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0158] [Operational Effects] According to the photodetector 1 of the twelfth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment and the manufacturing method thereof.

[0159] 13. Thirteenth embodiment A photodetector 1 according to a thirteenth embodiment of the present disclosure will be described with reference to Fig. 55. Fig. 55 shows an example of a block configuration of an electronic device 700.

[0160] 55 , electronic device 700 includes photodetector 1 according to any one of the first to twelfth embodiments as photodetector 70. Photodetector 70 is applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions.

[0161] The electronic device 700 includes an optical system 71, a photodetector 70, and a DSP (Digital Signal Processor) 72. In the electronic device 700, the DSP 72, a display device 73, an operation system 74, a memory 75, a recording device 76, and a power supply system 77 are connected via a bus 78. The electronic device 700 is capable of capturing still images and moving images.

[0162] The optical system 71 includes one or more lenses. The optical system 71 guides image light (incident light) from a subject to the photodetector 70, and forms an image on the light-receiving surface (sensor portion) of the photodetector 70.

[0163] The photodetector 70 uses, for example, the photodetector 1 according to any one of the first to eleventh embodiments. In the photodetector 70, electrons are accumulated for a certain period of time in accordance with an image formed on a light-receiving surface through an optical system 71. Then, a signal in accordance with the electrons accumulated in the photodetector 70 is supplied to a DSP 72.

[0164] The DSP 72 performs various signal processing on the signal from the photodetector 70 to acquire an image, and temporarily stores the image data in the memory 75. The image data stored in the memory 75 is recorded in the recording device 76. The image data stored in the memory 75 is also supplied to the display device 73, which displays the image. The operation system 74 accepts various operations by the user and supplies operation signals to each block of the electronic device 700. The power supply system 77 supplies the power necessary to drive each block of the electronic device 700.

[0165] 55, an electronic device 700 according to the twelfth embodiment includes a photodetector 70. As described in the photodetector 1 according to any one of the first to eleventh embodiments, the photodetector 70 is formed to include pixels 10 as phase difference detection pixels over the entire surface of the pixel region 100, for example. This allows the phase difference detection accuracy of the electronic device 700 to be improved.

[0166] 14. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0167] FIG. 56 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0168] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 56, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0169] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0170] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0171] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0172] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0173] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0174] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0175] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0176] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0177] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 56, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0178] FIG. 57 is a diagram showing an example of the installation position of the imaging unit 12031.

[0179] In FIG. 57, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0180] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0181] 57 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0182] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0183] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0184] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0185] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0186] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 among the components described above. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to realize an imaging unit 12031 that can improve the transfer efficiency of the transfer transistor.

[0187] 15. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0188] FIG. 58 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0189] Figure 58 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0190] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0191] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0192] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0193] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0194] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0195] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0196] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0197] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0198] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0199] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0200] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0201] FIG. 59 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0202] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0203] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0204] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. When the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0205] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0206] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0207] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0208] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0209] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0210] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0211] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0212] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0213] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0214] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0215] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0216] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0217] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0218] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the above-described configurations, the technology according to the present disclosure can be applied to the imaging unit 11402 of the camera head 11102. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to realize an imaging unit 11402 that can improve the transfer efficiency of the transfer transistor.

[0219] Although an endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to other systems, such as a microsurgery system.

[0220] 16. Other Embodiments The present technology is not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology. For example, among the photodetection devices according to the first to eleventh embodiments, photodetection devices according to two or more of the above-described embodiments may be combined.

[0221] A semiconductor device according to a first embodiment of the present disclosure includes a trench, a first insulated gate field effect transistor, a sidewall insulator, and an electrode. The trench extends from a first surface of a substrate toward a second surface opposite the first surface. The first insulated gate field effect transistor is disposed in a lower portion of the trench and has a first gate electrode embedded in a sidewall of the trench with a first gate insulating film interposed therebetween. The sidewall insulator is disposed on the sidewall of the trench at an upper portion thereof, and the thickness of the sidewall insulator in the same direction is greater than the thickness of the first gate insulating film. The electrode is embedded in an upper portion of the trench with the sidewall insulator interposed therebetween and is electrically connected to the first gate electrode. A semiconductor device configured in this manner can effectively suppress or prevent the influence of the field effect from the electrode on the semiconductor substrate via the sidewall insulator interposed therebetween, and can also effectively suppress or prevent variation in the influence of the field effect itself.

[0222] A semiconductor device according to a second embodiment of the present disclosure is the semiconductor device according to the first embodiment, further comprising an interlayer insulator disposed on the first surface, a connection hole disposed in the interlayer insulator and leading to the trench opening, and a wiring disposed at least in the connection hole, a portion of which serves as an electrode. With this semiconductor device configured in this manner, it is not necessary to provide a pad on the electrode that is larger in diameter than the electrode and serves as a connection region with the wiring. This allows the area occupied by the connection region to be reduced.

[0223] A photodetector according to a third embodiment of the present disclosure includes a trench, a transfer transistor, a sidewall insulator, an electrode, a photoelectric conversion element, and a floating diffusion. The trench is disposed from a first surface of a substrate toward a second surface opposite the first surface. The transfer transistor is disposed in a lower portion of the trench and has a first gate electrode embedded in a sidewall of the trench with a first gate insulating film interposed therebetween. The sidewall insulator is disposed on the sidewall of the trench at an upper portion thereof, and the thickness of the sidewall insulator in the same direction is thicker than the thickness of the first gate insulating film. The electrode is embedded in an upper portion of the trench with the sidewall insulator interposed therebetween and electrically connected to the first gate electrode. The photoelectric conversion element is disposed on the second surface side of the substrate and electrically connected to one end of the transfer transistor to convert light into electric charges. The floating diffusion is disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and the electrode, and is electrically connected to the other end of the transfer transistor. In a photodetector configured in this manner, the floating diffusion is disposed close to the periphery of the electrode, which effectively suppresses or prevents the influence of the electric field effect from the electrode to the floating diffusion, thereby stabilizing the transfer efficiency from the photoelectric conversion element to the floating diffusion by the transfer transistor and improving pixel characteristics.

[0224] A method for manufacturing a semiconductor device according to a fourth embodiment of the present disclosure includes the following steps: a trench is formed from a first surface of a substrate toward a second surface opposite the first surface; a first gate electrode is formed at a lower portion of the trench with a first gate insulating film interposed on a sidewall of the trench, thereby forming a first insulated gate field effect transistor; a sidewall insulator is formed at an upper portion of the trench on the sidewall of the trench by self-alignment with the trench, the sidewall insulator having a thickness greater in the same direction than that of the first gate insulating film; and an electrode is formed at an upper portion of the trench, electrically connected to the first gate electrode with the sidewall insulator interposed therebetween. According to this method for manufacturing a semiconductor device, the semiconductor device according to the first embodiment can be easily manufactured.

[0225] <Configuration of the Present Technology> The present technology has the following configuration. According to the present technology having the following configuration, it is possible to effectively suppress or prevent variations in the field effect from an electrode to a substrate in a semiconductor device or a photodetector. (1) A semiconductor device comprising: a trench arranged from a first surface of a substrate toward a second surface opposite the first surface; a first insulated gate field effect transistor arranged in a lower part of the trench and having a first gate electrode buried on a sidewall of the trench with a first gate insulating film interposed therebetween; a sidewall insulator arranged on a sidewall of the trench in an upper part of the trench and having a thickness in the same direction greater than that of the first gate insulating film; and an electrode buried in an upper part of the trench with the sidewall insulator interposed therebetween and electrically connected to the first gate electrode. (2) The semiconductor device according to (1), wherein the sidewall insulator and the electrode are each formed in a self-aligned manner with respect to the trench. (3) The semiconductor device according to (1) or (2), further comprising: a second insulated gate field effect transistor having a second gate electrode disposed on the first surface with a second gate insulating film interposed therebetween in a region different from that of the first insulated gate field effect transistor, the second gate insulating film being formed in the same insulating layer and made of the same insulating material as the first gate insulating film, and the second gate electrode being formed in the same conductive layer and made of the same conductive material as the first gate electrode. (4) The semiconductor device according to any one of (1) to (3), further comprising: an interlayer insulator disposed on the first surface; a connection hole disposed in the interlayer insulator and leading to the trench opening; and a wiring disposed at least in the connection hole, a portion of which serves as the electrode. (5) The semiconductor device according to any one of (1) to (4), wherein the sidewall insulator comprises a first sidewall insulator formed along the trench sidewall, and a second sidewall insulator formed on the trench sidewall with the first sidewall insulator interposed therebetween and having an etching selectivity with respect to the first sidewall insulator.(6) A photodetector comprising: a trench disposed from a first surface of a substrate toward a second surface opposite the first surface, a transfer transistor disposed in a lower portion of the trench and having a first gate electrode embedded in a sidewall of the trench with a first gate insulating film interposed therebetween, a sidewall insulator disposed in an upper portion of the trench on the sidewall of the trench and having a thickness greater in the same direction than a thickness of the first gate insulating film, an electrode embedded in an upper portion of the trench with the sidewall insulator interposed and electrically connected to the first gate electrode, a photoelectric conversion element disposed in the substrate and electrically connected to one end of the transfer transistor and converting light into electric charges, and a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and the electrode and electrically connected to the other end of the transfer transistor. (7) The photodetector according to (6), wherein the sidewall insulator and the electrode are each formed in a self-aligned manner with respect to the trench. (8) The photodetector according to (6) or (7), further comprising: a pixel transistor having a second gate electrode disposed on the first surface with a second gate insulating film interposed therebetween in a region different from the transfer transistor, the pixel transistor forming a pixel circuit, the second gate insulating film being formed in the same insulating layer and from the same insulating material as the first gate insulating film, and the second gate electrode being formed in the same conductive layer and from the same conductive material as the first gate electrode. (9) The photodetector according to any one of (6) to (8), further comprising: an interlayer insulator disposed on the first surface; a connection hole disposed in the interlayer insulator and leading to the groove opening; and wiring disposed at least in the connection hole, a portion of which serves as the electrode. (10) The photodetector according to any one of (6) to (9), wherein the sidewall insulator comprises a first sidewall insulator formed along the sidewall of the groove, and a second sidewall insulator formed on the sidewall of the groove with the first sidewall insulator interposed therebetween and having an etching selectivity with respect to the first sidewall insulator. (11) The photodetector according to any one of (6) to (10), wherein the floating diffusion is formed in contact with the sidewall insulator.(12) The photodetector according to any one of (6) to (11), wherein the floating diffusion is formed in contact with the sidewall insulator and is formed by self-alignment with the groove and the sidewall insulator. (13) The photodetector according to any one of (6) to (12), wherein a dimension of the sidewall insulator from the first surface to the second surface is equal to or greater than a dimension of the floating diffusion in the same direction. (14) The photodetector according to any one of (6) to (13), wherein a side perimeter of the first gate electrode is larger than a side perimeter of the electrode when viewed from the first surface to the second surface. (15) The photodetector according to any one of (6) to (13), wherein the first gate electrode and the electrode are integrally formed from the same conductive material. (16) The photodetector according to any one of (6) to (13), wherein the first gate electrode and the electrode are formed separately. (17) A method for manufacturing a semiconductor device, comprising: forming a trench from a first surface of a substrate toward a second surface opposite to the first surface; forming a first gate electrode at a lower portion of the trench with a first gate insulating film interposed on a side wall of the trench to form a first insulated gate field effect transistor; forming a sidewall insulator at an upper portion of the trench on the side wall of the trench by self-alignment with the trench, the sidewall insulator having a thickness greater in the same direction than that of the first gate insulating film; and forming an electrode at an upper portion of the trench with the sidewall insulator interposed and electrically connected to the first gate electrode.

[0226] This application claims priority based on Japanese Patent Application No. 2023-123725, filed on July 28, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0227] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; a first insulated gate field effect transistor disposed in a lower portion of the trench and having a first gate electrode embedded in a sidewall of the trench with a first gate insulating film interposed therebetween; a sidewall insulator disposed in an upper portion of the trench on the sidewall of the trench and having a thickness greater in the same direction than that of the first gate insulating film; and an electrode buried in an upper portion of the trench with the sidewall insulator interposed therebetween and electrically connected to the first gate electrode.

2. The semiconductor device according to claim 1, wherein each of said sidewall insulators and said electrode is formed by self-alignment with said groove.

3. The semiconductor device according to claim 1, further comprising a second insulated gate field effect transistor having a second gate electrode disposed on the first surface with a second gate insulating film interposed therebetween in a region different from that of the first insulated gate field effect transistor, the second gate insulating film being formed of the same insulating layer and insulating material as the first gate insulating film, and the second gate electrode being formed of the same conductive layer and conductive material as the first gate electrode.

4. The semiconductor device according to claim 1, further comprising: an interlayer insulator disposed on said first surface; a connection hole disposed in said interlayer insulator and communicating with said groove opening; and wiring disposed at least within said connection hole, a portion of which serves as said electrode.

5. The semiconductor device according to claim 1, wherein the sidewall insulator comprises a first sidewall insulator formed along the groove sidewall, and a second sidewall insulator formed on the groove sidewall with the first sidewall insulator interposed therebetween and having an etching selectivity relative to the first sidewall insulator.

6. A photodetector comprising: a groove disposed from a first surface of a substrate toward a second surface opposite to the first surface; a transfer transistor disposed in a lower portion of the groove and having a first gate electrode embedded in a sidewall of the groove with a first gate insulating film interposed therebetween; a sidewall insulator disposed in an upper portion of the groove on the sidewall of the groove and having a thickness in the same direction greater than that of the first gate insulating film; an electrode embedded in an upper portion of the groove with the sidewall insulator interposed therebetween and electrically connected to the first gate electrode; a photoelectric conversion element disposed in the substrate and electrically connected to one end of the transfer transistor for converting light into electric charges; and a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and the electrode and electrically connected to the other end of the transfer transistor.

7. The photodetector device according to claim 6, wherein each of said sidewall insulators and said electrodes is formed in a self-aligned manner with respect to said groove.

8. The photodetector according to claim 6, further comprising a pixel transistor which constitutes a pixel circuit and has a second gate electrode disposed on the first surface with a second gate insulating film interposed therebetween in a region different from the transfer transistor, wherein the second gate insulating film is formed in the same insulating layer and from the same insulating material as the first gate insulating film, and the second gate electrode is formed in the same conductive layer and from the same conductive material as the first gate electrode.

9. The photodetector device according to claim 6, further comprising: an interlayer insulator disposed on said first surface; a connection hole disposed in said interlayer insulator and leading to said groove opening; and wiring disposed at least within said connection hole, a portion of which serves as said electrode.

10. The photodetector device of claim 6, wherein the sidewall insulator comprises a first sidewall insulator formed along the groove sidewall, and a second sidewall insulator formed on the groove sidewall with the first sidewall insulator interposed therebetween and having an etching selectivity with respect to the first sidewall insulator.

11. The photodetector device according to claim 6, wherein the floating diffusion is formed in contact with the sidewall insulator.

12. The photodetector according to claim 6, wherein the floating diffusion is formed in contact with the sidewall insulator and is formed by self-alignment with the groove and the sidewall insulator.

13. The photodetector according to claim 6, wherein a dimension of the sidewall insulator from the first surface to the second surface is equal to or greater than a dimension of the floating diffusion in the same direction.

14. The photodetector according to claim 6, wherein the side perimeter of the first gate electrode is larger than the side perimeter of the electrode when viewed from the first surface side to the second surface side.

15. The photodetector according to claim 6, wherein the first gate electrode and the electrodes are integrally formed from the same conductive material.

16. The photodetector device according to claim 6, wherein the first gate electrode and each of the electrodes are formed separately.

17. A method for manufacturing a semiconductor device comprising the steps of: forming a trench from a first surface of a substrate toward a second surface opposite to the first surface; forming a first gate electrode at a lower portion of the trench with a first gate insulating film interposed on a sidewall of the trench; forming a first insulated gate field effect transistor; forming a sidewall insulator at an upper portion of the trench on the sidewall of the trench, the sidewall insulator having a thickness in the same direction greater than that of the first gate insulating film, by self-alignment with the trench; and forming an electrode at an upper portion of the trench electrically connected to the first gate electrode with the sidewall insulator interposed therebetween.

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