Light detection device and electronic apparatus

Abstract

Provided is a light detection device adapted for miniaturization. The light detection device comprises: a semiconductor layer which has a plurality of cell regions in a matrix, each cell region having a photoelectric conversion unit configured therein, and the semiconductor layer having a first semiconductor region of a first conductivity type configured therein; and a first gate electrode and a second gate electrode which are provided to face the first semiconductor region via a gate insulating film, and which are electrically separated from each other by being provided so as to be in contact with a surface on one side or a surface on the other side of the insulating thin film.

Description

Photodetector and electronic equipment

[0001] The present technology relates to a photodetector and an electronic device, and more particularly to a photodetector and an electronic device that are compatible with miniaturization.

[0002] CMOS image sensors (CIS) read out signal charges accumulated in a photodiode (PD), a photoelectric conversion element, via a MOS (Metal-Oxide-Semiconductor) transistor. CIS sensors are used as imaging elements mounted on cameras in mobile devices such as smartphones.

[0003] A CIS is composed of multiple unit pixels arranged in a two-dimensional array. Each unit pixel consists of one photodiode (PD) and multiple pixel transistors. A commonly used CIS with four transistors has an amplification transistor connected to a floating diffusion (FD) layer and a selection transistor that determines the readout row.

[0004] As pixel sizes become smaller, it is becoming more difficult to secure an active region in a unit pixel region where transistors such as amplifier transistors are provided. In response to this, a solid-state imaging device has been disclosed in which a second substrate on which pixel transistors are formed is bonded to a first substrate on which PDs are formed, thereby creating a two-stage pixel structure (for example, Patent Document 1).

[0005] International Publication No. 2019 / 131965

[0006] The present technology aims to provide a photodetector and electronic device that are compatible with miniaturization.

[0007] A photodetector according to one aspect of the present technology includes a semiconductor layer having a plurality of cell regions arranged in a matrix, each having a photoelectric conversion unit, and having a first semiconductor region of a first conductivity type, and a first gate electrode and a second gate electrode that are arranged opposite the first semiconductor region via a gate insulating film and are electrically isolated from each other by being arranged in contact with one surface or the other surface of an insulating thin film.

[0008] An electronic device according to an aspect of the present technology includes the light detection device and an optical system that forms an image light from a subject on the light detection device.

[0009] FIG. 5A is a chip layout diagram showing a configuration example of a photodetector according to a first embodiment of the present technology. FIG. 6A is a block diagram showing a configuration example of a photodetector according to a first embodiment of the present technology. FIG. 7A is an equivalent circuit diagram of a pixel of the photodetector according to the first embodiment of the present technology. FIG. 8A is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in the photodetector according to the first embodiment of the present technology. FIG. 9A is a plan view showing a positional relationship between an amplification transistor and a selection transistor included in the photodetector according to the first embodiment of the present technology. FIG. 5A is a longitudinal sectional view showing a cross-sectional configuration along the A-A cutting line of FIG. 5A. FIG. 9A is a plan view showing a positional relationship between an amplification transistor and a selection transistor included in a photodetector according to a first modification of the first embodiment of the present technology. FIG. 10A is a longitudinal sectional view showing a cross-sectional configuration along the A-A cutting line of FIG. 10A. 11A . FIG. 12A is a plan view showing a positional relationship between an amplification transistor and a selection transistor included in a photodetector according to a fourth modification of the first embodiment of the present technology. FIG. 13A is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in cross section along the A-A cutting line of FIG. 9A . FIG. 14A is a plan view showing a positional relationship between an amplification transistor and a selection transistor included in a photodetector according to a fifth modification of the first embodiment of the present technology. FIG. 15A is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in cross section along the A-A cutting line of FIG. 10A . FIG. 16A is a plan view showing a positional relationship between an amplification transistor and a selection transistor included in a photodetector according to a sixth modification of the first embodiment of the present technology. FIG. 17A is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in cross section along the A-A cutting line of FIG. 11A . FIG. 18A is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in cross section along the B-B cutting line of FIG. 11A . FIG. 19A is a plan view showing a positional relationship between an amplification transistor and a selection transistor included in a photodetector according to a seventh modification of the first embodiment of the present technology. FIG. 19A is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in cross section along the B-B cutting line of FIG.16A . FIG. 16B is a plan view showing a positional relationship between an amplification transistor and a selection transistor included in a photodetector according to an eighth modified example of the first embodiment of the present technology. FIG. 16C is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in cross section along the B-B cutting line of FIG. 13A. FIG. 16D is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in cross section along the D-D cutting line of FIG. 13A. FIG. 16E is a longitudinal cross-sectional view showing a cross-sectional configuration of a transfer transistor included in a photodetector according to a ninth modified example of the first embodiment of the present technology. FIG. 16F is an equivalent circuit diagram of a pixel of a photodetector according to a tenth modified example of the first embodiment of the present technology. FIG. 16G is a longitudinal cross-sectional view showing cross-sectional configurations of a transfer transistor and a MEM included in a photodetector according to a tenth modified example of the first embodiment of the present technology. FIG. 16H is an explanatory diagram showing a part of a pixel region 2A of a CCD-type photodetector 1 according to an eleventh modified example of the first embodiment of the present technology. FIG. 16H is a longitudinal cross-sectional view showing a cross-sectional configuration of a register when viewed in cross section along the E-E cutting line of FIG. FIG. 16A is a block diagram showing an example of a schematic configuration of an electronic device. FIG. 16I is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 16I is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit. FIG. 16I is a diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 16J is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. 10 is a vertical cross-sectional view showing the arrangement of an amplification transistor and a selection transistor included in a photodetector according to a comparative example.

[0010] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0011] In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings include parts with different dimensional relationships and ratios. Furthermore, since drawings suitable for explaining the present technology are used, there may be differences in configuration between the drawings.

[0012] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] The description will be given in the following order: 1. First embodiment 2. Second embodiment Application example to electronic devices Application example to mobile objects Application example to endoscopic surgery systems

[0015] First Embodiment In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0016] <Overall Configuration of Photodetection Device> First, the overall configuration of the photodetection device 1 will be described. As shown in Fig. 1 , the photodetection device 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape in a plan view. That is, the photodetection device 1 is mounted on the semiconductor chip 2. As shown in Fig. 17 , the photodetection device 1 captures image light (incident light 106) from a subject via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0017] As shown in FIG. 1, the semiconductor chip 2 on which the photodetector 1 is mounted includes, in a two-dimensional plane including an X direction and a Y direction that intersect with each other, a square-shaped pixel region 2A provided in the center, and a peripheral region 2B provided outside the pixel region 2A so as to surround the pixel region 2A.

[0018] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 17 . In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction, which intersect with each other, on the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. Furthermore, the direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction, depth direction). Furthermore, the direction perpendicular to the Z direction is the horizontal direction.

[0019] 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0020] 2, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0021] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0022] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0023] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0024] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0025] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0026] 3 is an equivalent circuit diagram showing an example of the configuration of a pixel 3. The pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) signal charges photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. The pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0027] The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0028] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD, and the gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0029] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0030] The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are made of, for example, silicon oxide (SiO ２ The transistors are configured as MOSFETs having a gate insulating film made of a silicon nitride (Si) film, a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. ３ N ４ Alternatively, the readout circuit 15 may be a MISFET (Metal Insulator Semiconductor FET) made of a stacked film of a silicon nitride film, a silicon oxide film, or the like. The readout circuit 15 may be provided for each photoelectric conversion element PD, or one readout circuit 15 may be shared by multiple photoelectric conversion elements PD. Similarly, the charge accumulation region FD may be provided for each photoelectric conversion element PD, or one charge accumulation region FD may be shared by multiple photoelectric conversion elements PD.

[0031] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line VDD and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0032] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a selection transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0033] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line VDD and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0034] <<Specific Configuration of Photodetector>> Next, a specific configuration of the photodetector 1 will be described with reference to Figures 4, 5A, and 5B. Note that illustrations of barrier metal layers, insulating films, etc. may be omitted.

[0035] 4 , the photodetector 1 (semiconductor chip 2) includes, for example, a semiconductor layer 20 having a first surface S1 and a second surface S2. A wiring layer 30 is laminated on the first surface S1 side of the semiconductor layer 20, and a light-incident surface-side laminate 40 is laminated on the second surface S2. That is, the photodetector 1 has a laminate structure of the light-incident surface-side laminate 40, the semiconductor layer 20, and the wiring layer 30.

[0036] <Semiconductor Layer> The semiconductor layer 20 is made of a semiconductor substrate. The semiconductor layer 20 is made of, for example, a single-crystal silicon (Si) substrate, although not limited thereto. The first surface S1 is sometimes called the element formation surface or main surface, and the second surface S2 is sometimes called the light incidence surface or back surface. A plurality of cell regions 20a arranged in a matrix along the row and column directions in a plan view are provided in the portion of the semiconductor layer 20 corresponding to the pixel region 2A. The cell region 20a is provided, for example, for each pixel 3. More specifically, an island-shaped cell region 20a partitioned by an isolation region 20b is provided for each pixel 3. The number of pixels 3 is not limited to that shown in FIG. 4.

[0037] The isolation region 20b is provided with an isolation structure that separates the cell regions 20a from each other. Fig. 4 shows, as an example of the isolation structure, a trench isolation structure FTI in which a known isolation material is buried in a trench groove.

[0038] Diffusion regions such as a well region 21 which is a semiconductor region of a first conductivity type (e.g., p-type), a photoelectric conversion unit 22 which is a semiconductor region of a second conductivity type (e.g., n-type), and a charge accumulation region 23 which is a semiconductor region of the second conductivity type (e.g., n+ type) are formed in the semiconductor layer 20. Also formed in the semiconductor layer 20 is the photoelectric conversion element PD shown in FIG.

[0039] The photoelectric conversion unit 22 is, for example, a photoelectric conversion region formed in each cell region 20 a, and the charge accumulation region 23 is, for example, but not limited to, formed in each cell region 20 a.

[0040] Elements such as the transfer transistor TR, amplification transistor AMP, selection transistor SEL, and reset transistor RST shown in Figure 3 are configured within the semiconductor layer 20. As shown in Figure 4, the transfer transistor TR has a gate electrode GT provided with respect to the well region 21 via a gate insulating film. The amplification transistor AMP and selection transistor SEL are not shown in the vertical cross-sectional view of Figure 4, and will be described in detail later with reference to other drawings. A detailed description of the configuration of the reset transistor RST will be omitted.

[0041] <Wiring Layer> As shown in Fig. 4, the wiring layer 30 is a multi-layer wiring layer having, for example, an insulating film 31 and wiring 32 provided in the insulating film 31, but is not limited thereto. The wiring 32 includes vertical wiring extending mainly in the thickness direction and horizontal wiring extending mainly in the horizontal direction, and constitutes, for example, at least a part of the wiring portion of the circuit shown in Fig. 3. The insulating film 31 is made of, for example, silicon oxide (SiO ２ ) film, silicon nitride (Si ３ N ４ The wiring 32 is made of a known conductive material such as a semiconductor material such as polysilicon, or a metal material such as copper (Cu), tungsten (W), or aluminum (Al).

[0042] <Light-incident surface side laminate> The light-incident surface side laminate 40 includes, for example, an insulating film 41, a color filter 42, and a microlens 43, in that order from closest to the semiconductor layer 20, although this is not limited thereto. The microlens 43 is an on-chip lens that focuses incident light onto the semiconductor layer 20. The color filter 42 separates the incident light after passing through the microlens 43 into colors. The color filter 42 and the microlens 43 are provided, for example, for each pixel 3. The color filter 42 and the microlens 43 are made of, for example, a resin material.

[0043] <Amplification Transistor and Selection Transistor> The amplification transistor AMP and the selection transistor SEL will be described in more detail below with reference to FIGS. 5A and 5B . As shown in FIG. 5B , the amplification transistor AMP has a gate electrode GA disposed opposite the well region 21 via a gate insulating film m1. In this embodiment, the gate electrode GA faces the first surface S1 via the gate insulating film m1. The first surface S1 is a horizontal plane extending along the horizontal direction. The gate electrode GA is an example of a first gate electrode. The gate electrode GA is electrically connected to the charge accumulation region 23 and is supplied with signal charges generated by the photoelectric conversion unit 22. In this embodiment, electrons are supplied to the gate electrode GA as signal charges. The amplification transistor AMP has a function of amplifying the generated signal charges. Depending on the amount of signal charges supplied to the gate electrode GA, a portion of the well region 21 facing the gate electrode GA via the gate insulating film m1 is modulated, and a channel ChA corresponding to the amount of signal charges is formed along the first surface S1.

[0044] The select transistor SEL has a gate electrode GS disposed opposite the well region 21 via the gate insulating film m1. In this embodiment, the gate electrode GS faces the first surface S1 via the gate insulating film m1. The gate electrode GS is an example of a second gate electrode. A portion of the well region 21 facing the gate electrode GS via the gate insulating film m1 is modulated depending on the voltage supplied to the gate electrode GS. The gate electrode GS is selectively supplied with a voltage that attracts electrons or holes in the same direction as the signal charges or a voltage that repels the signal charges. In this embodiment, since the signal charges are electrons, a positive voltage is supplied as a voltage that attracts electrons and a negative voltage is supplied as a voltage that repels electrons. When a positive voltage is supplied to the gate electrode GS, the select transistor SEL is turned on, and a channel ChS is formed along the first surface S1. When a negative voltage is supplied to the gate electrode GS, the select transistor SEL is turned off, and no channel ChS is formed. By controlling the timing at which the select transistor SEL turns on, the timing at which the signal amplified by the amplifier transistor AMP is output can be controlled.

[0045] As shown in FIGS. 5A and 5B , the gate electrode GA and the gate electrode GS are electrically isolated from each other by an insulating thin film m2. More specifically, the gate electrode GA contacts one surface of the insulating thin film m2, and the gate electrode GS contacts the other surface. The gate electrodes GA and GS are disposed between the semiconductor regions 24 and 25 formed in the semiconductor layer 20, and are arranged in that order along a first direction, which is the direction from the semiconductor region 24 to the semiconductor region 25. More specifically, the gate electrode GA is disposed closer to the semiconductor region 24, and the gate electrode GS is disposed closer to the semiconductor region 25. The semiconductor regions 24 and 25 constitute a pair of main electrode regions; for example, the semiconductor region 24 is the drain region and the semiconductor region 25 is the source region. Both the semiconductor region 24 and the semiconductor region 25 are of a second conductivity type (e.g., n-type) and are in contact with well regions 21 of a first conductivity type (e.g., p-type). The semiconductor regions 24 and 25 face the first surface S1. The semiconductor region 24 is electrically connected to the power supply line VDD, and the semiconductor region 25 is electrically connected to the vertical signal line 11 (VSL). The well region 21 is an example of a first semiconductor region, the semiconductor region 24 is an example of a second semiconductor region, and the semiconductor region 25 is an example of a third semiconductor region. Also, as shown in FIG. 5A , insulating films 31 a made of a known insulating material are provided on both sides of the gate electrodes GA and GS in a direction intersecting the first direction. The insulating films 31 a may be part of the insulating film 31 of the wiring layer 30.

[0046] As shown in FIG. 5B , the gate electrodes GA and GS face the well region 21 between the semiconductor region 24 and the semiconductor region 25. Therefore, depending on the voltage supplied to the gate electrodes GA and GS, a channel can be formed along the first surface S1 from the semiconductor region 24 to the semiconductor region 25. More specifically, channels ChA and ChS are formed in series in this order from the semiconductor region 24 to the semiconductor region 25. The formation of both channels ChA and ChS electrically connects the semiconductor region 24 and the semiconductor region 25. To ensure that channels ChA and ChS are formed continuously and that the channels are not interrupted midway, it is desirable to provide as narrow a distance between the gate electrodes GA and GS as possible. More specifically, it is desirable to provide as narrow a distance as possible between the gate electrodes GA and GS at the position where they contact the gate insulating film m1.

[0047] In response to the voltage supplied to the gate electrode GS, a current corresponding to the amount of signal charge generated by the photoelectric conversion unit 22 flows between the semiconductor region 24 and the semiconductor region 25. More specifically, when a positive voltage is supplied to the gate electrode GS while signal charge is supplied to the gate electrode GA from the charge accumulation region 23, electrical conduction is established between the semiconductor region 24 and the semiconductor region 25 via the channels ChA and ChS, and a current corresponding to the amount of signal charge generated flows.

[0048] Examples of materials constituting the gate electrodes GA and GS include semiconductor materials such as polysilicon and metal materials such as tungsten (W). The gate electrodes GA and GS may be made of the same material. Examples of materials constituting the gate insulating film m1 include known insulating films, such as silicon oxide (SiO ２ ), high dielectric constant insulating film called high K (e.g., hafnium oxide (HfO ２ Examples of materials constituting the thin film m2 include known insulating films, such as silicon oxide and silicon nitride.

[0049] <<Main Effects of First Embodiment>> The main effects of the first embodiment will be described below, but before that, a comparative example shown in FIG. 22 will be described. In the comparative example, a drain region and a source region are provided for each of the amplifier transistor AMP and the select transistor SEL. Specifically, a drain region 24A and a source region 25A are provided for the amplifier transistor AMP, and a drain region 24S and a source region 25S are provided for the select transistor SEL. The source region 25A and the drain region 24S are separated from each other by an insulating film 31b and electrically connected via wiring 32a.

[0050] Even when pixels are miniaturized, there is a demand for the area occupied by the photoelectric conversion unit to be as large as possible. When pixels are miniaturized, it is sometimes difficult to secure the area required for the layout in the configuration of the amplification transistor AMP and the selection transistor SEL shown in the comparative example. Therefore, in some cases, two semiconductor layers are used, with the photoelectric conversion unit provided in one semiconductor layer and the readout circuit 15 provided in the other semiconductor layer.

[0051] However, when two semiconductor layers are used, an ion implantation process must be performed for each semiconductor layer. Also, front-end processes such as a process for forming elements such as transistors on the main surface side and a process for forming wiring must be performed for each semiconductor layer. This roughly doubles the number of processes, raising manufacturing costs.

[0052] In contrast, the photodetector according to the first embodiment of the present technology includes a semiconductor layer 20 having a matrix of cell regions 20a each having a photoelectric conversion unit 22 and a p-type well region 21, and a gate electrode GA and a gate electrode GS provided opposite the well region 21 via a gate insulating film m1 and electrically isolated from each other by being provided in contact with one surface or the other surface of an insulating thin film m2. The photodetector also includes a second conductivity type semiconductor region 24 and a second conductivity type semiconductor region 25 that constitute a pair of main electrode regions and are provided in the semiconductor layer 20 so as to be in contact with the well region 21. The gate electrode GA and the gate electrode GS are arranged between the semiconductor region 24 and the semiconductor region 25 and are arranged in that order along a first direction from the semiconductor region 24 to the semiconductor region 25. The gate electrode GA can be supplied with signal charges generated by the photoelectric conversion unit 22, and a current corresponding to the amount of signal charges generated by the photoelectric conversion unit 22 flows between the semiconductor region 24 and the semiconductor region 25 in accordance with a voltage supplied to the gate electrode GS.

[0053] As described above, in the first embodiment according to the present technology, a main electrode region is not provided for each transistor, but is provided only in pairs, and the pair of main electrode regions is shared by a plurality of transistors (amplification transistor AMP and selection transistor SEL). Therefore, it is possible to prevent the area occupied by the transistors in the semiconductor layer 20 from increasing in plan view, and it is possible to accommodate miniaturization of the pixel 3. Furthermore, by preventing the area occupied by the transistors in the semiconductor layer 20 from increasing in plan view, it is possible to configure both the photoelectric conversion unit 22 and the readout circuit 15 in a single semiconductor layer. If this is realized, it is possible to prevent an increase in the number of processes and an increase in manufacturing costs.

[0054] Furthermore, in the photodetector according to the first embodiment of the present technology, the gate electrode GA and the gate electrode GS are electrically separated from each other by the insulating thin film m2, so that when both are turned on, the channels ChA and ChS can be prevented from being disconnected, and a current corresponding to the amount of signal charge generated by the photoelectric conversion unit 22 can be passed between the semiconductor region 24 and the semiconductor region 25.

[0055] Modifications of the First Embodiment Modifications of the first embodiment will be described below. Note that in the drawings describing the modifications, the illustration of insulating films may be partially omitted.

[0056] <Modification 1> In the photodetector 1 according to the first embodiment, as shown in Fig. 5B , the gate electrode GA and the gate electrode GS are provided on the first surface S1 (horizontal plane) of the semiconductor layer 20, which is a horizontal plane, via the gate insulating film m1, but the present technology is not limited to this. In the photodetector 1 according to Modification 1 of the first embodiment, as shown in Figs. 6A and 6B , the gate electrode GA and the gate electrode GS are configured to face both the horizontal plane and the vertical plane on the first surface S1 side of the semiconductor layer 20, via the gate insulating film m1. The horizontal plane is a surface of the surface of the well region 21 that extends along the horizontal direction, and the vertical plane is a surface of the surface of the well region 21 that extends along the thickness direction of the semiconductor layer 20.

[0057] In this modification, the photodetector 1 includes a recess T provided in the well region 21 from the first surface S1 side. As shown in FIG. 6A , the recess T is provided between the semiconductor region 24 and the semiconductor region 25 in a plan view. As shown in FIG. 6B , the recess T is recessed from the first surface S1 side along the thickness direction of the semiconductor layer 20, and has an inner side surface and an inner bottom surface as shown. The inner side surface of the recess T is a vertical plane extending along the thickness direction of the semiconductor layer 20, and the inner bottom surface of the recess T is a horizontal plane extending along the horizontal direction. The dimension of the recess T along the depth direction (thickness direction of the semiconductor layer 20) is larger than the dimensions of the semiconductor region 24 and the semiconductor region 25 along the depth direction (thickness direction of the semiconductor layer 20). In addition, well regions 21 are interposed between the semiconductor region 24 and the recess T, and between the semiconductor region 25 and the recess T, and the well regions 21 face the inner sides of the recess T that face each other along the first direction. In addition, in one recess T, both the gate electrode GA and the gate electrode GS are provided.

[0058] The gate electrode GA continuously faces the first surface S1, which is a horizontal plane, the inner side surfaces of the recessed portion T, which are vertical planes, and the inner bottom surface of the recessed portion T, which is also a horizontal plane, via the gate insulating film m1. The gate electrode GA faces one of the inner side surfaces that face each other along the first direction of the recessed portion T, more specifically, the inner side surface of the inner side surfaces that face each other along the first direction of the recessed portion T, which is closest to the semiconductor region 24, i.e., the inner side surface that is closest to the semiconductor region 24. The gate electrode GS continuously faces the first surface S1, which is a horizontal plane, the inner side surfaces of the recessed portion T, which are vertical planes, and the inner bottom surface of the recessed portion T, which is also a horizontal plane, via the gate insulating film m1. The gate electrode GS faces the other of the inner side surfaces that face each other along the first direction of the recessed portion T, more specifically, the inner side surface of the inner side surfaces that face each other along the first direction of the recessed portion T, which is closest to the semiconductor region 25, i.e., the inner side surface that is closest to the semiconductor region 25. The gate electrodes GA and GS are electrically isolated from each other by a thin film m2 at the inner bottom surface of the recessed portion T.

[0059] In this way, each of the gate electrodes GA and GS faces not only the horizontal plane but also the vertical plane. The gate electrodes GA and GS can form channels ChA and ChS in the region of the well region 21 facing the vertical plane as well as the region facing the horizontal plane. Therefore, if the area occupied by the transistor in the semiconductor layer 20 is the same in plan view, the gate length can be made longer and the area of ​​the gate electrodes GA and GS facing the well region 21 can be made wider than when the transistor faces only the horizontal plane.

[0060] Depending on the dimension between the semiconductor region 24 and the recess T and the dimension between the semiconductor region 25 and the recess T, channels ChA and ChS may be formed to connect the lower end side of the semiconductor region 24 and the lower end side of the semiconductor region 25. However, even in such a case, this modified example is configured such that the dimension along the depth direction of the recess T is larger than the dimension along the depth direction of the semiconductor region 24 and the semiconductor region 25. Therefore, in each of the gate electrode GA and the gate electrode GS, channels ChA and ChS can be formed not only in the region of the well region 21 facing the horizontal plane but also in the region facing the vertical plane.

[0061] The photodetector 1 according to the first modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0062] Furthermore, in the photodetector 1 according to the first modification of the first embodiment, the well region 21 has, on the first surface S1 side of the semiconductor layer 20, a horizontal plane extending along the horizontal direction and a vertical plane extending along the thickness direction of the semiconductor layer 20. The gate electrode GA and the gate electrode GS are configured to face both the horizontal plane and the vertical plane via the gate insulating film m1. This prevents the area occupied by the transistor in the semiconductor layer 20 from increasing in plan view, thereby enabling miniaturization of the pixel 3. Even if the area occupied by the transistor in the semiconductor layer 20 is reduced in plan view, the gate electrode GA and the gate electrode GS each face both the horizontal plane and the vertical plane, preventing the gate length from becoming too short. As a result, even if the area occupied by the transistor in the semiconductor layer 20 is reduced, the channels ChA and ChS are formed in the well region 21 facing the horizontal plane as well as the vertical plane, thereby suppressing the short channel effect and preventing excessive off-leakage current. Furthermore, since the area of ​​the gate electrodes GA and GS, more specifically, the area of ​​the gate electrodes GA and GS facing the well region 21, can be prevented from becoming too small, the random telegraph noise (RTS) can be prevented from becoming too large. In particular, the random telegraph noise of the amplification transistor AMP can be prevented from becoming too large.

[0063] Furthermore, the photodetector 1 according to the first modification of the first embodiment includes a recess T provided in the well region 21 from the first surface S1 side, with the inner side surface of the recess T being a vertical plane and the inner bottom surface of the recess being a horizontal plane. Since the gate electrodes GA and GS are provided using the inner side surface of the recess T, even if the area occupied by the transistor in the semiconductor layer 20 in plan view is reduced, the gate length can be further prevented from becoming too short, the short channel effect can be suppressed, and the off-leak current can be prevented from becoming too large. Furthermore, since the area of ​​the gate electrode can be prevented from becoming too small, random telegraph noise (RTS) can be prevented from becoming too large.

[0064] Furthermore, in the photodetector 1 according to the first modification of the first embodiment, the dimension of the recess T along the depth direction is set to be larger than the dimensions of the semiconductor region 24 and the semiconductor region 25 along the depth direction, so that the gate length can be prevented from becoming too short regardless of the dimension between the semiconductor region 24 and the recess T and the dimension between the semiconductor region 25 and the recess T. As a result, even if the area occupied by the transistor in the semiconductor layer 20 is reduced, the short channel effect can be suppressed, and the off-leak current can be prevented from becoming too large.

[0065] <Variation 2> In the photodetector 1 according to Variation 2 of the first embodiment, as shown in Figures 7A and 7B, of the inner surfaces facing each other along the first direction of the recess T, a semiconductor region 24 faces one of the inner surfaces, and a semiconductor region 25 faces the other inner surface.

[0066] 7B , of the inner surfaces of the recessed portion T that face each other along the first direction, the semiconductor region 24 faces the inner surface that faces the gate electrode GA via the gate insulating film m1, and the semiconductor region 25 faces the inner surface that faces the gate electrode GS via the gate insulating film m1. That is, the semiconductor region 24 and the semiconductor region 25 face the sidewall of the recessed portion T so as to face each other along the first direction. Furthermore, the gate electrode GA faces the semiconductor region 24 via the gate insulating film m1, and the gate electrode GS faces the semiconductor region 25 via the gate insulating film m1. With this configuration, even if a well region 21 is interposed between the semiconductor region 24 and the recessed portion T and between the semiconductor region 25 and the recessed portion T, it is only a small amount, which further prevents the area occupied by the transistor in the semiconductor layer 20 from increasing in plan view.

[0067] Furthermore, in the above-described configuration, since the well region 21 is not interposed between the semiconductor regions 24, 25 and the recess T, no channel is formed along the first surface S1, and the channels ChA, ChS are formed to connect the lower end of the semiconductor region 24 with the lower end of the semiconductor region 25. When the dimensions between the semiconductor region 24 and the recess T and between the semiconductor region 25 and the recess T are relatively small, even if the well region 21 is interposed between the semiconductor regions 24, 25 and the recess T, the channels ChA, ChS may be formed to connect the lower end of the semiconductor region 24 with the lower end of the semiconductor region 25. In such a case, applying the configuration of this modification can further prevent the area occupied by the transistor in the semiconductor layer 20 from increasing in plan view. Even in this case, since the depth dimension of the recess T is set larger than the depth dimensions of the semiconductor regions 24 and 25, the vertical plane can be used to prevent the gate length from becoming too short.

[0068] Even with the photodetector 1 according to this modified example 2 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to modified example 1 of the first embodiment described above can be obtained.

[0069] Furthermore, in the photodetector 1 according to the second modification of the first embodiment, even if there is a small amount of well region 21 interposed between the semiconductor region 24 and the recess T, and between the semiconductor region 25 and the recess T, the area occupied by the transistor in the semiconductor layer 20 in plan view can be further prevented from increasing, and the miniaturization of the pixel 3 can be accommodated.

[0070] 8A and 8B , in the photodetector 1 according to the third modification of the first embodiment, the gate electrode GS has a first portion GS1 and a second portion GS2 that are arranged along the first direction and electrically connected to each other, and the gate electrode GA is arranged between the first portion GS1 and the second portion GS2. That is, the select transistor SEL is configured as two separate transistors.

[0071] As shown in FIG. 8A , the first portion GS1 and the second portion GS2 are electrically connected via, for example, a connection portion GS3. The first portion GS1 constitutes the select transistor SEL1, and the second portion GS2 constitutes the select transistor SEL2. The first portion GS1 and the second portion GS2 may also be electrically connected via wiring. As shown in FIG. 8B , when a positive voltage is applied to the first portion GS1 and the second portion GS2, a channel ChS1 is formed in the well region 21 facing the first portion GS1, and a channel ChS2 is formed in the well region 21 facing the second portion GS2. A current corresponding to the amount of generated signal charge flows between the semiconductor region 24 and the semiconductor region 25 via the channels ChS1, ChA, and ChS2. On the other hand, when a negative voltage is applied to the first portion GS1 and the second portion GS2, the select transistor SEL is turned off, and the channels ChS1 and ChS2 are not formed. By disposing the gate electrodes GS separately on both sides of the gate electrode GA, the gate electrode GA can be separated from both the semiconductor regions 24 and 25, thereby further suppressing off-leak current when the signal amplified by the amplifier transistor AMP is not output. Even when signal charge is supplied to the gate electrode GA, the channel ChA and the semiconductor regions 24 and 25 are blocked from each other, so that the off-leak current can be further suppressed compared to when only the channel ChA and the semiconductor region 25 are blocked from each other.

[0072] Even with the photodetector 1 according to this modified example 3 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to modified example 1 of the first embodiment described above can be obtained.

[0073] Furthermore, in the photodetector 1 according to the third modification of the first embodiment, it is possible to further prevent the off-leak current from becoming too large.

[0074] Furthermore, in the photodetector 1 according to the third modification of the first embodiment, the recess T is provided, which provides more space for arranging the transistor, and therefore it is possible to improve the performance of the transistor, such as by further suppressing the off-leakage current.

[0075] 9A and 9B , in the photodetector 1 according to the fourth modification of the first embodiment, the semiconductor region 24 faces one of the inner surfaces facing each other along the first direction of the recess T, and the semiconductor region 25 faces the other inner surface. The gate electrode GS has a first portion GS1 and a second portion GS2 that are arranged along the first direction and electrically connected to each other, and the gate electrode GA is arranged between the first portion GS1 and the second portion GS2.

[0076] 9B , of the inner surfaces of the recessed portion T that face each other along the first direction, the semiconductor region 24 faces the inner surface facing the gate electrode GS1 via the gate insulating film m1, and the semiconductor region 25 faces the inner surface facing the gate electrode GS2 via the gate insulating film m1. That is, the semiconductor region 24 and the semiconductor region 25 face the sidewall of the recessed portion T so as to face each other along the first direction. Furthermore, the first portion GS1 faces the semiconductor region 24 via the gate insulating film m1, and the second portion GS2 faces the semiconductor region 25 via the gate insulating film m1. With this configuration, even if a well region 21 is interposed between the semiconductor region 24 and the recessed portion T and between the semiconductor region 25 and the recessed portion T, the well region 21 is only slight, which further prevents the area occupied by the transistor in the semiconductor layer 20 from increasing in plan view.

[0077] Furthermore, in the above-described configuration, since the well region 21 is not interposed between the semiconductor regions 24, 25 and the recess T, no channel is formed along the first surface S1, and channels ChS1, ChA, and ChS2 are formed to connect the lower end of the semiconductor region 24 with the lower end of the semiconductor region 25. When the dimensions between the semiconductor region 24 and the recess T and between the semiconductor region 25 and the recess T are relatively small, channels ChS1, ChA, and ChS2 may be formed to connect the lower end of the semiconductor region 24 with the lower end of the semiconductor region 25, even if the well region 21 is interposed between the semiconductor regions 24, 25 and the recess T. In such cases, applying the configuration of this modified example can further prevent the area occupied by the transistor in the semiconductor layer 20 from increasing in plan view. Even in this case, since the depth dimension of the recess T is set larger than the depth dimensions of the semiconductor regions 24 and 25, the vertical plane can be used to prevent the gate length from becoming too short.

[0078] Even with the photodetector 1 according to this fourth modification of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to the third modification of the first embodiment described above can be obtained.

[0079] Furthermore, in the photodetector 1 according to the fourth modification of the first embodiment, even if there is a small amount of well region 21 interposed between the semiconductor region 24 and the recess T, and between the semiconductor region 25 and the recess T, the area occupied by the transistor in the semiconductor layer 20 in plan view can be further prevented from increasing, and the miniaturization of the pixel 3 can be accommodated.

[0080] <Modification 5> In the photodetector 1 according to Modification 1 of the first embodiment, as shown in Fig. 6B , the recess T is provided in the well region 21, but the present technology is not limited to this. As shown in Figs. 10A and 10B , the photodetector 1 according to Modification 5 of the first embodiment includes a protrusion F made of the well region 21, and the gate electrode GA and the gate electrode GS are each provided to face the outer surface of the protrusion F with the gate insulating film m1 interposed therebetween. More specifically, both the gate electrode GA and the gate electrode GS are provided to face the outer surface of one protrusion F.

[0081] 10A , the protrusion F is provided between the semiconductor region 24 and the semiconductor region 25 in a plan view. As shown in FIG. 10B , the protrusion F is provided on the first surface S1 side of the semiconductor layer 20 and protrudes toward the wiring layer 30 along the thickness direction of the semiconductor layer 20. As shown in the figure, the protrusion F has an outer surface and an upper end surface. The outer surface of the protrusion F is a vertical plane extending along the thickness direction of the semiconductor layer 20, and the upper end surface of the protrusion F is a horizontal plane extending along the horizontal direction. The upper end surface of the protrusion F protrudes from the surfaces of the semiconductor regions 24 and 25 facing the wiring layer 30.

[0082] The gate electrode GA continuously faces the first surface S1, which is a horizontal plane, the outer side surfaces of the protrusions F, which are vertical planes, and the upper end surfaces of the protrusions F, which are horizontal planes, via the gate insulating film m1. The gate electrode GA faces one of the outer side surfaces (vertical planes) of the protrusions F that face each other along the first direction, more specifically, the outer side surface closest to the semiconductor region 24 among the outer side surfaces of the protrusions F that face each other along the first direction, i.e., the outer side surface closest to the semiconductor region 24. Here, the outer side surfaces of the protrusions F that face each other along the first direction are outer side surfaces whose normal vectors extend along the first direction. The gate electrode GS continuously faces the first surface S1, which is a horizontal plane, the outer side surfaces of the protrusions F, which are vertical planes, and the upper end surfaces of the protrusions F, which are horizontal planes, via the gate insulating film m1. The gate electrode GS faces the other of the outer surfaces (vertical planes) of the protrusion F that face each other along the first direction, more specifically, the outer surface that is closest to the semiconductor region 25 among the outer surfaces that face each other along the first direction of the protrusion F, i.e., the outer surface that is closest to the semiconductor region 25. The gate electrode GA and the gate electrode GS are electrically isolated from each other on the upper end surface of the protrusion F by a thin film m2.

[0083] In this way, each of the gate electrodes GA and GS faces not only the horizontal plane but also the vertical plane. The gate electrodes GA and GS can form channels ChA and ChS in the region of the well region 21 facing the vertical plane as well as the region facing the horizontal plane. Therefore, if the area occupied by the transistor in the semiconductor layer 20 is the same in plan view, the gate length can be made longer and the area of ​​the gate electrodes GA and GS facing the well region 21 can be made wider than when the transistor faces only the horizontal plane.

[0084] Even with the photodetector 1 according to this variant 5 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to variant 1 of the first embodiment described above can be obtained.

[0085] <Modification 6> In the photodetector 1 according to Modification 5 of the first embodiment, as shown in FIG. 10B , the gate electrodes GA and GS face outer surfaces of the convex portion F that face each other along the first direction, but the present technology is not limited to this. In the photodetector 1 according to Modification 6 of the first embodiment, as shown in FIGS. 11A to 11D , the gate electrode GA faces outer surfaces (vertical planes) of the convex portion F that face each other along a direction intersecting (e.g., perpendicular to) the first direction. Note that the outer surfaces of the convex portion F that face each other along the direction intersecting the first direction are outer surfaces whose normal vectors extend along a direction intersecting the first direction. FIG. 11B shows a cross-sectional configuration when viewed in a plane along the A-A cutting line in FIG. 11A , FIG. 11C shows a cross-sectional configuration when viewed in a plane along the B-B cutting line in FIG. 11A , and FIG. 11D shows a cross-sectional configuration when viewed in a plane along the D-D cutting line in FIG. 11A . The cross-sectional configuration of the gate electrode GS when viewed in a cross-section along the CC cutting line in Fig. 11A has the same configuration as the cross-sectional configuration of the gate electrode GA shown in Fig. 11C. Therefore, the cross-sectional configuration when viewed in a cross-section along the CC cutting line and its description will be omitted.

[0086] As shown in FIG. 11A , the protrusion F is provided between the semiconductor region 24 and the semiconductor region 25 in a plan view. As shown in FIG. 11B , the protrusion F has a channel ChA and a channel ChS formed in series in this order along the first direction. The gate electrode GA and the gate electrode GS each face the upper end surface of the well region 21, which is a horizontal plane, via a gate insulating film m1. As shown in FIG. 11C , the protrusion F protrudes toward the wiring layer 30 along the thickness direction of the semiconductor layer 20. As shown in FIG. 11D , the semiconductor region 25, like the protrusion F, protrudes toward the wiring layer 30 along the thickness direction of the semiconductor layer 20. The semiconductor region 24 has a similar configuration to the semiconductor region 25, and is therefore not shown. As shown in FIG. 11B , the semiconductor regions 24 and 25 are connected to the protrusion F along the first direction.

[0087] As shown in FIG. 11C , the protrusion F has a pair of outer surfaces facing each other along a direction intersecting the first direction (gate length direction), and both of the pair of outer surfaces correspond to vertical planes. The gate electrode GA is configured to face not just one but multiple (two in FIG. 11C ) vertical planes. The gate electrode GA covers the protrusion F from three directions along a direction intersecting the first direction (gate length direction) via the gate insulating film m1. This prevents the dimensions of the gate electrodes GA and GS along a direction intersecting the first direction (gate width direction) from becoming too small. Because the gate electrode GA has this configuration, the channel ChA is formed in the region of the protrusion F along the horizontal plane and the pair of vertical planes. The same applies to the channel ChS.

[0088] Even with the photodetector 1 according to this variant 6 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to variant 5 of the first embodiment described above can be obtained.

[0089] Furthermore, in the photodetector 1 according to the sixth modification of the first embodiment, the gate electrodes GA and GS cover the well region 21 from three directions, so even if the area that the transistor occupies in the semiconductor layer 20 is reduced in plan view, it is possible to prevent the potential controllability of the channels ChA and ChS from decreasing, and it is possible to prevent the off-leak current from becoming too large.

[0090] Furthermore, in the photodetector 1 according to the sixth modification of the first embodiment, the gate electrodes GA and GS cover the well region 21 from three directions, which prevents the gate width from becoming too small and prevents the area of ​​the gate electrodes GA and GS, more specifically, the area of ​​the gate electrodes GA and GS facing the well region 21, from becoming too small. This prevents the random telegraph noise (RTS) from becoming too large. In particular, it prevents the random telegraph noise of the amplification transistor AMP from becoming too large.

[0091] <Variation 7> In the photodetector 1 according to Variation 6 of the first embodiment, as shown in FIG. 11A , one convex portion F is provided, but the present technology is not limited to this. In the photodetector 1 according to Variation 7 of the first embodiment, as shown in FIGS. 12A and 12B , a plurality of convex portions F are provided along a direction intersecting the first direction. More specifically, a plurality of convex portions F are provided along a direction perpendicular to the first direction. Note that the cross-sectional configuration along the A-A cutting line in FIG. 12A is the same as the configuration shown in FIG. 11B described above, and therefore will not be illustrated or described here. FIG. 12B shows the cross-sectional configuration of the gate electrode GA when viewed along the B-B cutting line in FIG. 12A . The cross-sectional configuration of the gate electrode GS when viewed along the C-C cutting line in FIG. 12A is similar to the cross-sectional configuration of the gate electrode GA shown in FIG. 12B . Therefore, the cross-sectional configuration when viewed along the C-C cutting line and its description will be omitted.

[0092] 12B, by providing multiple protrusions F, it is possible to further increase the area of ​​both the horizontal and vertical planes compared to the case of the above-described sixth embodiment. If a similar transistor were to be constructed using only horizontal planes without providing protrusions, a very large space would be required. Furthermore, by increasing the number of protrusions F, it is possible to increase the current that can flow.

[0093] Even with the photodetector 1 according to this modified example 7 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to modified example 6 of the first embodiment described above can be obtained.

[0094] Furthermore, in the photodetector 1 according to the seventh modification of the first embodiment, the performance of the transistors can be further improved compared to the sixth modification described above.

[0095] <Variant 8> In the light detection device 1 according to variant 8 of the first embodiment, as shown in Figures 13A, 13B, and 13C, a convex portion F is formed between two concave portions T that extend along the first direction and are spaced apart in a direction perpendicular to the first direction.

[0096] In this embodiment, the protrusion F shown in Modification Example 6 is provided by being dug in the thickness direction of the semiconductor layer 20. Note that Fig. 13B shows the cross-sectional configuration of the gate electrode GA when viewed in a cross-section along the B-B cutting line in Fig. 13A. The cross-sectional configuration of the gate electrode GS when viewed in a cross-section along the C-C cutting line in Fig. 13A has the same configuration as the cross-sectional configuration of the gate electrode GA shown in Fig. 13B. Fig. 13C shows the cross-sectional configuration when viewed in a cross-section along the D-D cutting line in Fig. 13A.

[0097] Even with the photodetector 1 according to this variant 8 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to variant 6 of the first embodiment described above can be obtained.

[0098] In the photodetector 1 according to the eighth modification of the first embodiment, the convex portion F shown in the seventh modification may be provided by being dug in the thickness direction of the semiconductor layer 20 .

[0099] <Modification 9> In a photodetector 1 according to Modification 9 of the first embodiment, as shown in FIG. 14, the present technology is applied to a transfer transistor TR.

[0100] The photoelectric conversion section 22 and the charge accumulation region 23 each contact the well region 21. The charge accumulation region 23 is a region configured in the semiconductor layer 20 as the charge accumulation region FD shown in FIG. 3 and is an example of a first charge accumulation region. The charge accumulation region 23 is located closer to the first surface S1 than the photoelectric conversion section 22. More specifically, the charge accumulation region 23 faces the first surface S1.

[0101] The recess Ta, which is a recess in which the gate electrode GTa of the transfer transistor TR is provided, is recessed from the first surface S1 side along the thickness direction of the semiconductor layer 20, and has an inner side surface and an inner bottom surface as shown. The inner side surface of the recess Ta is a vertical plane extending along the thickness direction of the semiconductor layer 20, and the inner bottom surface of the recess Ta and the first surface S1 are horizontal planes extending along the horizontal direction. Within one recess Ta, two gate electrodes, a gate electrode GTa and a gate electrode GTb, are arranged. The gate electrodes GTa and GTb are configured to face each other in both the horizontal and vertical planes via a gate insulating film m1. Furthermore, within one recess Ta, both the gate electrode GTa, which is an example of a first gate electrode, and the gate electrode GTb, which is an example of a second gate electrode, are provided. The gate electrodes GTa and GTb are aligned horizontally and electrically isolated from each other by being in contact with one or the other of an insulating thin film m2.

[0102] The gate electrode GTa of the transfer transistor TR is located closer to the charge accumulation region 23 than the gate electrode GTb. Therefore, the region of the well region 21 facing the gate electrode GTa functions as a channel formation region. The transfer transistor TR is turned on or off depending on the voltage supplied to the gate electrode GTa. The gate electrode GTa is selectively supplied with a voltage that attracts electrons or holes in the same direction as the signal charge, or a voltage that repels the signal charge. In this embodiment, since the signal charge is electrons, a positive voltage is supplied as a voltage that attracts electrons, and a negative voltage is supplied as a voltage that repels electrons. When a positive voltage is supplied to the gate electrode GTa, the transfer transistor TR is turned on, and a channel ChT that electrically connects the photoelectric conversion unit 22 and the charge accumulation region 23 is formed. When a negative voltage is supplied to the gate electrode GTa, the transfer transistor TR is turned off, and the channel ChT is not formed, electrically isolating the photoelectric conversion unit 22 and the charge accumulation region 23.

[0103] The gate electrode GTb is located farther from the charge accumulation region 23 than the gate electrode GTa. Therefore, the region of the well region 21 facing the gate electrode GTb is difficult to use as a channel formation region. A voltage that repels electrons and holes in the same direction as the signal charges is supplied to the gate electrode GTb. In this embodiment, since the signal charges are electrons, a negative voltage is supplied as a voltage that repels the electrons. The gate electrode GTb is always fixed at a negative voltage, regardless of whether the gate electrode GTa is in an on state or an off state. As a result, holes are induced in the region 26 of the well region 21 facing the gate electrode GTb, thereby suppressing surface-generated current.

[0104] Even with the photodetector 1 according to this variant 9 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to variant 1 of the first embodiment described above can be obtained.

[0105] Furthermore, in the photodetector 1 according to the ninth modification of the first embodiment, the gate electrode GTa faces not only the horizontal plane but also the vertical plane, and therefore, deterioration of the transfer characteristics of the signal charge can be suppressed compared to when it faces only the horizontal plane.

[0106] Furthermore, if only one gate electrode were formed in the recess Ta, the portion of the well region 21 not used for signal charge transfer would be depleted, potentially generating a surface-generated current and becoming a noise source. In contrast, in the photodetector 1 according to the ninth modification of the first embodiment, the gate electrode is divided into two gate electrodes GTa and GTb, which are provided within a single recess T. The gate electrode GTa is positioned closer to the charge accumulation region 23 than the gate electrode GTb, and signal charges are transferred from the photoelectric conversion unit 22 to the charge accumulation region 23 in response to the voltage supplied to the gate electrode GTa. Furthermore, a voltage that repels the signal charges can be supplied to the gate electrode GTb, which is farther from the charge accumulation region 23. Therefore, holes can be induced in the region 26 that is difficult to use for signal charge transfer, thereby pinning and fixing the non-transfer surface. This prevents the non-transfer surface from being depleted and suppresses the surface-generated current.

[0107] 15A and 15B , in a photodetector 1 according to a modification 10 of the first embodiment, the present technology is applied to a photodetector 1 of a global shutter type that captures images of all pixels at the same time. For example, the present technology can be applied to a photodetector 1 of a memory-holding global shutter type.

[0108] As shown in FIG. 15A , a memory-retention global shutter photodetector 1 includes a charge accumulation region MEM that accumulates signal charges between a photoelectric conversion element PD and a charge accumulation region FD. In the global shutter photodetector 1, all pixels are exposed at the same time, and the generated signal charges are temporarily stored in the charge accumulation region MEM by a transfer transistor TRx. The signal charges stored in the charge accumulation region MEM are then sequentially read out by a transfer transistor TR and transferred to the charge accumulation region FD. The transfer transistor TR is connected between the transfer transistor TRx and the charge accumulation region MEM and the charge accumulation region 23, and transfers the signal charges stored in the charge accumulation region MEM to the charge accumulation region 23 in response to a voltage applied to the gate electrode GT ( FIG. 15B ) of the transfer transistor TR. For example, when the transfer transistor TRx is turned off and the transfer transistor TR is turned on, the signal charges stored in the charge accumulation region MEM are transferred to the charge accumulation region FD.

[0109] As shown in FIG. 15B , the charge accumulation region 27 is a region configured in the semiconductor layer 20 as the charge accumulation region MEM shown in FIG. 15A and is an example of a first charge accumulation region. The charge accumulation region 27 is a semiconductor region of a second conductivity type (e.g., n-type) and is in contact with the well region 21. The charge accumulation region 27 is located closer to the first surface S1 than the photoelectric conversion unit 22. The charge accumulation region FD, not shown in FIG. 15B , is an example of a second charge accumulation region. The charge accumulation region FD has a configuration similar to that of a known charge accumulation region in the semiconductor layer 20. Furthermore, the gate electrode GT of the transfer transistor TR may have a configuration similar to that of Modification 9 shown in FIG. 14 or the gate electrode GT of the first embodiment shown in FIG. 4 .

[0110] As shown in FIG. 15B , the recess Tb, which is a recess in which the gate electrode GTRx of the transfer transistor TRx is provided, is recessed from the first surface S1 side along the thickness direction of the semiconductor layer 20 and has an inner side surface and an inner bottom surface as shown. The inner side surface of the recess Tb is a vertical plane extending along the thickness direction of the semiconductor layer 20, and the inner bottom surface of the recess Tb and the first surface S1 are horizontal planes extending along the horizontal direction. The gate electrode GTRx and the gate electrode GTRy are each configured to face both the horizontal plane and the vertical plane via a gate insulating film m1. Furthermore, both the gate electrode GTRx, which is an example of a first gate electrode, and the gate electrode GTRy, which is an example of a second gate electrode, are provided in one recess Tb. The gate electrode GTRx and the gate electrode GTRy are aligned horizontally and electrically isolated from each other by being provided in contact with one surface or the other surface of an insulating thin film m2.

[0111] The gate electrode GTRx of the transfer transistor TRx is located closer to the charge accumulation region 27 than the gate electrode GTRy. Therefore, the region of the well region 21 facing the gate electrode GTRx functions as a channel formation region. The transfer transistor TRx is turned on or off depending on the voltage supplied to the gate electrode GTRx. The gate electrode GTRx is selectively supplied with a voltage that attracts electrons or holes in the same direction as the signal charges or a voltage that repels the signal charges. In this embodiment, since the signal charges are electrons, a positive voltage is supplied as a voltage that attracts electrons and a negative voltage is supplied as a voltage that repels electrons. When a positive voltage is supplied to the gate electrode GTRx, the transfer transistor TRx is turned on, and a channel ChTRx that electrically connects the photoelectric conversion unit 22 and the charge accumulation region 27 is formed. When a negative voltage is supplied to the gate electrode GTRx, the transfer transistor TRx is turned off, and the channel ChTRx is not formed, electrically isolating the photoelectric conversion unit 22 and the charge accumulation region 27.

[0112] The gate electrode GTRy is disposed at a position farther from the charge accumulation region 27 than the gate electrode GTRx. Therefore, the region of the well region 21 facing the gate electrode GTRy is unlikely to function as a channel formation region. A voltage that repels electrons and holes in the same direction as the signal charges is supplied to the gate electrode GTRy. In this embodiment, since the signal charges are electrons, a negative voltage is supplied as a voltage that repels the electrons. The gate electrode GTRy is always fixed at a negative voltage, regardless of whether the gate electrode GTRx is in an on state or an off state. As a result, holes are induced in the region 26 of the well region 21 facing the gate electrode GTRy, thereby suppressing surface-generated current.

[0113] Even with the photodetector 1 according to this modified example 10 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to modified example 9 of the first embodiment described above can be obtained.

[0114] <Modification 11> In a photodetector 1 according to Modification 11 of the first embodiment, as shown in FIGS. 16A and 16B, the present technology is applied to a CCD (Charge Coupled Device) type photodetector 1.

[0115] FIG. 16A shows a portion of a pixel region 2A of a CCD-type photodetector 1. The photoelectric conversion units 22 are arranged in a matrix. Vertical transfer registers (V registers) VR are provided between columns of the photoelectric conversion units 22, and horizontal transfer registers (H registers) HR are provided at the bottom ends (bottom of the paper) of the photoelectric conversion units 22. The vertical transfer registers VR transfer signal charges transferred from the photoelectric conversion units 22 via transfer transistors (not shown) in the vertical direction (up and down on the paper) and pass the signal charges to the horizontal transfer registers HR at their bottom ends. The horizontal transfer registers HR transfer the received signals in the horizontal direction (left and right on the paper). Because the vertical transfer registers VR and horizontal transfer registers HR have similar configurations, this modification will be described using the vertical transfer registers VR as an example.

[0116] FIG. 16B shows a portion of the cross-sectional configuration of the vertical transfer register VR when viewed along the E-E line in FIG. 16A . The vertical transfer register VR has a plurality of recesses T1 arranged in a row. The inner side surfaces of the recesses T1 are vertical planes, and the inner bottom surfaces of the recesses T1 are horizontal planes. A gate electrode G1, which is an example of a first gate electrode, and a gate electrode G2, which is an example of a second gate electrode, are provided for each recess T1. The gate electrodes G1 and G2 are arranged in that order along the arrangement direction of the recesses T1. The gate electrodes G1 and G2 face each other in both the horizontal and vertical planes via a gate insulating film m1. The gate electrodes G1 and G2 are electrically isolated from each other by an insulating thin film m2. Signal charges are transferred by selectively supplying a voltage that attracts signal charges or a voltage that repels signal charges to the gate electrodes G1 and G2. When a voltage that attracts signal charges is supplied to a gate electrode, the signal charges are stored in the region of well region 21 that faces that gate electrode. For example, in the example shown in FIG. 16B , signal charges are stored in region R1. Then, when a voltage that attracts signal charges is supplied to the gate electrode adjacent to the gate electrode facing region R1 and a voltage that repels the signal charges is supplied to the gate electrode facing region R1, the signal charges are transferred from region R1 to region R2. By repeating this control, the signal charges can be transferred in the order of region R1, region R2, region R3, and region R4.

[0117] Even with the photodetector 1 according to this variant 11 of the first embodiment, the same effects as those of the photodetector 1 according to the first embodiment described above and the photodetector 1 according to variant 1 of the first embodiment described above can be obtained.

[0118] Furthermore, the photodetector 1 according to variant example 11 of the first embodiment has a recess T1, and gate electrodes G1 and G2 are provided inside along the vertical plane as well as the horizontal plane of the recess T1. Therefore, compared to a case where the recess T1 is not provided, the amount of signal charge that can be received from the photoelectric conversion section 22 can be increased, and smear can be suppressed.

[0119] Furthermore, in the photodetector 1 relating to variant example 11 of the first embodiment, the gate electrode G1 and the gate electrode G2 each face the vertical plane in addition to the horizontal plane, so that even when the pixel is miniaturized, it is possible to prevent the amount of signal charge that can be received from the photoelectric conversion unit 22 from becoming insufficient.

[0120] Second Embodiment 1. Application Example to Electronic Device Next, an electronic device 100 according to a second embodiment of the present technology will be described, as shown in Fig. 17 . The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-described photodetector device 1 as the solid-state imaging device 101.

[0121] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transfer from the solid-state imaging device 101 is performed in accordance with the drive signal (timing signal) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0122] With this configuration, the electronic device 100 can reduce the area of ​​the transistors in the solid-state imaging device 101, which may enable miniaturization and prevent increases in manufacturing costs.

[0123] The electronic device 100 is not limited to a camera, but may be other electronic devices, such as an imaging device such as a camera module for a mobile device such as a mobile phone.

[0124] Furthermore, the electronic device 100 can be provided with, as the solid-state imaging device 101, a photodetector 1 according to either the first embodiment or its modified example, or a photodetector 1 according to a combination of at least two of the first embodiment and its modified examples.

[0125] 2. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0126] FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0127] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 18, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0128] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0129] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0130] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0131] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0132] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0133] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0134] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0135] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0136] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 18, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0137] FIG. 19 is a diagram showing an example of the installation position of the imaging unit 12031.

[0138] In FIG. 19, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0139] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0140] 19 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0141] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0142] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0143] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0144] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0145] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the above-described light detection device 1 can be applied to the imaging unit 12031. Applying the technology according to the present disclosure to the imaging unit 12031 can reduce the area of ​​the transistors, thereby enabling miniaturization and potentially suppressing increases in manufacturing costs.

[0146] 3. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0147] FIG. 20 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0148] 20 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0149] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0150] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0151] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0152] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0153] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0154] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing the surgical site, etc.

[0155] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0156] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0157] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0158] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0159] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light in a narrower band than the light irradiated during normal observation (i.e., white light) to capture high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, in what is known as narrow band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or may involve locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissues with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0160] FIG. 21 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0161] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0162] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0163] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (so-called single-chip type) or multiple (so-called multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0164] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0165] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0166] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0167] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0168] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0169] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0170] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0171] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0172] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0173] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0174] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0175] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0176] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0177] The foregoing has described an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 of the above-described configuration. Specifically, the above-described light detection device 1 can be applied to the imaging unit 11402. Applying the technology according to the present disclosure to the imaging unit 11402 can reduce the area of ​​transistors, thereby enabling miniaturization and potentially suppressing increases in manufacturing costs.

[0178] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0179] [Other Embodiments] As described above, the present technology has been described by the first and second embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0180] For example, it is also possible to combine the technical ideas described in the first and second embodiments.

[0181] Furthermore, this technology can be applied to photodetection devices in general, including not only the solid-state imaging device as the image sensor described above but also distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until when the reflected light is received. The above-described transistor structure can be adopted as the structure of this distance measurement sensor.

[0182] Furthermore, for example, the materials cited as constituting the above-mentioned components may contain additives, impurities, and the like.

[0183] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0184] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0185] The present technology may be configured as follows: (1) A photodetector comprising: a semiconductor layer having a plurality of cell regions in a matrix arrangement, each of which has a photoelectric conversion unit configured therein, and a first semiconductor region of a first conductivity type configured therein; and a first gate electrode and a second gate electrode provided opposite the first semiconductor region via a gate insulating film and electrically isolated from each other by being provided in contact with one surface or the other surface of an insulating thin film. (2) The photodetector according to (1), further comprising: a second semiconductor region and a third semiconductor region of a second conductivity type configured in the semiconductor layer so as to be in contact with the first semiconductor region, and configuring a pair of main electrode regions; the first gate electrode and the second gate electrode are disposed between the second semiconductor region and the third semiconductor region, and are arranged in that order along a first direction that is a direction from the second semiconductor region to the third semiconductor region; a signal charge generated by the photoelectric conversion unit can be supplied to the first gate electrode; and a current corresponding to the amount of signal charge generated by the photoelectric conversion unit flows between the second semiconductor region and the third semiconductor region in response to a voltage supplied to the second gate electrode. (3) The photodetector according to (1), wherein the first semiconductor region has a horizontal plane extending along the horizontal direction and a vertical plane extending along the thickness direction of the semiconductor layer on the element formation surface side of the semiconductor layer, and the first gate electrode and the second gate electrode are configured to face both the horizontal plane and the vertical plane via the gate insulating film. (4) The photodetector according to (3), further comprising a recess provided in the first semiconductor region from the element formation surface side, wherein an inner side surface of the recess is the vertical plane and an inner bottom surface of the recess is the horizontal plane.(5) The photodetector according to (4), further comprising: a second semiconductor region and a third semiconductor region of a second conductivity type that are configured in the semiconductor layer so as to be in contact with the first semiconductor region and that configure a pair of main electrode regions, the recess being provided between the second semiconductor region and the third semiconductor region in a plan view, the first gate electrode and the second gate electrode being arranged in that order along a first direction that is a direction from the second semiconductor region to the third semiconductor region, signal charges generated by the photoelectric conversion unit being supplyable to the first gate electrode, and a current corresponding to an amount of signal charges generated by the photoelectric conversion unit flows between the second semiconductor region and the third semiconductor region in accordance with a voltage supplied to the second gate electrode. (6) The photodetector according to (5), wherein a dimension along a depth direction of the recess is set larger than dimensions along the depth direction of the second semiconductor region and the third semiconductor region. (7) The photodetector according to any one of (3) to (6), wherein the second gate electrode has a first portion and a second portion arranged along a first direction and electrically connected to each other, and the first gate electrode is arranged between the first portion and the second portion. (8) The photodetector according to any one of (5) to (7), wherein the second semiconductor region faces one of inner surfaces of the recess facing each other along the first direction, and the third semiconductor region faces the other inner surface. (9) The photodetector according to (3), comprising: a convex portion consisting of the first semiconductor region; and a second semiconductor region and a third semiconductor region of a second conductivity type configured in the semiconductor layer so as to be in contact with the first semiconductor region and configuring a pair of main electrode regions, the convex portion being provided between the second semiconductor region and the third semiconductor region in a planar view, an outer side surface of the convex portion being the vertical plane and an upper end surface of the convex portion being the horizontal plane, the first gate electrode and the second gate electrode being arranged in that order along a first direction which is a direction from the second semiconductor region to the third semiconductor region, the first gate electrode being capable of being supplied with signal charges generated by the photoelectric conversion unit, and a current corresponding to the amount of signal charges generated by the photoelectric conversion unit flows between the second semiconductor region and the third semiconductor region depending on a voltage supplied to the second gate electrode.(10) The light detecting device according to (9), wherein outer surfaces of the convex portions facing each other along the first direction are the vertical planes. (11) The light detecting device according to (9), wherein outer surfaces of the convex portions facing each other along a direction intersecting the first direction are the vertical planes. (12) The light detecting device according to (11), wherein the convex portions are provided in a plurality along a direction intersecting the first direction. (13) The light detecting device according to (11) or (12), wherein the convex portions are formed between two recesses extending along the first direction with a gap therebetween in a direction perpendicular to the first direction. (14) The photodetector according to (4), further comprising: a first charge accumulation region of a second conductivity type configured in the semiconductor layer so as to be in contact with the first semiconductor region and located closer to the element formation surface than the photoelectric conversion unit, the first gate electrode being located closer to the first charge accumulation region than the second gate electrode, signal charges being transferred from the photoelectric conversion unit to the first charge accumulation region in response to a voltage supplied to the first gate electrode, and a voltage repelling the signal charges being supplied to the second gate electrode. (15) The photodetector according to (14), further comprising: a second charge accumulation region of the second conductivity type configured in the semiconductor layer so as to be in contact with the first semiconductor region, and a transistor provided between the first charge accumulation region and the second charge accumulation region, the transistor transferring signal charges from the first charge accumulation region to the second charge accumulation region in response to a voltage supplied to the gate electrode. (16) The photodetector device described in (4), which has a plurality of recesses, the recesses are arranged in a row, the first gate electrode and the second gate electrode are provided for each recess, the first gate electrode and the second gate electrode are aligned along the arrangement direction of the recesses, and signal charges generated by the photoelectric conversion unit are transferred along the arrangement direction of the recesses in response to voltages supplied to the first gate electrode and the second gate electrode.(17) An electronic device comprising: a photodetector; and an optical system that forms an image of image light from a subject on the photodetector, wherein the photodetector comprises: a semiconductor layer having a plurality of cell regions in a matrix arrangement, each having a photoelectric conversion unit, and in which a first semiconductor region of a first conductivity type is formed; and a first gate electrode and a second gate electrode that are provided opposite the first semiconductor region via a gate insulating film and are electrically isolated from each other by being provided so as to contact one surface or the other surface of an insulating thin film.

[0186] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0187] REFERENCE SIGNS LIST 1 Photodetector 2 Semiconductor chip 3 Pixel 20 Semiconductor layer 20a Cell region 21 Well region 22 Photoelectric conversion section 23 Charge accumulation region 24 Semiconductor region 25 Semiconductor region 27 Charge accumulation region 30 Wiring layer 40 Light incident surface side laminate 102 Optical system (optical lens) AMP Amplifying transistor ChA, ChS, ChS1, ChS2, ChT, ChTRx Channel F Convex portion G1, G2, GA, GS, GT, GTa, GTb, GTRx, GTRy Gate electrode GS1 First portion GS2 Second portion HR Horizontal transfer register m1 Gate insulating film m2 Thin film MEM Charge accumulation region PD Photoelectric conversion element S1 First surface S2 Second surface SEL, SEL1, SEL2 Select transistor T, T1, Ta, Tb Recess TR Transfer transistor TRx Transfer transistor VR Vertical transfer register

Claims

1. A photodetector comprising: a semiconductor layer having a plurality of cell regions in a matrix arrangement, each having a photoelectric conversion unit, and having a first semiconductor region of a first conductivity type; and a first gate electrode and a second gate electrode that are disposed opposite the first semiconductor region via a gate insulating film and are electrically isolated from each other by being disposed in contact with one surface or the other surface of an insulating thin film.

2. The photodetector according to claim 1, further comprising a second semiconductor region and a third semiconductor region of a second conductivity type which are configured in the semiconductor layer so as to be in contact with the first semiconductor region and which constitute a pair of main electrode regions, the first gate electrode and the second gate electrode being disposed between the second semiconductor region and the third semiconductor region and arranged in that order along a first direction which is a direction from the second semiconductor region to the third semiconductor region, the first gate electrode being capable of being supplied with signal charges generated by the photoelectric conversion unit, and a current corresponding to an amount of signal charges generated by the photoelectric conversion unit flows between the second semiconductor region and the third semiconductor region in response to a voltage supplied to the second gate electrode.

3. The photodetector device described in claim 1, wherein the first semiconductor region has, on the element formation surface side of the semiconductor layer, a horizontal plane extending along the horizontal direction and a vertical plane extending along the thickness direction of the semiconductor layer, and each of the first gate electrode and the second gate electrode is configured to face both the horizontal plane and the vertical plane via the gate insulating film.

4. The photodetector according to claim 3, further comprising a recess provided in said first semiconductor region from said element formation surface side, said inner side surface of said recess being said vertical plane, and said inner bottom surface of said recess being said horizontal plane.

5. The photodetector according to claim 4, further comprising a second semiconductor region and a third semiconductor region of a second conductivity type which are configured in the semiconductor layer so as to be in contact with the first semiconductor region and which constitute a pair of main electrode regions, the recess being provided between the second semiconductor region and the third semiconductor region in a planar view, the first gate electrode and the second gate electrode being arranged in that order along a first direction which is a direction from the second semiconductor region to the third semiconductor region, the first gate electrode being capable of being supplied with signal charges generated by the photoelectric conversion unit, and a current corresponding to an amount of signal charges generated by the photoelectric conversion unit flows between the second semiconductor region and the third semiconductor region in response to a voltage supplied to the second gate electrode.

6. The photodetector according to claim 5, wherein the dimension of the recess along the depth direction is set to be greater than the dimensions of the second semiconductor region and the third semiconductor region along the depth direction.

7. The photodetection device of claim 5, wherein the second gate electrode has a first portion and a second portion arranged along a first direction and electrically connected to each other, and the first gate electrode is arranged between the first portion and the second portion.

8. A photodetection device as described in claim 5, wherein the second semiconductor region faces one of inner surfaces facing each other along the first direction of the recess, and the third semiconductor region faces the other inner surface.

9. The photodetector according to claim 3, comprising: a convex portion consisting of the first semiconductor region; and a second semiconductor region and a third semiconductor region of a second conductivity type which are configured in the semiconductor layer so as to be in contact with the first semiconductor region and which constitute a pair of main electrode regions, the convex portion being provided between the second semiconductor region and the third semiconductor region in a planar view, an outer side surface of the convex portion being the vertical plane and an upper end surface of the convex portion being the horizontal plane, the first gate electrode and the second gate electrode being arranged in that order along a first direction which is a direction from the second semiconductor region to the third semiconductor region, the first gate electrode being capable of being supplied with signal charges generated by the photoelectric conversion unit, and a current corresponding to an amount of signal charges generated by the photoelectric conversion unit flows between the second semiconductor region and the third semiconductor region in accordance with a voltage supplied to the second gate electrode.

10. The light detection device according to claim 9, wherein outer surfaces of said convex portions opposing each other along the first direction are said vertical planes.

11. The light detection device according to claim 9, wherein outer surfaces of said convex portions facing each other in a direction intersecting with the first direction are said vertical planes.

12. The light detection device according to claim 11, wherein the protrusions are arranged in a direction intersecting the first direction.

13. The light detection device according to claim 11, wherein the convex portion is formed between two concave portions extending along the first direction and spaced apart in a direction perpendicular to the first direction.

14. The photodetector according to claim 4, further comprising a first charge accumulation region of a second conductivity type, the first charge accumulation region being configured in the semiconductor layer so as to be in contact with the first semiconductor region and being located closer to the element formation surface than the photoelectric conversion section, the first gate electrode being positioned closer to the first charge accumulation region than the second gate electrode, signal charges being transferred from the photoelectric conversion section to the first charge accumulation region in response to a voltage supplied to the first gate electrode, and a voltage repelling the signal charges being capable of being supplied to the second gate electrode.

15. The photodetector device of claim 14, comprising: a second charge accumulation region of a second conductivity type formed in the semiconductor layer so as to be in contact with the first semiconductor region; and a transistor provided between the first charge accumulation region and the second charge accumulation region, for transferring signal charges from the first charge accumulation region to the second charge accumulation region in response to a voltage supplied to a gate electrode.

16. The photodetection device of claim 4, comprising a plurality of the recesses, the recesses being arranged in a row, the first gate electrode and the second gate electrode being provided for each recess, the first gate electrode and the second gate electrode being aligned along the arrangement direction of the recesses, and signal charges generated by the photoelectric conversion unit being transferred along the arrangement direction of the recesses in response to voltages supplied to the first gate electrode and the second gate electrode.

17. An electronic device comprising: a photodetector; and an optical system for forming an image of light from a subject on the photodetector, wherein the photodetector comprises: a semiconductor layer having a plurality of cell regions in a matrix arrangement, each having a photoelectric conversion unit, and in which a first semiconductor region of a first conductivity type is formed; and first and second gate electrodes which are disposed opposite the first semiconductor region via a gate insulating film and are electrically isolated from each other by being disposed so as to contact one surface or the other surface of an insulating thin film.

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