Multilayer ceramic capacitor

Abstract

The present invention reduces the possibility of peeling of a side-face external electrode from a laminate. Provided is a three-terminal multilayer ceramic capacitor 1 including: end-face external electrodes 3 provided on both lengthwise end faces of a laminate 2; and a side-face external electrode 4 provided on at least one of widthwise side faces thereof, wherein an internal electrode 15 has an end-face exposed internal electrode 15A exposed on an end face and to be connected to the end-face external electrode 3, and a side-face exposed internal electrode 15B exposed on a side face and to be connected to the side-face external electrode 4. A lengthwise dimension Li of the side-face external electrode 4 satisfies 0.10 mm<Li<0.25 mm, and a total dimension Lall, which is a sum of respective lengthwise dimensions of side-face joint electrodes including side-face lead-out portions 15Bb of the side-face exposed internal electrode 15B that are exposed on a side face and connected to the side-face external electrode 4, and a total dimension Wall, which is a sum of respective widthwise dimensions of end-face lead-out portions 15Ab that are exposed on an end face and connected to the end-face external electrode 3, satisfy 0.4Wall≤Lall≤1.0Wall.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Recently, reducing the impedance of electronic circuit lines has become important, particularly in mobile device products. To achieve this, three-terminal multilayer ceramic capacitors are widely used for decoupling purposes. A three-terminal multilayer ceramic capacitor includes a laminate having an inner layer portion formed by alternately stacking multiple dielectric layers each having an end face internal electrode exposed on an end face and a side face internal electrode exposed on a side face, and outer layer portions disposed on one side and the other side of the inner layer portion in the stacking direction, as well as end face external electrodes disposed on the end faces and side face external electrodes disposed on the side faces (see Patent Document 1).

[0003] Three-terminal multilayer ceramic capacitors can achieve lower impedance at high frequencies by being made smaller. The lower impedance achieved by miniaturization comes from a decrease in the equivalent series inductance (ESL) of the multilayer ceramic capacitor.

[0004] Japanese Patent Application Laid-Open No. 2013-201417

[0005] As three-terminal multilayer ceramic capacitors become smaller, the side external electrodes in particular also become smaller, which reduces the joint length (area) between the side external electrodes and the side lead electrodes, reducing the adhesive strength of the side external electrodes to the laminate and making the side external electrodes more susceptible to peeling off due to external impact.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor in which the possibility of the side surface external electrodes peeling off from the laminate is reduced.

[0007] In order to solve the above problems, the present invention provides a three-terminal multilayer ceramic capacitor comprising: a laminate having an inner layer portion in which a plurality of dielectric layers and internal electrodes are alternately laminated; end face external electrodes provided on both end faces of the laminate in a length direction intersecting with the lamination direction; and a side face external electrode provided on at least one of the side faces of the laminate in a width direction intersecting with the lamination direction and the length direction, wherein the internal electrodes include end face exposed internal electrodes that are connected to the end face external electrodes, and side face exposed internal electrodes that are exposed on the side faces and connected to the side face external electrodes. a total dimension Lall obtained by adding up the respective lengthwise dimensions of the side joining electrodes, including the side lead portions of the side surface exposed internal electrodes, exposed on the side surfaces and connected to the side surface external electrodes, is such that 0.4Wall≦Lall≦1.0Wall is satisfied, where Lall is a total dimension Wall obtained by adding up the respective widthwise dimensions of the end surface lead portions of the end surface exposed internal electrodes, exposed on the end surfaces and connected to the end surface external electrodes.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the possibility of the side surface external electrodes peeling off from the laminate is reduced.

[0009] 1 is a schematic perspective view of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view of an embodiment of the multilayer ceramic capacitor 1 taken along the II-II direction in FIG. 1. FIG. 3 is a cross-sectional view of an embodiment of the multilayer ceramic capacitor 1 taken along the III-III direction in FIG. 1. FIG. 4 is a cross-sectional view taken along an end face exposed internal electrode 15A of the multilayer ceramic capacitor 1. FIG. 5 is a cross-sectional view taken along a side face exposed internal electrode 15B of the multilayer ceramic capacitor 1. FIG. 6 is a diagram illustrating a manufacturing process of a laminate 2 in a manufacturing method of the multilayer ceramic capacitor 1. FIG. 7 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1.

[0010] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along the II-II direction in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along the III-III direction in Fig. 1.

[0011] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 with a three-terminal structure, including a laminate 2, end surface external electrodes 3 provided on both end surfaces C of the laminate 2 in the length direction L, and side surface external electrodes 4 provided on both side surfaces B of the laminate 2 in the width direction W. The laminate 2 includes an inner layer portion 11 in which dielectric layers 14 and internal electrodes 15 are stacked, and an outer layer portion 12.

[0012] In this specification, the term indicating the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 as the stacking direction T. The direction that intersects with the stacking direction T and in which the pair of end face external electrodes 3 are provided is referred to as the length direction L. The direction that intersects with both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the stacking direction T, the length direction L, and the width direction W are perpendicular to one another.

[0013] In the following description, of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides of the stacking direction T will be referred to as main surfaces A, a pair of outer surfaces extending in the stacking direction T and on both sides of the width direction W will be referred to as side surfaces B, and a pair of outer surfaces extending in the stacking direction T and on both sides of the length direction L will be referred to as end surfaces C.

[0014] As shown in FIG. 2 or 3, the multilayer ceramic capacitor 1 has a length L dimension LC of 0.1 mm or more and 0.70 mm or less, a width W dimension WC of 0.05 mm or more and 0.40 mm or less, and a stacking direction T dimension TC of 0.10 mm or more and 0.55 mm or less.

[0015] Furthermore, the capacitance of the multilayer ceramic capacitor 1 is 0.022 μF to 10 μF, and preferably 1.0 μF to 2.2 μF. The ESL of the multilayer ceramic capacitor 1 is preferably 65 pH or less at 100 MHz, and preferably 50 pH or less at 1 GHz.

[0016] The capacitance of the multilayer ceramic capacitor 1 can be measured using an LCR meter (manufactured by Agilent Technologies, model number: E4980A) under conditions of 1 kHz and 0.5 Vrms. The ESL of the multilayer ceramic capacitor 1 can be calculated from the measured impedance value at a predetermined frequency using a network analyzer (manufactured by Agilent Technologies, model number: E5080A).

[0017] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate 2 intersect, and a ridge is a portion where two surfaces of the laminate 2 intersect.

[0018] The dimensions of the laminate 2 are as shown in Figure 2 or Figure 3: the length direction L dimension LL is 0.09 mm or more and 0.69 mm or less, the width direction W dimension WL is 0.04 mm or more and 0.39 mm or less, and the stacking direction T dimension TL is 0.09 mm or more and 0.54 mm or less.

[0019] (Inner Layer Portion 11) The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and internal electrodes 15 along the lamination direction T.

[0020] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material. The ceramic material is mainly composed of a ceramic material containing at least one of Ca, Zr, and Ti. Specifically, for example, a ceramic material containing Ca and Zr and having the general formula ABO ３ The ceramic material having such a perovskite structure is mainly composed of a ceramic material having a perovskite structure represented by the formula: BaTiO ３ (barium titanate) and CaZrO ３However, the ceramic material forming the dielectric layer 14 may contain all of Ca, Zr, and Ti as its main components.

[0021] (Internal Electrode 15) The internal electrode 15 is preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0022] The internal electrode 15 has a plurality of end-exposed internal electrodes 15A and a plurality of side-exposed internal electrodes 15B arranged alternately. When there is no need to particularly distinguish between the end-exposed internal electrodes 15A and the side-exposed internal electrodes 15B, they will be collectively referred to as the internal electrode 15.

[0023] Fig. 4 is a cross-sectional view taken along an end surface exposed internal electrode 15A of the multilayer ceramic capacitor 1. Fig. 5 is a cross-sectional view taken along a side surface exposed internal electrode 15B of the multilayer ceramic capacitor 1.

[0024] 4 , the end-exposed internal electrode 15A extends between both end faces C in the length direction L of the laminate 2 and is spaced a certain distance W1 from both side faces B in the width direction W. The end-exposed internal electrode 15A has an end-facing portion 15Aa located in the center between both end faces C, and end-drawn portions 15Ab extending from the end-facing portion 15Aa to both end faces C. In the embodiment, the end-facing portion 15Aa and the end-drawn portions 15Ab have the same dimension in the width direction W, and the end-exposed internal electrode 15A, including the end-facing portion 15Aa and the end-drawn portions 15Ab, is generally rectangular as a whole. The end surface drawing portion 15Ab extending from the end surface opposing portion 15Aa to the end surfaces C on both sides extends to the end surfaces C on both sides and is exposed at the end surfaces C of the laminate 2, and is joined to the end surface external electrodes 3 provided on both end surfaces C of the laminate 2 in the longitudinal direction L.

[0025] 5, the side-surface-exposed internal electrode 15B has a side-surface facing portion 15Ba located in the center between both side surfaces B, and side-surface drawn-out portions 15Bb extending from the side-surface facing portion 15Ba to both side surfaces B. The side-surface facing portion 15Ba has a substantially rectangular shape that is slightly smaller than the laminate 2, and is spaced a certain distance W1 from both side surfaces B in the width direction W.

[0026] The dimension L1 of the side lead portion 15Bb in the length direction L is smaller than the dimension of the side facing portion 15Ba in the length direction L. The side lead portion 15Bb extends to both side surfaces B, is exposed at the side surfaces B of the laminate 2, and is joined to the side surface external electrodes 4 provided on both side surfaces in the width direction W of the laminate 2.

[0027] The end surface facing portion 15Aa and the side surface facing portion 15Ba face each other to form a capacitor portion.

[0028] 4 , in the embodiment, a dummy electrode 16 is arranged on the side surface B of the first dielectric layer 14A on which the end-exposed internal electrode 15A is arranged, where the end-exposed internal electrode 15A is not exposed. The dummy electrode 16 is exposed on the side surface B.

[0029] The dummy electrode 16 and the side surface lead portion 15Bb are both exposed on the side surface B and joined to the side surface external electrode 4. In this specification, the dummy electrode 16 and the side surface lead portion 15Bb are collectively referred to as a side surface joined electrode. In addition, in this embodiment, the dimension in the length direction L of the dummy electrode 16 and the side surface lead portion 15Bb is approximately equal, and both are L1, with 0.04 mm<L1<0.100 mm.

[0030] Furthermore, the total dimension of the side joining electrode, which includes the dummy electrodes 16 and the side surface extended portions 15Bb, i.e., the dimension Lall obtained by adding up the dimension (length) of all of the individual dummy electrodes 16 (layers) and the dimension (length) of all of the individual dummy electrodes 16 (layers), is in the range of 3 mm < Lall < 40 mm, and preferably 12 mm < Lall < 25 mm. Although not limited thereto, in this embodiment, the number n of dummy electrodes 16 and the number n of side surface extended portions 15Bb are the same, and the dummy electrodes 16 and the side surface extended portions 15Bb are alternately stacked. Furthermore, in this embodiment, all of the dummy electrodes 16 have the same length L1, and all of the dummy electrodes 16 and the side surface extended portions 15Bb have the same length L1. In this case, Lall is n (number of dummy electrodes 16) x L1 (length of dummy electrodes 16) + n (number of side surface lead portions 15Bb) x L1 (length of side surface lead portion 15Bb), i.e., Lall = 2nL1.

[0031] If the total dimension of the widthwise dimensions of the end surface lead portions 15Ab is Wall, the relationship between Wall and Wall is 0.4 Wall≦Lall≦1.0 Wall.

[0032] The dummy electrode 16 has a concave shape in the cross-sectional view shown in Fig. 4. That is, the side of the dummy electrode 16 opposite to the side exposed on the side surface B is not parallel to the longitudinal direction L, but is curved so that the dimension WD in the width direction W at the center is smaller. The maximum dimension WDL of the dummy electrode 16 is preferably 20% to 80% of the dimension W1 of the side surface drawn-out portion 15Bb shown in Fig. 5 (i.e., the distance W1 from the side surface B of the end-exposed internal electrode 15A shown in Fig. 4), and the minimum dimension WDS is preferably 1% to 50% of W1.

[0033] In this embodiment, the difference in thickness in the stacking direction T between the end-face exposed internal electrode 15A, the side-face exposed internal electrode 15B, and the dummy electrode 16 is within ±10%, and is substantially equal.

[0034] The dielectric layer 14 is formed by alternately stacking multiple layers of a first dielectric layer 14A on which an end-face-exposed internal electrode 15A and a dummy electrode 16 are arranged and exposed on the end face C, and a second dielectric layer 14B on which a side-face-exposed internal electrode 15B is arranged and exposed on a portion of the side face B.

[0035] 2 and 3 , the outer layer portion 12 is a dielectric layer disposed on the main surface A side of the inner layer portion 11. The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11.

[0036] (End Face External Electrodes 3) End face external electrodes 3 are arranged on both end faces C of the laminate 2. End face drawn portions 15Ab of the end face exposed internal electrodes 15A are connected to the end face external electrodes 3. The end face external electrodes 3 cover not only the end faces C but also parts of the main faces A and side faces B on the end face C side.

[0037] (Side surface external electrode 4) Side surface external electrodes 4 are arranged on both side surfaces B of the laminate 2. Side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B are connected to the side surface external electrodes 4. The side surface external electrodes 4 cover not only the side surfaces B but also a portion of the side surface B side of the main surface A. In the embodiment, the dimension Li of the side surface external electrodes 4 in the length direction L is 0.10 mm<Li<0.25 mm.

[0038] The end surface external electrode 3 and the side surface external electrode 4 include a base electrode layer 31 and a plating layer 32 disposed on the base electrode layer 31. The plating layer 32 includes a Ni (nickel) plating layer 321 disposed on the base electrode layer 31, and a Sn (tin) plating layer 322 disposed on the Ni plating layer 321. However, without being limited thereto, the end surface external electrode 3 and the side surface external electrode 4 may have a structure in which, for example, the base electrode layer 31 is made of Ni, and a Cu plating layer, a Ni plating layer, and a Sn plating layer are disposed thereon in this order.

[0039] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Next, a manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment will be described. Fig. 6 is a diagram illustrating the manufacturing steps of the laminate 2 in the manufacturing method of the multilayer ceramic capacitor 1. Fig. 7 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1.

[0040] (Internal Electrode Pattern Forming Step S1) The internal electrode pattern forming step S1 includes an end surface exposed internal electrode forming step S11 and a side surface exposed internal electrode forming step S12.

[0041] On the ceramic green sheet 14A' that will become the first dielectric layer 14A, an end-face exposed internal electrode 15A and a concave dummy electrode 16 are formed using a conductive paste. The dummy electrode 16 may be formed simultaneously with the end-face exposed internal electrode 15A, or may be formed by inkjet printing after the end-face exposed internal electrode 15A is formed.

[0042] Similarly, side surface exposed internal electrodes 15B are formed from conductive paste on the ceramic green sheet 14B' that will become the second dielectric layer 14B.

[0043] The ceramic green sheet 14A' and the ceramic green sheet 14B' described below are strip-shaped sheets formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0044] The end-face exposed internal electrodes 15A and side-face exposed internal electrodes 15B are formed by printing, such as screen printing, gravure printing, or letterpress printing.

[0045] (Stacking step S2) Ceramic green sheets 14A' to become the first dielectric layers 14A on which the end-face exposed internal electrodes 15A are arranged and ceramic green sheets 14B' to become the second dielectric layers 14B on which the side-face exposed internal electrodes 15B are arranged are stacked alternately.

[0046] Next, ceramic green sheets for the outer layer portion 12 are arranged one above the other and thermocompression bonded to form a mother block.

[0047] (Mother Block Cutting Step S3) Next, the mother block is cut and divided in the length direction L and width direction W to manufacture a plurality of rectangular parallelepiped laminates 2.

[0048] (External electrode forming process S4) Next, side surface external electrodes 4 are formed on both side surfaces B of the laminate 2. The side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B are connected to the side surface external electrodes 4. The side surface external electrodes 4 are formed so as to cover not only the side surfaces B but also part of the side surface B side of the main surface A.

[0049] Then, end surface external electrodes 3 are formed on both end surfaces C of the laminate 2. End surface drawn portions 15Ab of the end surface exposed internal electrodes 15A are connected to the end surface external electrodes 3. The end surface external electrodes 3 are formed so as to cover not only the end surfaces C but also parts of the main surfaces A and side surfaces B on the end surface C side.

[0050] (Firing step S5) Then, the laminate is heated in a nitrogen atmosphere at the set firing temperature for a predetermined time, thereby firing the end surface external electrodes 3 and the side surface external electrodes 4 onto the laminate 2, and the multilayer ceramic capacitor 1 shown in FIG.

[0051] (Effects of the embodiment) As described above, the multilayer ceramic capacitor 1 of the embodiment has the following effects: (Effects of providing dummy electrodes) In a multilayer ceramic capacitor in which the dimension Li of the side surface external electrode 4 in the length direction L is relatively small, such as 0.10 mm<Li<0.25 mm, the dimension of the side surface extended portion 15Bb in the length direction L is also small, and the joint length between the side surface external electrode 4 and the side surface extended portion 15Bb is shortened (the joint area is reduced).

[0052] In this case, unlike the embodiment, if the side external electrode 4 is joined to the laminate 2 only by joining with the side lead portion 15Bb, the joining strength between the side external electrode 4 and the side lead portion 15Bb is small, and the side external electrode 4 is likely to peel off from the laminate 2.

[0053] However, in this embodiment, the side surface external electrode 4 is bonded not only to the side surface lead portion 15Bb but also to the dummy electrode 16. Therefore, the bonding strength of the side surface external electrode 4 to the laminate 2 is strong, making it less likely to peel off.

[0054] In the lamination step S2, the end surface facing portion 15Aa of the ceramic green sheet 14A' and the side surface facing portion 15Ba of the ceramic green sheet 14B' are stacked so as to overlap. However, the end surface drawn-out portion 15Ab of the ceramic green sheet 14A' and the side surface drawn-out portion 15Bb of the ceramic green sheet 14B' do not overlap. Therefore, unlike the embodiment, if dummy electrodes 16 are not provided, the portion where the drawn-out portion is located will be thinner in the lamination direction T than the portion where the facing portion is located. This makes it difficult to apply uniform pressure when forming the mother block.

[0055] However, in this embodiment, the ceramic green sheet 14A' is provided with a dummy electrode 16. Therefore, when the ceramic green sheets 14A' and 14B' are laminated together, the thickness in the lamination direction T on the side surface B side is maintained more uniform than when the dummy electrode 16 is not provided. As a result, the side surface lead portion 15Bb in contact with the side surface B is instantaneously pressurized and densified during thermocompression bonding after lamination in the lamination step S2. Therefore, flow of the lead portion is suppressed during thermocompression bonding, and the thickness of the side surface lead portion 15Bb in contact with the region B is maintained thick. This improves the bond between the side surface lead portion 15Bb in contact with the side surface B and the side external electrode 4, thereby reducing the equivalent series inductance (ESL).

[0056] (Effect of the concave shape) In the embodiment, the dummy electrode 16 has a concave shape in the cross section shown in Fig. 4. That is, the dummy electrode 16 has a portion where the dimension WD in the width direction W is smaller in a cross section passing through the length direction L and the width direction W. The maximum dimension WDL in the width direction W is 20% to 80% of the dimension W1 of the side lead portion, and the minimum dimension WDS is 1% to 50% of the dimension W1 of the side lead portion. Therefore, compared to when the dummy electrode is rectangular, there is a portion where the dummy electrode 16 is separated from the end-exposed internal electrode 15A, making it less likely to cause a short circuit.

[0057] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible, including the following, for example.

[0058] In the embodiment, the dimension in the length direction L of the dummy electrode 16 and the dimension in the length direction L of the side surface lead portion 15Bb are substantially equal, and the dimension in the length direction L of the dummy electrode 16 and the dimension in the length direction L of the side surface lead portion 15Bb are both L1. However, this is not limited to this, and for example, within the area covered by the side surface external electrode 4, the dimension in the length direction L of the dummy electrode 16 may be different from the dimension in the length direction L of the side surface lead portion 15Bb, for example, the dimension in the length direction L of the dummy electrode 16 may be larger than the dimension in the length direction L of the side surface lead portion 15Bb.

[0059] In the embodiment, the thicknesses of the end-face-exposed internal electrode 15A and the side-face-exposed internal electrode 15B in the stacking direction T are approximately equal, and the dummy electrode 16 having the same thickness is provided to increase the bonding area between the side-face external electrode 4 and the side-face joining electrode. However, this is not limitative, and the bonding area between the side-face external electrode 4 and the side-face joining electrode may be increased by, for example, increasing the dimension (thickness) of the side-face lead portion 15Bb in the stacking direction T.

[0060] From the viewpoint of achieving an equal balance between the bonding strength between the end surface external electrode 3 and the laminate 2 and the bonding strength between the side surface external electrode 4 and the laminate 2, the dimension in the width direction W of the end surface drawn-out portion 15Ab bonded to the end surface external electrode 3 may be reduced.

[0061] Furthermore, the present invention also includes the following: <1> A three-terminal multilayer ceramic capacitor comprising: a laminate having an inner layer portion in which a plurality of dielectric layers and internal electrodes are alternately laminated; end face external electrodes provided on both end faces of the laminate in a length direction intersecting with the stacking direction; and side face external electrodes provided on at least one of the side faces of the laminate in a width direction intersecting with the stacking direction and the length direction, wherein the internal electrodes include: end face exposed internal electrodes exposed on the end faces and connected to the end face external electrodes; and side face exposed internal electrodes exposed on the side faces and connected to the side face external electrodes, wherein the length direction dimension Li of the side face external electrodes is 0.10 mm<Li<0.25 mm, and a total dimension Lall obtained by adding up the length direction dimensions of side face joining electrodes including side face lead portions of the side face exposed internal electrodes exposed on the side faces and connected to the side face external electrodes is: A multilayer ceramic capacitor in which 0.4 Wall≦Wall≦1.0 Wall.

[0062] <2> The multilayer ceramic capacitor according to <1>, wherein the width L1 in the length direction of each of the side surface bonding electrodes is 0.04 mm<L1<0.100 mm.

[0063] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the total dimension Lall of the side joining electrodes is 3 mm<Lall<40 mm.

[0064] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the dimension of the laminate in the lamination direction is 0.10 mm or more and 0.50 mm or less.

[0065] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the side joining electrodes include dummy electrodes.

[0066] <6> The multilayer ceramic capacitor according to <5>, wherein the dummy electrode has a portion where the dimension WD in the width direction is smaller in a cross section passing through the length direction and the width direction, and the maximum dimension WDL in the width direction is 20% to 80% of the dimension W1 of the side lead portion, and the minimum dimension WDS is 1% to 50% of the dimension W1 of the side lead portion.

[0067] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the dimension in the length direction is 0.1 mm or more and 0.70 mm or less, the dimension in the width direction is 0.05 mm or more and 0.40 mm or less, and the dimension in the stacking direction is 0.10 mm or more and 0.55 mm or less.

[0068] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, having a capacitance of 0.022 μF or more and 10 μF or less.

[0069] <9> The multilayer ceramic capacitor according to any one of <1> to <8>, having an equivalent series inductance of 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

[0070] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 3 End face external electrode 4 Side face external electrode 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15Bb Side face drawn portion 15 Internal electrode 15A End face exposed internal electrode 15Aa End face opposing portion 15Ab End face drawn portion 15B Side face exposed internal electrode 15Ba Side face opposing portion 16 Dummy electrode

Claims

1. A three-terminal multilayer ceramic capacitor comprising: a laminate having an inner layer portion in which a plurality of dielectric layers and internal electrodes are alternately laminated; end face external electrodes provided on both end faces of the laminate in a length direction intersecting with the lamination direction; and a side face external electrode provided on at least one of the side faces of the laminate in a width direction intersecting with the lamination direction and the length direction, wherein the internal electrodes include: end face exposed internal electrodes exposed on the end faces and connected to the end face external electrodes; and side face exposed internal electrodes exposed on the side faces and connected to the side face external electrodes, wherein the length direction dimension Li of the side face external electrodes is 0.10 mm < Li < 0.25 mm, and a total dimension Lall obtained by adding up the respective length direction dimensions of side face joining electrodes including side lead portions of the side face exposed internal electrodes exposed on the side faces and connected to the side face external electrodes is, relative to a total dimension Wall obtained by adding up the respective width direction dimensions of the end face lead portions of the end face exposed internal electrodes exposed on the end faces and connected to the end face external electrodes, A multilayer ceramic capacitor having a wall thickness of 0.4 Wall≦Wall≦1.0 Wall.

2. The multilayer ceramic capacitor according to claim 1, wherein the width L1 in the longitudinal direction of each of the side joining electrodes is in the range of 0.04 mm<L1<0.100 mm.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the total dimension Lall of the side joining electrodes is 3 mm<Lall<40 mm.

4. The multilayer ceramic capacitor according to claim 1, wherein the dimension of the laminate in the lamination direction is not less than 0.10 mm and not more than 0.50 mm.

5. The multilayer ceramic capacitor according to claim 1, wherein the side joining electrodes include dummy electrodes.

6. The multilayer ceramic capacitor according to claim 5, wherein the dummy electrode has a portion in a cross section passing through the length direction and the width direction where the dimension WD in the width direction is smaller, the maximum dimension WDL in the width direction being 20% ​​or more and 80% or less of the dimension W1 of the side lead portion, and the minimum dimension WDS is 1% or more and 50% or less of the dimension W1 of the side lead portion.

7. A multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the dimension in the length direction is 0.1 mm or more and 0.70 mm or less, the dimension in the width direction is 0.05 mm or more and 0.40 mm or less, and the dimension in the lamination direction is 0.10 mm or more and 0.55 mm or less.

8. The multilayer ceramic capacitor according to any one of claims 1 to 7, having a capacitance of 0.022 μF or more and 10 μF or less.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, having an equivalent series inductance of 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

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