Multilayer ceramic capacitor

Abstract

The present invention reduces ESL in a small-sized and three-terminal multilayer ceramic capacitor. In the three-terminal type multilayer ceramic capacitor 1, a dimension LC in a length direction satisfies 0.1 mm ≤ LC ≤ 0.70 mm or is lower, a dimension WC in a width direction satisfies 0.05 mm ≤ WC ≤ 0.40 mm or is lower, and a dimension TC in a lamination direction satisfies 0.10 mm ≤ TC ≤ 0.55 mm or is lower. A side surface lead-out part 15Ab includes: a substantially rectangular base region 15Bbb that extends from a side surface facing part 15Aa to a side surface and has a dimension in the width direction of W1, and a dimension L1 in the length direction satisfying 10 μm ≤ L1 ≤ 100 μm; and an expansion region 15Bbk which is disposed in at least one length direction of the base region 15Bbb and which, when the dimension in the width direction between the side surface and the tip on the side surface side is designated as W2, satisfies 0 ≤ W2 ≤ 0.9W1, and when the dimension in the length direction of the portion connected to the side surface facing part 15Aa and the dimension in the length direction of the laminate 2 are respectively designated as L2 and LL, satisfies 0.1L1 ≤ L2 ≤ 0.4LL.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Recently, reducing the impedance of electronic circuit lines has become increasingly important, particularly in mobile device products. To achieve this, three-terminal multilayer ceramic capacitors are widely used for decoupling purposes. A three-terminal multilayer ceramic capacitor includes an inner layer section formed by alternating multiple dielectric layers each having an end face internal electrode exposed on the end face and a side face internal electrode exposed on the side face, and outer layer sections disposed on one side and the other side of the inner layer section in the lamination direction. The three-terminal multilayer ceramic capacitor also includes an end face external electrode disposed on the end face and a side face external electrode disposed on the side face (see Patent Document 1). Miniaturization of a three-terminal multilayer ceramic capacitor enables further reduction in impedance at high frequencies. The reduction in impedance due to miniaturization is due to a reduction in the equivalent series inductance (ESL) of the multilayer ceramic capacitor.

[0003] Japanese Patent Application Laid-Open No. 2013-201417

[0004] In recent years, multilayer ceramic capacitors have become increasingly smaller. An object of the present application is to further reduce the ESL in a small, three-terminal multilayer ceramic capacitor.

[0005] In order to solve the above problems, the present invention provides a three-terminal multilayer ceramic capacitor comprising: a laminate having an inner layer portion in which a plurality of dielectric layers and internal electrodes are alternately laminated; end face external electrodes provided on both end faces of the laminate in a length direction intersecting with the lamination direction; and a side face external electrode provided on at least one of the side faces of the laminate in a width direction intersecting with the lamination direction and the length direction, the internal electrodes comprising end face exposed internal electrodes exposed on the end faces and connected to the end face external electrodes, and side face exposed internal electrodes connected to the side face external electrodes exposed on the side faces, the side face exposed internal electrodes having side face opposing portions opposing the end face exposed internal electrodes and side face drawn portions drawn from the side face opposing portions to the side faces, the side lead-out portion extends from the side surface facing portion to the side surface and includes a substantially rectangular base region having a dimension W1 in the width direction and a dimension L1 in the length direction of 10 μm≦L1≦100 μm; and an extension region that is disposed on at least one side of the base region in the length direction, and where W2 is the dimension in the width direction between the tip on the side surface side and the side surface, the extension region having a dimension L2 in the length direction of the portion connected to the side surface facing portion and a dimension L2 in the length direction of the portion connected to the side surface facing portion and a dimension LL in the length direction of the laminate.

[0006] According to the present invention, the ESL can be further reduced in a small, three-terminal multilayer ceramic capacitor.

[0007] 6A, 6B, and 6C are diagrams illustrating modified forms of the extension region 15Bbk; FIGS. 6A to 6C are diagrams illustrating a manufacturing process of the laminate 2 in a manufacturing method of the laminated ceramic capacitor 1; FIGS. 6B to 6C are diagrams illustrating a manufacturing process of the laminate 2 in a manufacturing method of the laminated ceramic capacitor 1; FIGS. 6C to 6C are diagrams illustrating a manufacturing process of the laminated body 2 in a manufacturing method of the laminated ceramic capacitor 1; FIGS. 6D to 6C are diagrams illustrating a manufacturing process of the laminated ceramic capacitor 1; FIGS. 6E to 6C are diagrams illustrating a manufacturing process of the laminated ceramic capacitor 1;

[0008] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to a first embodiment taken along the II-II direction in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the III-III direction in Fig. 1.

[0009] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 with a three-terminal structure, including a laminate 2, end surface external electrodes 3 provided on both end surfaces C of the laminate 2 in the length direction L, and side surface external electrodes 4 provided on both side surfaces B of the laminate 2 in the width direction W. The laminate 2 includes an inner layer portion 11 in which dielectric layers 14 and internal electrodes 15 are stacked, and an outer layer portion 12.

[0010] In this specification, the term indicating the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 as the stacking direction T. The direction that intersects with the stacking direction T and in which the pair of end face external electrodes 3 are provided is referred to as the length direction L. The direction that intersects with both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the stacking direction T, the length direction L, and the width direction W are perpendicular to one another.

[0011] In the following description, of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides of the stacking direction T will be referred to as main surfaces A, a pair of outer surfaces extending in the stacking direction T and on both sides of the width direction W will be referred to as side surfaces B, and a pair of outer surfaces extending in the stacking direction T and on both sides of the length direction L will be referred to as end surfaces C.

[0012] As shown in FIG. 2 or 3, the multilayer ceramic capacitor 1 has a length L dimension LC of 0.1 mm or more and 0.70 mm or less, a width W dimension WC of 0.05 mm or more and 0.40 mm or less, and a stacking direction T dimension TC of 0.10 mm or more and 0.55 mm or less.

[0013] Furthermore, the capacitance of the multilayer ceramic capacitor 1 is 0.022 μF to 10 μF, and preferably 1.0 μF to 2.2 μF. The ESL of the multilayer ceramic capacitor 1 is preferably 65 pH or less at 100 MHz, and preferably 50 pH or less at 1 GHz.

[0014] The capacitance of the multilayer ceramic capacitor 1 can be measured using an LCR meter (manufactured by Agilent Technologies, model number: E4980A) under conditions of 1 kHz and 0.5 Vrms. The ESL of the multilayer ceramic capacitor 1 can be calculated from the measured impedance value at a predetermined frequency using a network analyzer (manufactured by Agilent Technologies, model number: E5080A).

[0015] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate 2 intersect, and a ridge is a portion where two surfaces of the laminate 2 intersect.

[0016] The dimensions of the laminate 2 are as shown in Figure 2 or Figure 3: the length direction L dimension LL is 0.09 mm or more and 0.69 mm or less, the width direction W dimension WL is 0.04 mm or more and 0.39 mm or less, and the stacking direction T dimension TL is 0.09 mm or more and 0.54 mm or less.

[0017] (Inner Layer Portion 11) The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and internal electrodes 15 along the lamination direction T.

[0018] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material. The ceramic material is mainly composed of a ceramic material containing at least one of Ca, Zr, and Ti. Specifically, for example, a ceramic material containing Ca and Zr and having the general formula ABO ３ The ceramic material having such a perovskite structure is mainly composed of a ceramic material having a perovskite structure represented by the formula: BaTiO ３ (barium titanate) and CaZrO ３ However, the ceramic material forming the dielectric layer 14 may contain all of Ca, Zr, and Ti as its main components.

[0019] (Internal Electrode 15) The internal electrode 15 is preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0020] The internal electrode 15 has a plurality of end-exposed internal electrodes 15A and a plurality of side-exposed internal electrodes 15B arranged alternately. When there is no need to particularly distinguish between the end-exposed internal electrodes 15A and the side-exposed internal electrodes 15B, they will be collectively referred to as the internal electrode 15.

[0021] Fig. 4 is a cross-sectional view taken along an end surface exposed internal electrode 15A of the multilayer ceramic capacitor 1. Fig. 5 is a cross-sectional view taken along a side surface exposed internal electrode 15B of the multilayer ceramic capacitor 1.

[0022] 4 , the end-exposed internal electrode 15A extends between both end faces C in the length direction L of the laminate 2 and is spaced a certain distance W1 from both side faces B in the width direction W. The end-exposed internal electrode 15A has an end-facing portion 15Aa located in the center between both end faces C, and end-drawn portions 15Ab extending from the end-facing portion 15Aa to both end faces C. In the embodiment, the end-facing portion 15Aa and the end-drawn portions 15Ab have the same dimension in the width direction W, and the end-exposed internal electrode 15A, including the end-facing portion 15Aa and the end-drawn portions 15Ab, is generally rectangular as a whole. The end surface drawing portion 15Ab extending from the end surface opposing portion 15Aa to the end surfaces C on both sides extends to the end surfaces C on both sides, is exposed at the end surfaces C of the laminate 2, and is connected to the end surface external electrodes 3 provided on both end surfaces C in the longitudinal direction L of the laminate 2.

[0023] 5, the side-surface-exposed internal electrode 15B has a side-surface facing portion 15Ba located in the center between both side surfaces B, and side-surface drawn-out portions 15Bb extending from the side-surface facing portion 15Ba to both side surfaces B. The side-surface facing portion 15Ba has a substantially rectangular shape that is slightly smaller than the laminate 2, and is spaced a certain distance W1 from both side surfaces B in the width direction W.

[0024] The dimension L1 of the side lead portion 15Bb in the length direction L is smaller than the dimension of the side surface opposing portion 15Ba in the length direction L. The side lead portion 15Bb extends to both side surfaces B, is exposed at the side surfaces B of the laminate 2, and is connected to the side surface external electrodes 4 provided on both side surfaces of the laminate 2 in the width direction W.

[0025] The end surface facing portion 15Aa and the side surface facing portion 15Ba face each other to form a capacitor portion.

[0026] (Dimension of Exposed Portion 15Bc: 10 μm≦L1≦100 μm) As shown in FIG. 5, the dimension L1 of the exposed portion 15Bc exposed on the side surface B of the side lead portion 15Bb is 10 μm≦L1≦100 μm.

[0027] The side-exposed internal electrode 15B includes a substantially rectangular base region 15Bbb including an exposed portion 15Bc, and an extension region 15Bbk arranged in a region including a corner between the side-facing portion 15Ba and the base region 15Bbb in at least one of the longitudinal directions L of the base region 15Bbb.

[0028] (Base Region 15Bbb) The base region 15Bbb extends from the side surface facing portion 15Ba to the side surface B, and is a substantially rectangular shape with a width W of W1 and a length L1 (dimension of the exposed portion 15Bc) of 10 μm≦L1≦100 μm.

[0029] (Expansion Regions 15Bbk) In this embodiment, the expansion regions 15Bbk are arranged on both sides of the base region 15Bbb in the length direction L. The shape of the expansion regions 15Bbk is a triangle whose hypotenuse is curved so that the area of ​​the triangle is smaller than that of the triangle. However, the number and shape of the expansion regions 15Bbk are not limited to this, as long as they extend the dimension of the entire side lead portion 15Bb in the length direction L of the connection portion with the side facing portion 15Ba beyond L1 for the base region 15Bbb alone.

[0030] (Shape of the extension region 15Bbk) Figure 6 shows modified forms of the extension region 15Bbk. The extension region 15Bbk does not have to be disposed on both sides of the base region 15Bbb in the longitudinal direction L, and may be disposed on only one side of the base region 15Bbb in the longitudinal direction L as shown in Figure 6(a).

[0031] The extension region 15Bbk does not have to have a curved contour so that its area is smaller than that of a substantially triangular shape as described above. For example, it may have a substantially triangular shape as shown in FIG. 6( a). It may also have a curved contour so that its area is larger than that of a substantially triangular shape, such as a substantially quarter-circular or quarter-elliptical shape, as shown on the left side of FIG. 6( b). Furthermore, it may have a smooth, stepped contour as shown in FIG. 6( c).

[0032] When the extension regions 15Bbk are arranged on both sides of the base region 15Bbb in the longitudinal direction L, the extension regions 15Bbk arranged on one side and the other side may have different shapes, as in the case of Figures 6(b) and 6(c).

[0033] Also, as shown in Figure 6 (c), the widthwise dimension W2 from the tip P on the side B side of the expansion region 15Bbk to the side B may be different between the expansion regions 15Bbk located on one side and the other side of the longitudinal direction L.

[0034] (Dimensions of expansion region 15Bbk: 0≦W2≦0.9W1) Furthermore, when the widthwise dimension from the tip P on the side B side of expansion region 15Bbk to side B is W2 as shown in Figure 5, in this embodiment, 0≦W2≦0.9W1.

[0035] The left side of Fig. 6(c) shows the case where the extension region 15Bbk has a width W of 0 = W2, i.e., the width W dimension of the extension region 15Bbk (W1-W2) (the length of the extension region 15Bbk) is W1. The right side of Fig. 6(c) shows the case where the extension region 15Bbk has a width W of W2 ≈ 0.9W1, i.e., the width W dimension of the extension region 15Bbk (W1-W2) (the length of the extension region 15Bbk) is ≈ 0.1W1.

[0036] As described above, the expansion region 15Bbk may have various shapes, but the area of ​​the expansion region 15Bbk is smaller than W1 × L2, where L2 (the width of the expansion region 15Bbk) is the longitudinal dimension of the connection portion with the side surface facing portion 15Ba. The side surface B side of the expansion region 15Bbk is not exposed to the side surface B (or only point P is exposed). It is also preferable that the longitudinal dimension of the expansion region 15Bbk gradually decreases from the connection portion with the side surface facing portion 15Ba toward the tip P on the side surface B side.

[0037] (Length dimension L2 of connection portion: 0.1L1≦L2≦0.4LL) The length dimension L2 of the connection portion of the expansion region 15Bbk with the side surface facing portion 15Ba has the following relationship with the length dimension LL of the laminate 2 in the length direction L and the dimension L1 of the exposed portion 15Bc exposed on the side surface B of the side lead portion 15Bb: 0.1L1≦L2≦0.4LL

[0038] The dielectric layer 14 is formed by alternately stacking multiple layers of a first dielectric layer 14A on which an end-face-exposed internal electrode 15A exposed on the end face C is arranged, and a second dielectric layer 14B on which a side-face-exposed internal electrode 15B exposed on a portion of the side face B is arranged.

[0039] 2 and 3 , the outer layer portion 12 is a dielectric layer disposed on the main surface A side of the inner layer portion 11. The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11.

[0040] (End Face External Electrodes 3) End face external electrodes 3 are arranged on both end faces C of the laminate 2. End face drawn portions 15Ab of the end face exposed internal electrodes 15A are connected to the end face external electrodes 3. The end face external electrodes 3 cover not only the end faces C but also parts of the main faces A and side faces B on the end face C side.

[0041] (Side surface external electrodes 4) Side surface external electrodes 4 are arranged on both side surfaces B of the laminate 2. The side surface external electrodes 4 are connected to the side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B. The side surface external electrodes 4 cover not only the side surfaces B but also a portion of the side surface B side of the main surface A.

[0042] The end surface external electrode 3 and the side surface external electrode 4 include a base electrode layer 31 and a plating layer 32 disposed on the base electrode layer 31. The plating layer 32 includes a Ni (nickel) plating layer 321 disposed on the base electrode layer 31, and a Sn (tin) plating layer 322 disposed on the Ni plating layer 321. However, without being limited thereto, the end surface external electrode 3 and the side surface external electrode 4 may have a structure in which, for example, the base electrode layer 31 is made of Ni, and a Cu plating layer, a Ni plating layer, and a Sn plating layer are disposed thereon in this order.

[0043] (Method of Manufacturing Multilayer Ceramic Capacitor 1) Next, a method of manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described. Fig. 7 is a diagram illustrating the steps of manufacturing the laminate 2 in the method of manufacturing the multilayer ceramic capacitor 1. Fig. 8 is a flowchart illustrating the method of manufacturing the multilayer ceramic capacitor 1.

[0044] (Internal electrode pattern forming step S1) The internal electrode pattern forming step S1 includes an end surface exposed internal electrode forming step S11 and a side surface exposed internal electrode forming step S12. Either the end surface exposed internal electrode forming step S11 or the side surface exposed internal electrode forming step S12 may be performed first.

[0045] (End Face Exposed Internal Electrode Forming Step S11) End face exposed internal electrodes 15A are formed on the ceramic green sheet 14A' that will become the first dielectric layer 14A using a conductive paste.

[0046] The ceramic green sheet 14A' and the ceramic green sheet 14B' described below are strip-shaped sheets formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0047] The end-face exposed internal electrode 15A, the side surface facing portion 15Ba, and the base region 15Bbb of the side surface drawn portion 15Bb are formed by printing such as screen printing, gravure printing, or letterpress printing.

[0048] (Side surface exposed internal electrode forming process S12) Then, a side surface exposed internal electrode 15B is formed using a conductive paste on the ceramic green sheet 14B' that will become the second dielectric layer 14B. The side surface exposed internal electrode forming process S12 includes a base region forming process S121 for the side surface facing portion 15Ba and the side surface extended portion 15Bb, and an extension region printing process S122 for the side surface extended portion 15Bb.

[0049] (Process S121 for forming base regions of side surface facing portion 15Ba and side surface drawn portion 15Bb) The printing of the side surface exposed internal electrode 15B is not limited to this, but for example, first, the side surface facing portion 15Ba and the base region 15Bbb of the side surface drawn portion 15Bb are formed first.

[0050] (Step S122 of Printing Extended Area of ​​Side Lead Portion) Next, the extended area 15Bbk of the side lead portion 15Bb is formed by, for example, inkjet printing.

[0051] (Laminating step S2) Ceramic sheets to become the first dielectric layers 14A on which the end-face exposed internal electrodes 15A are arranged and ceramic sheets to become the second dielectric layers 14B on which the side-face exposed internal electrodes 15B are arranged are alternately laminated.

[0052] Next, ceramic green sheets for the outer layer portions are arranged on top and bottom and thermocompression bonded to form a mother block.

[0053] (Mother Block Cutting Step S3) Next, the mother block is cut and divided in the length direction L and width direction W to manufacture a plurality of rectangular parallelepiped laminates 2.

[0054] (External electrode forming process S4) Next, side surface external electrodes 4 are formed on both side surfaces B of the laminate 2. The side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B are connected to the side surface external electrodes 4. The side surface external electrodes 4 are formed so as to cover not only the side surfaces B but also part of the side surface B side of the main surface A.

[0055] Then, end surface external electrodes 3 are formed on both end surfaces C of the laminate 2. End surface drawn portions 15Ab of the end surface exposed internal electrodes 15A are connected to the end surface external electrodes 3. The end surface external electrodes 3 are formed so as to cover not only the end surfaces C but also parts of the main surfaces A and side surfaces B on the end surface C side.

[0056] (Firing step S5) Then, the laminate is heated in a nitrogen atmosphere at a set firing temperature for a predetermined time, thereby firing the end surface external electrodes 3 and the side surface external electrodes 4 onto the laminate 2, and producing the multilayer ceramic capacitor 1 shown in FIG.

[0057] (Effects of the embodiment) (Dimension of exposed portion 15Bc 10 μm≦L1≦100 μm) As shown in FIG. 5, the dimension L1 of exposed portion 15Bc exposed on the side surface B of side lead portion 15Bb is 10 μm≦L1≦100 μm.

[0058] (Effect of 10 μm≦L1) If the dimension L1 of the exposed portion 15Bc is L1<10 μm, poor connection between the side external electrode 4 and the side exposed internal electrode 15B may occur, but in the embodiment, 10 μm≦L1, so the connection between the side external electrode 4 and the side exposed internal electrode 15B is good.

[0059] (Effect of L1≦100 μm) As described above, the dimension LL in the length direction L of the laminate 2 is 0.69 mm or less. In this case, if the dimension L1 of the exposed portion 15Bc is 100 μm<L1, the dimension L1 of the exposed portion 15Bc becomes large relative to the dimension LL of the laminate 2. In this case, since the end surface external electrode 3 also wraps around to the end surface B, there is a possibility that the wrapped-around portion of the end surface external electrode 3 will come into contact with the side surface external electrode 4 that covers the exposed portion 15Bc. However, in the embodiment, L1≦100 μm, so the possibility of contact between the side surface external electrode 4 and the end surface external electrode 3 can be reduced.

[0060] (Effect of Providing Extended Region 15Bbk) The current flowing from the side surface external electrode 4 to the side surface facing portion 15Ba or from the side surface facing portion 15Ba to the side surface external electrode 4 passes through the side surface drawn-out portion 15Bb.

[0061] Unlike the embodiment, when the extension region 15Bbk is not provided, the side lead portion 15Bb consists only of the base region 15Bbb. The dimension L1 in the length direction L of the base region 15Bbb (the dimension perpendicular to the direction of current flow) is significantly smaller than the dimension LL in the length direction L of the laminate 2. Therefore, it is difficult for current to flow from the side facing portion 15Ba through the side lead portion 15Bb.

[0062] However, in this embodiment, not only the base region 15Bbb but also the extension region 15Bbk is included. Therefore, the dimension in the length direction L (the dimension perpendicular to the direction of current flow) of the side lead portion 15Bb continuing from the side face facing portion 15Ba can be increased. This makes it easier for current to flow from the side face facing portion 15Ba to the side lead portion 15Bb, thereby reducing the ESL of the side lead portion 15Bb.

[0063] (Dimensions of expansion region 15Bbk: 0≦W2≦0.9W1) Furthermore, when the widthwise dimension from the tip P on the side B side of expansion region 15Bbk to side B is W2 as shown in Figure 5, in this embodiment, 0≦W2≦0.9W1.

[0064] (Effect of W2≦0.9W1) Unlike the embodiment, if 0.9W1<W2 is set, the dimension W1-W2 of the extension region 15Bbk in the width direction W (the length of the extension region 15Bbk) becomes smaller than 0.1W1. In this case, the ESL reduction effect achieved by providing the extension region 15Bbk cannot be fully obtained. However, in the embodiment, since W2≦0.9W1, the dimension W of the extension region 15Bbk in the width direction W (W1-W2, the length of the extension region 15Bbk) is 0.1W1 or greater. Therefore, the ESL reduction effect achieved by providing the extension region 15Bbk can be fully obtained.

[0065] (Length dimension L2 of connection portion: 0.1L1≦L2≦0.4LL) When the length dimension of the connection portion between the expansion region 15Bbk and the side surface facing portion 15Ba is L2 as shown in FIG. 5, the following relationship is satisfied between the length dimension LL of the laminate 2 in the length direction L and the dimension L1 of the exposed portion 15Bc exposed on the side surface B of the side lead portion 15Bb: 0.1L1≦L2≦0.4LL

[0066] (Effect of 0.1L1≦L2) Unlike the embodiment, when L2<0.1L1, that is, when the dimension L2 of the extension region 15Bbk in the longitudinal direction L is smaller than 0.1L1, the ESL reduction effect achieved by providing the extension region 15Bbk cannot be fully obtained. However, in the embodiment, 0.1L1≦L2, so the ESL reduction effect achieved by providing the extension region 15Bbk can be fully obtained.

[0067] It should be noted that L2≦0.4LL is a restriction imposed by the difficulty in manufacturing when 0.4LL<L2.

[0068] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible, including the following, for example.

[0069] <1> A three-terminal multilayer ceramic capacitor comprising: a laminate having an inner layer portion in which a plurality of dielectric layers and internal electrodes are alternately laminated; end face external electrodes provided on both end faces of the laminate in a length direction intersecting with a stacking direction; and side face external electrodes provided on at least one of the side faces of the laminate in a width direction intersecting with the stacking direction and the length direction, wherein the internal electrodes comprise: end face exposed internal electrodes exposed on the end faces and connected to the end face external electrodes; and side face exposed internal electrodes connected to the side face external electrodes exposed on the side faces, wherein the side face exposed internal electrodes have side face opposing portions opposing the end face exposed internal electrodes, and side face led portions led out from the side face opposing portions to the side faces, wherein the multilayer ceramic capacitor has: a dimension LC in the length direction of 0.1 mm≦LC≦0.70 mm or less; a dimension WC in the width direction of 0.05 mm≦WC≦0.40 mm or less; and a dimension TC in the stacking direction of 0.10 mm≦TC≦0.55 mm or less, the side drawn-out portion includes: a substantially rectangular base region extending from the side facing portion to the side surface, the width dimension of which is W1 and the length dimension of which is L1, such that 10 μm≦L1≦100 μm; and an extension region disposed on at least one side of the length direction of the base region, the width dimension between the tip of the side surface side and the side surface being W2, such that 0≦W2≦0.9W1, and the length dimension of the portion connected to the side facing portion being L2, such that LL is the length dimension of the laminate.

[0070] <2> The multilayer ceramic capacitor according to <1>, having a capacitance of 0.022 μF or more and 10 μF or less.

[0071] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the equivalent series inductance is 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

[0072] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the area of ​​the extension region is smaller than W1×L2.

[0073] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the dimension of the extension region in the length direction gradually decreases from the side surface facing portion toward the side surface.

[0074] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 End face external electrode 4 Side face external electrode 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 14A First dielectric layer 14B Second dielectric layer 15 Internal electrode 15A End face exposed internal electrode 15Aa End face opposing portion 15Ab End face drawn portion 15B Side face exposed internal electrode 15Ba Side face opposing portion 15Bb Side face drawn portion 15Bbb Base region 15Bbk Extension region

Claims

1. A three-terminal multilayer ceramic capacitor comprising: a laminate having an inner layer portion in which a plurality of dielectric layers and internal electrodes are alternately laminated; end face external electrodes provided on both end faces of the laminate in a length direction intersecting with a lamination direction; and a side face external electrode provided on at least one of the side faces of the laminate in a width direction intersecting with the lamination direction and the length direction, wherein the internal electrodes comprise: end face exposed internal electrodes exposed on the end faces and connected to the end face external electrodes; and side face exposed internal electrodes connected to the side face external electrodes exposed on the side faces, wherein the side face exposed internal electrodes have a side face opposing portion opposing the end face exposed internal electrode, and a side face extended portion extended from the side face opposing portion to the side face, wherein the multilayer ceramic capacitor has a dimension LC in the length direction of 0.1 mm≦LC≦0.70 mm or less, a dimension WC in the width direction of 0.05 mm≦WC≦0.40 mm or less, and a dimension TC in the lamination direction of 0.10 mm≦TC≦0.55 mm or less, the side drawn-out portion includes: a substantially rectangular base region extending from the side facing portion to the side and having a dimension W1 in the width direction and a dimension L1 in the length direction of 10 μm≦L1≦100 μm; and an extension region that is disposed on at least one side of the length direction of the base region and has a dimension W2 in the width direction between the tip of the side surface and the side surface such that 0≦W2≦0.9W1, and has a dimension L2 in the length direction of a portion connected to the side facing portion and a dimension LL in the length direction of the laminate, the dimension L2 being 0.1L1≦L2≦0.4LL.

2. The multilayer ceramic capacitor according to claim 1, having a capacitance of 0.022 μF or more and 10 μF or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, having an equivalent series inductance of 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

4. The multilayer ceramic capacitor according to claim 1, wherein the area of ​​the extension region is smaller than W1×L2.

5. The multilayer ceramic capacitor according to claim 1, wherein the extension region has a dimension in the longitudinal direction that gradually decreases from the side surface facing portion toward the side surface.

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