Voltage detection circuit

Abstract

This voltage detection circuit having a differential configuration comprises: a plurality of switches (S1-S4, S71) disposed between a pair of input nodes (Nip, Nim) and a pair of output nodes (Nop, Nom) and including series circuits (SC1-SC4, 76, 79) configured such that two MOS transistors (15-22, 74-78) are connected in series; and a capacitive couple drive unit (14). The capacitive couple drive unit is provided with drive capacities (Cdr1-Cdr4), and controls the ON / OFF of each of the plurality of switches by driving the gates of the MOS transistors provided to the plurality of switches via the drive capacities. The back gate of the MOS transistor is connected to a terminal, among the terminals of the source or drain thereof, on the side not connected to intermediate nodes (N1-N4, N71, N72) that are interconnection nodes of the two MOS transistors.

Description

Voltage Detection Circuit CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2023-126294, filed on August 2, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a voltage detection circuit with a fully differential configuration.

[0003] Patent Document 1 discloses a fully differential voltage detection circuit that employs a switch circuit known as a CCSW circuit. CCSW is an abbreviation for Capacitively-Coupled Switch. Hereinafter, the voltage detection circuit disclosed in Patent Document 1 will be referred to as the prior art. The prior art is configured with a selector that applies the higher of the voltages at two input nodes as the substrate potential of a P-channel MOS transistor and the lower of the voltages at the two input nodes as the substrate potential of an N-channel MOS transistor.

[0004] Patent No. 6673150

[0005] The prior art is intended for use in a battery monitoring IC that monitors battery voltage. IC stands for Integrated Circuit. As the number of types of batteries to be detected increases, the voltage range that can be detected by battery monitoring ICs tends to expand year by year. Changing the IC design for each type of battery leads to an increase in the number of product types, so it is desirable for a battery monitoring IC to be able to detect a wide range of voltages, both positive and negative, with a single chip, i.e., a single AFE. AFE stands for Analog Front End.

[0006] While the conventional technology is suitable for applications where the voltage of a fuel cell is to be detected because it can detect negative voltages, it is not suitable for applications where the voltage of a lithium-ion battery is to be detected because the input range of positive voltage is relatively narrow, for example, from 0 to 5 V. Furthermore, with the conventional technology, there is a risk that the selector will not operate when the input voltage is near 0 V, causing leakage current and reducing detection accuracy.

[0007] An object of the present disclosure is to provide a voltage detection circuit that can accurately detect a wide range of voltages while suppressing the occurrence of leakage current.

[0008] In one aspect of the present disclosure, a voltage detection circuit is a fully differential voltage detection circuit that receives voltages from a pair of input nodes, detects a differential voltage between the voltages, and outputs the differential voltage from a pair of output nodes, and includes a plurality of switches and a capacitive couple driver. The plurality of switches are provided between the pair of input nodes and the pair of output nodes and include a series circuit in which two MOS transistors are connected in series. The capacitive couple driver includes a drive capacitor and controls the on / off of each of the plurality of switches by driving the gates of the MOS transistors included in the plurality of switches via the drive capacitor. In this case, the back gate of the MOS transistor is connected to the terminal of its source or drain that is not connected to the intermediate node, which is the interconnection node between the two MOS transistors.

[0009] In this way, in each of the multiple switches, the body diodes of the two MOS transistors face each other. Therefore, with this configuration, no current flows through the body diode, eliminating the occurrence of errors. In particular, since no backflow occurs through the body diode when a negative voltage is input, the occurrence of errors associated with this can be suppressed. Therefore, with this configuration, the occurrence of leakage current is suppressed while the occurrence of a wide range of voltages can be accurately detected.

[0010] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. 1 is a diagram showing a schematic configuration of a voltage detection circuit according to a first embodiment; FIG. 2 is a diagram showing a schematic configuration of a battery monitoring IC according to a first embodiment; FIG. 3 is a diagram showing a specific configuration example of a switch circuit and a leak cancellation circuit according to a first embodiment; FIG. 4 is a diagram for explaining the potential state of each part during a sample period when a positive voltage is input according to a first embodiment; FIG. 5 is a diagram for explaining the potential state of each part during a hold period when a positive voltage is input according to a first embodiment; FIG. 6 is a diagram for explaining the potential state of each part during a sample period when a negative voltage is input according to a first embodiment;

[0011] Hereinafter, several embodiments will be described with reference to the drawings. Note that substantially the same components in each embodiment will be denoted by the same reference numerals and the description thereof will be omitted. (First Embodiment) Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 8.

[0012] <Overall Configuration> As shown in Figure 1, the voltage detection circuit 1 of this embodiment includes a fully differential switched capacitor amplifier 2 having a pair of input nodes Nip and Nim and a pair of output nodes Nop and Nom, as well as various circuits not shown. In this specification, the switched capacitor amplifier may be abbreviated as an SC amplifier. The voltage detection circuit 1 receives the voltage VINP at the input node Nip and the voltage VINM at the input node Nim, detects the difference between these voltages, and outputs the result from the output nodes Nop and Nom. The voltage detection circuit 1 is configured as an IC to be mounted on a vehicle such as an automobile together with other circuit elements not shown.

[0013] The SC amplifier 2 includes a differential output operational amplifier 3, capacitors Cs1, Cs2, Cf1, Cf2, Cd1, and Cd2, and switches S1 to S16. The on / off of the switches S1 to S16 is controlled by a control circuit (not shown). Each of the capacitors, including the capacitors Cs1, Cs2, Cf1, Cf2, Cd1, and Cd2, includes two terminals. In this specification, in order to distinguish between the two terminals of a capacitor, one of the two terminals may be referred to as a first terminal and the other of the two terminals may be referred to as a second terminal.

[0014] A first terminal of the capacitor Cs1 is connected to the inverting input terminal of the operational amplifier 3. A common potential VCM can be applied to the first terminal of the capacitor Cs1 via a switch S5. A second terminal of the capacitor Cs1 is connected to the input node Nip via a switch S1 and to the input node Nim via a switch S2. A first terminal of the capacitor Cs2 is connected to the non-inverting input terminal of the operational amplifier 3. A common potential VCM can be applied to the first terminal of the capacitor Cs2 via a switch S6. A second terminal of the capacitor Cs2 is connected to the input node Nim via a switch S3 and to the input node Nip via a switch S4.

[0015] In this way, the pair of capacitors Cs1 and Cs2 in the differential configuration have first terminals connected to the input terminals of the operational amplifier 3, and function as a pair of sampling capacitors. The capacitors Cs1 and Cs2 have the same capacitance value. Note that in this specification, "the same capacitance value" does not only mean that the capacitance values ​​are completely the same, but also includes capacitance values ​​that are slightly different and do not strictly match, as long as the desired effect is achieved.

[0016] A first terminal of the capacitor Cf1 is connected to the inverting input terminal of the operational amplifier 3. A second terminal of the capacitor Cf1 is connected to the non-inverting output terminal of the operational amplifier 3 via the switch S7. That is, the capacitor Cf1 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier 3 via the switch S7. A common potential VCM can be applied to the second terminal of the capacitor Cf1 via the switch S8.

[0017] A first terminal of capacitor Cf2 is connected to the non-inverting input terminal of the operational amplifier 3. A second terminal of capacitor Cf2 is connected to the inverting output terminal of the operational amplifier 3 via switch S9. In other words, capacitor Cf2 is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier 3 via switch S9. A common potential VCM can be applied to the second terminal of capacitor Cf2 via switch S10. In this way, the pair of capacitors Cf1 and Cf2 in the differential configuration are connected between the input terminal and the output terminal of the operational amplifier 3 and function as a pair of feedback capacitors. Capacitors Cf1 and Cf2 have the same capacitance value.

[0018] A first terminal of the capacitor Cd1 is connected to the inverting input terminal of the operational amplifier 3. A reference voltage VREFP can be applied to a second terminal of the capacitor Cd1 via a switch S11. A common potential VCM can be applied to the second terminal of the capacitor Cd1 via a switch S12. A reference voltage VREFM can be applied to the second terminal of the capacitor Cd1 via a switch S13. The reference voltages VREFP and VREFM are examples of DAC voltages output from a D / A converter (not shown). Note that in this specification, the D / A converter may be abbreviated as DAC.

[0019] A first terminal of the capacitor Cd2 is connected to the non-inverting input terminal of the operational amplifier 3. A reference voltage VREFP can be applied to a second terminal of the capacitor Cd2 via a switch S14. A common potential VCM can be applied to a second terminal of the capacitor Cd2 via a switch S15. A reference voltage VREFM can be applied to a second terminal of the capacitor Cd2 via a switch S16. Thus, the pair of capacitors Cd1 and Cd2 in the differential configuration can store charge according to the DAC voltage, and their first terminals are connected to the input terminals of the operational amplifier 3, functioning as a pair of DAC capacitances. The capacitors Cd1 and Cd2 have the same capacitance value.

[0020] Although not shown, the SC amplifier 2 includes a common-mode feedback circuit that controls the common-mode level of the output voltage of the operational amplifier 3. In the above configuration, the common-mode feedback circuit operates to feedback-control the common-mode level of the output voltage of the operational amplifier 3 to the common potential VCM. Note that in the SC amplifier 2, the common potentials of all circuits are set to the common potential VCM.

[0021] The SC amplifier 2 samples input voltages VINP and VINM, which are applied via a pair of input nodes Nip and Nim, using capacitors Cs1 and Cs2. The SC amplifier 2 transfers the sampled charge via capacitors Cf1 and Cf2, and outputs output voltages VOUTP and VOUTM, which are obtained by amplifying the input voltages VINP and VINM, from the output terminals of the operational amplifier 3. The non-inverting output terminal of the operational amplifier 3 is connected to the output node Nop. The inverting output terminal of the operational amplifier 3 is connected to the output node Nom. Therefore, the output voltages VOUTP and VOUTM are output to a subsequent circuit via the pair of output nodes Nop and Nom.

[0022] <Application Example of Voltage Detection Circuit> As shown in Figure 2, the voltage detection circuit 1 of this embodiment can be applied to a battery monitoring IC 5 that monitors an assembled battery 4 mounted on a vehicle. The assembled battery 4 is a lithium-ion battery, a fuel cell, or the like, and includes multiple battery cells 4a, 4b, etc. connected in series in multiple stages. As a result, a common-mode voltage is superimposed on the multiple battery cells 4a, 4b, etc. This common-mode voltage increases with the battery cells connected to the upper stage of the assembled battery 4, i.e., the higher potential side, and its maximum value can be a relatively high voltage of, for example, several hundred volts. Note that Figure 2 only illustrates two battery cells 4a, 4b, which are part of the assembled battery, and their corresponding configuration.

[0023] The negative terminal P9 of the battery cell (not shown) located at the bottom of the battery pack 4, i.e., on the lowest potential side, is connected to the ground line Lg. The battery monitoring IC 5 has functions such as detecting and amplifying the voltage between the terminals of the battery pack 4, i.e., the battery cells 4a and 4b. The battery monitoring IC 5 also has a function of detecting the current flowing through the battery cells 4a and 4b. The battery monitoring IC 5 has terminals P1 and P2 corresponding to the terminals of the battery cell 4a, terminals P3 and P4 corresponding to the terminals of the battery cell 4b, and a terminal P9 for supplying a ground potential of 0V.

[0024] Each terminal of battery cell 4a is connected to terminals P1 and P2 via filter 6a. Filter 6a is an RC filter and includes resistors R1 and R2 and a capacitor C1. Each terminal of battery cell 4b is connected to terminals P3 and P4 via filter 6b. Filter 6b is an RC filter configured similarly to filter 6a and includes resistors R3 and R4 and a capacitor C2. Terminal P9 is configured as the negative terminal of the battery cell with the lowest potential, and is connected to ground line Lg.

[0025] In addition to the voltage detection circuit 1, the battery monitoring IC 5 includes a multiplexer 7 and a switch circuit 8. The voltage detection circuit 1 includes an SC amplifier 2, a control circuit 9, a leak cancellation circuit 10, an A / D converter 11, and various digital circuits (not shown). In this specification, the A / D converter is sometimes abbreviated as ADC. The control circuit 9 controls the overall operation of the battery monitoring IC 5, and includes as part of its configuration a capacitive couple driver that controls the on / off of switches S1 to S4 included in the voltage detection circuit 1.

[0026] The leakage cancellation circuit 10 includes a DAC 10a, an amplifier 10b, and two switched capacitor blocks 10c and 10d connected in parallel. The leakage cancellation circuit 10 is a differential circuit that cancels the charge leaking from a pair of input nodes Nip and Nim due to the operation of the voltage detection circuit 1, more specifically, the operation of the switches S1 to S4, i.e., the leakage current. In FIG. 2, the leakage cancellation circuit is abbreviated as LC circuit, and the switched capacitor block is abbreviated as SCB.

[0027] The multiplexer 7 selects one of the voltages at terminals P1 and P2, the voltages at terminals P3 and P4, etc., by switching switches Sm1, Sm2, Sm3, Sm4, etc. on and off, and outputs the selected signal to a subsequent stage. The differential analog signal selected by the multiplexer 7 is input to a voltage detection circuit 1 via a switch circuit 8 including a chop switch in which four switches Sh1, Sh2, Sh3, and Sh4 are cross-connected. In the voltage detection circuit 1, an SC amplifier 2 receives and integrates the differential analog signal, and outputs the integrated voltage to an ADC 11 in a subsequent stage. When the ADC 11 receives the integrated voltage, it quantizes it into multiple levels and outputs a digital signal. The digital output is then output after undergoing predetermined digital processing.

[0028] According to the above configuration, the pair of input nodes Nip, Nim of the voltage detection circuit 1 can be connected to the terminals of each of the battery cells 4a, 4b, etc. that make up the battery pack 4. The voltage detection circuit 1 forms part of a differential sample-and-hold circuit that outputs a detection voltage corresponding to the input voltages VINP, VINM. The voltage detection circuit 1 also forms part of a level shift circuit that reduces the relatively high common-mode voltage superimposed on each of the battery cells 4a, 4b, etc. to a relatively low common-mode voltage.

[0029] The output voltages VOUTP and VOUTM output from the SC amplifier 2 of the voltage detection circuit 1 correspond to detected voltages corresponding to the input voltages VINP and VINM, and are converted into digital data by a differential input ADC 11. This digital data represents the detected values ​​of the input voltages VINP and VINM, and is acquired by a higher-level control device (not shown). The voltage detection circuit 1 is configured to be able to add an offset so that the output voltages VOUTP and VOUTM fall within the input voltage range of the ADC 11, for example, a voltage range of +2.5 V to -2.5 V.

[0030] <Specific Configuration of Switch Circuit and Leakage Cancellation Circuit> In the above configuration, the multiple switches S1 to S4 connected between the pair of input nodes Nip, Nim and the pair of sampling capacitors, ie, capacitors Cs1 and Cs2, together with the selector 13 and the capacitive couple drive unit 14, constitute a switch circuit 12, which is a CCSW circuit, as shown in Figures 1 and 2. Note that while Figures 1 and 2 show a simplified configuration of the selector 13 and the capacitive couple drive unit 14, their detailed configurations will be described later with reference to Figure 3. The switch circuit 12, including the switches S1 to S4, constitutes part of the SC amplifier 2, and a specific configuration such as that shown in Figure 3 can be adopted.

[0031] In the following description, of the pair of input nodes Nip, Nim, the input node Nip on the higher potential side may be referred to as the first input node, and the input node Nim on the lower potential side may be referred to as the second input node. Also, in the following description, of the multiple switches S1 to S4, the switches S1 and S4 connected to the first input node may be referred to as the first switches, and the switches S2 and S3 connected to the second node may be referred to as the second switches.

[0032] 3, the switch circuit 12 includes switches S1 to S4, as well as a selector 13 and a capacitive couple driver 14. The switches S1 to S4 are provided between input nodes Nip, Nim and output nodes Nop, Nom so as to be able to open and close the nodes, and include a series circuit in which two MOS transistors are connected in series. In this case, the MOS transistor of the first switch is a P-channel MOS transistor, and the MOS transistor of the second switch is an N-channel MOS transistor.

[0033] The specific configuration of switches S1 to S4 is as follows. The two MOS transistors 15 and 16 included in switch S1 are both P-channel MOS transistors. In this specification, P-channel MOS transistors may be abbreviated as PMOS. In other words, switch S1 includes a series circuit SC1 in which two PMOS transistors 15 and 16 are connected in series. The source of PMOS 15 is connected to input node Nip, and its drain is connected to node N1. The drain of PMOS 16 is connected to node N1, and its source is connected to node Np.

[0034] Node N1 is an example of an intermediate node, which is an interconnection node between two PMOS transistors 15 and 16. Node Np is connected to the second terminal of capacitor Cs1 and corresponds to the higher-potential output node of the pair of output nodes of switch circuit 12. The back gate of PMOS transistor 15 is connected to its source. The back gate of PMOS transistor 16 is connected to its source. In other words, the back gates of PMOS transistors 15 and 16 are connected to the terminal of their source or drain that is not connected to node N1, which is the intermediate node.

[0035] In a MOS transistor, the back gate and the body are synonymous, and therefore in this specification, the back gate of each MOS transistor, including PMOSs 15 and 16, may be referred to as the body. Between the body and drain of PMOS 15, there is a body diode D15 with the drain side as the anode. Between the body and drain of PMOS 16, there is a body diode D16 with the drain side as the anode. In other words, in switch S1, the body diodes D15 and D16 face each other. The gates of PMOSs 15 and 16 are connected to a capacitive couple driver 14, and their on / off states are controlled by the capacitive couple driver 14.

[0036] The two MOS transistors 17 and 18 included in the switch S2 are both N-channel MOS transistors. In this specification, an N-channel MOS transistor may be abbreviated as NMOS. In other words, the switch S2 includes a series circuit SC2 in which two NMOS transistors 17 and 18 are connected in series. The source of the NMOS 17 is connected to the input node Nim, and its drain is connected to the node N2. The drain of the NMOS 18 is connected to the node N2, and its source is connected to the node Np.

[0037] Node N2 is an example of an intermediate node, which is an interconnection node between two NMOSs 17 and 18. The back gate of NMOS 17 is connected to its source. The back gate of NMOS 18 is connected to its source. In other words, the back gates of NMOSs 17 and 18 are connected to the terminal of their source or drain that is not connected to node N2, which is the intermediate node.

[0038] Between the body and drain of NMOS 17, there is a body diode D17 with the body side as the anode. Between the body and drain of NMOS 18, there is a body diode D18 with the body side as the anode. In other words, in switch S2, the body diodes D17 and D18 face each other. The gates of NMOS 17 and NMOS 18 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0039] The two MOS transistors 19 and 20 included in the switch S3 are both NMOS transistors. That is, the switch S3 includes a series circuit SC3 in which two NMOS transistors 19 and 20 are connected in series. The source of the NMOS 19 is connected to the input node Nim, and its drain is connected to a node N3. The drain of the NMOS 20 is connected to the node N3, and its source is connected to a node Nm. The node N3 is an example of an intermediate node, which is an interconnection node between the two NMOS transistors 19 and 20.

[0040] Node Nm is connected to the second terminal of capacitor Cs2 and corresponds to the lower-potential output node of the pair of output nodes of switch circuit 12. The back gate of NMOS 19 is connected to its source. The back gate of NMOS 20 is connected to its source. In other words, the back gates of NMOSs 19 and 20 are connected to the source or drain terminal of the NMOS that is not connected to node N3, which is the intermediate node.

[0041] Between the body and drain of NMOS19, there is a body diode D19 with the body side as the anode. Between the body and drain of NMOS20, there is a body diode D20 with the body side as the anode. In other words, in switch S3, the body diodes D19 and D20 face each other. The gates of NMOS19 and NMOS20 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0042] The two MOS transistors 21 and 22 included in the switch S4 are both PMOS transistors. That is, the switch S4 includes a series circuit SC4 in which the two PMOS transistors 21 and 22 are connected in series. The source of the PMOS transistor 21 is connected to the input node Nip, and its drain is connected to a node N4. The drain of the PMOS transistor 22 is connected to the node N4, and its source is connected to a node Nm. The node N4 is an example of an intermediate node, which is an interconnection node between the two PMOS transistors 21 and 22.

[0043] The back gate of PMOS 21 is connected to its source, and the back gate of PMOS 22 is connected to its source. That is, the back gates of PMOSs 21 and 22 are connected to the source or drain terminal that is not connected to node N4, which is the intermediate node.

[0044] Between the body and drain of PMOS 21, there is a body diode D21 with the drain side as the anode. Between the body and drain of PMOS 22, there is a body diode D22 with the drain side as the anode. In other words, in switch S4, the body diodes D21 and D22 face each other. The gates of PMOS 21 and PMOS 22 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0045] The selector 13 is connected between a pair of input nodes Nip and Nim, selects one of the voltages VINP and VINM of the pair of input nodes Nip and Nim, and outputs a selection signal having a potential corresponding to the selected voltage, and includes a maximum selector 23, a minimum selector 24, and a Zener diode 25. The maximum selector 23 and the minimum selector 24 each include two MOS transistors connected in series between the pair of input nodes Nip and Nim. The two MOS transistors included in the maximum selector 23 are PMOSs 26 and 27.

[0046] The drain of PMOS 26 is connected to input node Nip, and the drain of PMOS 27 is connected to input node Nim. The gate of PMOS 26 is connected to input node Nim, and the gate of PMOS 27 is connected to input node Nip. The sources and back gates of PMOS 26 and 27 are both connected to node N5. Node N5 is an output node for outputting selection signal Vmax in maximum selector 23, and is connected to signal line 28. In other words, maximum selector 23 is configured to output the signal of node N5, which is the interconnection node between two PMOSs 26 and 27, as selection signal Vmax.

[0047] Between the body and drain of PMOS 26, there is a body diode D26 with the drain side as the anode. Between the body and drain of PMOS 27, there is a body diode D27 with the drain side as the anode. In other words, in the maximum selector 23, the body diodes D26 and D27 face each other. With this configuration, the maximum selector 23 selects the higher of the voltages VINP and VINM, and outputs a selection signal Vmax having a potential corresponding to the selected voltage to other circuits via node N5 and signal line 28.

[0048] A normal MOS transistor having a normal threshold is used as PMOS 27, which is one of the two PMOSs 26, 27 included in the maximum selector 23. A low-threshold MOS transistor having a threshold lower than the normal threshold is used as PMOS 26, which is the other of the two PMOSs 26, 27 included in the maximum selector 23. Low-threshold MOS transistors also include depletion MOS transistors with a threshold of 0 V. In this embodiment, a depletion MOS transistor is used as PMOS 26. In FIG. 2 and other figures, the symbols of MOS transistors that use depletion MOS transistors are distinguished by adding an * mark near the gate.

[0049] The two MOS transistors included in the minimum selector 24 are NMOS 29 and 30. The drain of NMOS 29 is connected to the input node Nip, and the drain of NMOS 30 is connected to the input node Nim. The gate of NMOS 29 is connected to the input node Nim, and the gate of NMOS 30 is connected to the input node Nip. The sources and back gates of NMOS 29 and 30 are both connected to a node N6. The node N6 is an output node for outputting a selection signal Vmin in the minimum selector 24, and is connected to a signal line 31. In other words, the minimum selector 24 is configured to output the signal of the node N6, which is the interconnection node of the two NMOS 29 and 30, as the selection signal Vmin.

[0050] Between the body and drain of NMOS 29, there is a body diode D29 with the body side as the anode. Between the body and drain of NMOS 30, there is a body diode D30 with the body side as the anode. In other words, in the minimum selector 24, the body diodes D29 and D30 face each other. With this configuration, the minimum selector 24 selects the lower of the voltages VINP and VINM, and outputs a selection signal Vmin having a potential corresponding to the selected voltage to other circuits via node N6 and signal line 31.

[0051] A normal MOS transistor having a normal threshold is used as the NMOS 29, which is one of the two NMOSs 29 and 30 included in the minimum selector 24. A low-threshold MOS transistor having a threshold lower than the normal threshold is used as the other NMOS 30, which is the other of the two NMOSs 29 and 30 included in the minimum selector 24. In this embodiment, a depletion MOS transistor is used as the NMOS 30.

[0052] In the selector 13 configured as described above, there exists an unstable operational region in which normal operation becomes impossible depending on the difference between the voltages VINP and VINM of the input nodes Nip and Nim. Therefore, in the configuration described above, a Zener diode 25 with the anode on the node N6 side is connected between the nodes N5 and N6. This fixes the potential relationship between the selection signals Vmax and Vmin to a predetermined value in the unstable operational region.

[0053] In the above configuration, switches S1 to S4 are provided on the input side of operational amplifier 3. These switches S1 to S4, together with capacitors Cs1 and Cs2, form an RC filter, thereby increasing the input impedance of operational amplifier 3. As a result, the above configuration is susceptible to the influence of leakage current flowing in from the multiplexer 7 side, and a leakage cancellation circuit 10 is provided to eliminate this influence. As shown in FIG. 2, the leakage cancellation circuit 10 is connected to input nodes Nip and Nim.

[0054] The leakage cancellation circuit 10 has a configuration as shown in FIG. 2. The DAC 10a is configured to receive a digital command value for generating a compensation current, convert it to analog, and output two command voltages to be input to the amplifier 10b. The DAC 10a is configured as a fully differential DAC. The fully differential DAC outputs two command voltages: a first voltage that is directly proportional to the digital command value with a positive gradient, and a second voltage that is directly proportional to the digital command value with a negative gradient. The DAC 10a may also be configured as a pseudo-differential DAC. The pseudo-differential DAC outputs two command voltages: a first voltage that is constant regardless of the digital command value, and a second voltage that is directly proportional to the digital command value.

[0055] The amplifier 10b is composed of two single-ended buffers configured as voltage followers. The amplifier 10b receives the two command voltages output by the DAC 10a, performs impedance conversion using the voltage followers, and outputs voltages Vdp and Vdm. The two switched capacitor blocks 10c and 10d have the same configuration and switch between the outputs of the two buffers to charge and discharge a pair of capacitors for output.

[0056] The switched capacitor blocks 10c and 10d include four switches connected in front of the two capacitors, i.e., between the two buffers and the first terminals of the two capacitors, and three switches connected in rear of the two capacitors, i.e., between the second terminals of the two capacitors and the input nodes Nip and Nim. Of the switches included in the leakage cancellation circuit 10, three switches connected in rear of the two capacitors are shown in FIG.

[0057] 3 shows three switches SL1, SL2, and SL3 connected to the rear stages of the two capacitors in the switched capacitor block 10 c, and three switches SL4, SL5, and SL6 connected to the rear stages of the two capacitors in the switched capacitor block 10 d. Also shown in FIG. 3 are a pair of input nodes NLi1 and NLi2 connected to the second terminals of the two capacitors in the switched capacitor block 10 c, and a pair of input nodes NLi3 and NLi4 connected to the second terminals of the two capacitors in the switched capacitor block 10 d.

[0058] The input nodes NLi1, NLi2 and the input nodes NLi3, NLi4 all function as a pair of cancellation input nodes for inputting cancellation charges for canceling leaking charges. In the above configuration, signals CLDAP, CLDAM, CLDBP, and CLDBM corresponding to the cancellation charges are supplied to the input nodes NLi1, NLi2, NLi3, and NLi4, respectively, in accordance with the operation of the leakage cancellation circuit 10.

[0059] The switches SL1 to SL3 are provided so as to be able to open and close between a pair of input nodes Nip, Nim and a pair of input nodes NLi1, NLi2, and function as a plurality of cancel switches. The switches SL1 to SL3 each include a series circuit configured with two MOS transistors connected in series. However, the switch SL3 has two of the above-mentioned series circuits, configured by connecting these two series circuits in parallel. The switches SL4 to SL6 are provided so as to be able to open and close between a pair of input nodes Nip, Nim and a pair of input nodes NLi3, NLi4, and function as a plurality of cancel switches. The switches SL4 to SL6 each include a series circuit configured with two MOS transistors connected in series. However, the switch SL6 has two of the above-mentioned series circuits, configured by connecting these two series circuits in parallel.

[0060] In the following description, of the pair of input nodes NLi1, NLi2 and the pair of input nodes NLi3, NLi4, the input nodes NLi1, NLi3 on the high potential side may be referred to as the first cancel input node, and the input nodes NLi2, NLi4 on the low potential side may be referred to as the second cancel input node. Also, in the following description, of the multiple switches SL1 to SL6, the switches SL1, SL4 connected between the first input node and the first cancel input node may be referred to as the first cancel switch, the switches SL2, SL5 connected between the second input node and the second cancel input node may be referred to as the second cancel switch, and the switches SL3, SL6 connected between the first cancel input node and the second cancel input node may be referred to as the third cancel switch.

[0061] In this case, the two MOS transistors included in the first cancel switch are both PMOS, and the two MOS transistors included in the second cancel switch are both NMOS. Also, in this case, the two MOS transistors included in one of the two series circuits included in the third cancel switch are both PMOS, and the two MOS transistors included in the other of the two series circuits included in the third cancel switch are both NMOS transistors.

[0062] The specific configuration of the switches SL1 to SL6 is as follows. The two MOS transistors 41 and 42 included in the switch SL1 are both PMOS. In other words, the switch SL1 includes a series circuit SCL1 configured with two PMOS transistors 41 and 42 connected in series. The source of the PMOS 41 is connected to the input node Nip, and its drain is connected to the node NL1. The drain of the PMOS 42 is connected to the node NL1, and its source is connected to the input node NLi1.

[0063] The node NL1 is an example of an intermediate node that is an interconnection node between the two PMOS transistors 41 and 42. The back gate of the PMOS transistor 41 is connected to its source. The back gate of the PMOS transistor 42 is connected to its source. In other words, the back gates of the PMOS transistors 41 and 42 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL1.

[0064] Between the body and drain of PMOS 41, there is a body diode D41 with the drain side as the anode. Between the body and drain of PMOS 42, there is a body diode D42 with the drain side as the anode. In other words, the body diodes D41 and D42 face each other in switch SL1. The gates of PMOS 41 and PMOS 42 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0065] The two MOS transistors 43 and 44 included in the switch SL2 are both NMOS. That is, the switch SL2 includes a series circuit SCL2 configured by connecting two NMOS transistors 43 and 44 in series. The source of the NMOS 43 is connected to the input node Nim, and its drain is connected to a node NL2. The drain of the NMOS 44 is connected to the node NL2, and its source is connected to a node NLi2.

[0066] The node NL2 is an example of an intermediate node that is an interconnection node between two NMOS transistors 43 and 44. The back gate of the NMOS transistor 43 is connected to its source. The back gate of the NMOS transistor 44 is connected to its source. In other words, the back gates of the NMOS transistors 43 and 44 are connected to the terminal of their source or drain that is not connected to the intermediate node, node NL2.

[0067] Between the body and drain of NMOS 43, there is a body diode D43 with the body side as the anode. Between the body and drain of NMOS 44, there is a body diode D44 with the body side as the anode. In other words, the body diodes D43 and D44 face each other in switch SL2. The gates of NMOS 43 and 44 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0068] The switch SL3 includes two PMOS transistors 45 and 46 and two NMOS transistors 47 and 48. The switch SL3 includes a series circuit SCL3a configured by connecting two PMOS transistors 45 and 46 in series, and a series circuit SCL3b configured by connecting two NMOS transistors 47 and 48 in series. The switch SL3 is configured by connecting the two series circuits SCL3a and SCL3b in parallel. The source of the PMOS transistor 45 is connected to the input node NLi1, and its drain is connected to the node NL3a. The drain of the PMOS transistor 46 is connected to the node NL3a, and its source is connected to the input node NLi2.

[0069] The node NL3a is an example of an intermediate node, which is an interconnection node between two PMOS transistors 45 and 46. The back gate of the PMOS transistor 45 is connected to its source. The back gate of the PMOS transistor 46 is connected to its source. In other words, the back gates of the PMOS transistors 45 and 46 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL3a.

[0070] Between the body and drain of PMOS 45, there is a body diode D45 with the drain side as the anode. Between the body and drain of PMOS 46, there is a body diode D46 with the drain side as the anode. That is, in the series circuit SCL3a of switch SL3, the body diodes D45 and D46 face each other. The gates of PMOS 45 and 46 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0071] The source of the NMOS 47 is connected to the input node NLi1, and its drain is connected to the node NL3b. The drain of the NMOS 48 is connected to the node NL3b, and its source is connected to the input node NLi2. The node NL3b is an example of an intermediate node, which is an interconnection node between the two NMOSs 47 and 48. The back gate of the NMOS 47 is connected to its source. The back gate of the NMOS 48 is connected to its source. In other words, the back gates of the NMOSs 47 and 48 are connected to the terminal of their source or drain that is not connected to the intermediate node, node NL3b.

[0072] Between the body and drain of NMOS 47, there is a body diode D47 with the body side as the anode. Between the body and drain of NMOS 48, there is a body diode D48 with the body side as the anode. That is, in the series circuit SCL3b of switch SL3, the body diodes D47 and D48 face each other. The gates of NMOS 47 and 48 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0073] The two MOS transistors 49 and 50 included in the switch SL4 are both PMOS transistors. That is, the switch SL4 includes a series circuit SCL4 configured with two PMOS transistors 49 and 50 connected in series. The source of the PMOS 49 is connected to the input node Nip, and its drain is connected to the node NL4. The drain of the PMOS 50 is connected to the node NL4, and its source is connected to the input node NLi3.

[0074] The node NL4 is an example of an intermediate node that is an interconnection node between the two PMOS transistors 49 and 50. The back gate of the PMOS transistor 49 is connected to its source. The back gate of the PMOS transistor 50 is connected to its source. In other words, the back gates of the PMOS transistors 49 and 50 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL4.

[0075] Between the body and drain of PMOS 49, there is a body diode D49 with the drain side as the anode. Between the body and drain of PMOS 50, there is a body diode D50 with the drain side as the anode. In other words, in switch SL4, the body diodes D49 and D50 face each other. The gates of PMOS 49 and 50 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0076] The two MOS transistors 51 and 52 included in the switch SL5 are both NMOS. That is, the switch SL5 includes a series circuit SCL5 configured with two NMOS transistors 51 and 52 connected in series. The source of the NMOS 51 is connected to the input node Nim, and its drain is connected to a node NL5. The drain of the NMOS 52 is connected to the node NL5, and its source is connected to a node NLi4.

[0077] The node NL5 is an example of an intermediate node, which is an interconnection node between two NMOS transistors 51 and 52. The back gate of the NMOS transistor 51 is connected to its source. The back gate of the NMOS transistor 52 is connected to its source. In other words, the back gates of the NMOS transistors 51 and 52 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL5.

[0078] Between the body and drain of NMOS 51, there is a body diode D51 with the body side as the anode. Between the body and drain of NMOS 52, there is a body diode D52 with the body side as the anode. In other words, the body diodes D51 and D52 face each other in switch SL5. The gates of NMOS 51 and 52 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0079] The switch SL6 includes two PMOS transistors 53 and 54 and two NMOS transistors 55 and 56. The switch SL6 includes a series circuit SCL6a configured by connecting two PMOS transistors 53 and 54 in series, and a series circuit SCL6b configured by connecting two NMOS transistors 55 and 56 in series. The switch SL6 is configured by connecting the two series circuits SCL6a and SCL6b in parallel. The source of the PMOS transistor 53 is connected to the input node NLi3, and its drain is connected to the node NL6a. The drain of the PMOS transistor 54 is connected to the node NL6a, and its source is connected to the input node NLi4.

[0080] The node NL6a is an example of an intermediate node that is an interconnection node between the two PMOS transistors 53 and 54. The back gate of the PMOS transistor 53 is connected to its source. The back gate of the PMOS transistor 54 is connected to its source. In other words, the back gates of the PMOS transistors 53 and 54 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL6a.

[0081] Between the body and drain of PMOS 53, there is a body diode D53 with the drain side as the anode. Between the body and drain of PMOS 54, there is a body diode D54 with the drain side as the anode. That is, in the series circuit SCL6a of switch SL6, the body diodes D53 and D54 face each other. The gates of PMOS 53 and 54 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0082] The source of NMOS 55 is connected to input node NLi3, and its drain is connected to node NL6b. The drain of NMOS 56 is connected to node NL6b, and its source is connected to input node NLi4. Node NL6b is an example of an intermediate node, which is an interconnection node between two NMOSs 55 and 56. The back gate of NMOS 55 is connected to its source. The back gate of NMOS 56 is connected to its source. In other words, the back gates of NMOSs 55 and 56 are connected to the terminal of their source or drain that is not connected to node NL6b, which is the intermediate node.

[0083] Between the body and drain of NMOS 55, there is a body diode D55 with the body side as the anode. Between the body and drain of NMOS 56, there is a body diode D56 with the body side as the anode. That is, in the series circuit SCL6b of switch SL6, the body diodes D55 and D56 face each other. The gates of NMOS 55 and 56 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14.

[0084] The capacitive couple driver 14 controls the operation of the switches S1 to S4 and SL1 to SL6 based on binary control signals SLSA0n, SLSB0n, SLSA0p, and SLSB0p provided from the outside. The high level of the control signals SLSA0n to SLSB0p is +5 V, and the low level is 0 V. The capacitive couple driver 14 controls the on / off of the switches S1 to S4 and SL1 to SL6 by driving the gates of the MOS transistors 15 to 22 and 41 to 56 via the drive capacitors Cdr1 to Cdr4.

[0085] The capacitive couple driver 14 is configured as part of the control circuit 9 described above, and its specific configuration is as follows. Specifically, the capacitive couple driver 14 includes a plurality of drive capacitors Cdr1, Cdr2, Cdr3, and Cdr4 provided corresponding to the switches S1 to S4, respectively, a PMOS driver 33, and an NMOS driver 34. In the following description, the PMOS driver 33 and the NMOS driver 34 may be simply referred to as the drivers 33 and 34. The drive capacitor Cdr1 is connected between a node N7 and a node N8 to which a control signal SLSA0n is applied. The node N8 is connected to the gates of the PMOSs 15, 16, 41, 42, 53, and 54 of the switches S1, SL1, and SL6. The drive capacitor Cdr2 is connected between a node N9 and a node N10 to which a control signal SLSB0p is applied. The node N10 is connected to the gates of the NMOS transistors 17, 18, 47, 48, 51, and 52 of the switches S2, SL3, and SL5.

[0086] The drive capacitance Cdr3 is connected between a node N11 to which a control signal SLSA0p is applied and a node N12. The node N12 is connected to the gates of NMOS transistors 19, 20, 43, 44, 55, and 56 of the switches S3, SL2, and SL6. The drive capacitance Cdr4 is connected between a node N13 to which a control signal SLSB0n is applied and a node N14. The node N14 is connected to the gates of PMOS transistors 21, 22, 45, 46, 49, and 50 of the switches S4, SL3, and SL4. In this embodiment, the drive capacitances Cdr1 to Cdr4 are configured as comb capacitances.

[0087] The driving units 33 and 34 supply driving signals SLSAn, SLSBn, SLSAp, and SLSBp to the gates of the MOS transistors 15 to 22 and 41 to 56 that constitute the switches S1 to S4 and SL1 to SL6, respectively. The driving signals SLSAn to SLSBp are binary signals that take on either an off level that turns off the MOS transistors 15 to 22 and 41 to 56, or an on level that turns on the MOS transistors 15 to 22 and 41 to 56. Specifically, the on and off levels are as follows:

[0088] That is, when the driving target is an NMOS, the ON level is a level that satisfies the following formula (1), when the driving target is a PMOS, the ON level is a level that satisfies the following formula (2), and the OFF level is a level that satisfies the following formula (3), where VGS is the gate-source voltage of the MOS transistor, and Vt is the threshold voltage of the MOS transistor. VGS>Vt (1) VGS<-Vt (2) VGS≈0 (3)

[0089] The PMOS driver 33 includes two PMOSs 35 and 36. The drain of the PMOS 35 is connected to a node N8, and its source is connected to a node N15. The node N15 is connected to the signal line 28. The back gate of the PMOS 35 is connected to its source. The gate of the PMOS 35 is connected to a node N14. Between the body and drain of the PMOS 35, there is a body diode D35 with the drain side as the anode.

[0090] The drain of PMOS 36 is connected to node N14, and its source is connected to node N15. The back gate of PMOS 36 is connected to its source. The gate of PMOS 36 is connected to node N8. Between the body and drain of PMOS 36, there is a body diode D36 with the drain side as the anode.

[0091] The PMOS driver 33 configured as described above uses the potential of the selection signal Vmax output from the selector 13 as a reference potential to generate a drive signal SLSAn for driving the gates of PMOSs 15, 16, 41, 42, 53, and 54, and a drive signal SLSBn for driving the gates of PMOSs 21, 22, 45, 46, 49, and 50. The drive signal SLSAn has the same logic as the control signal SLSA0n, and is supplied from node N8 to the gates of PMOSs 15, 16, 41, 42, 53, and 54 of switches S1, SL1, and SL6. The drive signal SLSBn has the same logic as the control signal SLSB0n, and is supplied from node N14 to the gates of PMOSs 21, 22, 45, 46, 49, and 50 of switches S4, SL3, and SL4.

[0092] The NMOS driver 34 includes two NMOSs 37 and 38. The drain of the NMOS 37 is connected to a node N10, and its source is connected to a node N16. The node N16 is connected to the signal line 31. The back gate of the NMOS 37 is connected to its source. The gate of the NMOS 37 is connected to a node N12. Between the body and drain of the NMOS 37, there is a body diode D37 with the body side as the anode.

[0093] The drain of NMOS 38 is connected to node N12, and its source is connected to node N16. The back gate of NMOS 38 is connected to its source. The gate of NMOS 38 is connected to node N10. Between the body and drain of NMOS 38, there is a body diode D38 with the body side as the anode.

[0094] The NMOS driver 34 configured as described above uses the potential of the selection signal Vmin output from the selector 13 as a reference potential to generate a drive signal SLSBp for driving the gates of NMOSs 17, 18, 47, 48, 51, and 52 and a drive signal SLSAp for driving the gates of NMOSs 19, 20, 43, 44, 55, and 56. The drive signal SLSBp has the same logic as the control signal SLSB0p, and is supplied from node N10 to the gates of NMOSs 17, 18, 47, 48, 51, and 52 of switches S2, SL3, and SL5. The drive signal SLSAp has the same logic as the control signal SLSA0p, and is supplied from node N12 to the gates of NMOSs 19, 20, 43, 44, 55, and 56 of switches S3, SL2, and SL6.

[0095] Next, the operation of the above configuration will be described with reference to FIGS. 4 to 6. The capacitive couple driver 14 controls the switches S1, S3, SL1, SL2, and SL6 and the switches S2, S4, SL3, SL4, and SL5 so that they are complementarily turned on and off. Note that the phrase "complementarily turned on and off" in this specification does not exclude the case where a period during which both switches are off, i.e., a so-called dead time, is provided. Hereinafter, the period during which the switches S1, S3, SL1, SL2, and SL6 are on and the switches S2, S4, SL3, SL4, and SL5 are off will be referred to as a sample period, and the period during which the switches S1, S3, SL1, SL2, and SL6 are off and the switches S2, S4, SL3, SL4, and SL5 are on will be referred to as a hold period.

[0096] In the SC amplifier 2 configured as described above, during the sample period, the capacitors Cs1 and Cs2 are charged by the voltages VINP and VINM of the input nodes Nip and Nim, respectively. That is, the voltages VINP and VINM of the input nodes Nip and Nim are sampled by the capacitors Cs1 and Cs2. Also, in the SC amplifier 2 configured as described above, during the hold period, the charge accumulated in the capacitors Cs1 and Cs2 is transferred to the subsequent circuit. Also, in the SC amplifier 2 configured as described above, the leakage cancellation circuit 10 operates to pass a compensation current during both the hold period and the sample period, thereby canceling the leakage current.

[0097] The following describes the potential states of each part when a positive voltage is input via the input nodes Nip and Nim, and when a negative voltage is input via the input nodes Nip and Nim, assuming such operation. Here, it is assumed that a positive voltage is input when the voltage VINP is +5 V and the voltage VINM is 0 V, and that a negative voltage is input when the voltage VINP is −3 V and the voltage VINM is 0 V. In FIGS. 4 to 6, the on / off states of each MOS transistor are indicated by the presence or absence of hatching. Specifically, in FIGS. 4 to 6, only the MOS transistors that are turned on are hatched.

[0098] [1] Potential States of Each Part When a Positive Voltage is Input As shown in Figures 4 and 5, when a positive voltage is input, in selector 13, PMOS 26 and NMOS 30 are turned on, and PMOS 27 and NMOS 29 are turned off. As a result, when a positive voltage is input, the potential of selection signal Vmax becomes 5 V, and the potential of selection signal Vmin becomes 0 V. As shown in Figures 4 and 6, during the sample period, control signals SLSA0n and SLSB0p become 0 V, and control signals SLSB0n and SLSA0p become 5 V.

[0099] 4, during the sample period when a positive voltage is input, PMOS 36 and NMOS 37 are turned on and PMOS 35 and NMOS 38 are turned off in the drivers 33 and 34. As a result, during the sample period when a positive voltage is input, the drive signal SLSAn becomes 1 V, the drive signal SLSBn becomes 5 V, the drive signal SLSAp becomes 4 V, and the drive signal SLSBp becomes 0 V.

[0100] Therefore, during the sample period when a positive voltage is input, PMOSs 15 and 16 of switch S1, NMOSs 19 and 20 of switch S3, PMOSs 41 and 42 of switch SL1, NMOSs 43 and 44 of switch SL2, and MOS transistors 53 to 56 of switch SL6 are turned on, while NMOSs 17 and 18 of switch S2, PMOSs 21 and 22 of switch S4, MOS transistors 45 to 48 of switch SL3, PMOSs 49 and 50 of switch SL4, and NMOSs 51 and 52 of switch SL5 are turned off.

[0101] 5, during the hold period, the control signals SLSA0n and SLSB0p are 5 V, and the control signals SLSB0n and SLSA0p are 0 V. Therefore, as shown in FIG. 5, during the hold period when a positive voltage is input, PMOS 35 and NMOS 38 are turned on, and PMOS 36 and NMOS 37 are turned off in the drivers 33 and 34. As a result, during the hold period when a positive voltage is input, the drive signal SLSAn is 5 V, the drive signal SLSBn is 1 V, the drive signal SLSAp is 0 V, and the drive signal SLSBp is 4 V.

[0102] Therefore, during the hold period when a positive voltage is input, PMOSs 15 and 16 of switch S1, NMOSs 19 and 20 of switch S3, PMOSs 41 and 42 of switch SL1, NMOSs 43 and 44 of switch SL2, and MOS transistors 53 to 56 of switch SL6 are turned off, while NMOSs 17 and 18 of switch S2, PMOSs 21 and 22 of switch S4, MOS transistors 45 to 48 of switch SL3, PMOSs 49 and 50 of switch SL4, and NMOSs 51 and 52 of switch SL5 are turned on.

[0103] As described above, according to the configuration of this embodiment, when a positive voltage is input, the potential states of the switches S1 to S4 and the switches SL1 to SL6 can be set to potential states equivalent to those in a configuration in which the selector 13 is not provided. Furthermore, according to the configuration of this embodiment, depletion MOS transistors are used as the PMOS 26 and NMOS 30 in the selector 13, which should be turned on when a positive voltage is input. Therefore, even when the input voltage VINP is near 0 V, these PMOS 26 and NMOS 30 can be reliably turned on. As a result, the potentials of the MOS transistors constituting the off switches do not become unstable, and high output precision can be achieved. Note that when the input voltage VINP is near 0 V, this refers to a case in which the input voltage VINP is equal to or lower than the threshold voltage Vt of the MOS transistor, for example, 0.7 V or lower.

[0104] [2] Potential States of Each Part When a Negative Voltage is Input As shown in FIG. 6 , when a negative voltage is input, in selector 13, PMOS 27 and NMOS 29 are turned on, and PMOS 26 and NMOS 30 are turned off. As a result, when a negative voltage is input, the potential of selection signal Vmax becomes 0 V, and the potential of selection signal Vmin becomes −3 V. Therefore, in drive units 33 and 34, PMOS 36 and NMOS 37 are turned on, and PMOS 35 and NMOS 38 are turned off, during the sample period when a negative voltage is input. As a result, during the sample period when a negative voltage is input, drive signal SLSAn becomes −4 V, drive signal SLSBn becomes 0 V, drive signal SLSAp becomes 1 V, and drive signal SLSBp becomes −3 V.

[0105] Therefore, during the sample period when a negative voltage is input, PMOSs 15 and 16 of switch S1, NMOSs 19 and 20 of switch S3, PMOSs 41 and 42 of switch SL1, NMOSs 43 and 44 of switch SL2, and MOS transistors 53 to 56 of switch SL6 are turned on, while NMOSs 17 and 18 of switch S2, PMOSs 21 and 22 of switch S4, MOS transistors 45 to 48 of switch SL3, PMOSs 49 and 50 of switch SL4, and NMOSs 51 and 52 of switch SL5 are turned off. The potential state during the hold period when a negative voltage is input is a differential object with respect to the sample period when a negative voltage is input, so a description thereof will be omitted.

[0106] As described above, according to the configuration of this embodiment, when a negative voltage is input, the voltage VINP, which is the lower potential of the voltages VINP and VINM, is applied to the gate of the NMOS that constitutes the switch that should be turned off among the switches S1 to S4 and SL1 to SL6, and the voltage VINM, which is the higher potential of the voltages VINP and VINM, is applied to the gate of the PMOS that constitutes the switch that should be turned off, thereby reliably turning off these switches.

[0107] Furthermore, according to the configuration of this embodiment, when a negative voltage is input, a drive signal whose potential is changed to be higher than voltage VINP by a level corresponding to the amplitude of the control signal is applied to the gate of an NMOS that constitutes one of the switches S1 to S4 and SL1 to SL6 that should be turned on, and a drive signal whose potential is changed to be lower than voltage VINM by a level corresponding to the amplitude of the control signal is applied to the gate of a PMOS that constitutes one of the switches that should be turned on, thereby reliably turning on those switches.

[0108] The present embodiment described above provides the following advantages. According to the configuration of the present embodiment, in each of the signal transmission switches S1 to S4 for transmitting the input signal voltages VINP and VINM to a subsequent stage and the switches SL1 to SL6 of the leakage cancellation circuit 10, the body diodes of the two MOS transistors face each other. Therefore, with the above configuration, no current flows through the body diode, and no errors occur. In particular, because no backflow occurs through the body diode when a negative voltage is input, the occurrence of errors associated with this can be suppressed.

[0109] Furthermore, with the configuration of this embodiment, when a positive voltage is input, the selector 13 does not become unstable and no leak current occurs, so the potential states of the multiple switches S1 to S4 and SL1 to SL6 can be made equivalent to those in a configuration without the selector 13. Therefore, with the configuration of this embodiment, the input range and detection accuracy of the positive voltage can be made equivalent to those in a configuration without the selector 13.

[0110] Furthermore, according to the configuration of this embodiment, similar to the prior art, negative voltage can be detected by the operation of the selector 13. As described above, according to the configuration of this embodiment, negative voltage can be detected while maintaining the input range and detection accuracy of positive voltage at the same level as in a configuration without the selector 13. Therefore, according to this embodiment, the excellent effect of being able to accurately detect a wide range of voltages while suppressing the occurrence of leakage current can be obtained.

[0111] The effects obtained by this embodiment become clearer when compared with the conventional technology. Therefore, the effects obtained by this embodiment will be described in detail below with reference to FIG. 7 , comparing this embodiment with a comparative example corresponding to the conventional technology. In FIG. 7 , arrows indicating the ranges corresponding to the comparative example are indicated by dotted lines, and arrows indicating the ranges corresponding to this embodiment are indicated by solid lines. Also in FIG. 7 , Vf is the forward voltage of the diode, and Vcc is the drive voltage in the drive units 33 and 34.

[0112] 7, assuming a sample period when a negative voltage is input, the gate voltage range of NMOS 19, 20, etc. of switch S3 that is turned on at that time, i.e., the voltage range of drive signal SLSAp, is shown as the ON SW gate voltage range, and the gate voltage range of NMOS 17, 18, etc. of switch S2 that is turned off at that time, i.e., the voltage range of drive signal SLSBp, is shown as the OFF SW gate voltage range. Note that the negative voltage input in this case is assumed to be when voltage VINP is in the range of "-Vt to 0V" and voltage VINM is 0V.

[0113] As shown in FIG. 7 , the positive-side operating range of the voltage detection circuit 1 of this embodiment is the same as that of the comparative example, with the differential voltage between the input nodes Nip and Nim in a range of approximately +5.0 V. Note that in this specification, the differential voltage between the input nodes Nip and Nim may be simply referred to as the differential voltage. The negative-side operating range of the voltage detection circuit 1 is the same as that of the comparative example, with the differential voltage in a range of approximately −3.0 V. In other words, the differential input operating range of the voltage detection circuit 1 of this embodiment is in the range of −3.0 V to +5.0 V.

[0114] However, in this embodiment, depletion MOS transistors are used for PMOS 26, which is one of the two PMOSs 26 and 27 that make up maximum selector 23, and NMOS 30, which is one of the two NMOSs 29 and 30 that make up minimum selector 24, so the operating range of selector 13 is wider than in the comparative example. That is, in the comparative example, the operating range on the positive side of the selector is a range equal to or greater than +Vtn, which is, for example, about 0.7 V. Here, Vtn is the threshold value of a normal MOS transistor.

[0115] Therefore, in the comparative example, the Vmin indeterminate range in which the selection signal Vmin output from the minimum selector is indeterminate is the range from -Vtn to +Vtn, that is, the range from -0.7V to +0.7V. As a result, in the comparative example, in the range from -0.7V to +0.7V, the gate voltage of the NMOS of the switch to be turned off becomes higher than the input voltage, causing leakage and reducing accuracy. In contrast, in this embodiment, the positive side operating range of the selector 13 is a range equal to or greater than +Vtd, which is, for example, 0V. Here, Vtd is the threshold value of the depletion MOS transistor.

[0116] Therefore, in this embodiment, the Vmin variable range is the range from −Vtn to +Vtd, that is, the range from −0.7 V to 0 V. As a result, in this embodiment, although there is a risk of leakage occurring in the range from −0.7 V to 0 V because the gate voltage of the NMOS of the switch that is turned off becomes higher than the input voltage, it is possible to prevent leakage from occurring in the range of 0 V or higher, that is, when a positive voltage is input.

[0117] As described above, according to this embodiment, the selector 13 always operates when the differential voltage is approximately 0 V or higher, and it is possible to reduce the decrease in accuracy due to leakage of the MOS transistors that constitute the selector 13 compared to the comparative example. Furthermore, in both the comparative example and this embodiment, the signal transmission range of the NMOS is approximately 0 V to +3.0 V. In the comparative example, since the NMOS is present in the path through which the voltage VINP passes, although the voltage VINP is expected to be approximately +5.0 V at most, it can only pass up to approximately +3.0 V, which narrows the input range of positive voltages.

[0118] In contrast, in this embodiment, since only a PMOS exists in the path through which the voltage VINP passes, the input range of positive voltages can be expanded compared to the comparative example. Furthermore, in this embodiment, since the NMOS exists only in the path through which the voltage VINM passes and only needs to pass 0 V, there is no risk of the input range being narrowed due to the signal transmission range of the NMOS. Although a detailed explanation will be omitted, according to this embodiment, the input range on the PMOS side is also expanded compared to the comparative example by the opposite operation to that on the NMOS side.

[0119] Each of the switches S1 to S4 and SL1 to SL6 includes a series circuit in which two MOS transistors are connected in series, and the back gates of the MOS transistors are connected to the source or drain terminal that is not connected to the intermediate node that is the interconnection node of the two MOS transistors. In this way, the body diodes of the two MOS transistors in the switches S1 to S4 and SL1 to SL6 face each other.

[0120] Therefore, with this configuration, no current flows through the body diode, preventing errors from occurring. In particular, when a large negative voltage is applied, no backflow occurs through the body diode, thereby suppressing the occurrence of errors associated with this. Specifically, the configuration of this embodiment has the following advantage over the comparative example. In the comparative example, when a negative voltage exceeding twice the Vf of the body diode is input, that is, when the differential voltage exceeds "-Vf x 2," the body diode of the switch that should be turned off turns on, causing current to flow and increasing errors.

[0121] That is, in the comparative example, the body diode operating range, which is the range in which the body diode of a switch that should be turned off turns on, is a range of less than or equal to "-Vf x 2." In contrast, in the configuration in which the body diodes are opposed as in this embodiment, the body diode of a switch that should be turned off does not turn on until a negative voltage exceeding the voltage obtained by adding the breakdown voltage BV to the Vf of the body diode is input, that is, until the differential voltage exceeds "-(Vf + BV)."

[0122] That is, in the configuration of this embodiment, the body diode operating range is a range of "-(Vf+BV)" or less, specifically a range of "-8.7 V (=0.7 V+8.0 V)" or less. Therefore, with the configuration of this embodiment, the problem of errors occurring due to backflow through the body diode does not occur in the differential input operating range, that is, in the range where the differential voltage is from -3.0 V to +5.0 V.

[0123] Furthermore, with the above configuration, the body potential of each MOS transistor constituting the switches S1 to S4 for transmitting the input signal voltages VINP and VINM to the subsequent stage can be fixed at the input signal voltages VINP and VINM, which has the advantage of increasing EMC tolerance. Furthermore, with the configuration of this embodiment, the body potential of each MOS transistor constituting the switches S1 to S4 can be fixed, which also has the following advantages.

[0124] That is, if the body potential of each MOS transistor constituting the switches S1 to S4 becomes unstable, there is a risk that the input terminal, body potential, and output terminal of the switch will be coupled together and the CMRR will deteriorate in the switch that is off. However, with the configuration of this embodiment, such a problem does not occur and the CMRR can be maintained at a good level. CMRR is an abbreviation for Common Mode Rejection Ratio. Furthermore, if the body potential of each MOS transistor constituting the switches S1 to S4 becomes unstable, the body potential must be set to the same potential as the signal after the switch is turned on, which requires a wait for settling that may result in a slowdown. However, with the configuration of this embodiment, such a problem does not occur and high speed can be achieved.

[0125] In this embodiment, the capacitive couple driver 14 controls the on / off of each of the switches S1 to S4 and SL1 to SL6 by driving the gates of the MOS transistors 15 to 22 and 41 to 56 via the drive capacitors Cdr1 to Cdr4, which are comb-tooth capacitors. That is, in this embodiment, the switches S1 to S4 and SL1 to SL6 are configured to be capacitively coupled. Furthermore, in this embodiment, the drive capacitors Cdr1 to Cdr4 are configured as comb-tooth capacitors.

[0126] This configuration provides the following advantages. That is, with the above configuration, compared to configurations in which drive capacitances Cdr1 to Cdr4 are configured using parallel plate capacitances, the circuit can be made more compact, and parasitic capacitance with other circuits inside the chip can be reduced, thereby reducing interference. Furthermore, while a capacitive coupled drive configuration emits noise in the sample / hold cycle, configuring drive capacitances Cdr1 to Cdr4 using comb capacitances can increase the drive speed.

[0127] Normally, in a capacitively coupled drive configuration, it is necessary to secure space between other circuits inside the chip or to place a guard ring to avoid noise interference, which inevitably increases the chip area. In contrast, with the above configuration, when high-speed drive is not desired, other circuits can be placed adjacent, which makes it possible to reduce the overall chip area while achieving the desired drive speed.

[0128] The voltage detection circuit 1 including the SC amplifier 2 of this embodiment constitutes part of a battery monitoring IC 5, and more specifically, can be used as a level shift circuit in the battery monitoring IC 5. With this configuration, it is possible to transmit only the differential voltage through the sampling capacitors Cs1 and Cs2, thereby enabling level shifting of the common-mode potential. Furthermore, with this configuration, it is possible to detect signals in a wider range than the power supply voltage or ground potential, both positive and negative.

[0129] Furthermore, by applying the voltage detection circuit 1 to a battery monitoring IC 5, not only can a single IC detect the voltages of multiple battery cells, but it can also detect the voltage of a fuel cell, whose battery cell voltage is negative. According to the configuration of this embodiment, as described above, the input range and detection accuracy of positive voltages can be made comparable to those of a configuration without the selector 13, so the same battery monitoring IC 5 can be used as both a regular battery monitoring IC that monitors lithium-ion batteries and a battery monitoring IC for FCs that monitors fuel cells. In addition, in products such as the battery monitoring IC 5, there is a possibility that a negative voltage may be applied to the IC in the event of a malfunction. However, by applying the voltage detection circuit 1 of this embodiment, signals can be transmitted without error even when a negative voltage is applied, enabling malfunction detection.

[0130] In this case, the voltage detection circuit 1 is provided with the leak cancellation circuit 10, which provides the following effect: The battery monitoring IC 5 has a high output impedance, with the anti-aliasing filters 6a and 6b disposed between the battery cells 4a and 4b to be detected and the AFE included in the battery monitoring IC 5. Even when the voltage detection circuit 1 of this embodiment is applied to such a configuration with high output impedance, the action of the leak cancellation circuit 10 makes it possible to increase the input impedance of the AFE, enabling the voltage of the battery cells 4a and 4b to be detected with high accuracy.

[0131] The switches SL3 and SL6 included in the leakage cancellation circuit 10 are configured by connecting in parallel series circuits SCL3a and SCL6a, each configured with two PMOS transistors connected in series, and series circuits SCL3b and SCL6b, each configured with two NMOS transistors connected in series. With this configuration, the switches SL3 and SL6 can also transmit an intermediate potential, and the operation related to leakage cancellation can be performed at a higher speed than when configured with a single series circuit.

[0132] <Modifications Related to Selector> The configuration of this embodiment can be modified so that low-threshold MOS transistors other than depletion MOS transistors are used as the PMOS 26 included in the maximum selector 23 and the NMOS 30 included in the minimum selector 24. According to such a modification, the selector 13 always operates when the differential voltage is equal to or higher than a voltage corresponding to a threshold lower than the normal threshold, and it is possible to reduce the deterioration in accuracy due to leakage of the MOS transistors that make up the selector 13 compared to the comparative example.

[0133] The configuration of this embodiment can be modified so that low-threshold MOS transistors including depletion MOS transistors are used as the PMOS 27 provided in the maximum selector 23 and the NMOS 29 provided in the minimum selector 24, and normal MOS transistors are used as the PMOS 26 provided in the maximum selector 23 and the NMOS 30 provided in the minimum selector 24.

[0134] According to this modification, the positive-side operating range of selector 13 is equivalent to that of the comparative example, but the negative-side operating range of selector 13 is, for example, a range below +Vtd, which is 0 V. Therefore, in this modification, the Vmin indeterminate range is the range from +Vtd to +Vtn, that is, the range from 0 V to +0.7 V. As a result, in this modification, although there is a risk of leakage occurring because the gate voltage of the NMOS of the switch to be turned off becomes higher than the input voltage in the range from 0 V to +0.7 V, leakage can be prevented in the range below 0 V, that is, when a negative voltage is input. Thus, according to this modification, selector 13 always operates when the differential voltage is approximately 0 V or less, and, compared to the comparative example, it is possible to reduce the deterioration in accuracy due to leakage of the MOS transistors that make up selector 13.

[0135] <Another Application Example of SC Amplifier> The SC amplifier 2 configured as described above can be used as an integrator in a ΔΣ ADC. The ΔΣ ADC is an ADC that includes a ΔΣ modulator 61 as shown in Figure 8 and obtains a high-resolution digital output by passing the output of the ΔΣ modulator 61 through a digital filter (not shown). The ΔΣ modulator 61 employs a type of pulse modulation method and includes an adder 62, an integrator 63, a comparator 64, and a DAC 65.

[0136] The adder 62 outputs a signal obtained by subtracting the output signal of the DAC 65 ​​from the input signal Input. The integrator 63 integrates the output signal of the adder 62 and can be configured using an SC amplifier 2. The comparator 64 binarizes the output signal of the integrator 63. The DAC 65 ​​receives the output signal of the comparator 64 and outputs a signal corresponding to the input. The ΔΣ modulator 61 configured in this manner integrates the input signal Input using the integrator 63, digitally converts the output using the comparator 64, and adds or subtracts from the input signal Input using the DAC 65 ​​according to the output, thereby enabling the output of the comparator 64 to be extracted as a ΔΣ modulated output Output.

[0137] According to the above configuration, the above-described operation shapes the power spectral density distribution of the quantization error output by the comparator 64, i.e., performs noise shaping, thereby improving the dynamic range of the passband. This configuration enables the ADC itself to level-shift the common-mode potential and detect signals in a wider range than the power supply voltage or ground potential, both positive and negative. Furthermore, the above configuration allows for a more compact design than a configuration in which a separate level shifter is provided before the ADC.

[0138] Second Embodiment A second embodiment will be described below with reference to Figures 9 and 10. <Overall Configuration> As shown in Figure 9, an SC amplifier 72 included in a voltage detection circuit 71 of this embodiment differs from the SC amplifier 2 of the first embodiment in that it includes a switch S71 instead of switches S2 and S4. Switch S71 is connected between the second terminal of capacitor Cs1 and the second terminal of capacitor Cs2.

[0139] <Specific Configuration of Switch Circuit> In the above configuration, the multiple switches S1, S3, and S71 connected between the pair of input nodes Nip, Nim and the capacitors Cs1, Cs2, together with the selector 13 and the capacitive couple drive unit 14, constitute a switch circuit 73, which is a CCSW circuit, as shown in FIG. 9. Note that FIG. 9 shows a simplified configuration of the selector 13 and the capacitive couple drive unit 14. The switch circuit 73, including the switches S1, S3, and S71, constitutes part of the SC amplifier 72, and a specific configuration such as that shown in FIG. 10 can be adopted. Note that the leakage cancellation circuit is not shown in FIG. 10.

[0140] The switch S71 is configured by connecting in parallel a series circuit 76 in which two PMOS transistors 74 and 75 are connected in series, and a series circuit 79 in which two NMOS transistors 77 and 78 are connected in series. The source of the PMOS transistor 74 is connected to a node Np, and its drain is connected to a node N71. The drain of the PMOS transistor 75 is connected to the node N71, and its source is connected to a node Nm. The node N71 is an example of an intermediate node that is an interconnection node between the two PMOS transistors 74 and 75.

[0141] The back gate of PMOS 74 is connected to its source. The back gate of PMOS 75 is connected to its source. In other words, the back gates of PMOS 74 and 75 are connected to the source or drain terminal that is not connected to node N71, which is the intermediate node. Between the body and drain of PMOS 74, there is a body diode D74 with the drain side as the anode. Between the body and drain of PMOS 75, there is a body diode D75 with the drain side as the anode.

[0142] That is, in the switch S71, the body diodes D74 and D75 face each other. The gates of the PMOSs 74 and 75 are connected to the capacitive couple driver 14, and are turned on and off by the capacitive couple driver 14. Specifically, the PMOSs 74 and 75 are turned on and off by a drive signal SLSBn.

[0143] The source of NMOS 77 is connected to node Np, and its drain is connected to node N72. The drain of NMOS 78 is connected to node N72, and its source is connected to node Nm. Node N72 is an example of an intermediate node, which is an interconnection node between two NMOSs 77 and 78. The back gate of NMOS 77 is connected to its source. The back gate of NMOS 78 is connected to its source. In other words, the back gates of NMOSs 77 and 78 are connected to the terminal of their source or drain that is not connected to node N72, which is the intermediate node.

[0144] Between the body and drain of NMOS 77, there is a body diode D77 with the body side as the anode. Between the body and drain of NMOS 78, there is a body diode D78 with the body side as the anode. In other words, in switch S71, the body diodes D77 and D78 face each other. The gates of NMOS 77 and 78 are connected to the capacitive couple driver 14, and their on / off switching is controlled by the capacitive couple driver 14. Specifically, the on / off switching of NMOS 77 and 78 is controlled by a drive signal SLSBp.

[0145] The present embodiment described above also achieves the same effects as the first embodiment. The switch S71 is configured by connecting a series circuit 76 of two PMOS transistors 74 and 75 and a series circuit 79 of two NMOS transistors 77 and 78 in parallel, with the back gates of these MOS transistors connected to the source or drain terminal that is not connected to the intermediate node, which is the interconnection node between the two MOS transistors. In this way, the body diodes of the two MOS transistors in the switch S71 also face each other, just like the switches S1 and S3. Therefore, with the configuration of this embodiment, as with the first embodiment, no current flows through the body diodes, eliminating the occurrence of errors.

[0146] Furthermore, this embodiment also provides the following advantages. The configuration of this embodiment has one fewer switch than the configuration of the first embodiment, which allows for a correspondingly smaller size. Furthermore, with the configuration of this embodiment, the operational amplifier 3 and other components are disconnected from the input during hold, thereby increasing the CMRR.

[0147] Furthermore, according to the configuration of this embodiment, the operational amplifier 3 and other components are disconnected from the input during hold, so that the signal in the preceding stage can be switched immediately after sampling is completed. Therefore, according to this embodiment, in a configuration in which a multiplexer is provided in the preceding stage, such as the battery monitoring IC 5 shown in FIG. 2, the overall system speed can be increased.

[0148] Third Embodiment A third embodiment will now be described with reference to FIG. 11. As shown in FIG. 11, a switch circuit 81 of this embodiment differs from the switch circuit 12 of the first embodiment in the configuration of the switches S1 to S4. Note that the leak cancellation circuit is not shown in FIG. 11. In this case, like the switch circuit 12 of the first embodiment, the switches S1 to S4 each include a series circuit configured with two MOS transistors connected in series, but the connection topology of the MOS transistors included in the series circuit is different.

[0149] That is, the switch S1 includes a series circuit SC81 configured with two PMOS transistors 15 and 16 connected in series. The drain of PMOS transistor 15 is connected to the input node Nip, and its source is connected to node N1. The source of PMOS transistor 16 is connected to node N1, and its drain is connected to node Np. In this case, the back gates of PMOS transistors 15 and 16 are connected to the source or drain terminal of the PMOS transistor that is connected to node N1, which is the intermediate node. According to the above configuration, the body diodes D15 and D16 face each other in the switch S1, as in the first embodiment, although the opposing directions are reversed.

[0150] The switch S2 includes a series circuit SC82 configured with two NMOS transistors 17 and 18 connected in series. The drain of NMOS transistor 17 is connected to the input node Nim, and its source is connected to node N2. The source of NMOS transistor 18 is connected to node N2, and its drain is connected to node Np. In this case, the back gates of NMOS transistors 17 and 18 are connected to the terminal of their source or drain that is connected to node N2, which is the intermediate node. According to the above configuration, the body diodes D17 and D18 face each other in the switch S2, as in the first embodiment, although the opposing directions are reversed.

[0151] The switch S3 includes a series circuit SC83 configured with two NMOS transistors 19 and 20 connected in series. The drain of NMOS transistor 19 is connected to the input node Nim, and its source is connected to node N3. The source of NMOS transistor 20 is connected to node N3, and its drain is connected to node Nm. In this case, the back gates of NMOS transistors 19 and 20 are connected to the terminal of their source or drain that is connected to node N3, which is the intermediate node. According to the above configuration, the body diodes D19 and D20 face each other in the switch S3, as in the first embodiment, although the opposing directions are reversed.

[0152] The switch S4 includes a series circuit SC84 in which two PMOS transistors 21 and 22 are connected in series. The drain of PMOS transistor 21 is connected to the input node Nip, and its source is connected to node N4. The source of PMOS transistor 22 is connected to node N4, and its drain is connected to node Nm. In this case, the back gates of PMOS transistors 21 and 22 are connected to the source or drain terminal of the PMOS transistor 21 that is connected to node N4, which is the intermediate node. With the above configuration, the body diodes D21 and D22 of the switch S4 face each other, as in the first embodiment, although the opposing directions are reversed.

[0153] The present embodiment described above also provides the same effects as the first embodiment. Furthermore, the present embodiment also provides the following effect. That is, since the body potentials of the two MOS transistors constituting each of the series circuits SC81 to SC84 are the same, they can be arranged in the same trench, which results in a reduction in the size of the circuit.

[0154] (Other Embodiments) The present disclosure is not limited to the embodiments described above and illustrated in the drawings, and can be modified, combined, or expanded as desired without departing from the spirit of the present disclosure. The numerical values ​​shown in the above embodiments are merely examples, and the present disclosure is not limited to these.

[0155] The selector 13 may be any device that selects one of the voltages VINP and VINM of a pair of input nodes Nip and Nim and outputs a selection signal having a potential corresponding to the selected voltage, and may be configured to include, for example, only one of the maximum selector 23 and the minimum selector 24.

[0156] The drive units 33 and 34 are only required to generate drive signals for driving the gates of the MOS transistors 15 to 22, etc., using the potential of the selection signal output from the selector 13 as a reference potential, and to supply the generated drive signals to the gates of the MOS transistors 15 to 22, etc., and the specific configuration thereof can be changed as appropriate.

[0157] The leakage cancellation circuit 10 may be provided as needed. For example, if the input impedance is low, the leakage cancellation circuit 10 can be omitted, which allows the voltage detection circuit 1 and other components to be implemented in a smaller size.

[0158] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0159] In addition to the inventions described in the claims, the present disclosure also includes the following inventions: [1] A fully differential voltage detection circuit that receives voltages from a pair of input nodes (Nip, Nim), detects a differential voltage between them, and outputs the differential voltage from a pair of output nodes (Nop, Nom), comprising: a plurality of switches (S1 to S4, S71) that are provided between the pair of input nodes and the pair of output nodes and include series circuits (SC1 to SC4, 76, 79) in which two MOS transistors (15 to 22, 74 to 78) are connected in series; and a capacitive couple driver (14) that includes drive capacitors (Cdr1 to Cdr4) and drives the gates of the MOS transistors included in the plurality of switches via the drive capacitors to control the on / off of each of the plurality of switches, wherein the back gates of the MOS transistors are connected to the terminal of the source or drain that is not connected to an intermediate node (N1 to N4, N71, N72) that is an interconnection node between the two MOS transistors. [2] The voltage detection circuit according to [1], wherein the higher potential side of the pair of input nodes is a first input node, the lower potential side of the pair of input nodes is a second input node, a switch of the plurality of switches connected to the first input node is a first switch, and a switch of the plurality of switches connected to the second input node is a second switch, the two MOS transistors of the first switch are both P-channel MOS transistors (15, 16, 21, 22), and the two MOS transistors of the second switch are both N-channel MOS transistors (17, 18, 19, 20).[3] The voltage detection circuit according to [1] or [2] further comprises a differential leakage cancellation circuit (10) that cancels charge leaking from the pair of input nodes due to operation of the plurality of switches, wherein the leakage cancellation circuit comprises: a pair of cancellation input nodes (NLi1 to NLi4) for inputting cancellation charge for canceling the leaking charge; and a plurality of cancellation switches (SL1 to SL6) that are provided so as to be able to open and close between the pair of input nodes and the pair of cancellation input nodes, wherein the plurality of cancellation switches include series circuits (SCL1 to SCL6b) in which two MOS transistors (41 to 56) are connected in series, and the back gates of the MOS transistors are connected to the terminal of their source or drain that is not connected to an intermediate node (NL1 to NL6) that is an interconnection node of the two MOS transistors. [4] The voltage detection circuit according to [3], wherein the high potential side of the pair of input nodes is a first input node, the low potential side of the pair of input nodes is a second input node, the high potential side of the pair of cancel input nodes is a first cancel input node, the low potential side of the pair of cancel input nodes is a second cancel input node, and the cancel switch of the plurality of cancel switches connected between the first input node and the first cancel input node is a first cancel switch, and the cancel switch of the plurality of cancel switches connected between the second input node and the second cancel input node is a second cancel switch, wherein the two MOS transistors of the first cancel switch are both P-channel MOS transistors (41, 42, 49, 50), and the two MOS transistors of the second cancel switch are both N-channel MOS transistors (43, 44, 51, 52).[5] The voltage detection circuit according to [4], wherein a cancel switch connected between the first cancel input node and the second cancel input node among the plurality of cancel switches is defined as a third cancel switch, the third cancel switch is configured by connecting two of the series circuits (SCL3a, SCL3b, SCL6a, SCL6b) in parallel, the two MOS transistors included in one of the two series circuits are both P-channel MOS transistors (45, 46, 53, 54), and the two MOS transistors included in the other of the two series circuits are both N-channel MOS transistors (47, 48, 55, 56). [6] A voltage detection circuit according to [1] or [2], comprising: a selector (13) connected between the pair of input nodes, selecting one of the voltages of the pair of input nodes, and outputting a selection signal having a potential corresponding to the selected voltage; and a drive unit (33, 34) in which the capacitive couple drive unit generates drive signals for driving gates of the MOS transistors provided in the plurality of switches using the potential of the selection signal output from the selector as a reference potential, and supplies the generated drive signals to the gates of the MOS transistors provided in the plurality of switches. [7] The voltage detection circuit according to any one of [3] to [5], further comprising a selector (13) connected between the pair of input nodes, selecting one of the voltages of the pair of input nodes, and outputting a selection signal having a potential corresponding to the selected voltage, wherein the capacitive couple drive unit controls the on / off of each of the plurality of cancel switches by driving the gates of the MOS transistors provided in the plurality of cancel switches via the drive capacitance, and a drive unit (33, 34) that generates drive signals for driving the gates of the MOS transistors provided in the plurality of cancel switches using the potential of the selection signal output from the selector as a reference potential, and supplies the generated drive signals to the gates of the MOS transistors provided in the plurality of cancel switches.[8] The voltage detection circuit according to any one of [1] to [7], further comprising a switched capacitor amplifier (2), wherein the plurality of switches constitute a part of the switched capacitor amplifier. [9] The voltage detection circuit according to any one of [1] to [8], wherein the pair of input nodes are connectable to terminals of each battery cell constituting a battery pack (4), and the plurality of switches constitute a part of a level shift circuit that reduces a relatively high common-mode voltage superimposed on each battery cell (4 a, 4 b) to a relatively low common-mode voltage.

[10] The voltage detection circuit according to any one of [1] to [9], wherein the drive capacitance is a comb capacitance.

Claims

1. A fully differential voltage detection circuit which inputs the respective voltages of a pair of input nodes (Nip, Nim), detects the difference between the voltages, and outputs the difference voltage from a pair of output nodes (Nop, Nom), the voltage detection circuit comprising: a plurality of switches (S1 to S4, S71) which are provided between the pair of input nodes and the pair of output nodes and include a series circuit (SC1 to SC4, 76, 79) in which two MOS transistors (15 to 22, 74 to 78) are connected in series; a capacitive couple driver (14) which has drive capacitances (Cdr1 to Cdr4) and drives the gates of the MOS transistors of the plurality of switches via the drive capacitances to control the on / off of each of the plurality of switches; and a back gate of the MOS transistor which is connected to one of its source or drain terminals which is not connected to an intermediate node (N1 to N4, N71, N72) which is an interconnection node of the two MOS transistors.

2. The voltage detection circuit of claim 1, wherein the higher potential side of the pair of input nodes is a first input node, the lower potential side of the pair of input nodes is a second input node, a switch of the plurality of switches connected to the first input node is a first switch, and a switch of the plurality of switches connected to the second input node is a second switch, the two MOS transistors of the first switch are both P-channel type MOS transistors (15, 16, 21, 22), and the two MOS transistors of the second switch are both N-channel type MOS transistors (17, 18, 19, 20).

3. The voltage detection circuit according to claim 1, further comprising a differential leakage cancellation circuit (10) for canceling charge leaking from the pair of input nodes due to operation of the plurality of switches, the leakage cancellation circuit comprising: a pair of cancellation input nodes (NLi1 to NLi4) for inputting cancellation charge for canceling the leaking charge; and a plurality of cancellation switches (SL1 to SL6) arranged to be able to open and close between the pair of input nodes and the pair of cancellation input nodes, the plurality of cancellation switches including series circuits (SCL1 to SCL6b) in which two MOS transistors (41 to 56) are connected in series, the back gates of the MOS transistors being connected to the terminal of their source or drain that is not connected to an intermediate node (NL1 to NL6) which is an interconnection node of the two MOS transistors.

4. The voltage detection circuit according to claim 3, wherein the high potential side of the pair of input nodes is a first input node, the low potential side of the pair of input nodes is a second input node, the high potential side of the pair of cancel input nodes is a first cancel input node, the low potential side of the pair of cancel input nodes is a second cancel input node, a cancel switch of the plurality of cancel switches connected between the first input node and the first cancel input node is a first cancel switch, and a cancel switch of the plurality of cancel switches connected between the second input node and the second cancel input node is a second cancel switch, 5. A voltage detection circuit as claimed in claim 4, wherein a cancel switch among said plurality of cancel switches connected between said first cancel input node and said second cancel input node is defined as a third cancel switch, said third cancel switch is configured by connecting two of said series circuits (SCL3a, SCL3b, SCL6a, SCL6b) in parallel, said two MOS transistors in one of said two series circuits are both P-channel type MOS transistors (45, 46, 53, 54), and said two MOS transistors in the other of said two series circuits are both N-channel type MOS transistors (47, 48, 55, 56).

6. A voltage detection circuit as described in claim 1 or 2, comprising: a selector (13) connected between the pair of input nodes, selecting one of the voltages of the pair of input nodes, and outputting a selection signal having a potential corresponding to the selected voltage; and a drive unit (33, 34) in which the capacitive couple drive unit generates a drive signal for driving the gates of the MOS transistors provided in the multiple switches using the potential of the selection signal output from the selector as a reference potential, and supplies the generated drive signal to the gates of the MOS transistors provided in the multiple switches.

7. A voltage detection circuit as claimed in any one of claims 3 to 5, further comprising a selector (13) connected between the pair of input nodes, selecting one of the voltages of the pair of input nodes and outputting a selection signal having a potential corresponding to the selected voltage, wherein the capacitive couple drive section controls the on / off of each of the multiple cancellation switches by driving the gates of the MOS transistors included in the multiple cancellation switches via the drive capacitance, and a drive section (33, 34) which generates a drive signal for driving the gates of the MOS transistors included in the multiple cancellation switches using the potential of the selection signal output from the selector as a reference potential and supplies the generated drive signal to the gates of the MOS transistors included in the multiple cancellation switches.

8. The voltage detection circuit according to claim 7, further comprising a switched capacitor amplifier (2), said plurality of switches constituting a part of said switched capacitor amplifier.

9. A voltage detection circuit as described in claim 8, wherein the pair of input nodes are connectable to terminals of each battery cell that constitutes a battery pack (4), and the plurality of switches form part of a level shift circuit that reduces a relatively high common mode voltage superimposed on each of the battery cells (4a, 4b) to a relatively low common mode voltage.

10. The voltage detection circuit according to claim 9, wherein the driving capacitance is a comb capacitance.

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