Disaggregated system architecture for remote data storage and transfer

Abstract

Systems and methods for providing high-bandwidth, low-latency disaggregated computing hardware are disclosed. A system includes a plurality of central processing units (CPUs), a plurality of graphics processing units (GPUs), and a plurality of memory modules. The system includes one or more first application-specific integrated circuits (ASICs) configured to convert electrical signals generated by the plurality of CPUs, the plurality of GPUs, or the plurality of memory modules and conforming to a first protocol (or a second protocol based on the first protocol) to an optical transmission protocol. The first ASICs then transmit signals through an optical network to one or more second ASICs, which convert the signals conforming to the optical transmission protocol to the first protocol or the second protocol. The signals are then transmitted to one or more of the plurality of CPUs, the plurality of GPUs, and / or the plurality of memory modules.

Description

DISAGGREGATED SYSTEM ARCHITECTURE FOR REMOTE DATA STORAGEAND TRANSFERCROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the priority benefit, under 35 U.S.C. 119(e), of U.S. Application No. 63 / 517,022, filed August 1, 2023 and entitled “System Architecture for Network-Based Remote Storage Access of Al Training Server,” U.S. Application No. 63 / 594,251, filed October 30, 2023 and entitled “Optical Network Based Memory Disaggregation Architecture for Next Generation Al Training,” and U.S. Application No. 63 / 597,579, filed November 9, 2023 and entitled “Disaggregate System Architecture for Next Generation Al Inference,” each of which is incorporated herein by reference in its entirety for all purposes.BACKGROUND

[0002] As feature sizes and transistor sizes have decreased for computing hardware such as integrated circuits (ICs) including chips and semiconductor dies, the amount of heat generated by a single chip, such as a microprocessor, has increased. Computing hardware that has traditionally been air cooled has evolved to levels of power consumption requiring more heat dissipation than can be provided by air alone. In some cases, immersion cooling of ICs in a tank containing a coolant liquid is employed to maintain ICs at appropriate operating temperatures.

[0003] One type of immersion cooling is two-phase immersion cooling, in which heat from a semiconductor die is high enough to boil the coolant liquid. The boiling creates a coolantliquid vapor in the tank, which is condensed by cooling coils back to liquid form. Heat from the semiconductor dies can then be sunk into the liquid-to-gas and gas-to-liquid phase transitions of the coolant liquid with the result that the semiconductor dies are kept at an acceptable temperature.

[0004] This improved heat removal capability has led to new computing hardware architectures for increased computational density and has pushed the boundaries of data processing speeds. However, this improvement to data processing speeds has introduced bottlenecks in data transfer speeds; computing hardware can process data faster than the data can be delivered to the computing hardware in the first place. Existing memory access solutions fail to meet thebandwidth and latency requirements of state-of-the-art computing hardware. Further, static ratios of computing hardware (e.g. CPU-to-GPU ratios) may limit how efficiently the computing hardware is used.SUMMARY

[0005] Computing systems, particularly high-end computing systems, generate waste heat as a function of their operation. Server facilities have traditionally dealt with this waste heat by forcing air over the computing systems, often cooling the air first using an air conditioning system. One way of improving the performance of these computing systems is to more efficiently remove this waste heat during operation by immersing the computing systems in a dielectric fluid with a higher thermal conductivity than air. These immersion cooling systems have provided significant improvements to the efficiency of waste heat removal, allowing for increasingly high-performance processes such as the rapid training of large artificial intelligence models using networked GPUs. However, the inventors have recognized and appreciated that in some cases, the increases in computational performance enabled by immersion cooling have outpaced computer architectures responsible for transferring computational results and other data generated by these computing systems.

[0006] In state-of-the-art artificial intelligence (Al) training clusters, inter-component communication plays a major role in overall training performance. In particular, GPU-to- GPU communication and GPU-to- storage communication use high bandwidth and ultra-low latency to meet the demands of training large Al models. However, network architecture supporting high-end Al training clusters and similar computing systems has traditionally required large numbers of ethemet switches and network interface cards, which mean high costs, high power consumption, and poor latency and bandwidth performance.

[0007] Servers containing semiconductor dies such as GPUs are generally interconnected using an ethemet network, which suffers from the drawbacks listed above. Current state-of- the-art GPUs may be limited to a single peripheral component interconnect express (PCIe) gen. 5 port, meaning each GPU may be paired with a single ethernet network interface card (NIC), which may be capable of transmitting a maximum of 400 gigabit per second (Gbps) of data. In a server containing eight GPUs, this means a total data bandwidth of 8^400 Gbps and may be insufficient for training large scale Al systems, particularly when these training systems are composed of thousands of servers.

[0008] Advancements in artificial intelligence (Al) algorithms present significant challenges for Al infrastructure encompassing computing speed, power efficiency, storage capacity, network bandwidth, and more. Due to constraints in physical space and power availability, a limited number of GPUs, CPUs, and memory can be put in each server (and within a single immersion cooling container), which may present a variety of shortcomings. These shortcomings include a fixed ratio of the number of CPUs to the number of GPUs within a server, which may lead to poor resource utilization efficiency.

[0009] Training of large scale Al models such as large language models can consume hundreds of terabytes (TB) or more of memory storage capacity, which can be at least an order of magnitude greater than the storage capacity available on a single server. Local storage such as solid-state drives (SSDs) placed adjacent to the servers (e.g., outside of an immersion cooling container) and accessed using an ethemet-based network may provide a temporary solution; however, this takes up additional on-site space, uses power- and costintensive networking hardware, and may fail to meet desired performance metrics (e.g., bandwidth, latency).

[0010] Further, because space is limited within an immersion cooling container, system memory and storage may be limited, which can cause processing bottlenecks while data is transferred to and from memory modules of limited size. While component disaggregation may be enabled in a rudimentary way using existing technologies, performance losses including high latency, low bandwidth, and low memory availability mean that state-of-the- art Al algorithms such as large language model (LLM) training and inference cannot be utilized using previously existing systems.

[0011] To address some or all of these issues, the present technology includes an optical- network-based disaggregation architecture for next generation Al inference infrastructure. The present technology utilizes one or more optical networks to enable high-bandwidth, low- latency communication between elements within a computing system including one or more central processing units (CPUs), one or more graphics processing units (GPUs), and one or more memory modules.

[0012] In particular, the present technology allows for dynamic assignment of CPUs to a selected number of GPUs and memory modules based on the needs of a given task. Further, the present technology allows for computing tasks to be split up dynamically according to the requirements of the task as well as available resources. This flexibility allows computationalresources to be utilized more efficiently, improves robustness of the computational systems to maintenance and repair requirements, and provides the performance required by modern Al algorithms.

[0013] In some aspects, the techniques described herein relate to a system for disaggregated computing, the system including: a plurality of central processing units (CPUs), the plurality of CPUs configured to assign one or more computing tasks to a plurality of graphics processing units (GPUs), the plurality of CPUs communicatively coupled to the plurality of GPUs through an optical network including a transmission medium; wherein: a latency through the transmission medium and between the plurality of CPUs and the plurality of GPUs is less than 500 nanoseconds; the transmission medium is configured to provide a path for signals dynamically assigning the one or more computing tasks to a first subgroup of the plurality of GPUs based on a workload of at least one of the plurality of GPUs; and both the plurality of CPUs and the plurality of GPUs are communicatively coupled to a plurality of memory modules through the transmission medium.

[0014] In some aspects, the techniques described herein relate to a system, wherein the plurality of CPUs, the plurality of GPUs, and the plurality of memory modules are all disposed within a same ambient environment.

[0015] In some aspects, the techniques described herein relate to a system, wherein: at least a first GPU of the plurality of GPUs is disposed within a first ambient environment; and at least a second GPU of the plurality of GPUs is disposed within a second ambient environment that is different from the first ambient environment.

[0016] In some aspects, the techniques described herein relate to a system, wherein the plurality of GPUs are disposed within a same ambient environment.

[0017] In some aspects, the techniques described herein relate to a system, wherein: at least a first CPU of the plurality of CPUs is disposed within a first ambient environment; and at least a second CPU of the plurality of CPUs is disposed within a second ambient environment that is different from the first ambient environment.

[0018] In some aspects, the techniques described herein relate to a system, wherein the plurality of CPUs are disposed within a same ambient environment.

[0019] In some aspects, the techniques described herein relate to a system, wherein: at least a first memory module of the plurality of memory modules is disposed within a first ambient environment; and at least a second memory module of the plurality of memory modules isdisposed within a second ambient environment that is different from the first ambient environment.

[0020] In some aspects, the techniques described herein relate to a system, wherein the plurality of memory modules are disposed within a same ambient environment.

[0021] In some aspects, the techniques described herein relate to a system, wherein the plurality of GPUs includes 8 or more GPUs.

[0022] In some aspects, the techniques described herein relate to a method for disaggregated computing, the method including: transmitting, through a transmission medium, one or more signals selectively assigning, by one or more central processing units (CPUs), one or more first computing tasks to a first subgroup of graphics processing units (GPUs) from a plurality of GPUs; and transmitting, through the transmission medium, one or more signals selectively assigning, by the one or more CPUs, one or more second computing tasks to a second subgroup of GPUs from the plurality of GPUs; wherein the one or more CPUs are communicatively coupled to the plurality of GPUs through the transmission medium having a latency of less than 500 nanoseconds.

[0023] In some aspects, the techniques described herein relate to a method, wherein: the first subgroup of GPUs is disposed within a first ambient environment; and the second subgroup of GPUs is disposed within a second ambient environment that is different from the first ambient environment.

[0024] In some aspects, the techniques described herein relate to a method, wherein the first subgroup of GPUs and the second subgroup of GPUs are disposed within a same ambient environment.

[0025] In some aspects, the techniques described herein relate to a method, further including: transmitting, through the transmission medium, first data retrieved by the first subgroup of GPUs from a plurality of memory modules; and transmitting, through the transmission medium, second data retrieved by the second subgroup of GPUs from the plurality of memory modules; wherein the plurality of memory modules is disposed in a different ambient environment than the first subgroup of GPUs and the second subgroup of GPUs.

[0026] In some aspects, the techniques described herein relate to a method, further including: transmitting, through the transmission medium, first data retrieved by the first subgroup of GPUs from a plurality of memory modules; and transmitting, through the transmission medium, second data retrieved by the second subgroup of GPUs from the plurality of memorymodules; wherein the plurality of memory modules is disposed in a same ambient environment as at least one of the first subgroup of GPUs and the second subgroup of GPUs.

[0027] In some aspects, the techniques described herein relate to a method, wherein: at least a first memory module of the plurality of memory modules is disposed within a first ambient environment; and at least a second memory module of the plurality of memory modules is disposed within a second ambient environment that is different from the first ambient environment.

[0028] In some aspects, the techniques described herein relate to a method, wherein the first subgroup of GPUs is distinct from the second subgroup of GPUs.

[0029] In some aspects, the techniques described herein relate to a method, wherein the one or more CPUs, the plurality of GPUs, and a plurality of memory modules are all disposed within a same ambient environment.

[0030] In some aspects, the techniques described herein relate to a method, wherein the plurality of GPUs are disposed within a same ambient environment.

[0031] In some aspects, the techniques described herein relate to a method, wherein the one or more CPUs are disposed within a same ambient environment.

[0032] In some aspects, the techniques described herein relate to a method, wherein the plurality of GPUs includes 8 or more GPUs.

[0033] In some aspects, the techniques described herein relate to a system for computer networking, the system including: an optical network including a transmission medium; wherein: a central processing unit (CPU) and at least one graphics processing unit (GPU), both disposed on a server, are configured to communicate with each other using a first communication protocol through the transmission medium; a memory is configured to communicate, through the transmission medium, with at least one of the CPU and the at least one GPU using a second communication protocol based on the first protocol; and an application specific integrated circuit (ASIC) is configured to convert a first signal, transmitted through the transmission medium and based on the first communication protocol or the second communication protocol, into a second signal based on a third communication protocol.

[0034] In some aspects, the techniques described herein relate to a system, wherein: the server is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.

[0035] In some aspects, the techniques described herein relate to a system, wherein the server and the memory are located within a same ambient environment.

[0036] In some aspects, the techniques described herein relate to a system, wherein: the first communication protocol includes a peripheral component interconnect express (PCIe) protocol; the second communication protocol includes a compute express link (CXL) protocol; and the third communication protocol includes a photonic protocol.

[0037] In some aspects, the techniques described herein relate to a system, wherein a latency between the memory and at least one of the CPU and the at least one GPU is 100 nanoseconds or less.

[0038] In some aspects, the techniques described herein relate to a method for computer networking, the method including: transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a first communication protocol or a second communication protocol; transmitting, through a transmission medium, a second signal conforming to a third communication protocol after converting, by a first application-specific integrated circuit (ASIC), the first signal to the second signal; transmitting, through the transmission medium, the second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted; transmitting, through the transmission medium, the third signal conforming to at least one of the first communication protocol or the second communication protocol to a memory upon converting, by the second ASIC, the second signal to the third signal.

[0039] In some aspects, the techniques described herein relate to a method, further including storing, by the memory, information represented by the third signal.

[0040] In some aspects, the techniques described herein relate to a method, wherein: the semiconductor die is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.

[0041] In some aspects, the techniques described herein relate to a method, wherein the semiconductor die and the memory are located within a same ambient environment.

[0042] In some aspects, the techniques described herein relate to a method, wherein: the first communication protocol includes a peripheral component interconnect express (PCIe) protocol; the second communication protocol includes a compute express link (CXL) protocol; and the third communication protocol includes a photonic protocol.

[0043] In some aspects, the techniques described herein relate to a method for computer networking, the method including: transmitting, through a transmission medium, a first signal conforming to at least one of a first communication protocol or a second communication protocol, the first signal generated at a memory; transmitting, through the transmission medium, a second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted, wherein the second signal is transmitted upon conversion, by a first application-specific integrated circuit (ASIC), the first signal to a second signal conforming to a third communication protocol; transmitting, through the transmission medium, the third signal to a semiconductor die upon conversion, by the second ASIC, the second signal to a third signal conforming to at least one of the first communication protocol or the second communication protocol.

[0044] In some aspects, the techniques described herein relate to a method, wherein: the semiconductor die is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.

[0045] In some aspects, the techniques described herein relate to a method, wherein the semiconductor die and the memory are located within a same ambient environment.

[0046] In some aspects, the techniques described herein relate to a method, wherein: the first communication protocol includes a peripheral component interconnect express (PCIe) protocol; the second communication protocol includes a compute express link (CXL) protocol; and the third communication protocol includes a photonic protocol.

[0047] In some aspects, the techniques described herein relate to a system for computer networking, the system including: a memory including an application-specific integrated circuit (ASIC) configured to convert signals between: at least one of a peripheral component interconnect express (PCIe) or a compute express link (CXL) protocol; and an ethemet protocol; a plurality of servers, each of the plurality of servers including: at least one semiconductor die; and a server ASIC configured to convert signals between: the PCIe or the CXL protocol; and an ethernet protocol; and an optical switching network including a transmission medium communicatively coupling the memory to the plurality of servers.

[0048] In some aspects, the techniques described herein relate to a method of transmitting information within a computer network, the method including: transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a peripheral component interconnect express (PCIe) or a compute express link(CXL) protocol; transmitting a second signal, through the transmission medium, upon converting the first signal to the second signal conforming to an RDMA over Converged Ethernet v2 (RoCEv2) protocol, the second signal converted by a first bridge and transmitted to a remote memory and received by the remote memory less than 200 nanoseconds after the second signal is transmitted; converting, by a second bridge, the second signal to a third signal conforming to at least one of the PCIe or the CXL protocol; and storing information represented by the third signal on the remote memory.

[0049] All combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are part of the inventive subject matter disclosed herein. The terminology used herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0051] FIG. 1 illustrates a system for the networking and connection of servers used for Al training and data storage.

[0052] FIG. 2 illustrates a system for providing an improved networking architecture for servers used in Al training and data storage.

[0053] FIG. 3 illustrates a networking system including disaggregated memory in accordance with the present technology.

[0054] FIG. 4 illustrates a disaggregated computing system in accordance with the present technology.

[0055] FIG. 5 illustrates an exemplary system architecture in accordance with the present technology.

[0056] FIG. 6 is a flowchart of an example method for disaggregated computing.

[0057] FIG. 7 is a flowchart of an example method for computer networking.

[0058] FIG. 8 is a flowchart of an example method for computer networking.

[0059] FIG. 9 is a flowchart of an example method for transmitting information within a computer network.

[0060] FIG. 10 depicts aspects of an immersion cooling system for dissipating heat from one or more heat-generating components such as semiconductor die packages via immersion cooling.DETAILED DESCRIPTION

[0061] The present technology includes systems and methods for high-speed computational networking architecture as well as data storage and transfer. Optical networks in accordance with the present technology enable ultra-low latency and high bandwidth for inter-GPU communication, remote storage and memory access, and dynamic assignment of computing components including CPUs and GPUs based on computing tasks to be performed, as well as available computational resources, power, and thermal dissipation.1. Ethernet-Based Switching Network

[0062] FIG. 1 illustrates a system 100 for the networking and connection of servers used for Al training and data storage. System 100 may include a remote storage service 110, front-end network 120 and back-end network 130, and servers 140a and 140b. Servers 140a and 140b may be communicatively coupled to storage service 110 through front-end network 120. Front-end network 120 may also provide communication between servers 140a and 140b and the Internet, as well as between server 140a and server 140b.

[0063] Front-end network 120 may include network components 125. Network components 125 may include one or more routers, one or more switches, one or more cables, one or more network interface controllers, one or more gateways, one or more hubs, one or more models, and the like. Back-end network 130 may include network components 135 analogous to network components 125. Back-end network 130 may differ from front-end network 120 inthat it is physically and / or logically isolated from front-end network 120 or any outside networks such as the Internet. Back-end network 130 may be particularly designed for high bandwidth and low latency; in some embodiments, back-end network 130 may have higher bandwidth capabilities and lower latency than front-end network 120.

[0064] Servers 140a and 140b may include several internal components allowing the servers to complete complex networked tasks such as training large Al models using remotely-stored training data. In an embodiment, server 140a includes GPUs 142a, 142b, and 142c. Server 140a may include additional GPUs. In alternative or additional embodiments, elements 142a- c may each be a semiconductor die such as a microprocessor (e.g., a central processing unit (CPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an ASIC, field-programmable gate array (FPGA), and / or other densely patterned semiconductor die.

[0065] Communication between GPUs (or similar semiconductor dies) 142a-c may be enabled by Interconnection layer 144a, which may be purpose built to allow for the highest possible bandwidth and lowest possible latency communication between GPUs on a single server while minimizing component complexity. Interconnection layer 144a may utilize copper wire, optical waveguides, or similar materials to enable the high speed and throughput desired for computationally intensive tasks.

[0066] Connections between GPUs 142a-c and network components such as PCIe / CXL to ethernet bridge 246a, NICs, and SSDs may be enabled by PCIe layer 146a, for instance implemented on one or more motherboards or printed circuit boards (not shown). PCIe layer 146a may utilize the PCIe serial expansion bus standard for linking GPUs 142a-c with other electronic components including local storage 150a, one or more front-end network interface card(s) (NIC(s)) 154a, and one or more back-end network interface card(s) 158a. In an embodiment, front-end network interface card 154a may provide connectivity between server 140a, GPUs 142a-c, and front-end network 120. Likewise, in an embodiment, back-end network interface card(s) 158a may provide a communicative connection between server 140a, GPUs 142a-c, and back-end network 130 (as well as other devices and platforms connected to back-end network 130 such as server 140b).

[0067] Servers 140a may further include local storage 150a. Local storage 150a may be used for process-specific data storage (such as storing Al training data or computational result data) as well as basic GPU functionality such as operating system software. However, thisshared functionality can reduce efficiency and data throughput; for example, data storage and retrieval for Al training computations may be delayed while the server retrieves and updates low-level GPU operational data for standard processes such as clearing a cache or downloading a software update. Further, local storage 150a may have significantly limited capacity compared to storage service 110. For example, local storage 150a may have about 500 gigabytes (GB) to about 10 terabytes (TB) of storage, whereas storage service 110 may have hundreds of (petabytes) PB or even exabytes (EB) of storage capacity or more.

[0068] Server 140b is analogous to server 140a and includes components analogous to those discussed with respect to server 140a including GPUs or similar semiconductor dies 142d-f, Interconnection layer 144b, PCIe layer 146b, local storage 150b, one or more front-end network interface card(s) 154b, and one or more back-end network interface card(s) 158b.

[0069] The components of system 100 are meant to be exemplary and do not indicate that system 100 is limited to only the instances of elements shown in FIG. 1. System 100 may include additional storage services, front- and back-end networks, and servers. For example, system 100 may include one or more additional servers analogous to 140a and 140b, each additional server including some or all of the internal components illustrated within servers 140a and 140b.

[0070] The networking architecture illustrated in FIG. 1 has several disadvantages as discussed above. In particular, the network interface cards and front- and back-end networks (including components such as ethemet switches) are expensive to install and maintain and consume significant amounts of power, which adds additional and undesirable cost to the implementation and operation of system 100. Each additional component within a network is a potential failure point, may be a source of latency and bandwidth inefficiencies, and may introduce additional heat to temperature-sensitive environments.2. Optical Switching Network

[0071] FIG. 2 illustrates a system 200 that provides an improved networking architecture for servers used in Al training and data storage. System 200 may include remote memory 210 communicatively connected by way of optical switching network 220 to one or more servers 240a-c. Remote memory 210 may provide flexible, high-speed, distributed memory for on- demand processing such as ingesting large training data sets for training machine learning models.

[0072] Remote memory 210 may be embodied in a variety of architectures including pooled memory - e.g., “just a bunch of disks,” (JBOD), “just a bunch of memory,” (JBOM), “just a bunch of flash”, (JBOF) - with multiple disk drives or memory modules used individually or as a single logical volume. In an embodiment, remote memory 210 may be embodied in a RAID (redundant array of independent disks) architecture, where a plurality of storage disks are treated as a single logical volume with configurable data redundancy and storage protocols such as data striping, data parity, and / or data mirroring. Remote memory 210 may be a cloud storage service located in a geographically distinct area from optical switching network 220 and servers 240a-c, or may be co-located with optical switching network 220 and servers 240a-c.

[0073] Remote memory 210 may include PCIe / CXL switch 214 and PCIe / CXL to ethernet bridge 216. PCIe / CXL switch 214 may be used to transmit and receive data in the form of PCIe and / or CXL packets (equivalently, signals) from PCIe / CXL to ethernet bridge 216 and forward those packets to physical memory modules (not shown) that make up remote memory 210. PCIe / CXL switch 214 may transmit and receive PCIe and / or CXL packets from PCIe / CXL to ethernet bridge 216 after PCIe / CXL to ethernet bridge 216 has converted received ethernet packets to PCIe or CXL signals conforming to the PCIe or CXL protocol. PCIe / CXL to ethernet bridge 216 may be an ASIC designed specifically for high-speed and low latency conversion of PCIe / CXL signals to ethernet signals such as RDMA over Converged Ethernet v2 (RoCEv2). RoCEv2 is an internet layer protocol allowing for the transmission, receipt, and routing of signals in switching networks such as optical switching network 220.

[0074] Optical switching network 220 may be configured to provide ultra-high speed packet routing and transmission between remote memory 210 and any or all of servers 240a-c as well as inter-server communication between servers 240a-c. Optical switching network 220 may provide latencies as low as hundreds or tens of nanoseconds with much lower power usage and higher bandwidth when compared to system 100 with plural front- and back-end networks as well accompanying network interface cards. In an embodiment, optical switching network may transmit signals from any or all of servers 240a-c to remote memory 210 with less than 200 nanoseconds of latency. In an embodiment, signals may be transmitted between any two components within system 200 with less than 200 nanoseconds of latency. Accordingly, optical switching network 220 may perform some or all of the functionality of front-end network 120 or back-end network 130, as well as enabling the replacement oflimited local storage 150a and 150b with the much larger and more easily configurable remote memory 210 with no reduction in performance of bandwidth and latency. Optical switching network 220 may include a transmission medium through which signals may be transmitted and / or propagated. A transmission medium may include one or more fiber optic cables, glass, plastic, guided pathways, unguided pathways, or any suitable medium.

[0075] Servers 240a-c perform functions analogous to those performed by servers 140a-b in FIG. 1. Server 240a is an exemplary embodiment of a server used in accordance with the present technology, for instance, as a high-performance Al training server. Server 240a may include GPUs 242a, 242b, and 242c. Server 240a may include additional GPUs. In alternative or additional embodiments, elements 242a-c may each be a semiconductor die such as a microprocessor (e.g., a central processing unit (CPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an ASIC, field- programmable gate array (FPGA), logic integrated circuit (IC), and / or other densely patterned semiconductor die.

[0076] Similarly to FIG. 1, communication between GPUs (or similar semiconductor dies) 242a-c may be enabled by interconnection layer 244a, which may be purpose built to allow for the highest possible bandwidth and lowest possible latency communication between GPUs on a single server while minimizing component complexity. Interconnection layer 244a may utilize copper wire, optical waveguides, or similar materials to enable the desired speed and throughput for computationally intensive tasks.

[0077] GPUs 242a-c may be configured to communicate with other devices using the PCIe and / or CXL protocols, and accordingly may utilize PCIe / CXL to ethemet bridge 246a, which may be similar to or the same as PCIe / CXL to ethernet bridge 216 in remote memory 210. This allows for GPUs 242a-c to be connected directly to optical switching network 220, which allows for back-end network 130 to be replaced with optical switching network 220 and eliminates the need for separate network interface cards such as 154a-b and 158a-b. This allows for reduced initial and maintenance costs, as well as providing improved power efficiency, greater bandwidth, and lower latency as compared to system 100 or prior art systems.

[0078] Servers 240b and 240c may be the same or substantially identical to server 240a. Interconnection layer 244b and interconnection layer 244c may be the same or substantially the same as interconnection layer 244a. PCIe / CXL to ethernet bridges 246b and 246c may bethe same or substantially the same as PCIe / CXL to ethernet bridges 216 and 246a. In an embodiment, system 200 may include more than three or fewer than three servers. System 200 may include servers with substantially the same components as those illustrated in servers 240a-c in FIG. 2, or may include servers with additional components such as additional GPUs, additional or alternative semiconductor dies as discussed above, or additional components not explicitly depicted in FIG. 2.3. Optical Network Including Optical Switches

[0079] FIG. 3 illustrates a networking system including disaggregated memory in accordance with the present technology. System 300 may include one or more servers 310a and 310b. Servers 310a-b may be configured to perform computationally intensive tasks such as training Al models including LLMs. Servers 3 lOa-b may include one or more CPUs 312a-b, one or more GPUs 314a-b, switches 316a-b, and one or more optical switch / electrical integrated circuits (EICs) 318a-b. Servers 310a-b may be communicatively coupled to one or more remote memory (also referred to herein as memory module) 340a-c through optical network 320. A network path between servers 3 lOa-b and remote memories 340a-c may include one or more signal conversion integrated circuits including optical switch / EIC 318a- b, optical switch / EIC 338, compute express link (CXL) switch 332, and / or switch application-specific integrated circuit (ASIC) 330. One or more of switch 316a-b, optical switch / EIC 318a-b, CXL switch 332, and / or optical switch / EIC 338 may be combined into a single multi-purpose ASIC such as switch ASIC 330. Optical network 320 may include a transmission medium through which signals may be transmitted and / or propagated. A transmission medium may include one or more fiber optic cables, glass, plastic, guided pathways, unguided pathways, or any suitable medium.

[0080] Servers 3 lOa-b may be GPU servers configured to perform Al training and / or inference or other high-computational -intensity tasks. Servers 310a-b may include CPUs 312a-b. CPUs 312a-b may be configured as head nodes for controlling operations of servers 310a-b including running operating system software, GPU task management / allocation, resource management (such as memory allocation, GPU clustering, etc.), firmware installation and updates, temperature and power management, networking, and the like.

[0081] GPUs 314a-b may include one or more GPUs configured to perform high- computational intensity tasks such as Al model / LLM training, Al model / LLM inference, video processing, or similar computational tasks. GPUs 314a and 314b may each include oneor more GPUs; for example, GPUs 314a and 314b may each represent clusters of 2 or more GPUs, 4 or more GPUs, 6 or more GPUs, 8 or more GPUs, 16 or more GPUs, 32 or more GPUs, 64 or more GPUs, or any suitable number of GPUs. Each of a plurality of GPUs on servers 310a and 310b may be connected to one another using any suitable interconnect protocol such as NVIDIA® NvLink®, AMD XGMI, or RDMA over Converged Ethernet v2 (RoCEv2). Signals sent and received between CPUs 312a-b, GPUs 314a-b, and other elements communicatively coupled to CPUs 312a-b and GPUs 314a-b may communicate using one or more protocols based on non-return-to-zero (NRZ) signals and / or pulse amplitude modulation 4-level (PAM4) signals; for example, PCIe 5 (NRZ), PCIe 6 (PAM4), and / or CXL (NRZ or PAM4) protocols.

[0082] Each GPU included in GPU 314a and 314b may be communicatively coupled with switch 316a and 316b respectively. Each GPU included in GPU 314a and 314b may include one or more CXL ports for inter-GPU communication and / or communication with switches 316a and 316b respectively. GPUs 314a and 314b may be communicatively coupled with CPUs 312a and 312b respectively using a PCIe protocol.

[0083] Optical switches / EICs 318a, 318b, and 338 may be configured to convert signals based on NRZ (PCIe 5, CXL) and / or PAM4 (PCIe 6, CXL) to photonic or optical signals and vice versa for transmission through optical network 320. Optical switches / EICs 318a, 318b, and 338 may additionally or alternatively include one or more photonic integrated circuits (PICs) configured to generate signals conforming to a photonic transmission protocol. Optical switches / EICs 318a, 318b, and 338 may be embodied as a single ASIC. Optical switches included in optical switches / EICs 318a, 318b, and 338 may allow for point-to-point connectivity between optical switch ports. Each of optical switches / EICs 318a, 318b, and 338 may be connected to one another directly (e.g., through fiber-optic cabling) or may be communicatively coupled to one another through optical network 320.

[0084] Optical network 320 may be configured to provide ultra-high speed packet routing and transmission between remote memory 340a-c and any or all of servers 3 lOa-b as well as inter-server communication between servers 310a-b. Optical network 320 may provide latencies between elements of system 300 as low as hundreds or tens of nanoseconds with much lower power usage and higher bandwidth when compared to network fabrics requiring plural front- and back-end networks as well accompanying network interface cards.

[0085] In an embodiment, optical switching network may transmit signals from any or all of servers 310a-b to remote memory 340a-c with less than 100 nanoseconds of latency. Remote memory 340a-c may subsequently store information included in these signals. This information may later be retrieved from memory 340a-c and transmitted to servers 3 lOa-b or to another suitable storage or computation element. In an embodiment, signals may be transmitted between any two components within system 400 with less than 100 nanoseconds of latency, including less than 100 nanoseconds of latency. Accordingly, optical network 320 enables the replacement of limited local storage on servers 3 lOa-b with the much larger and more easily configurable remote memory 340a-c with no reduction in performance of bandwidth and latency.

[0086] Remote memory 340a-c may be embodied in a variety of architectures including pooled memory - e.g., “just a bunch of disks,” (JBOD), “just a bunch of memory,” (JBOM), “just a bunch of flash”, (JBOF) - with multiple memory modules, disk drives, etc., used individually or as a single logical volume. In an embodiment, remote memory 340a-c may be embodied in a RAID (redundant array of independent disks) architecture, where a plurality of storage disks are treated as a single logical volume with configurable data redundancy and storage protocols such as data striping, data parity, and / or data mirroring.

[0087] Remote memory 340a-c may be a cloud storage service located in a geographically distinct area from optical network 320 and servers 3 lOa-b, or may be co-located with optical network 320 and servers 310a-b. In an embodiment, remote memory 340a-c may be located in the same ambient environment as servers 310a-b (e.g., located within the same immersion cooling tank, located within the same datacenter, located within the same data rack, etc.) or may be located within a different ambient environment (e.g., servers 3 lOa-b may be located inside of an immersion cooling tank and remote memory 340a-c may be located outside of the immersion cooling tank, servers 3 lOa-b may be located in a first building or datacenter and remote memory 340a-c may be located in a second building or datacenter, etc.).

[0088] Remote memory 340a-c may be communicatively coupled to optical network 320 and servers 310a-b through CXL switch 332 and optical switch / EIC 338. CXL switch 332 may be configured to transmit data packets and / or signals using the CXL or related protocol (such as peripheral component interconnect express [PCIe]). CXL switch 332 may be used to transmit and receive data in the form of PCIe and / or CXL packets (equivalently, signals) from optical switch / EIC 338 and forward those packets to remote memory 340a-c. CXL switch 332 may transmit and receive PCIe and / or CXL packets from optical switch / EIC 338 after opticalswitch / EIC 338 has converted received optical packets to PCIe or CXL signals conforming to the PCIe or CXL protocol. Optical switch / EIC 338 may be an ASIC designed specifically for high-speed and low latency conversion of PCIe / CXL signals to photonic signals and vice versa.4. Dynamically Grouping Disaggregated GPUs

[0089] FIG. 4 illustrates a disaggregated computing system 400 in accordance with the present technology. System 400 may include at least one central processing unit (CPU) server 410 including one or more CPUs 450a-b, optical network 420, switch application-specific integrated circuits (ASICs) 430a-c, memory modules 440a-c, and GPUs 460a-c. Each of switch ASICs 430a-c may include one or more CXL switches (e.g., CXL switches 432a-c) and optical switches / electronic integrated circuits (optical switch / EIC 438a-c). Optical network 420 may include a transmission medium through which signals may be transmitted and / or propagated. A transmission medium may include one or more fiber optic cables, glass, plastic, guided pathways, unguided pathways, or any suitable medium.

[0090] Components of disaggregated computing system 400 may be co-located, such as within an immersion cooling tank, or may be dispersed to a plurality of locations such as a plurality of racks or immersion cooling tanks. For example, CPU server 410, optical network 420, ASICs 430a-b, memory modules 440a-c, and GPUs 460a-c may be co-located within a single immersion cooling tank. In an embodiment, CPU server 410 and GPUs 460a-c may be located in a first immersion cooling tank, while optical network 420, ASICs 430a-b, and memory modules 440a-c may be located outside of the first immersion cooling tank. In an embodiment, CPU server 410 and GPUs 460a-c may be located in a first immersion cooling tank, optical network 420 and ASICs 430a-b may be located outside of the first immersion cooling tank, and memory modules 440a-c may be located within a second immersion cooling tank.

[0091] In an embodiment, memory modules 440a-c, CPUs 450a-c, and GPUs 460a-c may be located in the same ambient environment (e.g., located within the same immersion cooling tank, located within the same datacenter, located within the same data rack, etc.). Alternatively, one or more of memory modules 440a-c, CPUs 450a-c, and GPUs 460a-c may be located within a different ambient environment (e.g., CPUs 450a-c and GPUs 460a-c may be located inside of an immersion cooling tank and memory modules 440a-c may be located outside of the immersion cooling tank, CPUs 450a-c and GPUs 460a-c may be located in afirst building or datacenter and memory modules 440a-c may be located in a second building or datacenter, etc.). In an embodiment, CPU 450a, GPU 460a, and memory module 440a may be located within a first ambient environment; CPU 450b, GPU 460b, and memory module 440b may be located within a second ambient environment; and CPU 450c, GPU 460c, and memory module 440c may be located within a third ambient environment. CPUs 450a-c, GPUs 460a-c, and memory modules 440a-c may be distributed in any suitable combination of ambient environments.

[0092] Disaggregated computing system 400 may include at least one CPU server 410. CPUs 450a-c included in CPU server 410 may be configured as head nodes for controlling operations of GPUs 460a-c including running operating system software, GPU task management / allocation, resource management (such as memory allocation, GPU clustering, etc.), temperature and power management, networking, and the like. CPU server 410 may include one or more CPUs such as CPUs 450a-c. CPUs 450a-c may include 4 or more CPUs, 6 or more CPUs, 8 or more CPUs, 10 or more CPUs, 16 or more CPUs, 20 or more CPUs, 24 or more CPUs, 48 or more CPUs, 64 or more CPUs, or any suitable number of CPUs. Each CPU 450a-c may be communicatively coupled with all other CPUs in CPU server 410 and / or disaggregated computing system 400. GPUs 460a-c may include 4 or more GPUs, 8 or more GPUs, 16 or more GPUs, 32 or more GPUs, 64 or more GPUs, 128 or more GPUs, or any suitable number of GPUs. The communicative coupling may be in series, in parallel, or a combination of both series and parallel.

[0093] Optical network 420 may be configured to provide ultra-high speed packet routing and transmission between CPU server 410, memory modules 440a-c, and any or all of GPUs 460a-c as well as inter-GPU communication between GPUs 460a-c, memory modules 440a- c, or additional CPU servers 410. Optical network 420 may provide latencies between elements of system 400 as low as hundreds or tens of nanoseconds with much lower power usage and higher bandwidth when compared to network fabrics requiring plural front- and back-end networks as well accompanying network interface cards.

[0094] In an embodiment, optical switching network may transmit signals between any or all of CPU server 410, memory modules 440a-c, and GPUs 460a-c with less than 500 nanoseconds of latency. Memory modules 440a-c may store, retrieve, update, alter, create, or remove information included in these signals. This information may later be retrieved from memory modules 440a-c and transmitted to GPUs 460a-c or to another suitable storage or computation element. In an embodiment, signals may be transmitted between any twocomponents within system 400 with less than 300 nanoseconds of latency, including less than 100 nanoseconds of latency. Accordingly, optical network 420 enables the replacement of limited local storage on CPU server 410 with the much larger and more easily configurable memory modules 440a-c with no reduction in performance of bandwidth and latency. Further, this allows GPUs 460a-c to be grouped and located more flexibly such that power and latency is reduced while bandwidth and computational densities are increased.

[0095] Optical switches / EICs 438a-c may be configured to convert signals based on NRZ (PCIe 5, CXL) and / or PAM4 (PCIe 6, CXL) to photonic or optical signals and vice versa for transmission through optical network 420. Optical switches / EICs 438a-c may additionally or alternatively include one or more photonic integrated circuits (PICs) configured to generate signals conforming to a photonic transmission protocol. Optical switches / EICs 438a-c may each be embodied as a single ASIC such as any of ASICs 430a-c containing both switch and EIC functionality. Optical switches included in optical switches / EICs 438a-c may allow for point-to-point connectivity between optical switch ports. Each of optical switches / EICs 438a- c may be connected to one another directly (e.g., through fiber-optic cabling) or may be communicatively coupled to one another through optical network 420.

[0096] One or more CPU subgroups of CPUs 450a-c may be communicatively coupled dynamically with a memory subgroup of memory modules 440a-c and / or a GPU subgroup of GPUs 460a-c. For example, CPUs 450a may be communicatively coupled with GPUs 460a-b and memory module 440a-b to control a first computational task (such as a first LLM inference task) being performed by GPUs 460a-b and utilizing data stored on memory module 440a-b. Additionally or alternatively, CPUs 450b-c may be communicatively coupled to GPU 460c and memory module 440c to control a second computational task (such as a second LLM inference task) being performed by GPU 460c and utilizing memory module 440c. The communicative coupling may be in series, in parallel, or a combination of both series and parallel.

[0097] A subgroup of CPUs 450a-c may distribute, divide, and / or assign tasks to one or more GPUs, which may be a subgroup of a plurality of GPUs 460a-c. One or more tasks may be distributed partially or wholly to one or more GPUs. Multiple tasks may be distributed, divided, or assigned to a single GPU. For example, CPU 450a may distribute, divide, or assign two or more Al inference tasks to GPU 460a to be executed substantially simultaneously by assigning the two or more tasks to different groups of cores within GPU 460a.

[0098] Additionally or alternatively, CPUs 450a-c may assign a single task to a plurality of GPUs 460a-c. For example, CPU 450b may assign a single LLM inference task to GPUs 450a-b such that the single LLM inference task is split between GPUs 450a-b.5. Networked Components Distributed by Cooling Container

[0099] FIG. 5 illustrates an exemplary system architecture in accordance with the present technology. In particular, system 500 may include analogous elements to that of disaggregated computing system 400, with one or more components disposed within a first immersion cooling tank 502, one or more additional components disposed within a second immersion cooling tank 504, and optical network 520 disposed externally to both first immersion cooling tank 502 and second immersion cooling tank 504. Optical network 520 may include a transmission medium through which signals may be transmitted and / or propagated. A transmission medium may include one or more fiber optic cables, glass, plastic, guided pathways, unguided pathways, or any suitable medium.

[0100] First immersion cooling tank 502 may include memory modules 540a-c disposed within first immersion cooling tank 502 and communicatively coupled to switch ASIC 530a. ASIC 530a may include CXL switch 532a and optical switch / EIC 538a. Second immersion cooling tank 504 may include CPU server 510, switch ASIC 530b and switch ASIC 530c, and GPUs 560a-h. Switch ASIC 530b may include CXL switch 532b and optical switch / EIC 538b. Switch ASIC 530c may include CXL switch 532c and optical switch / EIC 538c. Switch ASIC 530c may be included in CPU server 510, and CPU server 510 may further include CPUs 550a-c. CPUs 550a-c may be communicatively coupled to GPUs 560a-h and memory module 540a-c through optical network 520 and switch ASIC 530c. The communicative coupling may be in series, in parallel, or a combination of both series and parallel.

[0101] First immersion cooling tank 502 may further include GPUs 560a-h, which are communicatively coupled to memory module 540a-c and CPUs 550a-c through switch ASIC 53b. One or more of GPUs 560a-h may be assigned computing tasks by one or more of CPUs 550a-c.

[0102] In an embodiment, memory module 540a-c, CPUs 550a-c, and GPUs 560a-h may be located in the same ambient environment (e.g., located within the same immersion cooling tank, located within the same datacenter, located within the same data rack, etc.). Alternatively, one or more of memory module 540a-c, CPUs 550a-c, and GPUs 560a-c may be located within a different ambient environment (e.g., CPUs 550a-c and GPUs 560a-h maybe located inside of an immersion cooling tank and memory module 540a-c may be located outside of the immersion cooling tank, CPUs 550a-c and GPUs 560a-d may be located in a first building or datacenter and GPUs 560e-h and memory module 540a-c may be located in a second building or datacenter, etc.). In an embodiment, CPU 550a, GPUs 560a-c, and memory module 540a may be located within a first ambient environment; CPU 550b, GPUs 560d-f, and memory module 540b may be located within a second ambient environment; and CPU 550c, GPUs 560g-h, and memory module 540c may be located within a third ambient environment. CPUs 550a-c, GPUs 560a-h, and memory modules 540a-c may be distributed in any suitable combination of ambient environments.

[0103] One or more CPU subgroups of CPUs 550a-c may be communicatively coupled dynamically with a memory subgroup of memory modules 540a-c and / or a GPU subgroup of GPUs 560a-h. For example, CPUs 550a may be communicatively coupled with GPUs 560a-b and memory modules 540a-b to control a first computational task (such as a first LLM inference task) being performed by GPUs 560a-b and utilizing data stored on memory modules 540a-b. Additionally or alternatively, CPUs 550b-c may be communicatively coupled to GPU 560c and memory module 540c to control a second computational task (such as a second LLM inference task) being performed by GPU 560c and utilizing memory module 540c. The communicative coupling may be in series, in parallel, or a combination of both series and parallel.

[0104] CPUs 550a-c may distribute, divide, and / or assign tasks to one or more GPUs 560a- h. One or more tasks may be distributed partially or wholly to one or more GPUs. Multiple tasks may be distributed, divided, or assigned to a single GPU. For example, CPU 550a may distribute, divide, or assign two or more Al inference tasks to GPU 560a to be executed substantially simultaneously by assigning the two or more tasks to different cores within GPU 560a.

[0105] Additionally or alternatively, CPUs 550a-c may assign a single task to a plurality of GPUs 560a-h. For example, CPUs 550a-b may assign a single LLM inference task to GPUs 550c-h such that the single LLM inference task is split between GPUs 550c-h.

[0106] CPUs 550a-c may include 4 or more CPUs, 6 or more CPUs, 8 or more CPUs, 10 or more CPUs, 16 or more CPUs, 20 or more CPUs, 24 or more CPUs, 48 or more CPUs, 128 or more CPUs, or any suitable number of CPUs. Each CPU of CPUs 550a-c may be communicatively coupled with all other CPUs, GPUs, and / or memory modules indisaggregated computing system 500, for example through optical network 520. The communicative coupling may be in series, in parallel, or a combination of both series and parallel.

[0107] GPUs 560a-c may include 4 or more GPUs, 8 or more GPUs, 16 or more GPUs, 32 or more GPUs, 64 or more GPUs, 128 or more GPUs, or any suitable number of GPUs. Each GPU of GPUs 560a-h may be communicatively coupled with all other CPUs, GPUs, and / or memory modules in disaggregated computing system 500, for example through optical network 520. The communicative coupling may be in series, in parallel, or a combination of both series and parallel.

[0108] Memory modules 540a-c may include 3 or more memory modules, 4 or more memory modules, 8 or more memory modules, 16 or more memory modules, 32 or more memory modules, 64 or more memory modules, 128 or more memory modules, 500 or more memory modules, 1000 or more memory modules, 2000 or more memory modules, 10,000 or more memory modules, or any suitable number of memory modules. Each memory module of memory modules 540a-c may be communicatively coupled with all other CPUs, GPUs, and / or memory modules in disaggregated computing system 500, for example through optical network 520. The communicative coupling may be in series, in parallel, or a combination of both series and parallel.

[0109] System 500 may further include optical network 520, which is analogous to optical network 420 in disaggregated computing system 400 and may perform some or all of the same functions as optical network 420. In an embodiment, optical network 520 may be disposed externally to first immersion cooling tank 502 and second immersion cooling tank 504. Optical network 520 may provide communicative coupling between any plurality of components of system 500 including between memory module 540a-c, CPUs 550a-c, and / or GPUs 550a-h.Method of Dynamically Assigning Computing Tasks to GPUs

[0110] FIG. 6 is a flowchart of an example method 600 for disaggregated computing. The method 600 includes steps 610-620 as follows:

[0111] Step 610 includes transmitting, through a transmission medium, one or more signals selectively assigning, by one or more central processing units (CPUs), one or more first computing tasks to a first subgroup of graphics processing units (GPUs) from a plurality of GPUs. Each of the one or more CPUs and each of the plurality of GPUs may be disposed inthe same ambient environment or different ambient environments in any combination or permutation. The different ambient environments may include two or more ambient environments.

[0112] Step 620 includes transmitting, through the transmission medium, one or more signals selectively assigning, by the one or more CPUs, one or more second computing tasks to a second subgroup of GPUs from the plurality of GPUs. The one or more CPUs are communicatively coupled to the plurality of GPUs through an optical network having a latency of less than 500 nanoseconds. The first and second subgroups of GPUs may be distinct. The plurality of GPUs may include 8 or more GPUs.

[0113] Step 610 and / or step 620 may further include transmitting, through the transmission medium, first data retrieved by the first subgroup of GPUs from a plurality of memory modules and transmitting, through the transmission medium, second data retrieved by the second subgroup of GPUs from the plurality of memory modules. The plurality of memory modules may be disposed in a same ambient environment as at least one of the first subgroup of GPUs and the second subgroup of GPUs, or may be disposed in a different ambient environment than the first and / or second subgroup of GPUs.Method for Computer Networking

[0114] FIG. 7 is a flowchart of an example method 700 for computer networking. The method 700 includes steps 710-740 as follows:

[0115] Step 710 includes transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a first communication protocol or a second communication protocol. The first communication protocol may include a peripheral component interconnect express (PCIe) protocol. The second communication protocol may include a compute express link (CXL) protocol.

[0116] Step 720 transmitting, through a transmission medium, a second signal conforming to a third communication protocol after converting, by a first application-specific integrated circuit (ASIC), the first signal to the second signal. The third communication protocol may include a photonic protocol.

[0117] Step 730 includes transmitting, through the transmission medium, the second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted.

[0118] Step 740 includes transmitting, through the transmission medium, the third signal conforming to at least one of the first communication protocol or the second communication protocol to a memory upon converting, by the second ASIC, the second signal to the third signal. A latency between the memory and at least one of the CPU and the at least one GPU may be 100 nanoseconds or less.Method for Computer Networking

[0119] FIG. 8 is a flowchart of an example method 800 of computer networking. The method 800 includes steps 810-830 as follows:

[0120] Step 810 includes transmitting, through a transmission medium, a first signal conforming to at least one of a first communication protocol or a second communication protocol, the first signal generated at a memory. The first communication protocol may include a peripheral component interconnect express (PCIe) protocol. The second communication protocol may include a compute express link (CXL) protocol.

[0121] Step 820 includes transmitting, through the transmission medium, a second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted, wherein the second signal is transmitted upon conversion, by a first application-specific integrated circuit (ASIC), the first signal to a second signal conforming to a third communication protocol.

[0122] Step 830 includes transmitting, through the transmission medium, the third signal to a semiconductor die upon conversion, by the second ASIC, the second signal to a third signal conforming to at least one of the first communication protocol or the second communication protocol.Method of Transmitting Information

[0123] FIG. 9 is a flowchart of an example method 900 of transmitting information within a computer network. The method comprises steps 910-940 as follows:

[0124] At step 910, transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a peripheral component interconnect express (PCIe) or a compute express link (CXL) protocol.

[0125] At step 920, transmitting a second signal, through the transmission medium, upon converting the first signal to the second signal conforming to an RDMA over Converged Ethernet v2 (RoCEv2) protocol, the second signal converted by a first bridge and transmittedto a remote memory and received by the remote memory less than 200 nanoseconds after the second signal is transmitted.

[0126] At step 930, converting, by a second bridge, the second signal to a third signal conforming to at least one of the PCIe or the CXL protocol.

[0127] At step 940, storing information represented by the third signal on the remote memory.

[0128] Any of the above steps may be performed by or in accordance with elements of systems described herein.Various Possible Configurations1) Configuration 1. A system for disaggregated computing, the system comprising: a plurality of central processing units (CPUs), the plurality of CPUs configured to assign one or more computing tasks to a plurality of graphics processing units (GPUs), the plurality of CPUs communicatively coupled to the plurality of GPUs through an optical network comprising a transmission medium; wherein: a latency through the transmission medium and between the plurality of CPUs and the plurality of GPUs is less than 500 nanoseconds; the transmission medium is configured to provide a path for signals dynamically assigning the one or more computing tasks to a first subgroup of the plurality of GPUs based on a workload of at least one of the plurality of GPUs; and both the plurality of CPUs and the plurality of GPUs are communicatively coupled to a plurality of memory modules through the transmission medium.2) Configuration 2. The system of configuration 1, wherein the plurality of CPUs, the plurality of GPUs, and the plurality of memory modules are all disposed within a same ambient environment.3) Configuration 3. The system of configuration 1, wherein: at least a first GPU of the plurality of GPUs is disposed within a first ambient environment; and at least a second GPU of the plurality of GPUs is disposed within a second ambient environment that is different from the first ambient environment.4) Configuration 4. The system of configuration 1, wherein the plurality of GPUs are disposed within a same ambient environment.5) Configuration 5. The system of any of configurations 1 or 3-4, wherein: at least a first CPU of the plurality of CPUs is disposed within a first ambient environment; and at least a secondCPU of the plurality of CPUs is disposed within a second ambient environment that is different from the first ambient environment.6) Configuration 6. The system of any of configurations 1 or 3-4, wherein the plurality of CPUs are disposed within a same ambient environment.7) Configuration 7. The system of any of configurations 1 or 3-6, wherein: at least a first memory module of the plurality of memory modules is disposed within a first ambient environment; and at least a second memory module of the plurality of memory modules is disposed within a second ambient environment that is different from the first ambient environment.8) Configuration 8. The system of any of configurations 1 or 3-6, wherein the plurality of memory modules are disposed within a same ambient environment.9) Configuration 9. The system of any of configurations 1-8, wherein the plurality of GPUs comprises 8 or more GPUs.10) Configuration 10. A method for disaggregated computing, the method comprising: transmitting, through a transmission medium, one or more signals selectively assigning, by one or more central processing units (CPUs), one or more first computing tasks to a first subgroup of graphics processing units (GPUs) from a plurality of GPUs; and transmitting, through the transmission medium, one or more signals selectively assigning, by the one or more CPUs, one or more second computing tasks to a second subgroup of GPUs from the plurality of GPUs; wherein the one or more CPUs are communicatively coupled to the plurality of GPUs through the transmission medium having a latency of less than 500 nanoseconds.11) Configuration 11. The method of configuration 10, wherein: the first subgroup of GPUs is disposed within a first ambient environment; and the second subgroup of GPUs is disposed within a second ambient environment that is different from the first ambient environment.12) Configuration 12. The method of configuration 10, wherein the first subgroup of GPUs and the second subgroup of GPUs are disposed within a same ambient environment.13) Configuration 13. The method of any of configurations 10-12, further comprising: transmitting, through the transmission medium, first data retrieved by the first subgroup of GPUs from a plurality of memory modules; and transmitting, through the transmission medium, second data retrieved by the second subgroup of GPUs from the plurality of memorymodules; wherein the plurality of memory modules is disposed in a different ambient environment than the first subgroup of GPUs and the second subgroup of GPUs.14) Configuration 14. The method of any of configurations 10-12, further comprising: transmitting, through the transmission medium, first data retrieved by the first subgroup of GPUs from a plurality of memory modules; and transmitting, through the transmission medium, second data retrieved by the second subgroup of GPUs from the plurality of memory modules; wherein the plurality of memory modules is disposed in a same ambient environment as at least one of the first subgroup of GPUs and the second subgroup of GPUs.15) Configuration 15. The method of configuration 13 or 14, wherein: at least a first memory module of the plurality of memory modules is disposed within a first ambient environment; and at least a second memory module of the plurality of memory modules is disposed within a second ambient environment that is different from the first ambient environment.16) Configuration 16. The method of any of configurations 10-12, wherein the first subgroup of GPUs is distinct from the second subgroup of GPUs.17) Configuration 17. The method of any of configurations 10, 12, 14, or 16, wherein the one or more CPUs, the plurality of GPUs, and a plurality of memory modules are all disposed within a same ambient environment.18) Configuration 18. The method of configuration 10, wherein the plurality of GPUs are disposed within a same ambient environment.19) Configuration 19. The method of any of configurations 10-16, wherein the one or more CPUs are disposed within a same ambient environment.20) Configuration 20. The method of any of configurations 10-19, wherein the plurality of GPUs comprises 8 or more GPUs.21) Configuration 21. A system for computer networking, the system comprising: an optical network comprising a transmission medium; wherein: a central processing unit (CPU) and at least one graphics processing unit (GPU), both disposed on a server, are configured to communicate with each other using a first communication protocol through the transmission medium; a memory is configured to communicate, through the transmission medium, with at least one of the CPU and the at least one GPU using a second communication protocol based on the first protocol; and an application specific integrated circuit (ASIC) is configured to convert a first signal, transmitted through the transmission medium and based on the firstcommunication protocol or the second communication protocol, into a second signal based on a third communication protocol.22) Configuration 22. The system of configuration 21, wherein: the server is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.23) Configuration 23. The system of configuration 21, wherein the server and the memory are located within a same ambient environment.24) Configuration 24. The system of any of configurations 21-23, wherein: the first communication protocol comprises a peripheral component interconnect express (PCIe) protocol; the second communication protocol comprises a compute express link (CXL) protocol; and the third communication protocol comprises a photonic protocol.25) Configuration 25. The system of configurations 21-23, wherein a latency between the memory and at least one of the CPU and the at least one GPU is 100 nanoseconds or less.26) Configuration 26. A method for computer networking, the method comprising: transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a first communication protocol or a second communication protocol; transmitting, through a transmission medium, a second signal conforming to a third communication protocol after converting, by a first application-specific integrated circuit (ASIC), the first signal to the second signal; transmitting, through the transmission medium, the second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted; transmitting, through the transmission medium, the third signal conforming to at least one of the first communication protocol or the second communication protocol to a memory upon converting, by the second ASIC, the second signal to the third signal.27) Configuration 27. The method of configuration 26, further comprising storing, by the memory, information represented by the third signal.28) Configuration 28. The method of configuration 26, wherein: the semiconductor die is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.29) Configuration 29. The method of configuration 26, wherein the semiconductor die and the memory are located within a same ambient environment.30) Configuration 30. The method of any one of configurations 26-29, wherein: the first communication protocol comprises a peripheral component interconnect express (PCIe) protocol; the second communication protocol comprises a compute express link (CXL) protocol; and the third communication protocol comprises a photonic protocol.31) Configuration 31. A method for computer networking, the method comprising: transmitting, through a transmission medium, a first signal conforming to at least one of a first communication protocol or a second communication protocol, the first signal generated at a memory; transmitting, through the transmission medium, a second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted, wherein the second signal is transmitted upon conversion, by a first application-specific integrated circuit (ASIC), the first signal to a second signal conforming to a third communication protocol; transmitting, through the transmission medium, the third signal to a semiconductor die upon conversion, by the second ASIC, the second signal to a third signal conforming to at least one of the first communication protocol or the second communication protocol.32) Configuration 32. The method of configuration 31, wherein: the semiconductor die is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.33) Configuration 33. The method of configuration 31, wherein the semiconductor die and the memory are located within a same ambient environment.34) Configuration 34. The method of any of configurations 31-33, wherein: the first communication protocol comprises a peripheral component interconnect express (PCIe) protocol; the second communication protocol comprises a compute express link (CXL) protocol; and the third communication protocol comprises a photonic protocol.35) Configuration 35. A system for computer networking, the system comprising: a memory comprising an application-specific integrated circuit (ASIC) configured to convert signals between: at least one of a peripheral component interconnect express (PCIe) or a compute express link (CXL) protocol; and an ethernet protocol; a plurality of servers, each of the plurality of servers comprising: at least one semiconductor die; and a server ASIC configured to convert signals between: the PCIe or the CXL protocol; and an ethernet protocol; and an optical switching network comprising a transmission medium communicatively coupling the memory to the plurality of servers.36) Configuration 36. A method of transmitting information within a computer network, the method comprising: transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a peripheral component interconnect express (PCIe) or a compute express link (CXL) protocol; transmitting a second signal, through the transmission medium, upon converting the first signal to the second signal conforming to an RDMA over Converged Ethernet v2 (RoCEv2) protocol, the second signal converted by a first bridge and transmitted to a remote memory and received by the remote memory less than 200 nanoseconds after the second signal is transmitted; converting, by a second bridge, the second signal to a third signal conforming to at least one of the PCIe or the CXL protocol; and storing information represented by the third signal on the remote memory.Immersion Cooling System Figure

[0129] FIG. 10 depicts aspects of an immersion cooling system 1000 for dissipating heat from one or more heat-generating components such as semiconductor die packages 1005 via immersion cooling. Each package 1005 can include one or more semiconductor dies that produce heat when the system is in operation. The immersion cooling system 1000 in the illustrated example of FIG. 10 is a two-phase immersion cooling system, though the invention may also be implemented in a single-phase immersion cooling system.

[0130] Immersion cooling system 1000 includes a container such as tank 1020 filled, at least in part, with immersion cooling liquid 1064. The immersion cooling system 1000 can further include at least one chiller 1080 that flows a heat-transfer fluid through at least one condenser tube 1070 that is disposed in the tank 1020 and headspace 1008. Condenser tubes 1070 and chiller 1080 may be part of a heat exchanger. The packages 1005 can be mounted on one or more printed circuit boards (PCBs) 1057 that are immersed, at least in part, in the immersion cooling liquid 1064. Immersion-cooling system 1000 may further include a filter 1075 disposed adjacent to the tank 1020.

[0131] Filter 1075 may include a filtration media, a housing, and a pump configured to force immersion cooling liquid 1064 through filter 1075 to remove contaminants, particulates, or other impurities that may be added to immersion cooling liquid 1064 during use. Filter 1075 may be housed outside of tank 1020 while being in fluidic communication with immersion cooling liquid 1064 in tank 1020. Alternatively, filter 1075 may be submerged within immersion cooling liquid 1064 inside of tank 1020.

[0132] Immersion cooling liquid 1064 may be a hydrocarbon, a fluoroketone, an oil, or asimilar dielectric liquid that will act as an insulator while simultaneously transferring heat from package 1005 more efficiently than air. Examples of immersion cooling liquid 1064 are Novec™ 649, Novec™ 7000, and Novec™ 7100 produced by 3M™. An exemplary immersion cooling liquid 1064 used in accordance with embodiments of the present invention may have a dielectric constant baseline value of about 1.8-2 at a frequency of about 1 kHz.

[0133] In an embodiment of the invention, immersion cooling liquid 1064 may be considered unacceptably contaminated if the dielectric constant and / or dielectric loss tangent of immersion cooling fluid being used in an immersion cooling system 1000 differs by a threshold amount as compared to unused or pure immersion cooling liquid 1064. For example, immersion cooling liquid 1064 may be considered unacceptably contaminated or degraded if the dielectric constant and / or dielectric loss tangent differs by a threshold of 10% or more as compared to unused or pure immersion cooling liquid 1064. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be 20%, 15%, 5%, 3%, 1%, or any suitable threshold.

[0134] Contamination of the immersion cooling liquid 1064 and resulting changes to dielectric constant and / or dielectric loss tangent may alter or negatively impact operation of components within immersion cooling liquid 1064 including semiconductor die(s) 1050. An altered dielectric constant and / or dielectric loss tangent may result in undesirable cross-talk between components on a PCB, additional noise or reduction in signal strength transmitted along exposed wires of a PCB or semiconductor die(s) 1050 submerged in immersion fluid, and / or signal dissipation through the immersion cooling liquid 1064. Signal loss may be severe enough that two elements may be effectively represented as being separated by an open circuit despite being physically connected. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be selected based on an observed or inferred effect on one or more submerged semiconductor die(s) 1050. For example, an increase in PCIe bit error rate above an error rate baseline may be correlated with an increase in dielectric constant and / or dielectric loss tangent above a dielectric constant and / or dielectric loss tangent baseline. Accordingly, operation of semiconductor die(s) 1050 may be throttled or suspended when a dielectric constant and / or dielectric loss tangent of immersion cooling liquid 1064 exceeds a predetermined threshold.

[0135] Changes to dielectric constant and / or dielectric loss tangent may be caused by contaminants within immersion cooling liquid 1064. In some cases, changes to dielectric constant and / or dielectric loss tangent may be reversed by filtering the contaminants fromimmersion cooling liquid 1064. In some embodiments, upon detecting an increase in dielectric constant and / or dielectric loss tangent of immersion cooling liquid 1064, controller 1002 may instruct filter 1075 to increase filtration throughput or notify a user that an immersion cooling liquid 1064 filtration media may need to be replaced. If a dielectric constant and / or dielectric loss tangent exceeds a predetermined threshold, controller 1002 may throttle or shut down one or more semiconductor die(s) 1050, generate a notification that immersion cooling liquid 1064 should be replaced, trigger an alarm, etc.

[0136] Further examples of sensors and methods for immersion cooling contamination monitoring may include probes for monitoring immersion cooling liquid parameters such as dielectric constant and dielectric loss tangent, and processors configured to identify trends in sensor data, model immersion cooling system behavior as a function of contamination, and alter operations of immersion cooling systems based on detected levels and / or states of contamination may be found in U.S. Provisional Patent Application 63 / 516,748, filed July 31, 2023 and entitled “Di-Electric Monitoring of Immersion Fluid During Cooling Operation,” the entirety of which is incorporated herein by reference.

[0137] The illustrated example of FIG. 10 is not intended to be to scale. The immersion cooling system 1000 may house and provide immersion cooling liquid 1064 to tens, hundreds, or even thousands of packages 1005. In some cases, the immersion cooling system 1000 can be small (e.g., the size of a floor unit air conditioner, approximately 1 meter high, 0.5 meter width, 0.5 meter depth or length). In some implementations, the immersion cooling system can be large (e.g., the size of a van or larger, approximately 2.5 meters high, 2.5 meters width, 4 meters depth or length).

[0138] The immersion cooling system 1000 can also include a controller 1002 (e.g., a microcontroller, programmable logic controller (PLC), microprocessor, field-programmable gate array, logic circuitry, memory, or some combination thereof) to manage system operation. Controller 1002 can perform various system functions such as monitoring temperatures of system components, cooling fluid level, tank access, chiller operation etc. The controller 1002 can further issue commands to control system operation such as executing a start-up sequence, executing a shut-down sequence, assigning workloads among the packages, changing cooling fluid level, changing the temperature of the heat-transfer fluid circulated by the chiller 1080, etc. In some implementations, controller 1002 can include (or itself be) a baseboard management controller (BMC) 1004. That is, the BMC 1004 may monitor and control all aspects of system operation for the immersion cooling system 1000 in addition to monitoringand controlling workloads of the semiconductor dies 1050 in the packages 1005 cooled by the system. The immersion cooling system 1000 can also include a network interface controller (NIC 1003) to allow the system to communicate over a network, such as a local area network or wide area network. The immersion cooling system 1000 can further include a fluid sensor array 1090 having a plurality of fluid sensors 1010. Fluid sensors 1010 may include one or more leak detection sensors at least partially submerged in immersion cooling liquid 1064.

[0139] The semiconductor die(s) 1050 and can be mounted on and attached to a printed circuit board (PCB) 1055 (sometimes referred to as a substrate) in device package 1005. The package 1005 can be made commercially available as an off-the-shelf (OTS) product. The package 1005 can be used for single-phase or two-phase immersion cooling of at least one semiconductor die 1050, such as a microprocessor (e.g., a central processing unit (CPU) and / or graphics processing unit (GPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), and / or other densely patterned semiconductor die.

[0140] In the two-phase immersion cooling system 1000 of FIG. 10, heat flows from the semiconductor die 1050 where it is generated into the heat spreader 1052. The heat spreader 1052 is in thermal contact with an immersion cooling liquid 1064 that can flow over and extract heat from the heat spreader 1052. The amount of heat delivered by the heat spreader 1052 to the immersion cooling liquid 1064 is enough to boil the immersion cooling liquid 1064 that contacts the heat spreader 1052 (creating bu71es 1065 and potentially creating froth 1067 when bu71es 1065 reach the surface of immersion cooling liquid 1064). The vapor 1066 from the boiled immersion cooling liquid 1064 can be cooled and condensed back to liquid droplets 1068, for example, by the condenser tube 1070. The heat-transfer fluid, such as chilled water, from the chiller 1080 can be circulated through the condenser tube 1070 to lower the temperature of the condenser tube 1070 below the condensation point in the headspace 1008 of the tank 1020. As a result, vapor 1066 condenses on exterior surfaces of the condenser tube 1070 and liquid droplets 1068 from the condensed vapor can drip and / or flow back to the immersion cooling liquid 1064. There may be a plurality of condenser tubes 1070 in tank 1020 to condense the vapor 1066 into droplets. Some or all of the condenser tubes 1070 may or may not be located directly over the PCBs 1057. Instead, the condenser tube(s) 1070 can be located near one or more walls of the tank 1020, such that the condenser tube(s) 1070 are not directly over the PCBs 1057 on which the packages 1005 are mounted.

[0141] To improve thermal performance in two-phase immersion cooling system 1000, the heat spreader 1052 can include a boiling enhancement coating (BEC) on at least one surface. The BEC can be formed from copper or a copper alloy and can be porous, for example, though BECs can take various forms. In some cases, the BEC is a micro porous copper coating having a thickness from approximately or exactly 50 microns to 500 microns thick (which may be produced by electroplating and / or etching). In some implementations, the BEC comprises a mesh copper layer bonded (e.g., via resistance heating) to at least an outer surface of the heat spreader 1052. In some cases, the BEC is applied as particulates to at least one smooth surface of the heat spreader 1052 and then subsequently sintered to adhere to one another and to the heat spreader 1052. The BEC provides an improved surface area to contact the immersion cooling liquid 1064 and can increase the heat transfer coefficient from the heat spreader 1052 to the immersion cooling liquid 1064 by up to a factor of 15 versus a smooth surface on the heat spreader 1052. Accordingly, BECs can increase thermal conductivity to, and accelerate the boiling of, the immersion cooling liquid 1064.

[0142] Further implementations of boiling enhancement coatings and enclosures are possible. Additional arrangements, applications, and methods of use of boiling enhancement coatings and enclosures, including with semiconductor dies and 3DIC stacks, are described in the below U.S. Patent Applications.

[0143] U.S. Patent Application No. 18 / 327,615, filed June 1, 2023 and entitled "Boiler Enhancement Coatings with Active Boiling Management,” discloses heat spreader and boiling enhancement enclosure architectures thermally and / or mechanically coupled to one or more semiconductor dies or logic ICs that may be used for passive and / or active management of immersion cooling fluid boiling, including through the use of valves to control pressure of boiling immersion cooling fluid within a boiling enhancement chamber, particularly in paragraphs

[0018] -

[0039] and FIGS. 3-5B. The entirety of U.S. Patent Application No. 18 / 327,615 is incorporated herein by reference.

[0144] U.S. Provisional Patent Application No. 63 / 500,167, filed May 4, 2023 and entitled “Direct to Chip Heat Spreader and Boiler Enhancement Coatings for Microelectronics,” discloses heat spreader and BECs thermally and / or mechanically coupled to one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0015] -

[0033] and FIGS. 2A-4. BEC form factors may include graphite heat spreader architectures, vapor chambers, heat pipes, copper plates, fins, and the like. BEC form factors may be thermally and / or mechanically coupled to the one or more semiconductor dies, logic ICs, and / or 3DICstacks through a thermally conductive epoxy, and may have varying dimensions relative to a surface to which the semiconductor dies and / or logic ICs are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 500,167 is incorporated herein by reference.

[0145] U.S. Patent Application No. 18 / 460,091, filed September 1, 2023 and entitled “Direct to Chip Application of Boiling Enhancement Coating,” discloses BECs and methods for applying BECs to semiconductor dies, logic ICs, and / or 3DIC stacks in accordance with the present technology. In particular, paragraphs

[0024] -

[0046] and FIGS. 2A-5 disclose embodiments of BEC layers, adhesives, solders, sintering, laser ablation, meshes, and other BECs and BEC application methods. The entirety of U.S. Patent Application No. 18 / 460,091 is incorporated herein by reference.

[0146] U.S. Provisional Patent Application No. 63 / 506,945, filed June 8, 2023 and entitled “Vapor- Shedding Structures for Boiler Plates in Two-Phase Immersion Cooling Systems,” discloses structures that may be thermally and / or mechanically coupled to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks to enable the shedding of immersion cooling vapors generated from the boiling of immersion cooling fluid during operation of the computing hardware. In particular, paragraphs

[0021] -

[0039] and FIGS. 3A-5 disclose vapor-shedding structures including varying porosities, constituent materials, and geometries relative to the computing hardware on which they are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 506,945 is incorporated herein by reference.

[0147] U.S. Provisional Application No. 63 / 513,828, filed July 14, 2023 and entitled “Grinding Apparatuses and Methods for Mechanically Modifying Surfaces of Processors to Promote Boiling of a Coolant Liquid,” discloses methods for creating boiling enhancement modifications to surfaces such as the surfaces of computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0036] -

[0095] and FIGS. 2A-8. For example, grooves, patterns, gouges, trenches, or other structures may be added to a surface or lid of a processor, semiconductor die, logic IC, 3DIC stack component, and / or BEC to encourage nucleation sites for bu71es of immersion cooling vapor to form during a cooling process, thus decreasing the thermal resistance between the processor, semiconductor die, logic IC, and / or 3DIC stack component and the surrounding immersion cooling fluid. The entirety of U.S. Provisional Application No. 63 / 513,828 is incorporated herein by reference.

[0148] U.S. Provisional Patent Application No. 63 / 513,829, filed July 14, 2023 and entitled “Electrical Connector Having a Heater to Facilitate Boiling of a Coolant Liquid to ImproveSignal Integrity in Immersion Cooling Environment,” discloses heaters for promoting boiling of immersion cooling fluid near electrical connectors such as connections between components of a 3DIC stack and enable improved impedances at those connectors, particularly in paragraphs

[0019] -

[0052] and FIGS. 1A-3B. The entirety of U.S. Provisional Patent Application No. 63 / 513,829 is incorporated herein by reference.

[0149] U.S. Provisional Patent Application No. 63 / 603,242, filed November 28, 2023 and entitled “Woven Boiler Enhancement Coatings,” provides additional examples of BECs including woven BECs with variable weave patterns, densities, attachment mechanisms, and materials (including copper and tungsten) that may be attached to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks in order to promote more efficient heat transfer and immersion cooling vapor nucleation, particularly in paragraphs [003 l]-

[0055] and FIGS. 3-7. The entirety of U.S. Provisional Patent Application No. 63 / 603,242 is incorporated herein by reference.Conclusion

[0150] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

[0151] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0152] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0153] Unless stated otherwise or not suitably clear from context, the terms “approximately” and “about” are used to mean within + / - 20% of a target value (e.g., dimension or orientation) in some embodiments, within + 10% of a target in some embodiments, within + 5% of a target in some embodiments, and yet within + 2% of a target in some embodiments. The terms “approximately” and “about” can include the target. The term “essentially” is used to mean within + 3% of a target.

[0154] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0155] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0156] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactlyone of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0157] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0158] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS1. A system for disaggregated computing, the system comprising: a plurality of central processing units (CPUs), the plurality of CPUs configured to assign one or more computing tasks to a plurality of graphics processing units (GPUs), the plurality of CPUs communicatively coupled to the plurality of GPUs through an optical network comprising a transmission medium; wherein: a latency through the transmission medium and between the plurality of CPUs and the plurality of GPUs is less than 500 nanoseconds; the transmission medium is configured to provide a path for signals dynamically assigning the one or more computing tasks to a first subgroup of the plurality of GPUs based on a workload of at least one of the plurality of GPUs; and both the plurality of CPUs and the plurality of GPUs are communicatively coupled to a plurality of memory modules through the transmission medium.

2. The system of claim 1, wherein the plurality of CPUs, the plurality of GPUs, and the plurality of memory modules are all disposed within a same ambient environment.

3. The system of claim 1, wherein: at least a first GPU of the plurality of GPUs is disposed within a first ambient environment; and at least a second GPU of the plurality of GPUs is disposed within a second ambient environment that is different from the first ambient environment.

4. The system of claim 1, wherein the plurality of GPUs are disposed within a same ambient environment.

5. The system of any of claims 1 or 3-4, wherein: at least a first CPU of the plurality of CPUs is disposed within a first ambient environment; and at least a second CPU of the plurality of CPUs is disposed within a second ambient environment that is different from the first ambient environment.

6. The system of any of claims 1 or 3-4, wherein the plurality of CPUs are disposed within a same ambient environment.

7. The system of any of claims 1 or 3-6, wherein: at least a first memory module of the plurality of memory modules is disposed within a first ambient environment; and at least a second memory module of the plurality of memory modules is disposed within a second ambient environment that is different from the first ambient environment.

8. The system of any of claims 1 or 3-6, wherein the plurality of memory modules are disposed within a same ambient environment.

9. The system of any of claims 1-8, wherein the plurality of GPUs comprises 8 or more GPUs.

10. A method for disaggregated computing, the method comprising: transmitting, through a transmission medium, one or more signals selectively assigning, by one or more central processing units (CPUs), one or more first computing tasks to a first subgroup of graphics processing units (GPUs) from a plurality of GPUs; and transmitting, through the transmission medium, one or more signals selectively assigning, by the one or more CPUs, one or more second computing tasks to a second subgroup of GPUs from the plurality of GPUs; wherein the one or more CPUs are communicatively coupled to the plurality of GPUs through the transmission medium having a latency of less than 500 nanoseconds.

11. The method of claim 10, wherein: the first subgroup of GPUs is disposed within a first ambient environment; and the second subgroup of GPUs is disposed within a second ambient environment that is different from the first ambient environment.

12. The method of claim 10, wherein the first subgroup of GPUs and the second subgroup of GPUs are disposed within a same ambient environment.

13. The method of any of claims 10-12, further comprising:transmitting, through the transmission medium, first data retrieved by the first subgroup of GPUs from a plurality of memory modules; and transmitting, through the transmission medium, second data retrieved by the second subgroup of GPUs from the plurality of memory modules; wherein the plurality of memory modules is disposed in a different ambient environment than the first subgroup of GPUs and the second subgroup of GPUs.

14. The method of any of claims 10-12, further comprising: transmitting, through the transmission medium, first data retrieved by the first subgroup of GPUs from a plurality of memory modules; and transmitting, through the transmission medium, second data retrieved by the second subgroup of GPUs from the plurality of memory modules; wherein the plurality of memory modules is disposed in a same ambient environment as at least one of the first subgroup of GPUs and the second subgroup of GPUs.

15. The method of claim 13 or 14, wherein: at least a first memory module of the plurality of memory modules is disposed within a first ambient environment; and at least a second memory module of the plurality of memory modules is disposed within a second ambient environment that is different from the first ambient environment.

16. The method of any of claims 10-12, wherein the first subgroup of GPUs is distinct from the second subgroup of GPUs.

17. The method of any of claims 10, 12, 14, or 16, wherein the one or more CPUs, the plurality of GPUs, and a plurality of memory modules are all disposed within a same ambient environment.

18. The method of claim 10, wherein the plurality of GPUs are disposed within a same ambient environment.

19. The method of any of claims 10-16, wherein the one or more CPUs are disposed within a same ambient environment.

20. The method of any of claims 10-19, wherein the plurality of GPUs comprises 8 or more GPUs.

21. A system for computer networking, the system comprising: an optical network comprising a transmission medium; wherein: a central processing unit (CPU) and at least one graphics processing unit (GPU), both disposed on a server, are configured to communicate with each other using a first communication protocol through the transmission medium; a memory is configured to communicate, through the transmission medium, with at least one of the CPU and the at least one GPU using a second communication protocol based on the first protocol; and an application specific integrated circuit (ASIC) is configured to convert a first signal, transmitted through the transmission medium and based on the first communication protocol or the second communication protocol, into a second signal based on a third communication protocol.

22. The system of claim 21, wherein: the server is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.

23. The system of claim 21, wherein the server and the memory are located within a same ambient environment.

24. The system of any of claims 21-23, wherein: the first communication protocol comprises a peripheral component interconnect express (PCIe) protocol; the second communication protocol comprises a compute express link (CXL) protocol; and the third communication protocol comprises a photonic protocol.

25. The system of claims 21-23, wherein a latency between the memory and at least one of the CPU and the at least one GPU is 100 nanoseconds or less.

26. A method for computer networking, the method comprising: transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a first communication protocol or a second communication protocol; transmitting, through a transmission medium, a second signal conforming to a third communication protocol after converting, by a first application-specific integrated circuit (ASIC), the first signal to the second signal; transmitting, through the transmission medium, the second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted; transmitting, through the transmission medium, the third signal conforming to at least one of the first communication protocol or the second communication protocol to a memory upon converting, by the second ASIC, the second signal to the third signal.

27. The method of claim 26, further comprising storing, by the memory, information represented by the third signal.

28. The method of claim 26, wherein: the semiconductor die is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.

29. The method of claim 26, wherein the semiconductor die and the memory are located within a same ambient environment.

30. The method of any one of claims 26-29, wherein: the first communication protocol comprises a peripheral component interconnect express (PCIe) protocol; the second communication protocol comprises a compute express link (CXL) protocol; and the third communication protocol comprises a photonic protocol.

31. A method for computer networking, the method comprising:transmitting, through a transmission medium, a first signal conforming to at least one of a first communication protocol or a second communication protocol, the first signal generated at a memory; transmitting, through the transmission medium, a second signal to a second ASIC and receiving, by the second ASIC, the second signal less than 100 nanoseconds after the second signal is transmitted, wherein the second signal is transmitted upon conversion, by a first application-specific integrated circuit (ASIC), the first signal to a second signal conforming to a third communication protocol; transmitting, through the transmission medium, the third signal to a semiconductor die upon conversion, by the second ASIC, the second signal to a third signal conforming to at least one of the first communication protocol or the second communication protocol.

32. The method of claim 31, wherein: the semiconductor die is located within a first ambient environment; and the memory is located within a second ambient environment different from the first ambient environment.

33. The method of claim 31, wherein the semiconductor die and the memory are located within a same ambient environment.

34. The method of any of claims 31-33, wherein: the first communication protocol comprises a peripheral component interconnect express (PCIe) protocol; the second communication protocol comprises a compute express link (CXL) protocol; and the third communication protocol comprises a photonic protocol.

35. A system for computer networking, the system comprising: a memory comprising an application-specific integrated circuit (ASIC) configured to convert signals between: at least one of a peripheral component interconnect express (PCIe) or a compute express link (CXL) protocol; and an ethernet protocol; a plurality of servers, each of the plurality of servers comprising:at least one semiconductor die; and a server ASIC configured to convert signals between: the PCIe or the CXL protocol; and an ethemet protocol; and an optical switching network comprising a transmission medium communicatively coupling the memory to the plurality of servers.

36. A method of transmitting information within a computer network, the method comprising: transmitting, through a transmission medium, a first signal generated by a semiconductor die and conforming to at least one of a peripheral component interconnect express (PCIe) or a compute express link (CXL) protocol; transmitting a second signal, through the transmission medium, upon converting the first signal to the second signal conforming to an RDMA over Converged Ethernet v2 (RoCEv2) protocol, the second signal converted by a first bridge and transmitted to a remote memory and received by the remote memory less than 200 nanoseconds after the second signal is transmitted; converting, by a second bridge, the second signal to a third signal conforming to at least one of the PCIe or the CXL protocol; and storing information represented by the third signal on the remote memory.

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