Mask generation model training method and apparatus, mask generation method and apparatus, and storage medium

Abstract

The present application provides a mask generation model training method and apparatus, a mask generation method and apparatus, and a storage medium. The mask generation model training method comprises: acquiring a training sample set, wherein each training sample comprises a target layout of a chip sample and a mask of the target layout; for at least one training sample, taking the target layout of the chip sample as an input of a mask generation model, to obtain a prediction mask of the target layout; inputting the prediction mask of the target layout into a photoetching physical model to obtain a wafer pattern corresponding to the prediction mask; determining the complexity of the prediction mask of the target layout on the basis of the sum of the perimeters of a plurality of graphics comprised in the target layout of the chip sample and the perimeter of the prediction mask of the target layout; and on the basis of the target layout of the chip sample, the wafer pattern corresponding to the prediction mask of the target layout, the mask of the target layout, the prediction mask of the target layout, and the complexity of the prediction mask of the target layout, adjusting parameters of the mask generation model until a training stop condition is met, to obtain a trained mask generation model.

Description

Mask generation model training method, mask generation method and device, and storage medium

[0001] Priority information

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on August 10, 2023, with application number 202311005424.2 and application name “Mask generation model training method, mask generation method and device and storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of artificial intelligence technology, and in particular to a mask generation model training method, a mask generation method and device, and a storage medium. Background Art

[0004] The photolithography process transfers the geometric patterns on the mask to the photoresist on the wafer surface. The photoresist processing equipment spin-coats the photoresist onto the wafer surface, and after repeated exposure and development processes, the desired pattern is formed on the wafer. As the feature size of ultra-large-scale integrated circuits continues to shrink and has fallen below the wavelength of the light source used in the photolithography process, interference and diffraction phenomena have become very significant. As a result, the pattern exposed on the wafer through the mask deviates significantly from the desired pattern, significantly affecting the performance, production capacity, and yield of the chip. To address this problem, deep learning technology has been applied to various fields of chip design and manufacturing. To ensure the high quality of the mask, the complexity of the generated mask must be kept low.

[0005] In existing technologies, one method uses deep learning algorithms to optimize and generate masks, while another method uses pixel-based reverse lithography to generate masks. However, the masks generated by these two methods are highly complex, making them difficult to apply to large-scale integrated circuit layout optimization.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a mask generation model training method, a mask generation method and device, and a storage medium, which can reduce the complexity of the mask.

[0008] In a first aspect, an embodiment of the present application provides a mask generation model training method, comprising:

[0009] Acquire a training sample set, each training sample including a target layout of a chip sample and a mask of the target layout;

[0010] For at least one training sample in the training sample set, using a target layout of a chip sample in the training sample as an input to a mask generation model to obtain a predicted mask of the target layout, and inputting the predicted mask of the target layout into a lithography physical model to obtain a wafer pattern corresponding to the predicted mask of the target layout;

[0011] Determining the complexity of the prediction mask of the target layout according to the sum of the perimeters of the plurality of graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout;

[0012] According to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout and the complexity of the predicted mask of the target layout, the parameters of the mask generation model are adjusted until the training stop condition is met to obtain a trained mask generation model.

[0013] In a second aspect, an embodiment of the present application provides a mask generation method, comprising:

[0014] Obtain the target chip layout;

[0015] The target chip layout is input into a trained mask generation model, and a mask corresponding to the target chip layout is output. The mask generation model is trained according to the method described in the first aspect.

[0016] In a third aspect, an embodiment of the present application provides a mask generation model training device, comprising:

[0017] An acquisition module is used to acquire a training sample set, each training sample including a target layout of a chip sample and a mask of the target layout;

[0018] a processing module, configured to obtain a predicted mask of at least one training sample in the training sample set by using a target layout of a chip sample in the training sample as an input of a mask generation model;

[0019] The processing module is further configured to: input the predicted mask of the target layout into a lithography physical model to obtain a wafer pattern corresponding to the predicted mask of the target layout;

[0020] a determination module, configured to determine the complexity of the prediction mask of the target layout according to the sum of the perimeters of the plurality of graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout;

[0021] A parameter adjustment module is used to adjust the parameters of the mask generation model according to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout, until the training stop condition is met to obtain a trained mask generation model.

[0022] In a fourth aspect, an embodiment of the present application provides a mask generating device, comprising:

[0023] An acquisition module is used to obtain the target chip layout;

[0024] A processing module is used to input the target chip layout into a trained mask generation model and output a mask corresponding to the target chip layout, wherein the mask generation model is trained according to the method described in the first aspect.

[0025] In a fifth aspect, an embodiment of the present application provides a computer device comprising: a processor and a memory, the memory being used to store a computer program, the processor being used to call and run the computer program stored in the memory to execute the method of the first aspect or the second aspect.

[0026] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium comprising instructions, which, when executed on a computer program, enables the computer to execute the method of the first aspect or the second aspect.

[0027] In a seventh aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute the method of the first aspect or the second aspect.

[0028] In summary, in an embodiment of the present application, a training sample set is first obtained, and for at least one training sample in the training sample set, the target layout of the chip sample in the training sample is input into the mask generation model to obtain the predicted mask of the target layout, and then the predicted mask of the target layout is input into the lithography physical model to obtain the wafer pattern corresponding to the predicted mask of the target layout. And according to the sum of the perimeters of the multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout, the complexity of the predicted mask of the target layout is determined. Then, according to the target layout of the chip sample and the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout and the predicted mask of the target layout, and the complexity of the predicted mask of the target layout, the parameters of the mask generation model are adjusted until the training stop condition is met to obtain a trained mask generation model. Therefore, when adjusting the model parameters of the mask generation model, the model parameters are adjusted not only based on the wafer pattern corresponding to the target layout of the chip sample and the predicted mask of the target layout, as well as the target layout's mask and the predicted mask of the target layout, but also based on the complexity of the predicted mask of the target layout. This reduces the complexity of the mask generated by the mask generation model. Furthermore, because the complexity of the predicted mask of the target layout is determined based on the sum of the perimeters of multiple patterns included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout, the complexity of the predicted mask of the target layout depends only on the shape of the target layout and the predicted mask of the target layout. This results in a highly transferable mask generation model and a low computational complexity in the model training process.

[0029] Furthermore, in the embodiment of the present application, the mask generation model is pre-trained, and the pre-trained mask generation model parameters are used as initial model parameters for subsequent training, thereby reducing the amount of calculation and making the model converge faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of an implementation scenario of a mask generation model training method and a mask generation method provided in an embodiment of the present application;

[0031] FIG2 is a flowchart of a mask generation model training method provided in an embodiment of the present application;

[0032] FIG3 is a schematic diagram of a model training process provided in an embodiment of the present application;

[0033] FIG4 is a schematic diagram of a target layout of a chip sample, a prediction mask of the target layout of the chip sample, and an outline of the prediction mask of the target layout of the chip sample;

[0034] FIG5 is a schematic diagram of a method for correcting edge placement errors;

[0035] FIG6 is a flowchart of a mask generation model training method provided in an embodiment of the present application;

[0036] FIG7 is a schematic diagram showing a comparison of mask effects provided in an embodiment of the present application;

[0037] FIG8 is a schematic diagram showing a comparison of mask effects provided by an embodiment of the present application;

[0038] FIG9 is a flowchart of a mask generation method provided in an embodiment of the present application;

[0039] FIG10 is a schematic structural diagram of a mask generation model training device provided in an embodiment of the present application;

[0040] FIG11 is a schematic structural diagram of a mask generating device provided in an embodiment of the present application;

[0041] FIG12 is a schematic block diagram of a computer device 300 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of them. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of the present application.

[0043] It should be noted that the terms "first", "second", etc. in the description and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] Before introducing the technical solutions of the embodiments of the present application, the following is an introduction to the relevant knowledge of the embodiments of the present application:

[0045] 1. Artificial Intelligence (AI): It is the theory, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, to perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive field within computer science that seeks to understand the essence of intelligence and produce new intelligent machines that can respond in a manner similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the capabilities of perception, reasoning, and decision-making. AI technology is an interdisciplinary discipline encompassing a wide range of fields, encompassing both hardware and software technologies. Foundational AI technologies generally include sensors, specialized AI chips, cloud computing, distributed storage, big data processing, operating / interaction systems, and mechatronics. AI software technologies primarily encompass computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0046] 2. Machine Learning (ML): This is a multidisciplinary field that encompasses probability theory, statistics, approximation theory, convex analysis, and algorithmic complexity theory. It specifically studies how computers can simulate or implement human learning behaviors to acquire new knowledge or skills and reorganize existing knowledge structures to continuously improve their performance. Machine learning is at the core of artificial intelligence and the fundamental way to make computers intelligent. Its applications span all areas of AI. Machine learning and deep learning typically include techniques such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and self-learning.

[0047] 3. Deep Learning (DL): A branch of machine learning, it is an algorithm that attempts to achieve high-level abstraction of data using multiple processing layers containing complex structures or consisting of multiple nonlinear transformations. Deep learning learns the inherent patterns and representational hierarchies of training sample data. The information gained during this learning process is highly helpful in interpreting data such as text, images, and sound. The ultimate goal of deep learning is to enable machines to have human-like analytical learning capabilities and to recognize data such as text, images, and sound. Deep learning is a complex machine learning algorithm that has achieved results in speech and image recognition that far surpass previous related technologies.

[0048] Neural Network (NN): A deep learning model in the field of machine learning and cognitive science that mimics the structure and function of biological neural networks.

[0049] In the related art, the complexity of the generated mask is relatively high. To solve this problem, the embodiment of the present application inputs the target layout of the chip sample in the training sample into the mask generation model for at least one training sample in the training sample set when training the mask generation model, obtains the predicted mask of the target layout, and then inputs the predicted mask of the target layout into the lithography physical model to obtain the wafer pattern corresponding to the predicted mask of the target layout. And the complexity of the predicted mask of the target layout is determined based on the sum of the perimeters of the multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout. Then, according to the target layout of the chip sample and the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout and the predicted mask of the target layout, and the complexity of the predicted mask of the target layout, the parameters of the mask generation model are adjusted until the training stop condition is met to obtain a trained mask generation model. Thus, in the embodiments of the present application, when adjusting the model parameters of the mask generation model, the model parameters are adjusted not only based on the wafer pattern corresponding to the target layout of the chip sample and the predicted mask of the target layout, as well as the mask of the target layout and the predicted mask of the target layout, but also based on the complexity of the predicted mask of the target layout. Therefore, the complexity of the mask generated by the mask generation model can be reduced. Moreover, since the complexity of the predicted mask of the target layout is determined based on the sum of the perimeters of multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout, the complexity of the predicted mask of the target layout only depends on the shape of the target layout and the predicted mask of the target layout. Therefore, the trained mask generation model has high mobility and the computational complexity of the model training process is low.

[0050] The embodiments of the present application can be applied to various scenarios where masks need to be generated, such as large-scale integrated circuit layout optimization. The mask generation model training method and mask generation method provided in the embodiments of the present application can be installed in computational lithography software. Chip mask manufacturers can obtain the mask corresponding to the target chip layout by inputting the target chip layout, and the mask complexity is low, which can provide a higher-quality mask for the subsequent chip lithography process. Specifically, for example, a lithography mask with low mask complexity can be provided, which significantly reduces the calculation time and manufacturing cost of the mask and improves the process window of the mask generation model to generate the mask. The process window can be understood as the tolerance for exposure and defocus. The mask generation model training method and mask generation method provided in the embodiments of the present application can also be expanded to fields such as computer vision image generation.

[0051] It should be noted that the application scenarios described above are only used to illustrate the embodiments of the present application and are not intended to limit the present application. In specific implementations, the technical solutions provided in the embodiments of the present application can be flexibly applied according to actual needs.

[0052] For example, FIG1 is a schematic diagram of an implementation scenario of a mask generation model training method and a mask generation method provided in an embodiment of the present application. As shown in FIG1 , the implementation scenario of the embodiment of the present application involves a server 1 and a terminal device 2. The terminal device 2 can communicate data with the server 1 through a communication network. The communication network can be a wireless or wired network such as an intranet, the Internet, the Global System of Mobile communication (GSM), Wideband Code Division Multiple Access (WCDMA), a 4G network, a 5G network, Bluetooth, Wi-Fi, or a call network.

[0053] In some implementations, terminal device 2 refers to a device that features a variety of human-computer interaction methods, internet access, various operating systems, and strong processing capabilities. The terminal device may be, but is not limited to, a smartphone, tablet computer, portable laptop computer, desktop computer, or a smartwatch. Optionally, in this embodiment of the present application, terminal device 2 may be installed with various applications, such as a lithography application.

[0054] Among them, in some possible implementations, the terminal device 2 includes but is not limited to mobile phones, computers, intelligent voice interaction devices, smart home appliances, car terminals, etc.

[0055] The server 1 in Figure 1 can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. This embodiment of the present application does not limit this. In this embodiment of the present application, the server 1 can be the background server of an application installed in the terminal device 2.

[0056] In some implementations, FIG1 exemplarily shows one terminal device and one server, but may actually include other numbers of terminal devices and servers, which is not limited in this embodiment of the present application.

[0057] In some embodiments, when it is necessary to obtain a mask corresponding to a target chip layout, the server 1 may use the method provided in an embodiment of the present application to first train a mask generation model, specifically: obtaining a training sample set, each training sample including a target layout of a chip sample and a mask of the target layout; for at least one training sample in the training sample set, using the target layout of the chip sample in the training sample as the input of the mask generation model to obtain a predicted mask of the target layout; inputting the predicted mask of the target layout into a lithography physical model to obtain a wafer pattern corresponding to the predicted mask of the target layout; determining the complexity of the predicted mask of the target layout based on the sum of the perimeters of multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout; adjusting the parameters of the mask generation model based on the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout until the training stop condition is met to obtain a trained mask generation model. After obtaining a trained mask generation model, the user can upload the target chip layout through the mask generation application installed and running on terminal device 2. Terminal device 2 then sends the uploaded target chip layout to server 1. After server 1 obtains the target chip layout, it inputs the target chip layout into the trained mask generation model and outputs the mask corresponding to the target chip layout. Thus, a mask corresponding to the target chip layout is obtained. Optionally, in one embodiment, the mask generation model can also be trained and the mask generation method can also be executed by the terminal device, but this embodiment does not limit this.

[0058] The technical solutions of the embodiments of the present application are described in detail below:

[0059] FIG2 is a flowchart of a mask generation model training method provided in an embodiment of the present application. The execution subject of the embodiment of the present application is a device having a model training function, such as a model training device, which may be a server, as shown in FIG2 . The method may include:

[0060] S101. Obtain a training sample set, where each training sample includes a target layout of a chip sample and a mask of the target layout.

[0061] Specifically, obtaining the training sample set may include receiving the training sample set. Optionally, a preset number of training samples may be obtained from a sample data set to form the training sample set. The sample data set may be pre-stored.

[0062] Each training sample includes a target layout of a chip sample and a mask of the target layout. This embodiment does not limit the method for obtaining the sample data set.

[0063] As an implementable method, a pixel-based reverse lithography method can be used to obtain a sample data set. Accordingly, the training sample set is obtained in S101, which can be specifically:

[0064] A preset number of sample data are selected from the sample data set, and the preset number of sample data are combined into a training sample set.

[0065] S102 : For at least one training sample in the training sample set, use the target layout of the chip sample in the training sample as an input of the mask generation model to obtain a predicted mask of the target layout.

[0066] S103 , inputting the predicted mask of the target layout into a lithography physical model to obtain a wafer pattern corresponding to the predicted mask of the target layout.

[0067] Specifically, FIG3 is a schematic diagram of a model training process provided by an embodiment of the present application. As shown in FIG3 , after obtaining the training sample set, for at least one training sample in the training sample set, the target layout of the chip sample in the training sample is input into the mask generation model 10. The mask generation model 10 outputs the predicted mask of the target layout of the chip sample. The predicted mask of the target layout is then input into the lithography physics model 20, which outputs the wafer pattern corresponding to the predicted mask of the target layout. The lithography physics model is a lithography physics model that takes process parameters into account. Optionally, for each training sample, after the processing process shown in FIG3 , the target layout of the chip sample in each training sample, the predicted mask of the target layout of the chip sample, and the wafer pattern corresponding to the predicted mask of the target layout of the chip sample can be obtained.

[0068] S104 , determining the complexity of the prediction mask of the target layout according to the sum of the perimeters of the multiple graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout.

[0069] Specifically, the complexity of the mask can be defined as the mask being substantially free of tiny structures such as holes, isolated items, and serrations. Therefore, the complexity of the predicted mask of the target layout can be determined based on the sum of the perimeters of the multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout. In this embodiment, in order to ensure that the mask generated by the mask generation model has a lower complexity, it is necessary to consider the complexity of the predicted mask of the target layout when adjusting the model parameters during the model training process. Therefore, it is necessary to first determine the complexity of the predicted mask of the target layout. For ease of description, Figure 4 is a schematic diagram of the target layout of the chip sample, the predicted mask of the target layout of the chip sample, and the outline of the predicted mask of the target layout of the chip sample. As shown in Figure 4, from left to right are the target layout of the chip sample, the predicted mask of the target layout of the chip sample, and the outline of the predicted mask of the target layout of the chip sample. As can be seen from Figure 4, the prediction mask of the target layout of the chip sample includes holes and isolated items. Figure 4 schematically illustrates a hole 30 and an isolated item 40. It is understandable that the prediction mask of the target layout shown in Figure 4 also includes other isolated items. The sum of the perimeters of the multiple graphics included in the target layout refers to the sum of the perimeters of all graphics included in the target layout. The perimeter of the prediction mask of the target layout refers to the sum of the lengths of the contour lines of the prediction mask of the target layout. The closer the sum of the perimeters of the multiple graphics included in the target layout is to the perimeter of the prediction mask of the target layout, the less complex the target layout prediction mask is. Conversely, the more complex the target layout prediction mask is.

[0070] Optionally, in an implementable manner, S104 may specifically be:

[0071] S1041 . Calculate the contour of the prediction mask of the target layout according to the sum of the square of the first-order derivative of the prediction mask of the target layout along the x direction and the square of the first-order derivative of the prediction mask of the target layout along the y direction.

[0072] S1042: Sum the contour lines of the prediction mask of the target layout to obtain the perimeter of the prediction mask of the target layout.

[0073] S1043. Obtain the sum L of the perimeters of multiple graphics included in the target layout of the chip sample.

[0074] S1044. Calculate the complexity of the prediction mask of the target layout according to the result of dividing the perimeter of the prediction mask of the target layout by L.

[0075] Optionally, in S1044, the complexity L of the predicted mask of the target layout is calculated based on the result of dividing the perimeter of the predicted mask of the target layout by L. c , which can be specifically expressed by the following formula (1):

[0076] in, Represents the predicted mask of the target layout pred The first derivative along the x direction, Represents the predicted mask of the target layout pred The first-order derivative along the y direction, L represents the sum of the perimeters of all graphics included in the target layout, The predicted mask of the target layout is shown in Figure 3. The white color represents the transparent area, the black color represents the shading area or the light blocking area, the white pixel value is 1, and the black color is 0. Therefore, the sum of the predicted mask contours of the target layout is the predicted mask of the target layout. pred The closer its perimeter is to the sum of the perimeters of the multiple graphics included in the target layout, the smaller the complexity of the prediction mask of the target layout, that is, L C On the contrary, the greater the complexity of the target layout's predicted mask, the smaller L C The larger it is. It can be seen that the mask complexity only depends on the shape of the target layout and the shape of the mask, and has nothing to do with the specific optical physics model. It can be used in other optical physics models. Specifically, when the mask generation model trained in the embodiment of the present application is used, the target chip layout is first obtained, the target chip layout is input into the trained mask generation model, and the mask corresponding to the target chip layout is output. During the chip lithography process, the mask corresponding to the target chip layout is input into the lithography physics model, and the wafer pattern corresponding to the predicted mask of the target layout can be obtained. Here, the lithography physics model can be any lithography physics model, and is not limited to the lithography physics model used when training the mask generation model. In the related art, only the lithography physics model used when training the mask generation model can be used, so the mobility is relatively high.

[0077] S105. According to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout, the parameters of the mask generation model are adjusted until the training stop conditions are met to obtain a trained mask generation model.

[0078] Specifically, after determining the complexity of the predicted mask of the target layout, the parameters of the mask generation model can be adjusted according to the target layout of each chip sample in the training sample set obtained in the current iteration process, the wafer pattern corresponding to the predicted mask of the target layout of the chip sample, the mask of the target layout of the chip sample, the predicted mask of the target layout of the chip sample, and the complexity of the predicted mask of the target layout of the chip sample, until the training stop condition is met. The parameters of the mask generation model can be adjusted by gradient descent so that the wafer pattern corresponding to the predicted mask of the target layout of the chip sample is as close as possible to the target layout of the chip sample, the mask of the target layout of the chip sample is as close as possible to the predicted mask of the target layout of the chip sample, and the complexity of the predicted mask of the target layout of the chip sample is reduced (for example, the complexity of the predicted mask is less than a preset threshold), and finally a trained mask generation model is obtained.

[0079] It should be noted that the mask can also be called a mask, and the two concepts are the same.

[0080] Optionally, in one practicable manner, in S105, the parameters of the mask generation model are adjusted according to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout. Specifically, the following steps may be performed:

[0081] S1051. Construct a first loss function according to the target layout of the chip sample and the wafer pattern corresponding to the predicted mask of the target layout.

[0082] S1052: Construct a second loss function based on the mask of the target layout and the predicted mask of the target layout.

[0083] S1053. Construct a target loss function based on the first loss function, the second loss function, and the complexity of the predicted mask of the target layout.

[0084] Optionally, S1053 may specifically be: calculating the target loss function according to the product of the first parameter and the first loss function, the product of the second parameter and the complexity of the predicted mask of the target layout, and the sum of the second loss function.

[0085] As an implementable method, the target loss function L is calculated based on the product of the first parameter and the first loss function, the product of the second parameter and the complexity of the predicted mask of the target layout, and the sum of the second loss function. Specifically, it can be expressed by the following formula (2): L = |Mask pred -Mask| 2 +α*L total +β*L c (2)

[0086] Where Mask represents the mask of the target layout, Mask pred Represents the predicted mask of the target layout, L total Represents the first loss function, |Mask pred -Mask| 2 Represents the second loss function, α is the first parameter, β represents the second parameter, α and β are adjustable parameters, L C It represents the complexity of the predicted mask of the target layout, which can be calculated by the above formula (1).

[0087] Among them, in one practicable manner, L total It can be expressed by the following formula (3):

[0088] Among them, ξ(h μ ) represents the defocusing process parameter distribution function, h μ represents the wafer at a distance h from the focal plane of the lithography machine, σ h represents the broadening of the distribution function. Optionally, in one embodiment, h μ =[h1,h2,h3]=[-80nm,0nm,80nm], μ refers to the subscript of h, and U represents h μ Array length, can be 3, σ h It can be taken as 80;ζ(t q ) represents the exposure dose deviation process parameter distribution function, t q Represents the exposure dose deviation of the lithography machine, σ q represents the broadening of the distribution function. Optionally, in one embodiment, t q =[t1,t2,t3]=[-0.1,0.0,0.1], q refers to the subscript of t, Q refers to t q Array length, which can be 3 here, σ q It can be 0.1; α, κ and β represent adjustable coefficients used to balance the relative sizes of various loss functions, for example, they can be 0.025, 0.06 and 2 respectively. D represents the discrete regularization term, R TV represents the total variation regularization term, L MEPE represents the corrected edge placement error loss function, L Aerial Indicates imaging error.

[0089] Specifically, the imaging error L Aerial The wafer pattern Z corresponding to the predicted mask representing the target layout and the target layout Z t The error between them can be calculated by the following formula (4):

[0090] Where L represents the sum of the perimeters of all graphics in the target layout. The dimension of the imaging error is the unit of length, which is consistent with the dimension of the chip node size. γ is an adjustable parameter, for example, it can be 2. μ and t q It has the same meaning as in the above formula (3).

[0091] The wafer pattern Z corresponding to the predicted mask of the target layout is calculated by a lithography physical model. The lithography physical model can be, for example, a Hopkins diffraction lithography physical model of a partially coherent imaging system. The model obtains the light intensity distribution I (x, y; h μ ), which is obtained by convolution of the mask M and the lithography system kernel function h, and the kernel function is obtained by singular value decomposition of the cross transfer coefficient of the lithography system (for example, a 193 nm ring light source). Optionally, the light intensity distribution I (x, y; h μ ) can be calculated by the following formula (5):

[0092] Among them, h k and ω k They are the kth kernel function and the corresponding weight coefficient after singular value decomposition. In the embodiment of the present application, the first 24 kernel functions and the corresponding weight coefficients after singular value decomposition can be used, that is, K=24, h μ It has the same meaning as in the above formula (3).

[0093] The imaging pattern on the wafer (i.e., wafer pattern Z) is obtained by converting the light intensity distribution I(x, y; h μ ) is converted, the wafer pattern Z can be calculated by the following formula (6):

[0094] Among them, θ z and I th 50 and 0.225 can be used respectively, h μ and t q It has the same meaning as in the above formula (3).

[0095] The optimized mask pixel value is continuously distributed between 0 and 1, which is different from the discrete distribution of the binary mask. The discrete regularization term R is used. D To characterize the difference between the two, R D It can be calculated by the following formula (7):

[0096] Total variation regularization term R TV It can be calculated by the following formula (8):

[0097] Among them, D represents the first-order derivative of the matrix, T represents the matrix transpose, ‖.‖1 represents the 1 norm, represents matrix product, M represents mask, Z t Indicates the target layout.

[0098] Corrected edge placement error loss function L MEPE It can be calculated by the following formula (9): L MEPE =L Aerial-MEPE +αR D-MEPE +κR RV-MEPE (9)

[0099] Among them, L Aerial-MEPE represents the imaging edge placement error, R D-MEPE represents the edge placement error discrete regularization term, R TV-MEPE represents the total variational regularization term of the edge placement error.

[0100] Imaging edge placement error L Aerial-MEPE The definition of can be as follows:

[0101] Among them, MEPE (Modified Edge Placement Error) stands for modified edge placement error. Figure 5 is a schematic diagram of a modified edge placement error. As shown in Figure 5, the matrix composed of black short line data points represents the modified edge placement error, the length of the black short line represents the edge placement error length, and multiple graphics composed of black long lines together constitute the target layout of the chip sample. ⊙ represents the multiplication of corresponding elements of the matrix composed of black short line data points.

[0102] Edge placement error discrete regularization term R D-MEPE The definition can be as follows:

[0103] Edge placement error total variation regularization term R TV-MEPE The definition can be as follows:

[0104] S1044. According to the target loss function, the parameters of the mask generation model are adjusted by a gradient descent algorithm until the training stop condition is met.

[0105] Specifically, the target loss function can be expressed as the above formula (2): L = |Mask pred -Mask| 2 +α*L total +β*L c (2)

[0106] Among them, Mask represents the mask of the target layout, Maskpred Represents the predicted mask of the target layout, L total Represents the first loss function, |Mask pred -Mask| 2 Represents the second loss function, α is the first parameter, β represents the second parameter, α and β are adjustable parameters, L c It represents the complexity of the predicted mask of the target layout, which can be calculated by the above formula (1).

[0107] Among them, the first loss function is calculated based on the target layout of the chip sample and the wafer pattern corresponding to the predicted mask of the target layout. The second loss function is calculated based on the mask of the target layout and the predicted mask of the target layout. The target loss function includes three parts. The target damage function is minimized by the gradient descent algorithm, and then the parameters of the mask generation model are continuously adjusted to make the wafer pattern corresponding to the predicted mask of the target layout of the chip sample and the target layout of the chip sample as close as possible, the mask of the target layout of the chip sample and the predicted mask of the target layout of the chip sample as close as possible, and reduce the complexity of the predicted mask of the target layout of the chip sample (for example, the complexity of the predicted mask is less than a preset threshold).

[0108] Optionally, as an implementable manner, S1054 may specifically be:

[0109] S10541. Calculate the gradient of the target loss function based on the parameters of the mask generation model in the current iterative process.

[0110] Specifically, taking the target loss function shown in formula (2) as an example, the gradient of the target loss function can be calculated by the following formula (13):

[0111] Among them, w represents the parameters of the mask generation model in the current iteration process. When the mask generation model is a deep learning model, the parameters of the mask generation model are the neuron weight parameters. Automatic differentiation can be used to obtain L fit represents the second loss function.

[0112] S10542. Adjust the parameters of the mask generation model according to the optimization direction and optimization step size of the gradient descent algorithm until the training stop condition is met.

[0113] Specifically, the training stop condition may be reaching a preset number of iterative training times, or the gradient of the target loss function reaching a preset value, or other training stop conditions, which are not limited in this embodiment.

[0114] Optionally, in one embodiment, the mask generation model in this embodiment may be a pre-trained model. Accordingly, the method of this embodiment may further include:

[0115] S106 , obtaining a sample data set, where each sample data set includes a target layout of a chip sample and a mask of the target layout of the chip sample.

[0116] Optionally, the sample data set is obtained in S106 by specifically obtaining the sample data set using a pixelation-based inverse lithography method.

[0117] Accordingly, the training sample set is obtained in S101, which may be specifically:

[0118] A preset number of sample data are selected from the sample data set, and the preset number of sample data are combined into a training sample set.

[0119] S107. Train a deep learning model based on the sample data set to obtain a mask generation model.

[0120] In this embodiment, a mask generation model is pre-trained. Here, the process of pre-training the mask generation model can be specifically: obtaining a training sample set, each training sample includes a target layout of a chip sample and a mask of the target layout, for at least one training sample in the training sample set, using the target layout of the chip sample in the training sample as the input of the mask generation model, obtaining a predicted mask of the target layout, calculating a loss function based on the mask of the target layout of the chip sample and the predicted mask of the target layout of the chip sample, adjusting the parameters of the mask generation model based on the loss function until the training stop condition is met, and obtaining a trained mask generation model.

[0121] In this embodiment, the mask generation model is pre-trained and then trained using the pre-trained mask generation model parameters as initial model parameters. The model parameters can be imported first to reduce the amount of calculation and make the model converge faster.

[0122] Optionally, the mask generation model in this embodiment may include an encoder and a decoder, wherein the encoder includes multiple convolutional neural network layers and the decoder includes multiple deconvolutional neural network layers. The specific structure is described in detail in the following embodiments.

[0123] The mask generation model training method provided in this embodiment first obtains a training sample set, and for at least one training sample in the training sample set, inputs the target layout of the chip sample in the training sample into the mask generation model to obtain the predicted mask of the target layout, and then inputs the predicted mask of the target layout into the lithography physical model to obtain the wafer pattern corresponding to the predicted mask of the target layout. The complexity of the predicted mask of the target layout is determined based on the sum of the perimeters of the multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout. Then, based on the target layout of the chip sample and the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout and the predicted mask of the target layout, and the complexity of the predicted mask of the target layout, the parameters of the mask generation model are adjusted until the training stop condition is met, thereby obtaining a trained mask generation model. Therefore, when adjusting the model parameters of the mask generation model, the model parameters are adjusted not only based on the wafer pattern corresponding to the target layout of the chip sample and the predicted mask of the target layout, as well as the target layout's mask and the predicted mask of the target layout, but also based on the complexity of the predicted mask of the target layout. This reduces the complexity of the mask generated by the mask generation model. Furthermore, because the complexity of the predicted mask of the target layout is determined based on the sum of the perimeters of multiple patterns included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout, the complexity of the predicted mask of the target layout depends only on the shape of the target layout and the predicted mask of the target layout. This results in a highly transferable mask generation model and a low computational complexity in the model training process.

[0124] The following describes in detail the process of training the mask generation model using a specific embodiment in conjunction with FIG6 .

[0125] FIG6 is a flowchart of a mask generation model training method provided in an embodiment of the present application. The execution subject of the method may be a server. As shown in FIG6 , the method may include:

[0126] S201 , obtaining a sample data set, where each sample data set includes a target layout of a chip sample and a mask of the target layout of the chip sample.

[0127] Specifically, a pixelation-based inverse photolithography method can be used to acquire a sample data set. The specific acquisition process is described in detail in the following embodiments.

[0128] S202: Pre-train a mask generation model based on a sample data set.

[0129] In this embodiment, by pre-training the mask generation model, the process of pre-training the mask generation model here can be specifically: obtaining a training sample set, each training sample includes a target layout of a chip sample and a mask of the target layout, for at least one training sample in the training sample set, using the target layout of the chip sample in the training sample as the input of the mask generation model, obtaining a predicted mask of the target layout, calculating a loss function based on the mask of the target layout of the chip sample and the predicted mask of the target layout of the chip sample, adjusting the parameters of the mask generation model according to the loss function until the training stop condition is met, and obtaining a trained mask generation model. The mask generation model here can be a deep learning model. After the pre-training is completed, the parameters of the pre-trained mask generation model can be obtained, which can be specifically the neuron weight parameters of the mask generation model.

[0130] S203 , obtaining a training sample set, where each training sample includes a target layout of a chip sample and a mask of the target layout of the chip sample.

[0131] Specifically, after pre-training the mask generation model, the neuron weight parameters of the pre-trained mask generation model are initialized ( S203 ) to the mask generation model to be trained, i.e., the neuron weight parameters of the pre-trained mask generation model are used as the initialization weight parameters of the mask generation model to be trained. Obtaining the training sample set may include selecting a preset number of sample data from the sample data set and forming the preset number of sample data into the training sample set.

[0132] S204. For at least one training sample in the training sample set, use the target layout of the chip sample in the training sample as the input of the mask generation model, output the predicted mask of the target layout, input the predicted mask of the target layout into the lithography physical model, and output the wafer pattern corresponding to the predicted mask of the target layout.

[0133] Specifically, for each training sample in the training sample set, through the processing shown in Figure 3, the target layout of the chip sample in each training sample, the predicted mask of the target layout of the chip sample, and the wafer pattern corresponding to the predicted mask of the target layout of the chip sample can be obtained.

[0134] S205 : Determine the complexity of the prediction mask of the target layout according to the sum of the perimeters of the multiple graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout.

[0135] Specifically, the complexity of the mask can be defined as the mask being basically free of tiny structures such as holes, isolated items, and serrations. Therefore, the complexity of the predicted mask of the target layout can be determined based on the sum of the perimeters of multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout.

[0136] Optionally, in an implementable manner, S205 may specifically be:

[0137] S2051 . Calculate the contour of the prediction mask of the target layout according to the sum of the square of the first-order derivative of the prediction mask of the target layout along the x direction and the square of the first-order derivative of the prediction mask of the target layout along the y direction.

[0138] S2052: Sum the contour lines of the prediction mask of the target layout to obtain the perimeter of the prediction mask of the target layout.

[0139] S2053. Obtain the sum L of the perimeters of multiple graphics included in the target layout of the chip sample.

[0140] S2054 . Calculate the complexity of the prediction mask of the target layout according to the result of dividing the perimeter of the prediction mask of the target layout by L.

[0141] Optionally, in S2054 , the complexity of the predicted mask of the target layout is calculated based on the result of dividing the perimeter of the predicted mask of the target layout by L, which can be specifically expressed by the above formula (1).

[0142] S206. According to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout, the parameters of the mask generation model are adjusted until the training stop conditions are met to obtain a trained mask generation model.

[0143] Optionally, in one practicable manner, in S206, the parameters of the mask generation model are adjusted according to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout. Specifically, the adjustment may be:

[0144] S2061. Construct a first loss function according to the target layout of the chip sample and the wafer pattern corresponding to the predicted mask of the target layout.

[0145] S2062: Construct a second loss function based on the mask of the target layout and the predicted mask of the target layout.

[0146] S2063. Construct a target loss function according to the first loss function, the second loss function, and the complexity of the predicted mask of the target layout.

[0147] As an implementable method, the target loss function L is constructed based on the first loss function, the second loss function and the complexity of the predicted mask of the target layout, which can be specifically expressed by the above formula (2).

[0148] Among them, in one practicable manner, L total It can be expressed by the above formula (3):

[0149] S2064. According to the target loss function, the parameters of the mask generation model are adjusted by a gradient descent algorithm until the training stop condition is met.

[0150] Among them, the first loss function is calculated based on the target layout of the chip sample and the wafer pattern corresponding to the predicted mask of the target layout. The second loss function is calculated based on the mask of the target layout and the predicted mask of the target layout. The target loss function includes three parts. The target damage function is minimized by the gradient descent algorithm, and then the parameters of the mask generation model are continuously adjusted to make the wafer pattern corresponding to the predicted mask of the target layout of the chip sample and the target layout of the chip sample as close as possible, the mask of the target layout of the chip sample and the predicted mask of the target layout of the chip sample as close as possible, and reduce the complexity of the predicted mask of the target layout of the chip sample (for example, the complexity of the predicted mask is less than a preset threshold).

[0151] Optionally, as an implementable manner, S2064 may specifically be:

[0152] S20641. Calculate the gradient of the target loss function based on the parameters of the mask generation model in the current iterative process.

[0153] Specifically, taking the target loss function shown in formula (2) as an example, the gradient of the target loss function can be calculated by the following formula (13):

[0154] Among them, w represents the parameters of the mask generation model in the current iteration process. When the mask generation model is a deep learning model, the parameters of the mask generation model are the neuron weight parameters. Automatic differentiation can be used to obtain L fit represents the second loss function.

[0155] S20642. Adjust the parameters of the mask generation model according to the optimization direction and optimization step size of the gradient descent algorithm until the training stop condition is met.

[0156] Specifically, the above w is adjusted until a training stop condition is met, where the training stop condition may be reaching a preset number of iterative training times, or other training stop conditions, which are not limited in this embodiment.

[0157] The mask generation model training method provided in this embodiment, when training the mask generation model, inputs the target layout of the chip sample in the training sample into the mask generation model to obtain a predicted mask of the target layout, then inputs the predicted mask of the target layout into the lithography physical model to obtain a wafer pattern corresponding to the predicted mask of the target layout. The complexity of the predicted mask of the target layout is determined based on the sum of the perimeters of multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout, and a target loss function is constructed based on the wafer pattern corresponding to the target layout of the chip sample and the predicted mask of the target layout, the mask of the target layout and the predicted mask of the target layout, and the complexity of the predicted mask of the target layout. Through gradient descent, the wafer pattern corresponding to the predicted mask of the target layout is made closer and closer to the target layout of the chip sample, the mask of the target layout of the chip sample is as close as possible to the predicted mask of the target layout of the chip sample, and the complexity of the predicted mask of the target layout of the chip sample is reduced. This reduces the complexity of the mask generated by the trained mask generation model. Moreover, since the complexity of the predicted mask of the target layout is determined based on the sum of the perimeters of multiple graphics included in the target layout of the chip sample and the perimeter of the predicted mask of the target layout, the complexity of the predicted mask of the target layout only depends on the shape of the target layout and the predicted mask of the target layout. Therefore, the trained mask generation model has higher mobility and the computational complexity of the model training process is lower.

[0158] The following details the use of a pixelation-based inverse lithography method to obtain a sample dataset. The method for obtaining the sample dataset may include:

[0159] S1. Determine the loss function.

[0160] Specifically, determine the loss function L total It can be expressed by the following formula (3):

[0161] The definitions of the various parameters in the loss function can be found in the description of the embodiment shown in FIG1 , and will not be repeated here.

[0162] S2. Initialize the mask.

[0163] Specifically, the modified chip layout is adopted in this embodiment, namely where Z t is the target layout of the chip sample, w1 and w2 can be taken as 0.98 and 0.1 respectively, so that the calculated gradient will not be too small, which is conducive to the subsequent gradient descent. In addition, the discontinuous optimization of the binary mask is very difficult, so in this embodiment, the sigmoid function is used to transform the discrete optimization problem of the mask into a continuous optimization problem, that is, where θ M and M thThe sigmoid function can also act as a filter to filter out small complex structures (islands, hollows, serrations, and protrusions) in the generated mask, thereby increasing the manufacturability of the mask.

[0164] S3. Calculation optimization direction.

[0165] For the steepest descent method, the optimization direction is the loss function L total About the gradient of the mask For the conjugate gradient method, the initial descent direction is The subsequent descent direction retains the optimization direction of the previous step, and the conjugate gradient factor η is automatically adjusted. k To avoid optimization stagnation. Loss function L total The gradient of can be defined by the following formula (14):

[0166] in θ M and M th 4 and 0.225 can be used respectively.

[0167] Imaging error L Aerial The gradient of can be defined by the following formula (15):

[0168] Among them, θ M and θ Z Take 4 and 50 respectively, H * is the complex conjugate of the lithography system kernel function H, H flip H flip 180 ° Get, Represents the matrix convolution operation, and L represents the sum of the perimeters of all graphics in the target layout.

[0169] Discrete regularization term R D The gradient of can be defined by the following formula (16):

[0170] Total variation regularization term R TV The gradient of can be defined by the following formula (17):

[0171] Where sign represents the sign function, that is, sign(x) = 0, x = 0; sign(x) = 1, x> 0; sign(x) = -1, x< 0

[0172] Imaging edge placement error L Aerial-MEPE The gradient of can be defined by the following formula (18):

[0173] Edge placement error discrete regularization term R D-MEPE The gradient of can be defined by the following formula (19):

[0174] Edge placement error total variation regularization term R TV-MEPE The gradient of can be defined by the following formula (20):

[0175] S4. Update the mask according to the optimization direction.

[0176] Specifically, the optimization step size can be The step factor ε is a small value, such as 0.1. The mask is updated according to the optimization direction, specifically the pixel value of the mask is updated. The updated mask pixel value may exceed 1 or be less than 0. The sigmoid function can be used to fix the mask value to between 0 and 1. The updated mask M i This is the mask before updating.

[0177] S5. Repeat S3 and S4 until the optimization process reaches the preset number of iterative training times or the gradient reaches the expected value.

[0178] Specifically, in one practicable manner, S3 and S4 are repeated until the optimization process reaches a preset number of iterative training times, for example, the preset number of iterative training times is 1000. The optimization process is stopped when the number of iterative training times reaches 1000. In another practicable manner, S3 and S4 are repeated until the optimization process reaches an expected value, and the optimization process is stopped. The expected value of the gradient can be preset.

[0179] S6. Binarize the optimized mask, that is, take 1 if the pixel value in the mask exceeds 0.5, and take 0 if the pixel value is less than 0.5.

[0180] Finally, the optimized mask is the mask of the target layout. For the target layout of each chip sample, the mask of the target layout of the chip sample is obtained by the above method.

[0181] The following experimental data further illustrates the technical effects of the mask generation model training method provided in the embodiments of the present application.

[0182] To verify the effectiveness of the mask generation model training method and apply it to the design of photolithography masks for chip layouts, this example selected a widely used public photolithography mask dataset. These datasets contain a total of 10,271 chip layouts and corresponding masks. The chip layouts meet the 32nm process node and are generated using certain design rules. The masks in this photolithography mask dataset were generated using the aforementioned pixelation-based inverse lithography method.

[0183] Using the above-mentioned photolithography mask dataset, a mask generation model is trained according to the mask generation model training method provided in an embodiment of the present application to obtain a mask generation model.

[0184] Figure 7 is a schematic diagram for comparing mask effects provided by an embodiment of the present application. As shown in Figure 7, the four columns in Figure 7 represent the target layout, the mask of the target layout, the wafer pattern, and the difference between the target layout and the wafer pattern, respectively. For the same target layout (the first column of target layouts as shown in Figure 7), the first line is the mask, wafer pattern, and the difference between the target layout and the wafer pattern generated by the mask generation model training method provided by the embodiment of the present application. The second line is the mask, wafer pattern, and the difference between the target layout and the wafer pattern generated by an existing mask optimization algorithm. The third line is the mask, wafer pattern, and the difference between the target layout and the wafer pattern generated by an existing reverse lithography mask optimization algorithm. After comparing the three, it can be seen that the method provided by the embodiment of the present application has the lowest complexity of the mask generated, without holes, isolated items, sawtooth and other tiny structures, and the target layout is closest to the wafer pattern.

[0185] FIG8 is a schematic diagram of a mask effect comparison provided by an embodiment of the present application. As shown in FIG8 , the four columns in FIG8 represent the target layout, the mask of the target layout, the wafer pattern, and the difference between the target layout and the wafer pattern, respectively. For the same target layout (the first column of target layouts shown in FIG8 ), the first line is the mask, wafer pattern, and the difference between the target layout and the wafer pattern generated by the mask generation model training method provided by the embodiment of the present application. The second line is the mask, wafer pattern, and the difference between the target layout and the wafer pattern generated by an existing mask optimization algorithm. The third line is the mask, wafer pattern, and the difference between the target layout and the wafer pattern generated by an existing reverse lithography mask optimization algorithm. After comparing the three, it can be seen that the method provided by the embodiment of the present application has the lowest complexity of the mask generated, without holes, isolated items, sawtooth and other tiny structures, and the target layout is closest to the wafer pattern. The masks generated by the other two methods are more complex, with holes and isolated items.

[0186] Optionally, the mask generation model in this embodiment may include an encoder and a decoder, the encoder includes multiple convolutional neural network layers, and the decoder includes multiple deconvolutional neural network layers. In one practicable manner, the encoder includes 8 convolutional neural network layers, and the decoder includes 8 deconvolutional neural network layers. Specifically, the 8 convolutional layers are respectively composed of 8 3×3 filters, 16 3×3 filters, 32 3×3 filters, 64 3×3 filters, 128 3×3 filters, 256 3×3 filters, 512 3×3 filters, and 1024 3×3 filters. A batch normalization layer is established after each convolution layer and the subsequent activation function adopts a rectified linear unit (ReLU). After inputting the target chip layout (dimension (256, 256, 1)), the final output (dimension (1, 1, 1024)) is used as the decoder input. The first seven deconvolution layers consist of 1024 3×3 filters, 512 3×3 filters, 256 3×3 filters, 128 3×3 filters, 64 3×3 filters, 32 3×3 filters, and 16 3×3 filters, respectively. After each deconvolution layer, a batch normalization layer is established and the Leaky Rectified Linear Unit (Leaky-ReLU) is used as the subsequent activation function. Finally, a deconvolutional neural network layer consisting of 8 3×3 filters and a sigmoid activation function produces a predicted mask of dimension (256, 256, 1) with values ​​ranging from 0 to 1. The mask is then binarized to obtain the final mask.

[0187] FIG9 is a flowchart of a mask generation method provided in an embodiment of the present application. The execution subject of the method may be a server. As shown in FIG9 , the method may include:

[0188] S301, obtaining the target chip layout.

[0189] S302: Input the target chip layout into the trained mask generation model, and output the mask corresponding to the target chip layout.

[0190] The mask generation model is trained according to the method of the embodiment shown in FIG. 2 or FIG. 6 .

[0191] The mask generation method provided in this embodiment can generate a mask with lower complexity through a mask generation model, and can provide a higher-quality mask for subsequent chip lithography processes, thereby reducing mask calculation time and manufacturing costs.

[0192] FIG10 is a schematic structural diagram of a mask generation model training device provided in an embodiment of the present application. As shown in FIG11 , the device may include: an acquisition module 11 , a processing module 12 , a determination module 13 and a parameter adjustment module 14 .

[0193] The acquisition module 11 is used to acquire a training sample set, each training sample including a target layout of a chip sample and a mask of the target layout.

[0194] The processing module 12 is configured to use a target layout of a chip sample in the training sample as an input of a mask generation model for at least one training sample in the training sample set.

[0195] The processing module 12 is further configured to obtain a predicted mask of a target layout, input the predicted mask of the target layout into a lithography physical model, and obtain a wafer pattern corresponding to the predicted mask of the target layout.

[0196] The determination module 13 is configured to determine the complexity of the prediction mask of the target layout according to the sum of the perimeters of the plurality of graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout.

[0197] The parameter adjustment module 14 is used to adjust the parameters of the mask generation model according to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout until the training stop condition is met to obtain a trained mask generation model.

[0198] In one embodiment, the determination module 13 is configured to: calculate the contour line of the predicted mask of the target layout according to the sum of the square of the first-order derivative of the predicted mask of the target layout along the x-direction and the square of the first-order derivative of the predicted mask of the target layout along the y-direction;

[0199] Sum the contour lines of the predicted mask of the target layout to obtain the perimeter of the predicted mask of the target layout;

[0200] Obtaining the sum L of perimeters of multiple graphics included in the target layout of the chip sample;

[0201] The complexity of the prediction mask of the target layout is calculated according to the result of dividing the perimeter of the prediction mask of the target layout by L.

[0202] In one embodiment, the parameter adjustment module 14 is configured to:

[0203] Constructing a first loss function according to a target layout of the chip sample and a wafer pattern corresponding to a predicted mask of the target layout;

[0204] Constructing a second loss function according to the mask of the target layout and the predicted mask of the target layout;

[0205] Constructing a target loss function according to the first loss function, the second loss function, and the complexity of the predicted mask of the target layout;

[0206] According to the target loss function, the parameters of the mask generation model are adjusted through the gradient descent algorithm until the training stop condition is met.

[0207] In one embodiment, the parameter adjustment module 14 is specifically configured to:

[0208] The target loss function is calculated according to the product of the first parameter and the first loss function, the product of the second parameter and the complexity of the predicted mask of the target layout, and the sum of the second loss function.

[0209] In one embodiment, the parameter adjustment module 14 is specifically configured to:

[0210] Calculate the gradient of the target loss function based on the parameters of the mask generation model in the current iteration;

[0211] According to the optimization direction and optimization step size of the gradient descent algorithm, the parameters of the mask generation model are adjusted until the training stop conditions are met.

[0212] In one embodiment, the mask generation model is a pre-trained model, and the acquisition module 11 is further configured to:

[0213] Acquire a sample data set, where each sample data set includes a target layout of a chip sample and a mask of the target layout;

[0214] The processing module 12 is further configured to train a deep learning model based on the sample data set to obtain a mask generation model.

[0215] In one embodiment, the acquisition module 11 is specifically configured to:

[0216] A sample dataset was acquired using a pixelation-based inverse lithography approach;

[0217] A preset number of sample data are selected from the sample data set, and the preset number of sample data are combined into a training sample set.

[0218] In one embodiment, the mask generation model includes an encoder and a decoder, the encoder includes multiple convolutional neural network layers, and the decoder includes multiple deconvolutional neural network layers.

[0219] FIG11 is a schematic structural diagram of a mask generating device provided in an embodiment of the present application. As shown in FIG11 , the device may include: an acquisition module 21 and a processing module 22 .

[0220] The acquisition module 21 is used to acquire the target chip layout.

[0221] The processing module 22 is used to input the target chip layout into the trained mask generation model and output the mask corresponding to the target chip layout. The mask generation model is trained according to the method of the embodiment shown in FIG1 .

[0222] It should be understood that the device embodiments and method embodiments may correspond to each other, and similar descriptions may refer to the method embodiments. To avoid repetition, they will not be described here. Specifically, the mask generation model training device shown in FIG10 or the mask generation device shown in FIG11 can execute the method embodiments corresponding to the terminal device or server, and the aforementioned and other operations and / or functions of each module in the device are respectively for implementing the method embodiments corresponding to the terminal device or server. For the sake of brevity, they will not be described here.

[0223] The mask generation model training device and mask generation device of the embodiment of the present application are described above from the perspective of functional modules in conjunction with the accompanying drawings. It should be understood that the functional module can be implemented in the form of hardware, can be implemented by instructions in the form of software, or can be implemented by a combination of hardware and software modules. Specifically, the steps of the method embodiment in the embodiment of the present application can be completed by the hardware integrated logic circuit and / or software instructions in the processor, and the steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. Optionally, the software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method embodiment in combination with its hardware.

[0224] FIG12 is a schematic block diagram of a computer device 300 provided in an embodiment of the present application.

[0225] As shown in FIG12 , the computer device 300 may include:

[0226] The memory 310 and the processor 320 are configured to store computer programs and transmit the program code to the processor 320. In other words, the processor 320 can call and run the computer program from the memory 310 to implement the method in the embodiment of the present application.

[0227] For example, the processor 320 may be configured to execute the above method embodiments according to instructions in the computer program.

[0228] In some embodiments of the present application, the processor 320 may include but is not limited to:

[0229] General-purpose processor, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.

[0230] In some embodiments of the present application, the memory 310 includes but is not limited to:

[0231] Volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0232] In some embodiments of the present application, the computer program may be divided into one or more modules, which are stored in the memory 310 and executed by the processor 320 to implement the method provided by the embodiment of the present application. The one or more modules may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0233] As shown in FIG12 , the computer device may further include:

[0234] The transceiver 330 may be connected to the processor 320 or the memory 310 .

[0235] The processor 320 may control the transceiver 330 to communicate with other devices. Specifically, the processor 320 may send information or data to other devices or receive information or data sent by other devices. The transceiver 330 may include a transmitter and a receiver. The transceiver 330 may further include one or more antennas.

[0236] It should be understood that the various components in the electronic device are connected via a bus system, wherein the bus system includes not only a data bus but also a power bus, a control bus and a status signal bus.

[0237] The present application also provides a computer storage medium having a computer program stored thereon, which, when executed by a computer, enables the computer to perform the method of the above-mentioned method embodiment. In other words, the present application also provides a computer program product containing instructions, which, when executed by a computer, enables the computer to perform the method of the above-mentioned method embodiment.

[0238] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0239] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0240] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0241] Modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules may be selected based on actual needs to achieve the purpose of the solution of this embodiment. For example, the functional modules in each embodiment of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module.

[0242] The above content is merely a specific implementation of the embodiments of the present application, but the scope of protection of the embodiments of the present application is not limited thereto. Any person skilled in the art who can easily conceive of changes or substitutions within the technical scope disclosed in the embodiments of the present application should be included in the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the embodiments of the present application should be based on the scope of protection of the claims.

Claims

1. A mask generation model training method, characterized in that: include: Acquire a training sample set, each training sample including a target layout of a chip sample and a mask of the target layout; For at least one training sample in the training sample set, using the target layout of the chip sample in the training sample as the input of the mask generation model to obtain a predicted mask of the target layout; Inputting the predicted mask of the target layout into a lithography physical model to obtain a wafer pattern corresponding to the predicted mask of the target layout; Determining the complexity of the prediction mask of the target layout according to the sum of the perimeters of the plurality of graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout; According to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout and the complexity of the predicted mask of the target layout, the parameters of the mask generation model are adjusted until the training stop condition is met to obtain a trained mask generation model.

2. The method according to claim 1, characterized in that Determining the complexity of the prediction mask of the target layout according to the sum of the perimeters of the plurality of graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout includes: Calculating a contour line of the prediction mask of the target layout according to the sum of the square of the first-order derivative of the prediction mask of the target layout along the x-direction and the square of the first-order derivative of the prediction mask of the target layout along the y-direction; Summing the contour lines of the prediction mask of the target layout to obtain the perimeter of the prediction mask of the target layout; Obtaining the sum L of the perimeters of a plurality of graphics included in the target layout of the chip sample; The complexity of the prediction mask of the target layout is calculated according to the result of dividing the perimeter of the prediction mask of the target layout by the L.

3. The method according to claim 1 or 2, characterized in that: The step of adjusting the parameters of the mask generation model according to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout until the training stop condition is met includes: Constructing a first loss function according to a target layout of the chip sample and a wafer pattern corresponding to a predicted mask of the target layout; Constructing a second loss function according to the mask of the target layout and the predicted mask of the target layout; Constructing a target loss function according to the first loss function, the second loss function and the complexity of the predicted mask of the target layout; According to the target loss function, the parameters of the mask generation model are adjusted by a gradient descent algorithm until a training stop condition is met.

4. The method according to claim 3, characterized in that: The constructing a target loss function according to the first loss function, the second loss function and the complexity of the predicted mask of the target layout includes: The target loss function is calculated based on the product of the first parameter and the first loss function, the product of the second parameter and the complexity of the predicted mask of the target layout, and the sum of the second loss function.

5. The method according to claim 3, characterized in that: The step of adjusting the parameters of the mask generation model according to the target loss function by using a gradient descent algorithm until a training stop condition is met includes: Calculating the gradient of the target loss function according to the parameters of the mask generation model in the current iteration process; According to the optimization direction and optimization step size of the gradient descent algorithm, the parameters of the mask generation model are adjusted until the training stop condition is met.

6. The method according to any one of claims 1 to 5, characterized in that: The mask generation model is a pre-trained model, and the method further includes: Acquire a sample data set, each sample data including a target layout of a chip sample and a mask of the target layout; A deep learning model is trained according to the sample data set to obtain the mask generation model.

7. The method according to claim 6, characterized in that The obtaining of the sample data set comprises: A sample dataset was acquired using a pixelation-based inverse lithography approach; The step of obtaining a training sample set includes: A preset number of sample data are selected from the sample data set, and the preset number of sample data are combined into the training sample set.

8. The method according to any one of claims 1 to 7, characterized in that: The mask generation model includes an encoder and a decoder, the encoder includes multiple convolutional neural network layers, and the decoder includes multiple deconvolutional neural network layers.

9. A mask generation method, characterized in that: include: Obtain the target chip layout; The target chip layout is input into a trained mask generation model, and a mask corresponding to the target chip layout is output, wherein the mask generation model is trained according to the method according to any one of claims 1-8.

10. A mask generation model training device, characterized in that: include: An acquisition module, used for acquiring a training sample set, each training sample including a target layout of a chip sample and a mask of the target layout; A processing module, for obtaining a predicted mask of at least one training sample in the training sample set by taking a target layout of a chip sample in the training sample as an input of a mask generation model; The processing module is also used to: input the predicted mask of the target layout into a lithography physical model to obtain a wafer pattern corresponding to the predicted mask of the target layout; A determination module, configured to determine the complexity of the prediction mask of the target layout according to the sum of the perimeters of the plurality of graphics included in the target layout of the chip sample and the perimeter of the prediction mask of the target layout; A parameter adjustment module is used to adjust the parameters of the mask generation model according to the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout and the complexity of the predicted mask of the target layout, until the training stop condition is met to obtain a trained mask generation model.

11. A mask generating device, characterized in that: include: An acquisition module is used to acquire the target chip layout; A processing module is used to input the target chip layout into a trained mask generation model and output a mask corresponding to the target chip layout, wherein the mask generation model is trained according to the method according to any one of claims 1-8.

12. A computer device, characterized in that: include: A processor and a memory, the memory being used to store a computer program, and the processor being used to call and run the computer program stored in the memory to execute the method according to any one of claims 1 to 8 or 9.

13. A computer-readable storage medium, characterized in that: The invention comprises instructions which, when executed on a computer program, cause the computer to perform the method as claimed in any one of claims 1 to 8 or 9.

14. A computer program product comprising instructions, characterized in that When the instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 8 or 9.

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