Manufacturing method for memory device, and memory device

Abstract

Disclosed in the present invention are a manufacturing method for a memory device, and a memory device. The manufacturing method comprises: providing a semiconductor substrate, comprising a base and a first groove formed from the surface of the base to the base; forming a gate insulating layer and a first gate material layer on the surface of the base and in the first groove, or forming the gate insulating layer and the first gate material layer in the first groove; removing part of the first gate material layer and part of the gate insulating layer to form a contact window on the surface of the base or the sidewall of the first groove; forming a second gate on the contact window, wherein the second gate is in contact with the base, and a continuous lattice configuration is formed between the second gate and the base; and forming an island-shaped structure, wherein the residual first gate material layer in the island-shaped structure serves as a first gate, the first gate is in contact with the second gate and is separated from the base by means of the gate insulating layer, and the first gate and the second gate form a semi-floating gate of a memory cell in the memory device. Therefore, the present application can effectively improve the interface flatness of the contact window in a semi-floating gate structure, and improve the storage performance of the memory device.

Description

Method for manufacturing a memory device and memory device

[0001]

Cross-reference

[0002] This application claims priority to Chinese patent application No. CN202310993856.2 filed on August 7, 2023, the entire contents of which are incorporated herein by reference.

Technical field

[0003] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a memory device and the memory device. [Background Technology]

[0004] In the application process of integrated circuits, the performance of various devices will be affected by the interface between the layers of materials, especially memory devices. Because the interface flatness between the layers of materials is different, the storage performance of the memory device is affected.

[0005] During actual operation, the researchers of this application discovered that in the current memory device manufacturing scheme, etching is generally used to form a contact window to expose the substrate, thereby forming a semi-floating gate structure. In the process of forming the semi-floating gate structure, the interface at the contact window will become uneven, affecting the storage performance of the memory device.

[0006] [Summary of the invention]

[0007] According to various embodiments of the present application, a method for manufacturing a memory device and a memory device are provided.

[0008] The present application provides a method for manufacturing a memory device, comprising: providing a semiconductor base, wherein the semiconductor base includes a substrate and a first groove opened from the substrate surface toward the substrate; forming a gate insulating layer and a first gate material layer on the substrate surface and in the first groove, or forming a gate insulating layer and a first gate material layer in the first groove, wherein the first gate material layer fills the first groove; removing a portion of the first gate material layer and the gate insulating layer to form a contact window on the substrate surface or the sidewall of the first groove; forming a second gate on the contact window, wherein the second gate contacts the substrate and has a continuous lattice structure with the substrate; forming an island structure, wherein the island structure covers the first groove, the first gate material layer remaining in the island structure serves as a first gate, the first gate contacts the second gate and is separated from the substrate by the gate insulating layer, and the first gate and the second gate constitute a semi-floating gate of a memory cell in the memory device.

[0009] On the other hand, the present application provides a memory device comprising a substrate, a groove, and an island structure; wherein the groove extends from a side surface of the substrate toward the substrate; the island structure at least fills the groove, and the island structure comprises a first gate and a second gate, the second gate contacts the substrate through a contact window and has a continuous lattice structure with the substrate, and the first gate is separated from the substrate by a gate insulating layer, wherein the first gate and the second gate contact and constitute a semi-floating gate of a memory cell in the memory device, and the contact window is located on the surface of the substrate or on the sidewall of the groove.

[0010] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description, drawings, and claims.

Brief Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0012] FIG1 is a schematic flow chart of a first embodiment of a method for manufacturing a memory device in the present application;

[0013] FIG2 is a schematic structural diagram of an embodiment of a semiconductor substrate in the present application;

[0014] 3 is a schematic structural diagram of a first embodiment of forming a gate insulating layer and a first gate material layer in the present application;

[0015] FIG4 is a schematic structural diagram of a first embodiment of forming a contact window in the present application;

[0016] FIG5 is a schematic structural diagram of a first embodiment of growing a second gate in the present application;

[0017] FIG6 is a structural diagram of the first embodiment of continuing to form the first gate material in this application;

[0018] FIG7 is a structural diagram of a first embodiment of patterning the first gate material layer in the present application;

[0019] FIG8 is a schematic structural diagram of a first embodiment of forming an inter-gate dielectric layer in the present application;

[0020] FIG9 is a schematic structural diagram of a first embodiment of forming a third gate material layer in the present application;

[0021] FIG10 is a schematic structural diagram of a first embodiment of an island structure formed in the present application;

[0022] FIG11 is a schematic structural diagram of a second embodiment of forming a gate insulating layer and a first gate material layer in the present application;

[0023] FIG12 is a schematic structural diagram of a second embodiment of forming a contact window in the present application;

[0024] FIG13 is a schematic structural diagram of a second embodiment of forming a second gate in the present application;

[0025] FIG14 is a schematic structural diagram of a second embodiment of forming an inter-gate dielectric layer and a third gate material layer in the present application;

[0026] FIG15 is a schematic structural diagram of a second embodiment of an island structure formed in the present application;

[0027] FIG16 is a schematic structural diagram of a third embodiment of forming an inter-gate dielectric layer and a third gate material layer in the present application.

[0028] In the drawings, there are a semiconductor body 100 , a substrate 110 , a first groove 101 , a gate insulating layer 200 , a first gate material layer 300 , a second groove 201 , a first gate 310 , a second gate 400 , an inter-gate dielectric layer 500 , a third gate material layer 600 , and a third gate 610 . [Specific implementation method]

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back, etc.) are only used to explain the relative positional relationship and movement of the various components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to such process, method, product, or device.

[0031] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0033] Traditional floating-gate transistors tunnel electrons through the high-barrier silicon dioxide insulating dielectric with a bandgap of 8.9 eV, while semi-floating gates tunnel through silicon with a bandgap of 1.1 eV. This significantly reduces the tunneling barrier, enabling faster data write and erase at low voltages and meeting the chip's low-power requirements. In current memory device manufacturing, etching is generally used to form contact windows, exposing the substrate and forming a semi-floating gate structure. However, during the formation of the semi-floating gate structure, the etching process can lead to an uneven interface at the contact window and potentially damage the substrate. During operation, the memory device is affected by trapped charge at the damaged contact window interface, resulting in significant variations in data storage time, which in turn affects the device's storage performance.

[0034] Therefore, a method for manufacturing a memory device is provided, which can effectively improve the interface flatness of the contact window in the semi-floating gate structure and enhance the storage performance of the memory device.

[0035] Please refer to FIG. 1 , which is a schematic flow chart of a method for manufacturing a memory device in this application.

[0036] As shown in FIG1 , the method for manufacturing a memory device of the present application includes:

[0037] S11, providing a semiconductor base, the semiconductor base comprising a substrate and a first groove extending from a surface of the substrate toward the substrate;

[0038] S12, forming a gate insulating layer and a first gate material layer on the substrate surface and in the first groove, or forming a gate insulating layer and a first gate material layer in the first groove, wherein the first gate material layer fills the first groove;

[0039] S13, removing a portion of the first gate material layer and the gate insulating layer to form a contact window on the substrate surface or the sidewall of the first groove; forming a second gate on the contact window, wherein the second gate contacts the substrate and has a continuous lattice structure with the substrate;

[0040] S14. An island structure is formed, wherein the island structure covers the first groove, the first gate material layer remaining in the island structure serves as a first gate, the first gate contacts the second gate, and is separated from the substrate by a gate insulating layer, and the first gate and the second gate constitute a semi-floating gate of a storage unit in the memory device.

[0041] The following Figures 2-10 are schematic structural diagrams of the method for manufacturing the memory device in the first embodiment.

[0042] The operation flow of step S11 in the embodiment is as follows:

[0043] First, a semiconductor body is provided, wherein the semiconductor body includes a substrate and a first groove opened from a surface of the substrate toward the substrate.

[0044] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).

[0045] Please refer to FIG. 2 , which is a schematic structural diagram of a semiconductor substrate according to an embodiment of the present application.

[0046] The semiconductor body 100 includes a substrate 110 and a first groove 101 formed from a surface of the substrate 110 toward the substrate 110 .

[0047] In some embodiments, a doped region may be formed by ion implantation in the substrate 110, such that the substrate 110 is a substrate having a doped region. For example, the substrate may have a deep P-type well region and an N-type well region above the deep P-type well region, and the first recess 101 may extend into the substrate, with the bottom of the first recess 101 partially exposing the deep P-type well region.

[0048] In some embodiments, the gate insulating layer 200 may be a nitride layer, an oxide layer, an oxynitride layer, etc., such as at least one of silicon nitride, silicon oxide, and silicon oxynitride. In the following embodiments, the gate insulating layer 200 is silicon oxide.

[0049] In some embodiments, a plurality of spaced-apart first grooves 101 are opened in the active area from one side surface of the substrate 110 toward the substrate 110, wherein the plurality of first grooves 101 are distributed sequentially along the second direction. In the first direction, a plurality of active areas are defined by the shallow trench isolation structure, and the first direction and the second direction are directions perpendicular to each other in the same horizontal plane.

[0050] The operation flow of step S12 in an embodiment is as follows:

[0051] A gate insulating layer and a first gate material layer are formed on the surface of the substrate and in the first groove, wherein the first gate material layer fills the first groove.

[0052] Please refer to FIG. 3 , which is a structural diagram of a first embodiment of forming a gate insulating layer and a first gate material layer in the present application.

[0053] As shown in Figure 3, a gate insulation layer 200 is sequentially formed on the surface of the substrate 110 and the sidewalls of the first groove 101, and a first gate material layer 300 is covered on the gate insulation layer 200, and the first gate material layer 300 fills the first groove 101, so that the gate insulation layer 200 and the first gate material layer 300 cover the surface of the substrate 110 and the sidewalls of the first groove 101.

[0054] In some embodiments, after forming the first gate material layer 300 , a chemical mechanical polishing process is further performed on the surface of the first gate material layer 300 to planarize the surface of the first gate material layer 300 .

[0055] Next, a portion of the first gate material layer and the gate insulating layer is removed to form a contact window on the substrate surface; and a second gate is formed on the contact window, wherein the second gate contacts the substrate and has a continuous lattice structure with the substrate.

[0056] The operation flow of step S13 in an embodiment is as follows:

[0057] A portion of the first gate material layer 300 and the gate insulation layer 200 is patterned to form a contact window on the surface of the substrate 110 , exposing a portion of the substrate 110 .

[0058] Please refer to FIG. 4 , which is a structural diagram of a first embodiment of forming a contact window in the present application.

[0059] As shown in FIG4 , the first gate material layer 300 and the gate insulation layer 200 are patterned on one side of the first groove 101 to form a second groove 201 , wherein the bottom of the second groove 201 exposes the substrate 110 to form a corresponding contact window.

[0060] In some embodiments, patterning may be performed using photolithography, dry etching, and / or wet etching.

[0061] Before growing the second gate, the substrate 110 is exposed due to patterning, so that a natural oxide layer naturally grows on the exposed portion of the substrate 110. Therefore, the following steps are also included:

[0062] The native oxide layer formed naturally on the exposed portion of the substrate 110 at the contact window is removed.

[0063] The removal of the naturally formed native oxide layer on the exposed portion of the substrate 110 needs to be performed within a certain temperature range and under corresponding reaction gases. Specifically, the native oxide layer is removed using a first reaction gas within a first temperature range, such as 900-1000 degrees Celsius.

[0064] In some embodiments, the first reaction gas may be a gas that reacts with the oxide layer to remove the natural oxide layer, such as hydrogen gas, HF gas, etc., or a combination of two or more gases.

[0065] A second gate material is then epitaxially grown on the exposed portion of substrate 110 using a second reactant gas and a third reactant gas. This second gate material serves as second gate 400. The second reactant gas can be a silicon source gas, such as silane (SiH4) or dichlorosilane (SiH2Cl2), or a combination of two or more gases. The third reactant gas can be hydrogen chloride (HCl). Removal of the native oxide layer and epitaxial growth of the second gate material are performed in the same chamber to prevent re-formation of the oxide layer during chamber transfer after removal of the native oxide layer.

[0066] That is, at 900-1000 degrees Celsius, hydrogen and / or HF gas is used to remove the natural oxide layer; then, a second gate material is grown in the second groove 201 by epitaxial growth using silicon source gas to serve as the second gate 400, and hydrogen chloride gas is introduced at the same time so that the second gate material grows only in the exposed area of ​​the substrate 110.

[0067] Please refer to FIG. 5 , which is a structural diagram of a first embodiment of growing a second gate in the present application.

[0068] As shown in FIG5 , based on FIG4 , a second gate material is grown in the portion of the second groove 201 where the substrate is exposed, using silicon source gas, silane gas (SiH 4 ) and / or dichlorosilane (SiH 2 Cl 2 ) by epitaxial growth, while hydrogen chloride gas (HCl) is introduced so that the second gate material grows only on the exposed portion of the substrate 110 , and the grown second gate material serves as the second gate 400 ; wherein the grown second gate 400 has a continuous lattice structure with the substrate 110 .

[0069] The first gate material may be a polycrystalline material, such as polysilicon, and the second gate material may be a single crystal material, such as single crystal silicon.

[0070] Specifically, single crystal silicon is grown on the single crystal silicon substrate in the second groove 201 by epitaxial growth to serve as the second gate 400 , so that the second gate 400 and the substrate 110 have a continuous lattice structure.

[0071] In one embodiment, after forming the second gate 400, the first gate material is continued to be formed in the same chamber, and the continued first gate material fills the second groove 201 formed by patterning the first gate material layer 300, that is, the second groove 201 on the contact window, to complete the first gate material layer 300.

[0072] Please refer to FIG. 6 , which is a structural diagram of the first embodiment of the present application in which the first gate material is further formed.

[0073] As shown in FIG6 , after the second gate 400 is formed, the introduction of hydrogen chloride gas is stopped, and the first gate material continues to grow in the second groove 201 so that the first gate material fills the second groove 201 formed by patterning. The continuously grown first gate material is chemically mechanically polished to make its surface flat, that is, the filled first gate material is planarized to form a first gate material layer 300.

[0074] In some embodiments, the first gate material is a polycrystalline material, such as polysilicon; and the second gate material is a single crystal material, such as single crystal silicon.

[0075] In some embodiments, after the first gate material continues to grow, a P-type gate structure may be formed by ion implantation.

[0076] In another embodiment, a second gate 400 is formed on the contact window to fill the second groove 201 , and a chemical mechanical polishing is performed on the surface of the second gate to make the surface flat.

[0077] An island structure is then formed, wherein the island structure covers the first groove, the first gate material layer remaining in the island structure serves as a first gate, the first gate contacts the second gate, and is separated from the substrate by a gate insulating layer, and the first gate and the second gate constitute a semi-floating gate of a storage unit in the memory device.

[0078] The operation flow of step S14 in an embodiment is as follows:

[0079] patterning the first gate material layer, forming an inter-gate dielectric layer on the remaining first gate material layer, the second gate, and the gate insulating layer, forming a third gate material layer on the inter-gate dielectric layer, and patterning the third gate material layer and the inter-gate dielectric layer to form an island structure;

[0080] The third gate material layer remaining in the island structure serves as the third gate and is separated from the first gate and the second gate by the remaining inter-gate dielectric layer.

[0081] Please refer to FIG. 7 , which is a structural diagram of a first embodiment of patterning the first gate material layer in the present application.

[0082] As shown in FIG. 7 , based on FIG. 6 , the first gate material layer 300 is patterned. In this embodiment, the first gate material layer 300 after patterning exposes the side of the second gate 400 .

[0083] The patterning process may be photolithography, dry etching and / or wet etching.

[0084] In some embodiments, the first gate material layer 300 is removed in the patterned area to expose the gate insulation layer 200 and a portion of the substrate 110 , thereby forming a first island structure. The substrate on one side of the side of the second gate 400 is also exposed.

[0085] In some embodiments, the patterning process can stop inside, outside or at the boundary of the second groove 201; if it stops inside the second groove 201, part of the first gate material layer 300 and the second gate 400 inside the second groove 201 is removed; if it stops outside or at the boundary of the second groove 201, part of the first gate material layer 300 and the second gate 400 inside the second groove 201 is retained, and part of the first gate material layer 300 outside the second groove 201 is removed.

[0086] Next, an inter-gate dielectric layer is formed on the first island structure.

[0087] Please refer to FIG. 8 , which is a structural diagram of a first embodiment of forming an inter-gate dielectric layer in the present application.

[0088] As shown in FIG8 , based on FIG7 , after patterning, an inter-gate dielectric layer 500 is formed on the remaining first gate material layer 300 , the second gate 400 and the gate insulating layer 200 , so that the inter-gate dielectric layer 500 covers the first gate material layer 300 , the second gate 400 and the gate insulating layer 200 .

[0089] In some embodiments, if a portion of the substrate 110 is exposed in the patterned area, the inter-gate dielectric layer 500 will also cover the substrate 110 .

[0090] In some embodiments, the inter-gate dielectric layer may be a multi-layer structure, such as a two-layer structure, including an oxide layer and a nitride layer, such as a silicon oxide layer and a silicon nitride layer, to form an ON structure.

[0091] Afterwards, a third gate material layer is formed on the inter-gate dielectric layer 500 .

[0092] Please refer to FIG. 9 , which is a structural diagram of a first embodiment of forming a third gate material layer in this application.

[0093] As shown in FIG9 , based on FIG8 , a third gate material layer 600 is formed on the inter-gate dielectric layer 500 so that the third gate material layer 600 covers the inter-gate dielectric layer 500 , and the third gate material layer 600 is chemically mechanically polished so that the surface of the third gate material layer 600 is flat.

[0094] The third gate material layer 600 and the inter-gate dielectric layer 500 are then patterned to form a second island structure.

[0095] Please refer to FIG. 10 , which is a schematic structural diagram of a first embodiment of forming a second island structure in the present application.

[0096] As shown in Figure 10, based on Figure 9, the third gate material layer 600 and the inter-gate dielectric layer 500 are patterned to remove the third gate material layer 600, the inter-gate dielectric layer 500 and the first gate material layer 300 on the side of the first groove 101 away from the second gate 400, thereby forming a second island structure; wherein, the remaining third gate material layer 600 in the second island structure serves as the third gate 610, and the remaining first gate material layer 300 serves as the first gate 310, and the third gate 610 is separated from the first gate 310 and the second gate 400 by the remaining inter-gate dielectric layer 500.

[0097] In some embodiments, the first gate 310 and the second gate 400 in the second island structure serve as semi-floating gates of a memory cell in the memory, and the semi-floating gate contacts the substrate 110 through the second gate 400, that is, the second gate 400 has a corresponding contact window in the contact portion with the substrate, and the remaining portion of the semi-floating gate is separated from the substrate by the gate insulating layer 200; the third gate 610 in the second island structure serves as the control gate of the memory cell in the memory, and is separated from the semi-floating gate by the inter-gate dielectric layer 500.

[0098] Among them, because the natural oxide layer at the contact window is removed under a vacuum state during the formation of the second gate 400, the epitaxially grown second gate 400 can grow on the interface of the single crystal silicon substrate, thereby making the interface of the contact window uniform, that is, the second gate 400 and the substrate 110 have a continuous lattice structure, which can effectively improve the interface flatness of the contact window in the semi-floating gate structure and enhance the storage performance of the storage device.

[0099] In some embodiments, side walls may be further provided on both sides of the island structure.

[0100] In some embodiments, ion implantation is performed on the substrate to form source and drain electrodes in the substrate on both sides of the island structure, such as forming a common source electrode in the substrate 110 between the two island structures and forming corresponding drain electrodes in the substrate 110 on both sides.

[0101] 11-15 are schematic structural diagrams of a method for manufacturing a memory device in a second embodiment.

[0102] In the second embodiment, the same parts as those in the first embodiment will not be described in detail. The differences from the first embodiment are as follows:

[0103] S21. Provide a semiconductor body, wherein the semiconductor body includes a substrate and a first groove opened from a surface of the substrate toward the substrate.

[0104] S22 . Form a gate insulating layer and a first gate material layer in the first groove, wherein the first gate material layer fills the first groove.

[0105] Please refer to FIG. 11 , which is a structural diagram of a second embodiment of forming a gate insulating layer and a first gate material layer in the present application.

[0106] As shown in Figure 11, the semiconductor base 100 includes a substrate 110, a first groove 101 opened from the surface of the substrate toward the substrate, a gate insulation layer 200 is formed on the side wall of the first groove 101, and a first gate material layer 300 is formed on the gate insulation layer 200, and the first gate material layer 300 fills the first groove 101, so that the gate insulation layer 200 covers the first groove 101, and the first gate material layer 300 covers the first groove 101.

[0107] S23, removing a portion of the first gate material layer and the gate insulating layer to form a contact window on the sidewall of the first groove; forming a second gate on the contact window, wherein the second gate contacts the substrate and has a continuous lattice structure with the substrate.

[0108] Please refer to FIG. 12 , which is a structural diagram of a second embodiment of forming a contact window in the present application.

[0109] As shown in Figure 12, part of the first gate material layer 300 and the gate insulation layer 200 in the first groove 101 are patterned, so that part of the first gate material layer 300 and the gate insulation layer 200 in the first groove 101 are removed to form a second groove 201, and the substrate 110 is exposed through the second groove 201 to form a corresponding contact window.

[0110] Please refer to FIG. 13 , which is a structural diagram of a second embodiment of forming a second gate in the present application.

[0111] As shown in FIG. 13 , the contact window is processed using the processing method of the first embodiment, thereby forming a second gate 400 at the contact window, so that the second gate 400 is in contact with the substrate through the contact window.

[0112] In some embodiments, the second gate 400 fills the second groove 201 such that the second gate 400 is flush with the substrate 110 .

[0113] In other embodiments, if the second groove 201 is not filled after the second gate 400 is grown, the first gate material layer 300 is further grown on the second gate 400 to fill the second groove 201 so that the first gate material layer is flush with the substrate 110 .

[0114] S24. An island structure is formed, wherein the island structure covers the first groove, the first gate material layer remaining in the island structure serves as a first gate, the first gate contacts the second gate, and is separated from the substrate by a gate insulating layer, and the first gate and the second gate constitute a semi-floating gate of a storage unit in the memory device.

[0115] Before forming the island structure, an intergate dielectric layer 500 and a third gate material layer 600 need to be formed. Forming the island structure includes: forming the intergate dielectric layer 500 on the first gate material layer 300 and the second gate 400; then forming the third gate material layer 600 on the intergate dielectric layer 500, and patterning the third gate material layer 600 and the intergate dielectric layer 500 to form an island structure; wherein the remaining third gate material layer in the island structure serves as the third gate 610, which is separated from the first gate 310 and the second gate 400 by the remaining intergate dielectric layer 500.

[0116] Please refer to FIG. 14 , which is a structural diagram of a second embodiment of forming an inter-gate dielectric layer and a third gate material layer in the present application.

[0117] As shown in Figure 14, based on Figure 13, an inter-gate dielectric layer 500 is formed on the surface of the substrate 110, the second gate 400, the first gate material layer 300 and the gate insulating layer 200, and a third gate material layer 600 is formed on the inter-gate dielectric layer 500, that is, the inter-gate dielectric layer 500 covers the surface of the substrate 110, and the second gate 400, the first gate material layer 300 and the gate insulating layer 200 exposed through the surface of the substrate 110, and the third gate material layer 600 covers the inter-gate dielectric layer 500.

[0118] The third gate material layer 600 is then patterned to form an island structure.

[0119] Please refer to FIG. 15 , which is a structural diagram of a second embodiment of forming an island structure in the present application.

[0120] As shown in Figure 15, based on Figure 14, the third gate material layer 600 and the inter-gate dielectric layer 500 are patterned to remove part of the third gate material layer 600 and the inter-gate dielectric layer 500 on one side of the first groove 101, thereby forming an island structure; wherein, the remaining third gate material layer 600 in the island structure serves as the third gate 610, and the remaining first gate material layer 300 serves as the first gate 310, and the third gate 610 is separated from the first gate 310 and the second gate 400 by the remaining inter-gate dielectric layer 500.

[0121] Please refer to FIG. 16 , which is a structural diagram of a third embodiment of forming an inter-gate dielectric layer and a third gate material layer.

[0122] In another embodiment, as shown in FIG16 , after FIG13 , the heights of the first gate and the second gate can be lowered so that the semi-floating gate structure including the first gate and the second gate is located at the lower part of the first groove; an inter-gate dielectric layer and a third gate material layer are formed on the semi-floating gate structure so that the subsequently formed third gate (i.e., the control gate) is located in the first groove to form a buried gate structure.

[0123] The present application also relates to a memory device comprising a substrate, a groove, and an island structure. The groove extends from the surface of the substrate toward the substrate; the island structure at least fills the groove; the island structure comprises a first gate and a second gate, the second gate contacting the substrate through a contact window and having a continuous lattice structure with the substrate; the first gate is separated from the substrate by a gate insulating layer; the first gate and the second gate constitute a semi-floating gate of a memory cell in the memory device; and the contact window is located on the substrate surface or on the sidewall of the groove.

[0124] In some embodiments, the memory device further includes an intergate dielectric layer and a third gate, wherein the intergate dielectric layer is located above the first gate, the second gate, and the gate insulating layer; or the intergate dielectric layer is located above the first gate and the second gate; the third gate is located above the intergate dielectric layer, and the third gate constitutes a control gate of a memory cell in the memory device, thereby forming a semi-floating gate transistor through the semi-floating gate and the control gate.

[0125] In some embodiments, the memory device further includes sidewalls disposed on both sides of the island structure.

[0126] In some embodiments, the half-floating gate and the third gate are located in the recess.

[0127] In some embodiments, the first gate material is polysilicon, and the second gate material is single crystal silicon.

[0128] In some embodiments, a doped region and a shallow trench isolation structure for isolating memory cells in a memory device are formed in a substrate, wherein the doped region is located on one side of the substrate, wherein the doped region has a first doping type and / or a second doping type, and the first doping type is opposite to the doping type of the second doping type.

[0129] In some embodiments, the number of half-floating-gate transistors in the memory device may be multiple, for example, 2, 3, 4, etc.

[0130] In the present application, a method for manufacturing a memory device includes: providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a first groove extending from a surface of the substrate toward the substrate; forming a gate insulating layer and a first gate material layer on the substrate surface and in the first groove, or forming a gate insulating layer and a first gate material layer in the first groove, wherein the first gate material layer fills the first groove; removing a portion of the first gate material layer and the gate insulating layer to form a contact window on the substrate surface or on the sidewall of the first groove; forming a second gate on the contact window, wherein the second gate contacts the substrate and has a continuous lattice structure with the substrate; and forming an island structure, wherein the island structure covers the first groove, the first gate material layer remaining in the island structure serves as a first gate, the first gate contacts the second gate, and is separated from the substrate by the gate insulating layer, the first gate and the second gate constituting a semi-floating gate of a memory cell in the memory device. Through the above method, the second gate formed has a continuous lattice structure with the substrate, making the interface between the semi-floating gate and the contact window corresponding to the substrate uniform, effectively improving the interface flatness of the contact window in the semi-floating gate structure and enhancing the storage performance of the memory device.

[0131] The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a memory device, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate comprises a substrate and a first groove opened from a surface of the substrate toward the substrate; forming a gate insulating layer and a first gate material layer on the surface of the substrate and in the first groove, or forming a gate insulating layer and a first gate material layer in the first groove, wherein the first gate material layer fills the first groove; Removing a portion of the first gate material layer and the gate insulating layer to form a contact window on the substrate surface or the sidewall of the first groove; forming a second gate on the contact window, wherein the second gate contacts the substrate and has a continuous lattice structure with the substrate; An island structure is formed, wherein the island structure covers the first groove, the first gate material layer remaining in the island structure serves as a first gate, the first gate contacts the second gate and is separated from the substrate by the gate insulating layer, and the first gate and the second gate constitute a semi-floating gate of a storage unit in a storage device.

2. The method according to claim 1, characterized in that removing a portion of the first gate material layer and the gate insulating layer to form a contact window on the substrate surface or on the sidewall of the first groove; Forming a second gate at the contact window, comprising: Performing patterning on the first gate material layer and the gate insulating layer to form the contact window on the surface of the substrate or the sidewall of the first groove to expose a portion of the substrate; A second gate is grown on the contact window, and the first gate material is continuously formed so that the first gate material covers the second gate, and the first gate material continuously formed at least partially fills the second groove on the contact window to complete the first gate material layer.

3. The method according to claim 1, characterized in that Before growing the second gate on the contact window, the method comprises: A natural oxide layer naturally formed on the exposed portion of the substrate at the contact window is removed.

4. The method according to claim 1, characterized in that: The first gate material is polycrystalline silicon, and the second gate material is single crystal silicon.

5. The method according to claim 3, characterized in that: The removing of the natural oxide layer naturally formed on the exposed portion of the substrate at the contact window comprises: The natural oxide layer is removed by using a first reaction gas within a first temperature range, wherein the first temperature range is 900-1000 degrees Celsius, and the first reaction gas includes hydrogen and / or HF gas.

6. The method according to claim 1, characterized in that The step of growing a second gate on the contact window comprises: epitaxially growing a second gate material on the portion of the substrate exposed by the contact window using a second reaction gas and a third reaction gas; Wherein, the second reaction gas includes silane gas and / or dichlorosilane gas, and the third reaction gas includes hydrogen chloride gas.

7. The method according to claim 2, characterized in that: The step of growing the second gate on the contact window and continuing to form the first gate material so that the first gate material covers the second gate comprises: The first gate material is continued to be epitaxially grown on the second gate by using a second reaction gas; wherein the second reaction gas includes silane gas and / or dichlorosilane gas.

8. The method according to claim 3, characterized in that Removing the native oxide layer and growing the second gate are performed in the same chamber.

9. The method according to claim 1, characterized in that: The forming of the island structure comprises: performing patterning on the first gate material layer; forming an inter-gate dielectric layer on the remaining first gate material layer, the second gate and the gate insulating layer; Alternatively, forming an inter-gate dielectric layer on the first gate material layer and the second gate; forming a third gate material layer on the inter-gate dielectric layer, and patterning the third gate material layer and the inter-gate dielectric layer to form the island structure; The third gate material layer remaining in the island structure serves as the third gate. The first gate and the second gate are separated by the remaining inter-gate dielectric layer.

10. The method according to claim 9, characterized in that The inter-gate dielectric layer includes an oxide layer and a nitride layer.

11. A storage device, characterized in that: include: substrate; A groove extending from a side surface of the substrate toward the substrate; An island structure at least fills the groove, the island structure includes a first gate and a second gate, the second gate contacts the substrate through a contact window and has a continuous lattice structure with the substrate, the first gate is separated from the substrate by a gate insulating layer, wherein the first gate and the second gate contact and constitute a semi-floating gate of a storage unit in a storage device, and the contact window is located on the surface of the substrate or on the sidewall of the groove.

12. The memory device according to claim 11, wherein: Also includes: an inter-gate dielectric layer, located on the first gate, the second gate and the gate insulating layer; The third gate is located on the inter-gate dielectric layer, wherein the third gate constitutes a control gate of a storage unit in the storage device.

13. The memory device according to claim 11, wherein: Also includes: Side walls are arranged on both sides of the island structure.

14. The memory device according to claim 12, wherein: The semi-floating gate and the third gate are located in the groove.

15. The storage device according to any one of claims 11 to 14, characterized in that: The first gate material is polycrystalline silicon, and the second gate material is single crystal silicon.

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