Data transmission method, apparatus, network interface controller, network interface controller chip and computer

Abstract

The present application provides a data transmission method, an apparatus, a network interface controller, a network interface controller chip and a computer. In an embodiment, a first network interface controller receives a plurality of data requests, the plurality of data requests being respectively from different virtual processors in a first processor, and a destination node of each data request being different; the first network interface controller respectively adds the plurality of data requests into core queues, each virtual processor corresponding to one core queue, and the data requests from different virtual processors entering different core queues; the first network interface controller extracts the plurality of data requests from the core queues, and on the basis of the destination node of each data request of the plurality of data requests, respectively adds the plurality of data requests into shared queues, each destination node corresponding to one shared queue, and data requests having an identical destination node entering a same shared queue; and the first network interface controller extracts the plurality of data requests from the shared queues, and sends the plurality of data requests to destination computer systems where the corresponding destination nodes are located. Thus, the time delay of data transmission is reduced, and occupation of CPU resources in nodes is reduced.

Description

Data transmission method, device, network card, network card chip and computer

[0001] This application claims priority to a Chinese patent application filed with the State Intellectual Property Office of China on August 9, 2023, with application number 202310997519.0 and entitled “Data transmission method, device, network card, network card chip and computer”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a data transmission method, device, network card, network card chip and computer. Background Art

[0003] With the rapid development of cloud computing, big data, the Internet of Things, artificial intelligence and other related industries, the requirements of network communications for data transmission latency have also increased.

[0004] The Remote Direct Memory Access over Converged Ethernet (RoCE) protocol provides remote memory access from one Internet Protocol (IP) to another. Based on the RoCE protocol, data is transferred between processes using queue pairs (QPs) established between nodes. However, QPs only support one-to-one service, meaning that messages within a QP can only reach one specific node from one node. This makes data transfer insufficient for network communication.

[0005] Therefore, a data transmission method based on the RoCE protocol is urgently needed to meet current network communication needs.

[0006] Summary of the Invention

[0007] In order to solve the above problems, the embodiments of the present application provide a data transmission method, device, network card, network card chip and computer, which can reduce the delay of data transmission.

[0008] In a first aspect, an embodiment of the present application provides a data transmission method, wherein a first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card via a bus, and the first node communicates with multiple computer systems via the first network card, the method comprising:

[0009] The first network card receives multiple data requests, where the multiple data requests come from different virtual processors in the first processor, and the destination node of each data request is different;

[0010] The first network card adds the multiple data requests to the core queues respectively, wherein each virtual processor corresponds to one core queue, and data requests from different virtual processors enter different core queues;

[0011] The first network card retrieves multiple data requests from the core queue and adds the multiple data requests to a shared queue according to the destination node of each data request. Each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue.

[0012] The first network card takes out multiple data requests from the shared queue and sends the multiple data requests to a destination computer system where the corresponding destination nodes are located.

[0013] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture comprises multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0014] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0015] In a possible implementation, the first network card is configured with first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue. Adding the multiple data requests to the shared queue according to a destination node of each of the multiple data requests includes:

[0016] According to the identity of the destination node, determining the identity of the shared queue corresponding to the destination node from the first mapping relationship information;

[0017] According to the identity identifier of the shared queue corresponding to the destination node, the data request is added to the shared queue.

[0018] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0019] In one possible implementation, the first network card is configured with second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue. The data request includes the identity of the virtual processor from which the data request originates. Adding multiple data requests to the core queues respectively includes:

[0020] Determining, from the second mapping relationship information, an identity of a core queue to which each data request is to be added, according to an identity of a virtual processor from which each data request comes from among the multiple data requests;

[0021] According to the identity identifier of the core queue, multiple data requests are added to the core queue respectively.

[0022] In this way, the virtual processors in the node can monopolize the core QP, eliminating the need for resource preemption in the CPU, thus reducing CPU resource usage.

[0023] In a second aspect, an embodiment of the present application provides a data transmission method, wherein a second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card via a bus, and the second node communicates with multiple computer systems via the second network card, the method comprising:

[0024] The second network card receives multiple data requests, where the multiple data requests come from different nodes;

[0025] The second network card adds multiple data requests to the shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue;

[0026] The second network card retrieves multiple data requests from the shared queue and adds the multiple data requests to the core queue according to the destination virtual processor of each data request, wherein data requests with different destination virtual processors enter different core queues;

[0027] The second network card takes out multiple data requests from the core queue and sends the multiple data requests to corresponding destination virtual processors.

[0028] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture consists of multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different destination VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0029] Taking the example of receiving a data request, if the node sending the data request is called the source node, and the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the ultimate recipient of the data request), multiple data requests originating from the same source node and sent to different destination virtual processors can be added to the shared QP corresponding to the source node and then to the core QP corresponding to each destination virtual processor. This allows the virtual processor to exclusively occupy the core QP, satisfying the virtual processor's requirement for exclusive QPs. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0030] In one possible implementation, the second network card includes first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue. The data request includes the identity of a node from which the data request comes. Adding the multiple data requests to the shared queue respectively includes:

[0031] Determining, from the first mapping relationship information, an identity of a shared queue corresponding to the node according to an identity of a node in each of the multiple data requests;

[0032] According to the identity identifier of the shared queue, multiple data requests are added to the corresponding shared queue respectively.

[0033] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0034] In one possible implementation, the second network card includes second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue; the data request includes an identity of a destination virtual processor of the data request; and the multiple data requests are added to the core queue according to the destination virtual processor of each of the multiple data requests, including:

[0035] According to the identity of the destination virtual processor of each data request, determining the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information;

[0036] According to the identity identifier of the core queue corresponding to the destination virtual processor, the data request is added to the corresponding core queue.

[0037] In this way, the virtual processors in the node can monopolize the core QP, eliminating the need for resource preemption in the CPU, thus reducing CPU resource usage.

[0038] In a third aspect, an embodiment of the present application provides a data transmission device, wherein a first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card via a bus, and the first node communicates with multiple computer systems via the first network card. The device is applied to the first network card and includes:

[0039] a receiving module, configured to receive multiple data requests, the multiple data requests respectively coming from different virtual processors in the first processor, and the destination node of each data request being different;

[0040] A processing module is used to add multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0041] The processing module is further configured to retrieve multiple data requests from the core queue and add the multiple data requests to a shared queue according to the destination nodes of each data request. Each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue.

[0042] The sending module is used to take out multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the corresponding destination nodes are located.

[0043] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture comprises multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0044] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0045] In a possible implementation, the first network card is configured with first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the processing module is configured to:

[0046] According to the identity of the destination node, determining the identity of the shared queue corresponding to the destination node from the first mapping relationship information;

[0047] According to the identity identifier of the shared queue corresponding to the destination node, the data request is added to the shared queue.

[0048] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0049] In one possible implementation, the first network card is configured with second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes the identity of the virtual processor from which the data request originates, and the processing module is used to:

[0050] Determining, from the second mapping relationship information, an identity of a core queue to which each data request is to be added, according to an identity of a virtual processor from which each data request comes from among the multiple data requests;

[0051] According to the identity identifier of the core queue, multiple data requests are added to the core queue respectively.

[0052] In this way, the virtual processors in the node can monopolize the core QP, eliminating the need for resource preemption in the CPU, thus reducing CPU resource usage.

[0053] In a fourth aspect, an embodiment of the present application provides a data transmission device, wherein a second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card via a bus, and the second node communicates with multiple computer systems via the second network card. The device is applied to the second network card, and the device includes:

[0054] A receiving module, configured to receive multiple data requests from different nodes;

[0055] A processing module, configured to add multiple data requests to a shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue;

[0056] The processing module is further configured to retrieve multiple data requests from the shared queue and add the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein data requests with different destination virtual processors enter different core queues;

[0057] The sending module is used to take out multiple data requests from the core queue and send the multiple data requests to the corresponding destination virtual processors.

[0058] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture consists of multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different destination VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0059] Taking the example of receiving a data request, if the node sending the data request is called the source node, and the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the ultimate recipient of the data request), multiple data requests originating from the same source node and sent to different destination virtual processors can be added to the shared QP corresponding to the source node and then to the core QP corresponding to each destination virtual processor. This allows the virtual processor to exclusively occupy the core QP, satisfying the virtual processor's requirement for exclusive QPs. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0060] In one possible implementation, the second network card includes first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue. The data request includes the identity of a node from which the data request comes. Adding the multiple data requests to the shared queue respectively includes:

[0061] Determining, from the first mapping relationship information, an identity of a shared queue corresponding to the node according to an identity of a node in each of the multiple data requests;

[0062] According to the identity identifier of the shared queue, multiple data requests are added to the corresponding shared queue respectively.

[0063] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0064] In one possible implementation, the second network card includes second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue; the data request includes an identity of a destination virtual processor for the data request; and the processing module is used to:

[0065] According to the identity of the destination virtual processor of each data request, determining the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information;

[0066] According to the identity identifier of the core queue corresponding to the destination virtual processor, the data request is added to the corresponding core queue.

[0067] In this way, the virtual processors in the node can monopolize the core QP, eliminating the need for resource preemption in the CPU, thus reducing CPU resource usage.

[0068] In a fifth aspect, an embodiment of the present application provides a network card. A computer system includes a network card and a node. The node includes a processor. The network card includes:

[0069] Computer bus interface for communicating with nodes;

[0070] Network interfaces for communicating with other computer systems;

[0071] Processors provide core and shared queues and are also used to:

[0072] Obtain multiple data requests from the node through the computer bus interface, and add the multiple data requests to the core queue respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0073] Taking multiple data requests from the core queue, and adding the multiple data requests to the shared queue according to the destination nodes of each data request, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0074] Multiple data requests are taken out from the shared queue and sent to the computer system where the corresponding destination nodes are located through the network interface.

[0075] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture comprises multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0076] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0077] In a sixth aspect, an embodiment of the present application provides a network card chip, a computer system including a network card and a node, the network card and the node communicating via a computer bus, the node communicating with other nodes via the network card, the network card including a network card chip, a computer bus interface, and a network interface;

[0078] Network card chips include:

[0079] Power supply, used to supply power to the network card chip;

[0080] The NIC chip itself is used to provide core queues and shared queues. The NIC chip is also used to:

[0081] Add multiple data requests to core queues respectively, where each virtual processor corresponds to one core queue, and data requests from different virtual processors enter different core queues;

[0082] Taking multiple data requests from the core queue, and adding the multiple data requests to the shared queue according to the destination nodes of each data request, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0083] Multiple data requests are taken out from the shared queue and sent to the computer system where the corresponding destination nodes are located through the network interface.

[0084] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture comprises multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0085] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0086] In a seventh aspect, an embodiment of the present application provides a computer, characterized in that it includes a node and a network card, and the network card is used to execute the method of the first aspect, or execute the method of the second aspect.

[0087] In an eighth aspect, an embodiment of the present application provides a data transmission device, comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method of the first aspect, or to execute the method of the second aspect.

[0088] In a ninth aspect, an embodiment of the present application provides a data transmission device, characterized in that the device runs computer program instructions to execute the method of the first aspect, or execute the method of the second aspect. Exemplarily, the device can be a chip or a processor.

[0089] In one example, the apparatus may include a processor, which may be coupled to a memory, read instructions from the memory, and execute the method provided in the first aspect or the method provided in the second aspect according to the instructions. The memory may be integrated into a chip or processor, or may be independent of the chip or processor.

[0090] In a tenth aspect, an embodiment of the present application provides a computer storage medium, in which instructions are stored. When the instructions are executed on a computer, the computer executes the method described in the first aspect, or executes the method described in the second aspect.

[0091] In the eleventh aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect or the method described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] FIG1 is a schematic diagram of an inter-process communication based on the RoCE protocol provided in an embodiment of the present application;

[0093] FIG2 is a schematic diagram of the architecture of a clustered RDMA network provided in an embodiment of the present application;

[0094] FIG3 is a logical diagram of inter-node communication in a network provided by an embodiment of the present application;

[0095] FIG4 is a schematic diagram of the architecture of a computer system in which a virtual processor accesses a QP based on a lock, provided by an embodiment of the present application;

[0096] FIG5 is a schematic diagram of the architecture of a computer system in which a virtual processor exclusively owns a QP, provided by an embodiment of the present application;

[0097] FIG6 a is a schematic diagram of the architecture of a computer system based on a network card with a double-layer QP architecture provided by an embodiment of the present application;

[0098] FIG6 b is a schematic diagram of the architecture of another computer system based on a network card with a double-layer QP architecture provided by an embodiment of the present application;

[0099] FIG6 c is a schematic diagram of the architecture of another computer system based on a network card with a double-layer QP architecture provided by an embodiment of the present application;

[0100] FIG7 is a communication diagram of a data transmission method provided in an embodiment of the present application;

[0101] FIG8 is a flow chart of a data transmission method provided in an embodiment of the present application;

[0102] FIG9 is a flow chart of another data transmission method provided in an embodiment of the present application;

[0103] FIG10 is a flow chart of another data transmission method provided in an embodiment of the present application;

[0104] FIG11 is a schematic structural diagram of a data transmission device provided in an embodiment of the present application;

[0105] FIG12 is a schematic structural diagram of another data transmission device provided in an embodiment of the present application;

[0106] FIG13 is a schematic diagram of the structure of a network card provided in an embodiment of the present application;

[0107] FIG14 is a schematic structural diagram of a network card chip provided in an embodiment of the present application;

[0108] FIG15 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0109] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0110] In the description of the embodiments of the present application, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of the present application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0111] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "plurality" means two or more. For example, "multiple systems" refers to two or more systems, and "multiple terminals" refers to two or more terminals.

[0112] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0113] The Remote Direct Memory Access Over Converged Ethernet (RoCE) protocol provides an Internet Protocol (IP) to IP remote memory access capability.

[0114] Based on the RoCE protocol, data is transmitted between processes through queue pairs (QPs) established between nodes. Among them, QP only supports one-to-one services, that is, messages in a QP can only reach another specific node from one node. For example, as shown in Figure 1, node A and node B communicate through a network, where each node can be connected to multiple network ports, and each node has multiple processes. For example, node A includes multiple process A, and node B includes multiple process B. Multiple process A can transmit data to multiple process Bs through the queues established between node A and node B.

[0115] For example, as shown in Figure 1, a clustered RDMA network includes multiple computer systems, each of which includes nodes and network cards. Nodes and network cards communicate via a bus, and nodes communicate with switches via the network cards, thereby transmitting data to other nodes. Here, nodes and network cards can be considered two parts of the computer system. In some embodiments, the network cards are removable. The computer system can function as both a data sending system and a data receiving system.

[0116] It should be noted that QP includes a send queue and a receive queue. For the sake of simplicity, the following only uses QP to describe the data receiving and sending processes. However, in actual applications, the send queue in QP is used to send data, and the receive queue in QP is used to receive data.

[0117] Based on the clustered RDMA network shown in Figure 1, Figure 2 shows a schematic diagram of the logical relationship between nodes in a clustered RDMA network. Each node can communicate with the remaining n-1 nodes using the RDMA protocol. When two nodes transmit data, a QP must be established. This QP is exclusive to the two nodes, allowing the nodes to transmit data based on the QP.

[0118] In one scenario, based on the networking shown in Figures 1 and 2 , during data transmission between nodes based on QPs, when multiple virtual central processing units (CPUs) in a node need to simultaneously send data to other nodes, access to the QPs needs to be protected by locks. For example, based on the networking architecture shown in Figure 1 , as shown in Figure 4 , node n includes virtual processors vCPU1 through vCPU3, node n also includes QPs 1 through QPn-1, and network cards include QPs 1' through QP1n-1'. There is a one-to-one correspondence between the QPs in the node and the QPs in the network card. When virtual processors vCPU1 through vCPU3 all send data to node 1, node n needs to establish QP1, and all virtual processors in node n need to access QP1 to send data to node 1. Virtual processors vCPU1 through vCPU3 need to acquire lock 10 to protect access to QP1. If vCPU1 acquires lock 10, it can access QP1 and then send data to Node 1 via QP' in the network interface card. While vCPU1 is sending data to Node 1 via QP1, vCPU2 and vCPU3 are both in a waiting state and unable to access QP1. However, protecting access to QPs in the CPU with locks can lead to CPU resource preemption between vCPUs, resulting in CPU resource usage and increased data transmission latency.

[0119] In another scenario, based on the networking shown in Figures 1 and 2, during QP-based data transmission between nodes, each virtual processor can exclusively occupy a QP. For example, based on the networking architecture shown in Figure 1, as shown in Figure 5, the CPU in node n has m cores, meaning the CPU can be divided into m virtual processors (vCPUs). Node n includes n-1 QP groups (note: the node number and the number of QPs are unrelated), namely QPG1 through QPGn-1, each QP group including m QPs. Each QP group is used to send data to the node corresponding to the QP group. For example, all QPs in QPG1 are used to send data to node 1. There is a one-to-one correspondence between QPs and vCPUs in a QP group, meaning that each virtual processor has exclusive access to one QP. This allows multiple vCPUs to send data concurrently to the same node, and multiple vCPUs to send data concurrently to different nodes, avoiding resource preemption. However, each vCPU occupies a dedicated QP, and each node corresponds to a QP group. Therefore, the network card corresponding to the node needs to support m*(n-1) QPs. However, QP resources are limited, and a large number of QPs can easily exceed the network card specifications. Furthermore, QPs consume memory resources when reading and writing memory, managing and sending and receiving data. A large number of QPs consumes a large amount of node memory.

[0120] In other words, for a system consisting of n nodes, one node has m virtual processors. In the prior art, QPs only have one layer. For this node with m virtual processors, each virtual processor requires n-1 QPs to communicate with any of the n-1 nodes. Therefore, its network interface card needs to provide a total of m*(n-1) QPs to ensure that each of the m virtual processors can communicate with any other node. Conversely, based on the solution provided by the embodiments of the present invention, the QP structure is divided into a core layer (first layer) and a shared layer (second layer). Since the second-layer QPs can be shared by multiple virtual processors, the network interface card of this node only needs to provide m first-layer QPs and n-1 second-layer QPs, thus ensuring that each of the m virtual processors can communicate with any other node. The total number of QPs is reduced from m*(n-1) to m+(n-1), conserving the network interface card's QP resources and reducing the memory usage of the network interface card.

[0121] It should be noted that the nodes shown in Figures 4 and 5 transmit data via RDMA during data transmission. That is, the virtual processor transmits data via the user-mode QP corresponding to the virtual processor and the QP in the network card (not specifically shown in Figures 4 and 5). In this context, data transmission includes receiving data or sending data.

[0122] Based on this, embodiments of the present application provide a data transmission method, apparatus, network card, network card chip, and computer. According to this solution, the method utilizes a two-tier QP architecture in the network card, comprising multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor in a node, enabling the virtual processor in the node to exclusively occupy a core QP. Data requests from different virtual processors are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0123] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the ultimate recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first reach the core QP corresponding to each source virtual processor, and then reach the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs. The number of QPs in a node's CPU does not need to increase with the number of nodes in the network, reducing CPU overhead in the node.

[0124] Next, the computer system in the network provided in the embodiment of the present application is described in detail.

[0125] Figure 6a is a schematic diagram of the architecture of the computer system provided in an embodiment of the present application. As shown in Figure 6a, the computer system provided in an embodiment of the present application includes a node 61 and a network card 62. Among them, node 61 is the i-th node in the network, i = 1, 2, ..., n, and n is a positive integer greater than 1. Node 61 communicates with the network through the network card 62, so that multiple nodes can communicate with each other. It should be noted that the network card can be integrated on the node, and the network card can also be a detachable network card. The embodiment of the present application does not specifically limit the form of the network card.

[0126] In an embodiment of the present application, node 61 includes a CPU and memory. The CPU can be an m-core CPU, namely vCPUi1 through vCPUim. The vCPU reads data from the memory and sends it to the network card via a user-state QP. Alternatively, the vCPU receives data from the network card via a user-state QP and writes the data to the memory. In an embodiment of the present application, there is a one-to-one correspondence between the vCPU and the user-state QP. As shown in Figure 6a, the node includes m user-state QPs, namely user-state QPyi1 through user-state QPyim. For example, user-state QP1 corresponds one-to-one with vCPU1. When vCPUi1 is transmitting data to the network card, vCPUi1 places data into user-state QPyi1 and then sends the data in user-state QPyi1 to the network card. Similarly, vCPUi2 corresponds one-to-one with user-state QPyi2, and so on, with vCPUim corresponding one-to-one with user-state QPyim. The data transmission process within a node can be found in the detailed description of the node in the RDMA protocol and will not be repeated here.

[0127] The network card 62 includes a data processing unit (DPU) and physical ports. The DPU is used to assemble data into network packets or parse network packets received by the network card. The physical ports are used to communicate with the network, receiving network packets from the network, or sending network packets to the network. Network packets carry data transmitted between nodes.

[0128] To improve the performance of the entire system during data transmission and reduce the use of resources such as memory and CPU, a dual-layer QP architecture is designed on the network card side during data reception or transmission, allowing the network card to transmit data through the dual-layer QP architecture. As shown in Figure 6a, the dual-layer QP architecture of the network card includes multiple core QPs and multiple shared QPs. The core QPs correspond one-to-one with the user-state QPs in the node. As shown in Figure 6a, the network card includes m core QPs, namely core QPhi1 to core QPhim. Core QPhi1 corresponds one-to-one with the user-state QPyi1 in the node, core QPhi2 corresponds one-to-one with the user-state QPyi2 in the node, and so on, core QPhim corresponds one-to-one with the user-state QPyim in the node. For example, when vCPUi1 in the node sends data to the network card, vCPUi1 puts the data into user-state QPyi1 and then sends it to core QPhi1 in the network card.

[0129] The core QP and shared QP in the network card can communicate, wherein one shared QP supports data transmission of multiple core QPs. Shared QPs correspond one-to-one with other nodes in the network. In this way, data in the core QP can be transmitted with multiple other nodes in the network. Exemplarily, as shown in Figure 6a, the network card includes shared QPpi1 to shared QPpin-1, where n is a positive integer and n is greater than 1. Among them, the shared QPs correspond one-to-one with other nodes in the network. The node shown in Figure 6a is node n in the network, and the network also includes nodes 1 to node n-1. Among them, shared QPpi1 corresponds one-to-one with node 1, shared QPpi1 corresponds one-to-one with node 2, and so on. Shared QPpin-1 corresponds one-to-one with node n-1.

[0130] Exemplarily, when vCPUn1 of node n sends data to node 1, node n reads the data from memory and places the data into user-state QPyn1, transmitting the data to core QPhn1 in the network card via user-state QPyn1. Core QPhn1 sends the data to shared QPpn1, and the data is then transmitted to node 1 via shared QPpn1. As another example, when node 1 sends data to vCPUn1 in node n, the network card corresponding to node n receives the data sent by node 1 over the network via shared QPp11. Shared QPp11 transmits the data to core QPhn1, and then transmits the data to user-state QPyn1 in node n. In this way, vCPUn1 in node n reads the data sent by node 1 from user-state QPyn1.

[0131] It should be noted that the user QP in the node, the core QP in the network card, and the shared QP in the network card all include paired receive queues and transmit queues, so that the user QP in the node, the core QP in the network card, and the shared QP in the network card can all be used to send data and also to receive data.

[0132] This dual-tier QP architecture within the NIC eliminates the need for the vCPU to lock QP access when a node sends data to the NIC. This prevents CPU resource usage during resource preemption between vCPUs and reduces data transmission latency. Furthermore, the dual-tier QP architecture within the NIC reduces the number of QPs, preventing them from exceeding the NIC's specifications and preventing the node's memory from being consumed excessively during QP reads and writes.

[0133] In some embodiments, the network card provided by the embodiments of the present application includes multiple core QPs and multiple shared QPs. The multiple core QPs correspond one-to-one to the multiple virtual processors in the node. In the process of the CPU in the node sending data to the network card, the network card is used to receive multiple data requests, and the multiple data requests come from different virtual processors in the CPU. After receiving the multiple data requests, the network card adds the multiple data requests to the core QP respectively. The core QP and the virtual processor have a one-to-one correspondence, and data requests from different virtual processors enter different core queues. For example, as shown in Figure 6a, the network card adds data from vCPUi1 to core QPhi1, the network card adds data from vCPUi2 to core QPhi2, and the network card adds data from vCPUim to core QPhim.

[0134] When the NIC sends data to a node's CPU, it retrieves multiple data requests from the shared QP and adds them to the core QPs. Data requests enter different core QPs depending on their destination virtual processors. For example, if data request A's destination virtual processor is vCPUi1, the NIC adds data request A to core QPhi1. If data request B's destination virtual processor is vCPUi2, the NIC adds data request B to core QPhi2. If data request C's destination virtual processor is vCPUim, the NIC adds data request C to core QPhim.

[0135] There is a one-to-one correspondence between shared QPs and nodes in the network. Data requests from different nodes enter different shared QPs, while data requests from the same node enter the same shared QP. As shown in Figure 6a, shared QPpi1 has a one-to-one correspondence with node 1. When the network interface card receives a data request from node 1, it adds the data request from node 1 to shared QPhi1. Shared QPpi2 has a one-to-one correspondence with node 2. When the network interface card receives a data request from node 2, it adds the data request from node 2 to shared QPpi2.

[0136] For example, as shown in Figure 6b, a two-tier QP architecture in a network card can include a set of core QPs and n-1 sets of shared QPs, each of which includes a shared QP. A core QP corresponds one-to-one with a vCPU in a node. A shared QP can communicate with all core QPs. The shared QP in QPG 1 is used to communicate with node 1, the shared QP in QPG 2 is used to communicate with node 2, and so on. The shared QP in QPG n-1 is used to communicate with node n-1.

[0137] In the dual-sided QP architecture of node i and network card i1 shown in Figure 6b, when node i is the nth node in the network, the logical relationship between vCPU, core QP, shared QP and communication between nodes is shown in Table 1.

[0138] Table 1

[0139] According to this solution, a dual-tier QP architecture is implemented in the network interface card (NIC). This architecture includes multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0140] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0141] In other embodiments, a dual-tier QP architecture in a network card may include multiple core QP groups P and n-1 shared QP groups, wherein a core QP group includes multiple core QPs and a shared QP group includes multiple shared QPs. A core QP group corresponds one-to-one with a shared QP in a shared QP group, and a shared QP supports data transmission between multiple core QPs in the same core QP group. Specifically, the network card includes multiple core queue groups and multiple shared queue groups. Each of the multiple core queue groups includes multiple core queues, and the multiple core queues correspond one-to-one to multiple virtual processors in a node. For example, as shown in FIG6 c , the network card includes core QP group G11, core QP group G22, and core QP group G33. Core QP group G11, core QP group G22, and core QP group G33 each include m core QPs. The network card includes shared QP group QP1, shared QP group QP2, ..., and shared QP group QPn-1. Shared QP group QPG1 is used for data transmission with node 1, shared QP group QPG2 is used for data transmission with node 2, and so on. Shared QP group QPGn-1 is used for data transmission with node n-1. Each shared QP group includes three shared QPs, and each shared QP corresponds to a core QP group.

[0142] The NIC receives multiple data requests from different virtual processors. Data requests from the same virtual processor enter different core QP groups. Data requests from different virtual processors enter different core QPs. For example, as shown in Figure 6c, data request A and data request B both originate from vCPUi1. The NIC adds data request A to core QPhi1 in core QP group G11 and data request B to core QPhi1 in core QP group G22. This allows the NIC to process multiple data requests from the same virtual processor in parallel, improving data transmission efficiency.

[0143] For example, as shown in FIG6c , the network card includes three core QP groups, namely G11, G22, and G33. Each core QP group includes m core QPs, corresponding one-to-one to m vCPUs. The network card includes n-1 shared QP groups, namely QPG1 to QPGn-1, and each shared QP group includes three shared QPs, namely G1, G2, and G3. Different shared QPs in each shared QP group correspond to different core QP groups. For example, when a core QP in core QP group G11 sends data to node 1, core QP group G11 sends the data to shared QPg1 in the shared QPs. Here, shared QPg1 is included in shared QP groups QPG1 to QPGn-1. Based on the two-tier QP architecture shown in FIG6c , the same vCPU in a node can process different services in parallel. For example, based on the networking architecture shown in Figure 1, vCPU 1 can send data to both node 1 and node 2 in parallel. The data sent by node n to node 1 is data 1, and the data sent by node n to node 2 is data 2. vCPU n1 sends data 1 to core QPhn1 corresponding to vCPU n1 in core QP group G11, and vCPU n1 sends data 2 to core QPhn1 corresponding to vCPU n1 in core QP group G22. Subsequently, the core QP corresponding to vCPU n1 in core QP group G11 sends data 1 to shared QPg1 in shared QP group QPG1, and the core QPhn1 corresponding to vCPU n1 in core QP group G22 sends data 2 to shared QPg2 in shared QP group QPG2.

[0144] In the dual-sided QP architecture of node i and network card i1 shown in Figure 6c, when node i is the nth node in the network, the logical relationship between vCPU, core QP, shared QP, and communication between nodes is shown in Table 2.

[0145] Table 2

[0146] According to this solution, a dual-tier QP architecture is implemented in the network card. The dual-tier QP architecture includes multiple core QPs and multiple shared QPs. The core QPs correspond one-to-one to the virtual processors in the node, allowing the virtual processors in the node to exclusively use the core QPs without resource preemption, thereby reducing CPU resource usage. A shared QP supports data transmission for multiple core QPs. Nodes in the network correspond one-to-one to shared queues, allowing nodes in the network to exclusively use the shared queues, enabling multiple vCPUs in the node to transmit data with multiple other nodes in the network, thereby reducing data transmission latency. Furthermore, since the virtual processors can exclusively use the core QPs, and a shared QP supports data transmission for multiple core QPs, the CPU overhead in the node is reduced. Furthermore, through the one-to-one correspondence between the core queue group and the shared queues in a shared queue group, and the one-to-one correspondence between the shared queue group and the node, multiple vCPUs can transmit data in parallel with the same node, or the same vCPU can transmit data in parallel with the same node, thereby improving data transmission efficiency.

[0147] It should be noted that FIG6b and FIG6c are only for illustrating the dual-layer QP architecture in the network card. For the sake of brevity, detailed descriptions of some modules or components are omitted. For details, please refer to the detailed description of FIG6a.

[0148] The above is a detailed description of the architecture of the computer system provided by the embodiment of the present application. Next, based on Figures 2 and 6a to 6c, and taking Figure 7 as an example, the data transmission method provided by the embodiment of the present application is exemplarily described.

[0149] Before describing the data transmission method provided in the embodiment of the present application, the architecture for data transmission between nodes in the network provided in FIG7 is described. As shown in FIG7 , the network includes a sending end and a receiving end. The sending end includes node 1 and network card 11, and the receiving end includes node n and network card n1. The CPU of node 1 is m-core, that is, node 1 includes m vCPUs, namely vCPU11 to vCPU1m, and node 1 includes m user-state QPs, namely user-state QPy11 to user-state QPy1m. As shown in FIG7 , the m user-state QPs correspond one-to-one to the m vCPUs. The network card 11 includes m core QPs, namely core QPh11 to core QPh12. As shown in FIG7 , the m core QPs correspond one-to-one to the m user-state QPs in node 1. Network card 11 also includes n-1 shared QPs. Different shared QPs send data to different nodes. For example, shared QP t2 in Figure 7 indicates a shared QP used to send data to node 2, shared QP t3 indicates a shared QP used to send data to node 3, and so on. Shared QP tn indicates a shared QP used to send data to node n. Node n has k cores, meaning it includes k vCPUs, namely vCPUn1 through vCPUnk. Node n also includes k user-mode QPs, namely user-mode QPn1 through user-mode QPnk. As shown in Figure 7, the k user-mode QPs correspond one-to-one to the k vCPUs. Network card n1 includes k core QPs, namely core QPhn1 through core QPhnk. As shown in Figure 7, the k core QPs correspond one-to-one to the k user-mode QPs in node n. Network card n1 also includes n-1 shared QPs. Different shared QPs are used to receive data from different nodes. As shown in Figure 7, shared QPf1 is used to receive data from node 1, shared QPf2 is used to receive data from node 2, and so on. Shared QPfn-1 is used to receive data from node n-1.

[0150] The following uses the example of node 1 sending data to node n in Figure 7 as an example to exemplify the data transmission method provided in the embodiment of the present application.

[0151] FIG8 is a flow chart of a data transmission method provided in an embodiment of the present application. The data transmission method provided in an embodiment of the present application is applied to the computer system shown in FIG2 and FIG6a to FIG6c. As shown in FIG8, the data transmission method provided in an embodiment of the present application includes steps S801 to S815.

[0152] S801, vCPU12 in node 1 adds information about service A to user-state QP12.

[0153] Node 1 and Node n can communicate with each other for various services. Different services can use different vCPUs for data transmission. For example, when Node 1 transmits data for Service A to Node n, vCPU 12 in Node 1 processes Service A's data. vCPU 12 can retrieve Service A's data from memory (not specifically shown in Figure 7 ). Based on the preconfigured architecture in Node 1, vCPU 12 corresponds one-to-one with User Mode Query Provider 12, and vCPU 12 transfers Service A's information to User Mode Query Provider 12.

[0154] In this embodiment of the present application, the information of service A includes the data of service A and the identity of the destination node and the identity of the destination vCPU corresponding to the data of service A. The destination node corresponding to the data of service A is node n, so the identity of the destination node is n. The destination vCPU corresponding to the data of service A is vCPUhnk in node n, so the identity of the destination vCPU is hnk.

[0155] As a possible implementation manner, the information of service A is sent to the network card in the form of a command prompt (CMD).

[0156] S802 , vCPU 12 sends the data of service A in user-mode QP 12 to network card 11 .

[0157] S803 , the network card 11 adds the information of service A to the core QPh 12 .

[0158] According to the pre-configured architecture in the network card, the user state QP12 in node 1 corresponds one-to-one with the core QP12 in the network card. After receiving the information of service A, the network card adds the information of service A to the core QP12.

[0159] S804 , the NPU 1 in the network card 11 parses the information of the service A and obtains the identity of the destination node corresponding to the data of the service A.

[0160] S805 , the NPU 1 in the network card 11 determines the identity of the shared QP corresponding to the identity of the destination node according to the mapping relationship information.

[0161] The network interface card (NIC) is preconfigured with mapping information. This mapping information in NIC 11 indicates the mapping relationship between the shared QP in NIC 11 and the destination node. The mapping information includes the destination node's identity and the shared QP's identity. NPU 1 can determine the shared QP's identity corresponding to the destination node's identity from the mapping information. The shared QP corresponding to the destination node is the shared QP used to send data to the destination node.

[0162] For example, the mapping relationship information in the network card 11 is shown in Table 3, wherein node 2 corresponds to shared QPt2, node 3 corresponds to shared QPt3, and so on, node n corresponds to shared QPtn.

[0163] Table 3

[0164] In this way, when the node sends data to the network card, the vCPU does not need to protect the QP access through a lock, avoiding the occupation of CPU resources during resource preemption between vCPUs and reducing the delay in data transmission.

[0165] It should be noted that the node referred to in the mapping relationship information can serve as a destination node or a source node. In different data transmission scenarios, the role of the node referred to in the mapping relationship information is different. In the scenario of the embodiment of the present application, the node referred to in the mapping relationship information refers to the destination node to which the data is to be sent.

[0166] S806 , the NPU 1 in the network card 11 adds the information of the service A to the shared QP corresponding to the shared QP identity.

[0167] Exemplarily, the destination node of service A is node n. According to the mapping relationship information, the shared QP corresponding to node n is shared QPtn. NPU1 adds the information of service A to the shared QPtn.

[0168] S807 , the NPU 1 in the network card 11 packages the information of service A to obtain a message of service A.

[0169] NPU1 adds an IP packet header to the information of service A, thereby assembling the information of service A into a network packet.

[0170] S808 , the network card 11 sends the message of the service A in the shared QP to the network card n1 at the receiving end.

[0171] The network card 11 can send the message of service A to the network, thereby transmitting the message of service A to the receiving end through the network. The network card n1 in the receiving end can receive the message of service A from the network through the physical port of the network card n1.

[0172] S809 , the network card n1 adds the message of service A to the shared QPf1 in the network card n1 .

[0173] The message of service A includes the identity of the source node of the message. In this embodiment of the present application, the source node of the message of service A is node 1, and the shared QPf1 in network card n1 is used to receive data from node 1. Therefore, after network card n1 receives the message of service A, it adds the message of service A to the shared QPf1.

[0174] S809 , the NPUn in the network card n1 parses the message of service A to obtain data of service A and the identity of the destination vCPU corresponding to the data of service A.

[0175] S810 , the NPUn in the network card n1 determines the identity of the core QP corresponding to the identity of the destination vCPU according to the mapping relationship information in the network card n1 .

[0176] The mapping information in NIC n1 indicates the mapping relationship between the destination vCPU and the core QP in NIC n1. The mapping information in NIC n1 includes the identity of the destination vCPU and the identity of the core QP in NIC n1. The NPUn can determine the identity of the core QP corresponding to the identity of the destination vCPU from the mapping information. The core QP corresponding to the destination vCPU is the core QP that sends data to the destination vCPU.

[0177] For example, the mapping relationship information in the network card n1 is shown in Table 4. Among them, vCPUn1 corresponds to core QPhn1, vCPUn2 corresponds to core QPhn2, and so on, vCPUnk corresponds to core QPnk.

[0178] Table 4

[0179] It should be noted that the node referred to in the mapping relationship information can serve as a destination node or a source node. In different data transmission scenarios, the role of the node referred to in the mapping relationship information is different. In the scenario of the embodiment of the present application, the node referred to in the mapping relationship information refers to the destination node to which the data is to be sent.

[0180] S811 , network card n1 adds the data of service A in shared QPf1 to the core QP corresponding to the destination vCPU.

[0181] In the embodiment of the present application, the destination vCPU for the data of service A is vCPUnk. According to Table 4, the core QP corresponding to vCPUnk is core QPhnk. Network card n1 adds the data of service A to core QPhnk.

[0182] S812 , the network card n1 sends the data of service A in the core QP to the target storage space corresponding to the vCPUnk.

[0183] In an embodiment of the present application, a node may include a memory, which may include multiple storage spaces, with different vCPUs corresponding to different storage spaces. As a possible implementation, the vCPU stores the received data in a target storage space corresponding to the vCPU.

[0184] In this way, when the network card sends data to the node, the vCPU does not need to protect the QP access through a lock, avoiding the occupation of CPU resources during resource preemption between vCPUs and reducing the delay in the data reception process.

[0185] According to the solution provided by the embodiments of the present application, a dual-tier QP architecture is implemented in the network card, comprising multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor in the node, enabling the virtual processor in the node to exclusively occupy a core QP. Data requests from different virtual processors are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0186] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0187] The data transmission method provided in the embodiment of the present application is described in detail below based on Figures 2, 3, 6a to 6c, 7 and 8.

[0188] Figure 9 is a flow chart of a data transmission method provided in an embodiment of the present application. The data transmission method provided in an embodiment of the present application can be applied to the network card in the computer system shown in Figures 1 and 6a to 6c. In the embodiment of the present application, the computer system serves as the sending end. For ease of description, the network card at the sending end is referred to as the first network card, and the node at the sending end is referred to as the first node. It should be noted that any computer system in the network can serve as the sending end. As shown in Figure 9, the data transmission method provided in an embodiment of the present application includes S901 to S904.

[0189] S901: Receive multiple data requests, where the multiple data requests come from different virtual processors in a first processor.

[0190] The first node includes a first processor, which can be virtualized into multiple virtual processors. A data request is a request for transmitting data. The data request can include data, thereby transmitting the data to other nodes. The data request can also request data from other nodes.

[0191] The network card can receive multiple data requests, each of which originates from different virtual processors in the first processor. For example, as shown in Figure 6a, network card 62 receives data requests A, B, and C. Data request A originates from vCPUi1, data request B originates from vCPUi2, and data request C originates from vCPUim.

[0192] S902 , adding multiple data requests to core queues respectively, wherein each virtual processor corresponds to one core queue, and data requests from different virtual processors enter different core queues.

[0193] The first network card includes multiple core QPs, each of which corresponds one-to-one to a virtual processor in the node. That is, a virtual processor in the node exclusively occupies one core QP. After receiving multiple data requests, the first network card can add each of the multiple data requests to the core QP. Data requests from different virtual processors enter different core QPs. For example, as shown in Figure 6a, data request A comes from vCPUi1, which corresponds to core QPhi1. Network card 62 adds data request A to core QPhi1. Data request B comes from vCPUi2, which corresponds to core QPhi2. Network card 62 adds data request B to core QPhi2. Data request C comes from vCPUim, which corresponds to core QPhim. Network card 62 adds data request C to core QPhim.

[0194] In this way, the virtual processor in the node can exclusively access the core QP in the network card, avoiding resource preemption in the node's processor during data transmission and reducing the processor overhead in the node.

[0195] As one possible implementation, the data request includes the identity of the virtual processor from which the data request originates. For example, as shown in FIG7 , the source virtual processor is virtual processor vCPU12 in node 1, and the virtual processor's identity is vCPU12. Therefore, the service information includes vCPU12. Here, vCPU12 is merely used as an example of the virtual processor's identity. In actual applications, the virtual processor's identity can take other forms, such as the virtual processor's address in the node, and this embodiment of the application does not specifically limit this.

[0196] The first network card is pre-configured with second mapping relationship information. The second mapping relationship information indicates the mapping relationship between the virtual processor identifiers and the core QP identifiers. For example, as shown in FIG7 , vCPU11 in node 1 corresponds to core QPh11, vCPU12 corresponds to core QPh12, and so on, with vcpu1m corresponding to core QPh1m. The second mapping relationship information between the virtual processors in node n and network card n1 in Table 4 is described in the mapping information table for network card n1 and is not further described here.

[0197] Based on the virtual processor identity in the data request, the first network interface card determines the core QP identity corresponding to the virtual processor identity from the second mapping relationship information. Based on the core QP identity, the data request is added to the core QP. For example, as shown in Figure 6a, the second mapping relationship information for node i is shown in Table 5. The source virtual processor identity is i1. According to the second mapping relationship, the core QP identity corresponding to vCPUi1 is hi1. Therefore, the first core QP is core QPhi1, and the service data from vCPUi1 is added to core QPhi1.

[0198] Table 5

[0199] S903, taking out multiple data requests from the core queue, and adding the multiple data requests to the shared queue according to the destination nodes of each data request. Each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue.

[0200] The first network interface card includes multiple shared queues, each used to send data requests to the node corresponding to the shared queue. To avoid CPU resource contention when sending data requests to multiple nodes, shared queues correspond one-to-one with each node, and the shared queue where a data request resides is the shared queue corresponding to the destination node of the data request. For example, as shown in Figure 6a, shared QPpi1 is used to send data requests to node 1. Data requests destined for node 1 can enter shared QPpi1. Shared QPpi2 is used to send data requests to node 2. Data requests destined for node 2 can enter shared QPpi2.

[0201] The first NIC can retrieve multiple data requests from the core queue and, based on their respective destination nodes, add them to corresponding shared QPs. Data requests with the same destination node enter the same shared queue. This allows multiple core QPs to share multiple shared QPs, improving data transmission efficiency while reducing the number of shared QPs on the NIC.

[0202] In an embodiment of the present application, the data request includes an identity identifier of the destination node, and the first network card adds the data request to the shared QP corresponding to the destination node based on the identity identifier in the data request. In one possible implementation, the first network card is pre-configured with first mapping relationship information. The first mapping relationship information is used to indicate the mapping relationship between the identity identifier of the virtual processor and the identity identifier of the core queue. Based on the identity identifier of the destination node in the data request, the first network card can determine the identity identifier of the shared queue corresponding to the destination node from the first mapping relationship information, thereby determining the shared queue corresponding to the destination node. The first network card adds the data request to the shared queue based on the identity identifier of the shared queue.

[0203] For example, as shown in FIG6a , the first mapping relationship information is shown in Table 6. The first node corresponding to the first network interface card is node 1, and the destination node identifier of data request A is n. According to Table 6, the shared QP identifier corresponding to node n is p1n, that is, the first shared QP is shared QPp1n. The first network interface card adds data request A to the shared QPp1n.

[0204] Table 6

[0205] S904: Take out multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the corresponding destination node is located.

[0206] The first network card can take out multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the destination node of the data request is located.

[0207] In a possible implementation, the first network card can assemble the data request into a network message, thereby sending the network message to the network, and sending the data request to the destination computer system where the destination node is located through the network.

[0208] Here, illustratively, the process of data transmission by the first network card can also refer to the detailed description of S803 to S807 in the embodiment corresponding to FIG8 , which will not be repeated here.

[0209] According to an embodiment of the present application, a dual-tier QP architecture is implemented in a network card. The dual-tier QP architecture includes multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor in a node, allowing the virtual processor in the node to exclusively occupy a core QP. Data requests from different virtual processors are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0210] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0211] The data transmission method provided in the embodiment of the present application is described in detail below based on Figures 2, 3, 6a to 6c, 7 and 8.

[0212] Figure 10 is a flow chart of a data transmission method provided in an embodiment of the present application. The data transmission method provided in an embodiment of the present application can be applied to the network card in the computer system shown in Figures 1 and 6a to 6c. In this embodiment of the present application, the computer system is the receiving end. For ease of description, the network card at the receiving end is referred to as the second network card, and the node at the receiving end is referred to as the second node. As shown in Figure 10, the data transmission method provided in an embodiment of the present application includes S1001 to S1004.

[0213] S1001, receiving multiple data requests, where the multiple data requests come from different nodes.

[0214] The second network card can receive data requests from different nodes through the network.

[0215] A data request is a request for transmitting data. The data request may include data, thereby transmitting the data to the node where the second network card is located, that is, the second node. The data request may also request data from the second node.

[0216] S1002 , adding multiple data requests to shared queues respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue.

[0217] The second network interface card includes multiple shared queues, with different shared queues corresponding to different nodes. The second network interface card can receive data requests from different nodes, where data requests from different nodes enter different shared queues. For example, as shown in Figure 6a, data requests from node 1 enter shared QPpi1, data requests from node 2 enter shared QPpi2, and so on. Data requests from node n-1 enter shared QPpin-1.

[0218] As a possible implementation, the second network interface card is pre-configured with first mapping information, which indicates a mapping between a node's identity and a shared queue's identity. For example, the first mapping information may be as shown in Table 3. For details, see the detailed description of Table 3 in the above embodiment, and will not be repeated here.

[0219] The second network card can determine the identity of the shared queue corresponding to the identity of the node from the first mapping relationship information, thereby adding the data request to the shared queue.

[0220] For example, as shown in FIG7 , the network card n1 receives service information from the node 1 , the shared QPf1 in the network card n1 corresponds to the node 1 one-to-one, and the network card n1 adds the service information to the shared QPf1 .

[0221] S1003, taking out multiple data requests from the shared queue, and adding the multiple data requests to the core queue respectively according to the destination virtual processor of each data request, wherein data requests with different destination virtual processors enter different core queues.

[0222] The destination virtual processor is the endpoint of the data request. Different data requests can have the same or different destination virtual processors. The second network card adds the data request to the core queue based on the destination virtual processor of each data request. Data requests with different destination virtual processors enter different core queues. For example, as shown in Figure 6a, the destination virtual processor of data request A is vCPUi1. The second network card adds data request A to core QPhi1. The destination virtual processor of data request B is vCPUi2. The second network card adds data request B to core QPhi2.

[0223] In some possible implementations, the data request includes an identity of a destination virtual processor. The second network interface card can add the multiple data requests to a core queue based on the identity of the destination virtual processor. After adding the data request to the shared queue, the second network interface card can parse the data request to obtain the identity of the data request. Based on the identity of the destination virtual processor, the data request is added to the core queue corresponding to the destination virtual processor.

[0224] As a possible implementation, the second network interface card is pre-configured with second mapping information, which is used to indicate the mapping between the virtual processor identifier and the core queue identifier. For example, the second mapping information may be as shown in Table 4. For details, see the detailed description of Table 4 in the embodiment corresponding to FIG8 , and will not be repeated here.

[0225] Exemplarily, as shown in FIG7 , the identity of the destination virtual processor of the data of service A is nk, the identity of the core queue corresponding to vCPUnk is ynk, and the network card n1 adds the service data to the core QPynk.

[0226] The second network card can determine the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information based on the identity of the destination virtual processor. The second network card adds the service data to the core queue based on the identity of the core queue corresponding to the destination virtual processor.

[0227] S1004 , taking out multiple data requests from the core queue, and sending the multiple data requests to corresponding destination virtual processors.

[0228] According to an embodiment of the present application, a dual-tier QP architecture is implemented in a network interface card (NIC). The dual-tier QP architecture includes multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in a node, allowing the VPs in the node to exclusively use the core QP. Data requests from different destination VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0229] Taking the example of receiving a data request, if the node sending the data request is called the source node, and the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the ultimate recipient of the data request), multiple data requests originating from the same source node and sent to different destination virtual processors can be added to the shared QP corresponding to the source node and then to the core QP corresponding to each destination virtual processor. This allows the virtual processor to exclusively occupy the core QP, satisfying the virtual processor's requirement for exclusive QPs. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0230] Based on the same concept as the embodiment of the method of the present application, the embodiment of the present application also provides a data transmission device. The data transmission device includes several modules, each module is used to perform each step in the data transmission method provided in the embodiment of the present application, and the division of the modules is not limited here. Those skilled in the art can clearly understand that in actual applications, the various steps in the data transmission method provided in the embodiment of the present application can be assigned to different modules as needed, that is, the internal structure of the device is divided into different modules to complete all or part of the functions described above. The modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more modules can be integrated into a unit, and the above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the modules are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the modules in the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0231] For example, FIG11 is a schematic diagram of the structure of a data transmission device 1100 provided in an embodiment of the present application. The data transmission device provided in an embodiment of the present application can be applied to the network card in the computer system shown in FIG1 and FIG6a to FIG6c to execute the data transmission method in the embodiment corresponding to FIG9. For the convenience of description, the computer system is referred to as a first computer system, the first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, the first node communicates with multiple computer systems through the first network card, and the device is applied to the first network card. As shown in FIG11, the data transmission device 1100 provided in an embodiment of the present application includes:

[0232] A receiving module 1101 is configured to receive multiple data requests, each of which is from different virtual processors in the first processor and has a different destination node.

[0233] The processing module 1102 is configured to add multiple data requests to core queues respectively, wherein each virtual processor corresponds to one core queue, and data requests from different virtual processors enter different core queues;

[0234] The processing module is further configured to retrieve multiple data requests from the core queue and add the multiple data requests to a shared queue according to the destination nodes of each data request. Each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue.

[0235] The sending module 1103 is used to take out multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the corresponding destination node is located.

[0236] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture comprises multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0237] Taking sending a data request as an example, if the processor sending the data request is called the source processor, and the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data), multiple data requests from different source virtual processors sent to the same destination node first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. This allows the virtual processor to exclusively occupy the core QP, satisfying the requirement for exclusive QP ownership. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0238] In a possible implementation, the first network card is configured with first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the processing module is configured to:

[0239] According to the identity of the destination node, determining the identity of the shared queue corresponding to the destination node from the first mapping relationship information;

[0240] According to the identity identifier of the shared queue corresponding to the destination node, the data request is added to the shared queue.

[0241] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0242] In one possible implementation, the first network card is configured with second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes the identity of the virtual processor from which the data request originates, and the processing module is used to:

[0243] Determining, from the second mapping relationship information, an identity of a core queue to which each data request is to be added, according to an identity of a virtual processor from which each data request comes from among the multiple data requests;

[0244] According to the identity identifier of the core queue, multiple data requests are added to the core queue respectively.

[0245] In this way, the virtual processors in the node can monopolize the core QP, eliminating the need for resource preemption in the CPU, thus reducing CPU resource usage.

[0246] For example, Figure 12 is a schematic diagram of the structure of the data transmission device provided in an embodiment of the present application. The data transmission device provided in an embodiment of the present application can be applied to the network card in the computer system shown in Figure 1 and Figures 6a to 6c, and execute the data transmission method in the embodiment corresponding to Figure 10. In the embodiment of the present application, for the convenience of description, the computer system in the embodiment of the present application is referred to as the second computer system. The second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card through a bus, the second node communicates with multiple computer systems through the second network card, and the device is applied to the second network card. As shown in Figure 12, the data transmission device provided in an embodiment of the present application includes:

[0247] Receiving module 1201, configured to receive multiple data requests from different nodes;

[0248] The processing module 1202 is configured to add multiple data requests to a shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue;

[0249] The processing module 1202 is further configured to retrieve multiple data requests from the shared queue and add the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein data requests with different destination virtual processors enter different core queues;

[0250] The sending module 1203 is configured to retrieve multiple data requests from the core queue and send the multiple data requests to corresponding destination virtual processors.

[0251] This solution utilizes a two-tier QP architecture within the network interface card (NIC). This architecture consists of multiple core QPs in the first tier and multiple shared QPs in the second tier. Each core QP corresponds one-to-one with a virtual processor (VP) in the node, allowing the VPs in the node to exclusively use a core QP. Data requests from different destination VPs are then added to different core queues. Each shared QP corresponds one-to-one with a node in the network, and a single shared QP supports data transmission from multiple core QPs.

[0252] Taking the example of receiving a data request, if the node sending the data request is called the source node, and the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the ultimate recipient of the data request), multiple data requests originating from the same source node and sent to different destination virtual processors can be added to the shared QP corresponding to the source node and then to the core QP corresponding to each destination virtual processor. This allows the virtual processor to exclusively occupy the core QP, satisfying the virtual processor's requirement for exclusive QPs. Furthermore, a single shared QP can support data transmission from multiple core QPs, reducing CPU overhead within the node.

[0253] In one possible implementation, the second network card includes first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue. The data request includes the identity of a node from which the data request comes. Adding the multiple data requests to the shared queue respectively includes:

[0254] Determining, from the first mapping relationship information, an identity of a shared queue corresponding to the node according to an identity of a node in each of the multiple data requests;

[0255] According to the identity identifier of the shared queue, multiple data requests are added to the corresponding shared queue respectively.

[0256] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0257] In one possible implementation, the second network card includes second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue; the data request includes an identity of a destination virtual processor for the data request; and the processing module is used to:

[0258] According to the identity of the destination virtual processor of each data request, determining the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information;

[0259] According to the identity identifier of the core queue corresponding to the destination virtual processor, the data request is added to the corresponding core queue.

[0260] In this way, the virtual processors in the node can monopolize the core QP, eliminating the need for resource preemption in the CPU, thus reducing CPU resource usage.

[0261] Based on the same concept as the embodiment of the method of the present application, the embodiment of the present application also provides a network card. Figure 13 is a schematic diagram of the structure of a network card provided by the embodiment of the present application. As shown in Figure 13, the computer system includes a network card and a node, the node includes a processor, and the network card includes:

[0262] Computer bus interface 1301, for communicating with the node;

[0263] Network interface 1302, for communicating with other computer systems;

[0264] Processor 1303 is used to provide a core queue and a shared queue, and is further used to:

[0265] Acquire multiple data requests from the node via the computer bus interface, and add the multiple data requests to core queues respectively, wherein each virtual processor corresponds to one core queue, and data requests from different virtual processors enter different core queues;

[0266] Retrieving the multiple data requests from the core queue, and adding the multiple data requests to a shared queue respectively according to the destination node of each data request, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0267] The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

[0268] As a possible implementation manner, the processor 1303 provided in the embodiment of the present application may be a DPU.

[0269] The functions of the network card in the embodiment of the present application can be referred to the detailed description of the network card in Figures 6a to 6c and Figures 7 to 12 above, and will not be repeated here.

[0270] Based on the same concept as the embodiment of the method of the present application, the embodiment of the present application also provides a network card chip. Figure 14 is a schematic diagram of the structure of a network card chip provided in the embodiment of the present application. As shown in Figure 14, the computer system includes a network card and a node. The network card and the node communicate via a computer bus. The node communicates with other nodes via the network card. The network card includes a network card chip 1401, a computer bus interface 1402, and a network interface 1403.

[0271] The network card chip 1401 includes:

[0272] Power supply 1411, used to supply power to the network card chip;

[0273] The main body 1412 of the network card chip is used to provide a core queue and a shared queue, wherein the network card chip is also used to:

[0274] Adding the multiple data requests to core queues respectively, wherein each virtual processor corresponds to one core queue, and data requests from different virtual processors enter different core queues;

[0275] Retrieving the multiple data requests from the core queue, and adding the multiple data requests to a shared queue respectively according to the destination node of each data request, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0276] The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

[0277] The functions of the network card chip in the embodiment of the present application can be found in the detailed description of the network card in Figures 6a to 6c and Figures 7 to 12 above, and will not be repeated here.

[0278] Based on the same concept as the method embodiment of the present application, the embodiment of the present application further provides a computing device, which can be a server, a storage node, etc.

[0279] FIG14 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application.

[0280] As shown in FIG. 15 , the computing device 1500 includes a processor 1501 , a memory 102 , and a network interface 1503 .

[0281] The processor 1501 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0282] Among them, the non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0283] For example, the memory 1502 may store a computer program, and when the processor 1501 executes the computer program, the steps in the above-mentioned method embodiment are implemented. Alternatively, when the processor 1501 executes the computer program, the functions of the modules in the above-mentioned device embodiment are implemented. For example, the computer program can be divided into one or more modules / units, and the one or more modules / units can be a series of computer program instruction segments that can perform specific functions. The one or more modules / units are stored in the memory 1502 and executed by the processor 1501 to complete the present application. For example, the computer program can be divided into multiple modules, such as the modules in the device described above.

[0284] The network interface 1503 is used to send and receive data, for example, to send data processed by the processor 1501 to other computing devices, or to receive data sent by other computing devices.

[0285] Of course, for the sake of simplicity, FIG15 only shows some of the components of the computing device 1500 that are relevant to the present application, omitting components such as buses, input / output interfaces, and the like. Furthermore, depending on the specific application, the computing device 1500 may also include any other appropriate components. Furthermore, the computing device may be a desktop computer, a notebook, a PDA, a cloud server, or other computing devices. Those skilled in the art will appreciate that FIG15 is merely an example of a computing device 1500 and does not constitute a limitation of the computing device. The computing device may include more or fewer components than shown, or a combination of certain components, or different components. For example, the computing device may also include input devices, output devices, network access devices, buses, and the like. For example, the input device may be a microphone array, or may include, for example, a keyboard, a mouse, and the like. For example, the output device may output various information to the outside world and may include, for example, a display, a speaker, a printer, a communication network, and its connected remote output devices.

[0286] In addition to the above-mentioned methods, devices and electronic devices, embodiments of the present application may also provide a computer program product, which includes computer program instructions, which, when executed by a processor, cause the processor to execute the steps in the methods of the various embodiments of the present application described in the "Method" section above. The computer program product may be written in any combination of one or more programming languages ​​to write computer program codes for executing the operations of the embodiments of the present application, and the programming languages ​​include object-oriented programming languages ​​such as Java, C++, etc., and also include conventional procedural programming languages ​​such as "C" language or similar programming languages. The computer program code may be in source code form, object code form, executable file or some intermediate form, etc. The computer program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0287] In addition, an embodiment of the present application may also provide a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, causes the processor to execute the steps in the display control method according to various embodiments of the present application described in the "Method" section above. The computer-readable storage medium may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, include but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0288] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0289] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0290] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0291] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0292] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of this application. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit this application to necessarily being implemented using the above specific details.

[0293] The block diagrams of the devices, devices, equipment, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0294] It should also be noted that in the apparatus, device, and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0295] The above description has been provided for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0296] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

Claims

1. A data transmission method, characterized in that: The first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, and the first node communicates with multiple computer systems through the first network card. The method includes: The first network card receives a plurality of data requests, where the plurality of data requests come from different virtual processors in the first processor respectively; The first network card adds the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; The first network card takes out the multiple data requests from the core queue, and adds the multiple data requests to a shared queue respectively according to a destination node of each of the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue; The first network card takes out the multiple data requests from the shared queue, and sends the multiple data requests to a destination computer system where a corresponding destination node is located.

2. The method according to claim 1, characterized in that The first network card is configured with first mapping relationship information, the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the adding the multiple data requests to the shared queue respectively according to a destination node of each of the multiple data requests comprises: According to the identity of the destination node, determining the identity of the shared queue corresponding to the destination node from the first mapping relationship information; The data request is added to the shared queue according to the identity identifier of the shared queue corresponding to the destination node.

3. The method according to claim 1 or 2, characterized in that: The first network card is configured with second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes the identity of the virtual processor from which the data request comes, and the adding the multiple data requests to the core queues respectively includes: According to the identity of the virtual processor from which each of the multiple data requests comes, determining from the second mapping relationship information the identity of the core queue to which each of the data requests is to be added; According to the identity identifier of the core queue, the multiple data requests are added to the core queue respectively.

4. A data transmission method, characterized in that: The second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card via a bus, and the second node communicates with a plurality of computer systems via the second network card, the method including: The second network card receives multiple data requests, where the multiple data requests come from different nodes; The second network card adds the multiple data requests to a shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue; The second network card takes out the multiple data requests from the shared queue, and adds the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein the data requests with different destination virtual processors enter different core queues; The second network card takes out the multiple data requests from the core queue, and sends the multiple data requests to corresponding destination virtual processors.

5. A data transmission device, characterized in that: The first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, the first node communicates with a plurality of computer systems through the first network card, the device is applied to the first network card, and the device includes: A receiving module, configured to receive a plurality of data requests, wherein the plurality of data requests are respectively from different virtual processors in the first processor, and the destination node of each of the data requests is different; A processing module, used for adding the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; The processing module is also used to take out the multiple data requests from the core queue, and add the multiple data requests to the shared queue respectively according to the destination node of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, and the destination node corresponds to a shared queue. Data requests with the same target node enter the same shared queue; The sending module is used to take out the multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the corresponding destination node is located.

6. The device according to claim 5, characterized in that The first network card is configured with first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the processing module is used to: According to the identity of the destination node, determining the identity of the shared queue corresponding to the destination node from the first mapping relationship information; The data request is added to the shared queue according to the identity identifier of the shared queue corresponding to the destination node.

7. The device according to claim 5 or 6, characterized in that The first network card is configured with second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes an identity of a virtual processor from which the data request comes, and the processing module is used to: According to the identity of the virtual processor from which each of the multiple data requests comes, determining from the second mapping relationship information the identity of the core queue to which each of the data requests is to be added; According to the identity identifier of the core queue, the multiple data requests are added to the core queue respectively.

8. A data transmission device, characterized in that: The second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card via a bus, the second node communicates with a plurality of computer systems via the second network card, the device is applied to the second network card, and the device includes: A receiving module, used for receiving multiple data requests, where the multiple data requests come from different nodes; A processing module, used for adding the multiple data requests to a shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue; The second network card takes out the multiple data requests from the shared queue, and adds the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein the data requests with different destination virtual processors enter different core queues; The second network card takes out the multiple data requests from the core queue, and sends the multiple data requests to corresponding destination virtual processors.

9. A network card, characterized in that: The computer system includes a network card and a node, wherein the node includes a processor, and the network card includes: A computer bus interface for communicating with the node; Network interfaces for communicating with other computer systems; Processors are used to provide core queues and shared queues, and are also used to: Acquire multiple data requests from the node through the computer bus interface, and add the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; Taking out the multiple data requests from the core queue, and adding the multiple data requests to the shared queue respectively according to the destination node of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue; The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

10. A network card chip, characterized in that: The computer system includes a network card and a node, the network card and the node communicate via a computer bus, the node communicates with other nodes via the network card, and the network card includes a network card chip, a computer bus interface and a network interface; The network card chip comprises: A power supply, used to supply power to the main body of the network card chip; The main body of the network card chip is used to provide a core queue and a shared queue, wherein the network card chip is also used to: Adding multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; The plurality of data requests are taken out from the core queue, and the plurality of data requests are added to the shared queue respectively according to the destination node of each data request in the plurality of data requests, wherein each destination node corresponds to a shared queue. Column, data requests with the same target node enter the same shared queue; The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

11. A computer, characterized in that: The method comprises a node and a network card, wherein the network card is used to execute the method according to any one of claims 1 to 3, or execute the method according to claim 4.

12. A data transmission device, characterized in that: include: at least one memory for storing a program; At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method according to any one of claims 1 to 3, or execute the method according to claim 4.

13. A data transmission device, characterized in that: The device runs computer program instructions to perform the method according to any one of claims 1 to 3, or to perform the method according to claim 4.

14. A computer storage medium, wherein instructions are stored in the computer storage medium, and when the instructions are executed on a computer, the computer executes the method according to any one of claims 1 to 3, or executes the method according to claim 4.

15. A computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method according to any one of claims 1 to 3, or the method according to claim 4.

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