Capacitor and manufacturing method therefor, semiconductor assembly, and electronic device

Abstract

A capacitor and a manufacturing method therefor, a semiconductor assembly, and an electronic device, relating to the technical field of electronics, used for reducing the impact of capacitor vibration on carrier plates. The semiconductor assembly comprises a carrier plate and a capacitor arranged on the carrier plate. The capacitor comprises a capacitor body and first electrodes; the first electrodes are respectively arranged at two opposite ends of the capacitor body; the capacitor body comprises a plurality of dielectric layers and a plurality of layers of second electrodes; the plurality of dielectric layers are stacked, and the dielectric layers intersect with the carrier plate; the second electrodes are arranged between two adjacent dielectric layers, two adjacent layers of second electrodes are staggered, and two adjacent layers of second electrodes are coupled with the first electrodes located on different sides. By adjusting the shape of the first electrodes, the dielectric layers in the capacitor all intersect with or are all perpendicular to the carrier plate. As a result, the vibration direction of the capacitor intersects with or is perpendicular to the carrier plate, thereby reducing resonance of the carrier plate and inhibiting the problem of "plate vibration".

Description

Capacitor and preparation method thereof, semiconductor component, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on August 4, 2023, with application number 202310984255.5 and application name “Capacitors and methods for their preparation, semiconductor components, and electronic devices,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a capacitor and a preparation method thereof, a semiconductor component, and an electronic device. Background Art

[0003] Multi-layer ceramic capacitors (MLCCs) are one of the main passive chip components in electronic devices due to their high reliability, high precision, high frequency, low power consumption, large capacity, miniaturization and low cost.

[0004] Mainstream MLCCs are formed by stacking dielectric layers with printed second electrodes in an offset manner, then sealing the first electrodes at both ends of the stack. During use, due to the inverse piezoelectric effect of the dielectric layer, when an AC voltage is applied, the dielectric layer expands and contracts in the direction of the stack, causing the MLCC to vibrate. This vibration can cause the substrate supporting the MLCC to resonate, leading to substrate bending, lead breakage, and disconnection of coupling components, thus affecting the overall performance of the device.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a capacitor and a method for manufacturing the same, a semiconductor component, and an electronic device for reducing the impact of capacitor vibration on a carrier.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present application, a semiconductor component is provided, comprising a carrier and a capacitor disposed on the carrier. The capacitor comprises a capacitor body and a first electrode, wherein the first electrodes are disposed at opposite ends of the capacitor body; the capacitor body comprises multiple dielectric layers and multiple second electrodes; the multiple dielectric layers are stacked and intersect with the carrier; the second electrode is disposed between two adjacent dielectric layers, the two adjacent layers of second electrodes are staggered, and the two adjacent layers of second electrodes are coupled to the first electrode on different sides. The first electrode comprises a first surface and a second surface, wherein the first surface intersects with the dielectric layer and is parallel to the carrier, and can be understood as the top and bottom surfaces of the first electrode; the second surface is parallel to the dielectric layer and intersects with the carrier, and can be understood as the front and back surfaces of the first electrode. The capacitor is coupled to the carrier via the first surface; the area of ​​the first surface is greater than the area of ​​the second surface. In other words, the surface with the larger area of ​​the first electrode is used for coupling with the carrier.

[0009] In the semiconductor assembly provided by the embodiments of the present application, the first surface of the first electrode intersects the dielectric layer, and the second surface of the first electrode is parallel to the dielectric layer. By setting the area of ​​the first surface of the first electrode to be larger than the area of ​​the second surface, the first surface for coupling to the carrier can be clearly distinguished. Therefore, during the capacitor manufacturing process, each capacitor can be directly placed in the desired position, with little or no random placement, thereby limiting the placement of the capacitors. In this way, when the capacitors are assembled with the carrier, the first and second surfaces of the capacitors have different shapes, and the capacitors are all placed in the desired position. Therefore, the first surface of the capacitor can be identified, ensuring that the stack of the dielectric layer and the second electrode of the capacitor is positioned intersecting (e.g., perpendicular) with the carrier. In this way, even if an electric field is applied to the first electrode, the dielectric layer expands in the direction of the applied electric field and contracts perpendicular to the applied electric field, the capacitor will still vibrate during operation. However, the orientation of the dielectric layer stack intersects the carrier, and the capacitor vibration direction is parallel to the carrier. This can reduce the resonance of the carrier, minimize the impact of capacitor vibration on the carrier, and suppress the "plate vibration" problem of the carrier.

[0010] In one possible implementation, a first dimension of the first electrode along a first direction (capacitor width direction) is greater than a second dimension of the first electrode along a second direction (capacitor thickness direction or capacitor length direction); the first direction is the direction in which multiple dielectric layers are stacked, and the second direction intersects the first direction. By setting the first dimension of the first electrode to be greater than the second dimension of the first electrode, the long side and short side of the capacitor (the stacking direction and parallel direction of the dielectric layers) can be clearly distinguished, so that all capacitors are placed in the expected position to better suppress the "plate vibration" problem.

[0011] In one possible implementation, the second direction also intersects the carrier. In other words, the second direction is the thickness direction of the capacitor. This can clearly distinguish between the direction in which the dielectric layers are stacked and the direction in which the dielectric layers are parallel.

[0012] In one possible implementation, the first dimension is more than twice the second dimension. Since the first surface and the second surface share the third dimension, setting the first dimension to more than twice the second dimension can increase the difference between the first surface and the second surface, making it easier to place the capacitor in a desired orientation.

[0013] In one possible implementation, the first dimension is less than 0.5 mm. The capacitor structure provided in the embodiment of the present application is still applicable even when the width of the capacitor is less than 0.5 mm, and is applicable to capacitors of various sizes.

[0014] In one possible implementation, the first surface is a rectangle, and the first size is the size of the long side of the rectangle. This can clearly distinguish the long side and the short side of the capacitor, so that all capacitors are placed in the expected position to better suppress the "board vibration" problem.

[0015] In one possible implementation, the dielectric layer is perpendicular to the carrier. In this placement, the capacitor's vibration component parallel to the carrier is almost zero, effectively suppressing "plate vibration."

[0016] According to a second aspect of an embodiment of the present application, a capacitor is provided, comprising: a capacitor body and a first electrode; the first electrodes are respectively provided at opposite ends of the capacitor body; the capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the plurality of dielectric layers are stacked along a first direction; the second electrode is provided between two adjacent dielectric layers, the two adjacent second electrodes are staggered, and the two adjacent second electrodes are coupled to the first electrodes on different sides; the first electrode comprises a first surface and a second surface, the first surface intersects with the dielectric layer, and the first surfaces of the two first electrodes are located in the same plane, and the second surface is parallel to the dielectric layer; the area of ​​the first surface is greater than the area of ​​the second surface. The capacitor provided in an embodiment of the present application can clearly distinguish the stacking direction and the parallel direction of the dielectric layer by setting the area of ​​the first surface of the first electrode to be greater than the area of ​​the second surface, so that all capacitors are patched in the expected position to better suppress the "plate vibration" problem.

[0017] In one possible implementation, a first dimension of the first electrode along a first direction is greater than a second dimension of the first electrode along a second direction, the second direction intersects the first direction, and the second direction also intersects a direction from one first electrode to another first electrode. The capacitor provided in the embodiment of the present application, by setting the first dimension of the first electrode along the dielectric layer stacking direction to be greater than the second dimension of the first electrode along the second direction, can clearly distinguish between the dielectric layer stacking direction and the parallel direction, so that all capacitors are patched in the expected position, thereby better suppressing the "plate vibration" problem.

[0018] In one possible implementation, the first size is more than twice the second size, which can increase the difference between the first size and the second size, making it easier to place the capacitor in a desired position.

[0019] In one possible implementation, the first dimension is less than 0.5 mm. The capacitor structure provided in the embodiment of the present application is still applicable even when the width of the capacitor is less than 0.5 mm, and is applicable to capacitors of various sizes.

[0020] A third aspect of the present application provides an electronic device, comprising: a housing and a semiconductor component disposed within the housing; the semiconductor component comprising any of the semiconductor components of the first aspect; or a housing and a capacitor disposed within the housing; the capacitor comprising any of the capacitors of the second aspect.

[0021] According to a fourth aspect of an embodiment of the present application, a method for preparing a capacitor is provided, comprising: forming a capacitor body stack, the capacitor body stack comprising a plurality of dielectric films with a second electrode printed on the surface thereof; cutting the capacitor body stack to form a plurality of capacitor bodies; the fourth dimension of the capacitor body being greater than the fifth dimension of the capacitor body, the fourth dimension being the dimension in the dielectric film stacking direction, and the fifth dimension being the dimension in the second electrode width direction; forming a first electrode at both ends of the capacitor body in a direction parallel to the length of the second electrode to form a capacitor; positioning the capacitor on a carrier so that the surface where the fourth dimension of the capacitor is located is parallel to the carrier; and taping the capacitor.

[0022] By adopting the method for preparing capacitors provided in the embodiment of the present application, the prepared capacitors are all placed according to the patch angle, so that the "plate vibration" problem can be suppressed after the capacitors are patched.

[0023] In a possible implementation, performing a positional processing on the capacitor includes performing a vibration screening process on the capacitor. This positional processing method is simple in process, easy to implement, and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention;

[0025] FIG2 is a perspective schematic diagram of a capacitor according to an embodiment of the present application;

[0026] FIG3 is a schematic diagram of the layout of a second electrode in a capacitor according to an embodiment of the present application;

[0027] FIG4 is a schematic structural diagram of a semiconductor assembly consisting of a capacitor and a circuit board according to an embodiment of the present application;

[0028] FIG5 is a schematic structural diagram of a capacitor provided in an embodiment of the present application;

[0029] FIG6 is a schematic diagram of the layout of a second electrode in a capacitor provided in an embodiment of the present application;

[0030] FIG7 is a schematic diagram of a preparation process of a capacitor provided in an embodiment of the present application;

[0031] FIG8 is a schematic diagram of a portion of the preparation process of a capacitor provided in an embodiment of the present application;

[0032] FIG9 is a schematic structural diagram of a semiconductor assembly provided in an embodiment of the present application;

[0033] FIG10 is an architectural diagram of a radio frequency front-end module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0035] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0036] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0037] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0038] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0039] An embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product with a camera or display function, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronic products include servers, non-volatile memories, radars, base stations and other communication equipment. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device.

[0040] FIG1 is an architecture diagram of an electronic device provided in an embodiment of the present application.

[0041] Taking the electronic device provided in the embodiment of the present application as a mobile phone as an example, illustratively, as shown in Figure 1, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a camera 190 and a display screen 191, etc.

[0042] It should be understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0043] In some embodiments, the electronic device 100 also includes a circuit board. The processor 110, internal memory 121, power management module 141, microphone 170C and other electronic components in the electronic device 100 can be set on the circuit board. The circuit board is used to carry the above-mentioned electronic components and complete signal interaction with the above-mentioned electronic components.

[0044] In some embodiments, the electronic device 100 further includes a capacitor mounted on the circuit board. For example, the capacitor can be secured to the circuit board by soldering. The capacitor is electrically connected to the circuit board to provide circuit tuning, bypassing, coupling, or filtering functions. Of course, the capacitor can be integrated into other electronic devices mounted on the circuit board, or it can be independently mounted on the circuit board.

[0045] FIG2 is a three-dimensional schematic diagram of a capacitor according to an embodiment of the present application, and FIG3 is a schematic diagram of the layout of a second electrode in a capacitor according to an embodiment of the present application.

[0046] Regarding the structure of the capacitor, in some embodiments, as shown in Figures 2 and 3, the capacitor 10 includes a capacitor body 11 and a first electrode (or terminal electrode) 12. The first electrode 12 has a first dimension s1 along a first direction X that is equal to a second dimension s2 along a second direction Z. The shape of the first surface a1 of the first electrode 12 is the same as the shape of the second surface a2.

[0047] The capacitor body 11 includes multiple dielectric layers 111 and multiple second electrodes 112, which are alternately arranged along a second direction Z. Therefore, the dimension of the first electrode 12 in the arrangement direction of the capacitor body 11 is equal to the width of the dielectric layer 111. To clearly illustrate the structure of the second electrode 112, the dielectric layer 111 is not shown in FIG3. The arrangement of the dielectric layer 111 can refer to FIG2.

[0048] FIG4 is a schematic structural diagram of a semiconductor assembly consisting of a capacitor and a circuit board according to an embodiment of the present application.

[0049] As shown in FIG4 , the surface of the circuit board 20 used to support the capacitor 10 is parallel to the plane formed by the first direction X and the third direction Y. The capacitor 10 is disposed on the surface of the circuit board 20 , and the arrangement direction of the multi-layer dielectric layers 111 and the multi-layer second electrodes 112 in the capacitor 10 is perpendicular to the circuit board 20 .

[0050] During use, due to the inverse piezoelectric effect of the dielectric layer 111, when an AC voltage is applied, the dielectric layer 111 expands and contracts in the second direction Z, causing the capacitor 10 to vibrate in the second direction Z. The vibration of the capacitor 10 can cause resonance in the circuit board supporting the capacitor 10, which is commonly referred to in the art as the "board vibration" problem.

[0051] At present, there are the following board-level countermeasures to the "board vibration" problem: first, simplify the capacitors, second, split the large package capacitors into multiple small package capacitors, third, control the periodic voltage drop across the capacitor 10, fourth, adjust the board-level layout position and placement direction of the capacitor 10, and fifth, prepare the capacitor 10 with a pad or a bracket.

[0052] However, the existing board-level countermeasures cannot completely solve the "board vibration" problem in various application scenarios and are of limited use. Moreover, these board-level countermeasures are difficult to process, expensive, and require large packages. For example, the smallest package structure of the current capacitor 10 with a pad has a metric size of length * width (the seventh dimension s7 * the first dimension s1 in the third direction Y) of 1.0mm * 0.5mm, which is commonly referred to in the art as the "04*02" specification, and cannot be further applied to capacitors 10 of smaller sizes.

[0053] Based on this, an embodiment of the present application provides a capacitor 10 for effectively improving the "plate vibration" problem in various application scenarios.

[0054] The following is an illustrative description of the capacitor and the components including the capacitor provided in the embodiments of the present application.

[0055] FIG5 is a schematic diagram of the structure of a capacitor provided in an embodiment of the present application, and FIG6 is a schematic diagram of the layout of a second electrode in a capacitor provided in an embodiment of the present application.

[0056] As shown in FIG5 , an embodiment of the present application provides a capacitor 10 , which is, for example, a multi-layer ceramic capacitor (MLCC) and includes a capacitor body 11 and a first electrode 12 .

[0057] First electrodes 12 are provided at opposite ends of the capacitor body 11. When the capacitor 10 is coupled to the circuit board 20, the capacitor 10 is coupled to the circuit board 20 via the first electrodes 12 to complete signal exchange. Therefore, the first electrodes 12 can serve as lead terminals of the capacitor body 11, thereby facilitating electrical connection of the capacitor body 11 to an external circuit.

[0058] As shown in Figures 5 and 6, the capacitor body 11 includes a multi-layer dielectric layer 111 and a multi-layer second electrode 112. The dielectric layer 111 and the second electrode 112 extend in a plane enclosed by the second direction Z and the third direction Y, and the multi-layer dielectric layer 111 and the multi-layer second electrode 112 are stacked along the first direction X. For example, along the first direction X, the multi-layer dielectric layer 111 is stacked, and the second electrode 112 is arranged between two adjacent dielectric layers 111. For example, along the first direction X, the dielectric layer 111 and the second electrode 112 are alternately arranged. That is, a second electrode 112 is arranged between any two dielectric layers 111. Or, for example, along the first direction X, the second electrode 112 is arranged between some of the dielectric layers 111, and the second electrode 112 is not arranged between some of the dielectric layers 111. The embodiment of the present application is not limited to this, as long as a dielectric layer 111 is provided on both sides of any second electrode 112.

[0059] It should be understood that the embodiment of the present application does not limit the shape of the second electrode 112. The second electrode 112 can be a sheet electrode as shown in Figure 6, or it can be an electrode of any other shape. The figure is only a schematic diagram. For example, the shape of the second electrode 112 is selected from at least one of a rectangle, a trapezoid, a triangle, a diamond or a circle. The embodiment of the present application does not limit the number of layers of the second electrode 112. A total of four second electrodes 112 are shown in Figure 6. However, any number of second electrodes 112 can be used in the capacitor 10 to obtain the capacitance required for the application. In order to clearly illustrate the arrangement of the second electrode 112, the dielectric layer 111 is not illustrated in Figure 6. The arrangement of the dielectric layer 111 can refer to that shown in Figure 5.

[0060] In addition, the staggered arrangement of two adjacent layers of second electrodes 112 in the capacitor body 11 can also be understood as the projections of the two adjacent layers of second electrodes 112 on the dielectric layer 111 overlapping but not overlapping (overlapping). Alternatively, it can be understood as the staggered arrangement of two adjacent layers of second electrodes 112 in a relative and spaced-apart manner along the first direction X.

[0061] On this basis, two adjacent layers of second electrodes 112 are coupled to the first electrodes 12 located on different sides. For example, along the third direction Y, two first electrodes 12 are arranged on opposite first sides (e.g., the left side) and second sides (e.g., the right side) of the multi-layer second electrodes 112. The second electrodes 112 of the odd-numbered layers are coupled to the first electrodes 12 on the first side, and the second electrodes 112 of the even-numbered layers are coupled to the first electrodes 12 on the second side.

[0062] In some embodiments, the distance between the surfaces of the two first electrodes 12 coupled to the second electrode 112 is greater than the dimension of the second electrode 112 along the first direction X. Therefore, a gap exists between the second electrode 112 coupled to the first electrode 12 on the first side and the first electrode 12 on the second side. Similarly, a gap exists between the second electrode 112 coupled to the first electrode 12 on the second side and the first electrode 12 on the first side.

[0063] In the embodiment of the present application, the dielectric layer 111 may be formed of a specific type of material having a specific dielectric constant. For example, in some embodiments, the dielectric layer 111 may be formed of a material having a relatively high dielectric constant (K).

[0064] In some embodiments, the material of dielectric layer 111 may include ceramic. The ceramic may be provided in various forms, for example, as a pre-fired wafer or as a co-fired dielectric material within the device itself.

[0065] For example, the material of the dielectric layer 111 may include perovskite. For example, the material of the dielectric layer 111 may include barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc.

[0066] In other embodiments, the material of the dielectric layer 111 may include oxide.

[0067] For example, the material of the dielectric layer 111 may include zinc, zirconium, niobium, magnesium, tantalum, titanium, cobalt, strontium, neodymium, samarium, silicon, etc., or a mixture thereof.

[0068] In yet other embodiments, the material of the dielectric layer 111 may include a combination of titanate and oxide.

[0069] For example, the material of the dielectric layer 111 may include a combination of barium titanate and oxide.

[0070] In the embodiment of the present application, the first electrode 12 and the second electrode 112 can be formed of any conductive metal known in the art.

[0071] In some embodiments, the materials of the first electrode 12 and the second electrode 112 may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, aluminum, zinc, etc.), alloys (e.g., titanium / tungsten alloy, chromium / nickel alloy, copper alloy), etc., and various combinations thereof.

[0072] The first electrode 12 is coupled to the second electrode 112. For example, the first electrode 12 may wrap around the entire end of the capacitor body 11 where the second electrode 112 is exposed. In this way, the connection strength between the first electrode 12 and the capacitor body 11 can be improved, while ensuring reliable electrical connection between the first electrode 12 and each second electrode 112 exposed from the end of the capacitor body 11.

[0073] In some embodiments, the surface of the first electrode 12 may be plated with other conductive materials.

[0074] Of course, the embodiment of the present application does not limit the structural relationship between the first electrode 12 and the capacitor body 11. When identifying the size of the first electrode 12 in the capacitor 10 provided in the embodiment of the present application, the size of the first electrode 12 that can be directly seen from the appearance of the capacitor 10 without cutting open the capacitor 10 shall prevail.

[0075] In the embodiment of the present application, the first direction X is the direction in which the dielectric layers 111 are stacked, the third direction Y is the direction from one first electrode 12 to another first electrode 12 (or understood as the length direction of the second electrode 112), and the second direction Z intersects both the first direction X and the third direction Z. The second direction Z is the width direction of the second electrode 112.

[0076] 5 , in some embodiments, the first electrode 12 includes two first surfaces a1 parallel to the first direction X and the third direction Y, two second surfaces a2 parallel to the second direction Z and the third direction Y, and two third surfaces a3 parallel to the first direction X and the second direction Z.

[0077] One of the two first surfaces a1 of the first electrode 12 is used for coupling with the carrier, while the other first surface a1 intersects with the dielectric layer 111 and is parallel to the carrier. After the capacitor 10 is coupled to the carrier, the two second surfaces a2 of the first electrode 12 are parallel to the dielectric layer 111 and intersect with the carrier (e.g., perpendicularly). The two third surfaces a3 of the first electrode 12 also intersect with the dielectric layer 111 and intersect with the carrier (e.g., perpendicularly). One of the two third surfaces a3 of the first electrode 12 (the inner surface) is coupled to the second electrode 112.

[0078] The first surfaces a1 of the two first electrodes 12 of the capacitor 10 coupled to the carrier are located in the same plane, and the first surfaces a1 of the two first electrodes 12 not coupled to the carrier are located in the same plane. The second surfaces a2 of the two first electrodes 12 located on the same side of the capacitor 10 are located in the same plane, and the third surfaces a3 of the two first electrodes 12 are located in different planes.

[0079] In some embodiments, from an external perspective, the area of ​​the first surface a1 of the first electrode 12 is larger than the area of ​​the second surface a2 .

[0080] For example, the first surface a1 and the second surface a2 are both rectangular, and a first dimension s1 of the first electrode 12 along the first direction X is greater than a second dimension s2 of the first electrode 12 along the second direction Z.

[0081] For example, the first dimension s1 is larger than the third dimension s3 of the first electrode 12 along the third direction Y. The first surface a1 is a rectangle, the first dimension s1 is the dimension of the long side of the rectangle, and the third dimension s3 is the dimension of the short side of the rectangle. The second surface a2 is a square.

[0082] Alternatively, for example, the first size s1 is equal to the third size s3 of the first electrode 12 along the third direction Y, the first surface a1 is a square, and the second surface a2 is a rectangle.

[0083] Of course, in the above two cases, the first surface a1 and the second surface a2 may both be rectangular.

[0084] In some embodiments, from an appearance perspective, the area of ​​the first surface a1 of the first electrode 12 is greater than or equal to the area of ​​the third surface a3 .

[0085] For example, the first surface a1 and the third surface a3 are both rectangular. For example, the first surface a1 is a rectangle, and the third surface a3 is a rectangle.

[0086] In some embodiments, from the appearance, among the first size s1 , the second size s2 , and the third size s3 of the first electrode, the first size s1 is the largest, and the second size s2 and the third size s3 may be equal or unequal.

[0087] It should be noted that in the embodiment of the present application, the second direction may also be a direction from one first electrode 12 to another first electrode 12. Correspondingly, the third direction intersects both the first direction X and the second direction and is the width direction of the second electrode 112. The embodiment of the present application is merely illustrative and does not constitute any limitation.

[0088] By setting the first dimension s1 of the first electrode 12 along the first direction X to be larger than the second dimension s2 of the first electrode 12 along the second direction Z, the long side and the short side of the capacitor 10 can be clearly distinguished so that all capacitors 10 are placed in the expected position to better suppress the "plate vibration" problem.

[0089] In some embodiments, the first size s1 is more than twice the second size s2.

[0090] Since the first surface a1 and the second surface a2 share the third size s3, setting the first size s1 to be more than twice the second size s2 can increase the difference between the first surface a1 and the second surface a2, making it easier to place the capacitor 10 in a desired orientation when preparing the capacitor 10.

[0091] In some embodiments, the capacitor 10 provided in the embodiment of the present application is suitable for s7*s1 (length*width) of 2.5mm*2.0mm (metric "2520", imperial "1008"), s7*s1 of 2.0mm*1.25mm (metric "2012", imperial "0805"), s7*s1 of 1.6mm*0.8mm (metric "1608", imperial "0603"), s7*s1 of 1.0mm*0.5mm (metric "1005", imperial " 0402”), s7*s1 is 0.6mm*0.3mm (metric “0603”, imperial “0201”), s7*s1 is 0.4mm*0.2mm (metric “0402”, imperial “01005”), s7*s1 is 0.3mm*0.15mm (metric “03015”, imperial “009005”), s7*s1 is 0.25mm*0.125mm (metric “0201”, imperial “008004”) size capacitor 10.

[0092] In some embodiments, the first dimension of the first electrode 12 is less than 0.5 mm.

[0093] The structure of the capacitor 10 provided in the embodiment of the present application is still applicable when the width of the capacitor 10 is less than 0.5 mm, and is applicable to capacitors 10 of various sizes.

[0094] FIG7 is a schematic diagram of a preparation process of a capacitor provided in an embodiment of the present application, and FIG8 is a schematic diagram of a partial preparation process of a capacitor provided in an embodiment of the present application.

[0095] The embodiment of the present application further provides a method for preparing a capacitor 10, as shown in FIG7 , comprising:

[0096] S1. Ingredients.

[0097] Ceramic materials, adhesives, solvents, etc. are ball-milled in a certain proportion for a certain period of time to form ceramic slurry.

[0098] S2: Casting.

[0099] The ceramic slurry is passed through the pouring nozzle of the casting machine and coated on the circulating polyethylene terephthalate (PET) film, thereby forming a uniform thin layer of slurry. The slurry then passes through the hot air zone (to evaporate most of the solvent in the slurry) and is dried to obtain a dielectric film (ceramic diaphragm).

[0100] S3: Printing.

[0101] The second electrode 112 slurry is printed onto the dielectric film using a screen printing plate according to process requirements.

[0102] S4: Lamination.

[0103] The dielectric films printed with the second electrode are stacked together according to the designed offset requirements, and upper and lower protective layer films are made to form a capacitor body stack (Bar), which includes multiple layers of dielectric films with the second electrode 112 printed on the surface.

[0104] S5: Lamination.

[0105] The capacitor body is stacked in a laminating bag, vacuum-encapsulated, and then pressurized by isostatic pressing to make the layers of the capacitor body stack more tightly and tightly bonded.

[0106] S6: Cutting.

[0107] The capacitor body stack is cut to form multiple independent capacitor green sheets. Each capacitor green sheet includes a stacked dielectric layer 111 and a second electrode 112 located on the surface of the dielectric layer 111. As shown in Figure 8, the fourth dimension s4 of the capacitor green sheet is greater than the fifth dimension s5 of the capacitor green sheet. The fourth dimension s4 is the dimension of the capacitor green sheet in the direction of the dielectric layer stacking, and the fifth dimension s5 is the dimension of the capacitor green sheet in the width direction of the second electrode 12.

[0108] The length direction of the second electrode 112 is the direction from one second electrode 112 to another second electrode 112. After the first electrode 12 is formed, the length direction of the second electrode 112 is the direction from one first electrode 12 to another first electrode 12. The width direction of the second electrode 112 intersects with the length direction. In some embodiments, the length of the second electrode 112 can be equal to the width, but the length direction and width direction are always the same as described above.

[0109] S7. Debinding.

[0110] The capacitor green body is placed on a firing plate and baked at a high temperature according to a certain temperature curve (the maximum temperature is generally around 400°C) to remove organic substances such as adhesives in the capacitor body 11 to avoid rapid volatilization of organic substances during firing, causing product stratification and cracking, to ensure that a complete capacitor green body with the desired shape is fired, and to eliminate the reducing effect of the adhesive during firing.

[0111] S8: Sintering.

[0112] The capacitor green body after debinding is subjected to high temperature treatment, and the sintering temperature is generally between 1140℃ and 1340℃, so as to improve the mechanical strength of the capacitor green body and optimize the electrical performance of the capacitor green body.

[0113] S9: Chamfer.

[0114] The sintered capacitor green body is placed in a chamfering pot and moved by ball milling, planetary milling, etc. to form a smooth surface to ensure that the second electrode 112 is fully exposed at both ends of the capacitor green body along the direction parallel to the length of the second electrode 112 to process the capacitor body 11.

[0115] S10: Capping (or termination).

[0116] The first electrode slurry is coated on the two ends of the exposed second electrode 112 of the capacitor body 11 in a direction parallel to the length of the second electrode 112, or the two ends of the exposed second electrode 112 of the capacitor body 11 are dipped into the first electrode slurry respectively, or the first electrode slurry is sputtered onto the two ends of the exposed second electrode 112 of the capacitor body 11 by a sputtering process to form the first electrode 12.

[0117] S11: Burning end.

[0118] The sealed product is sintered at a low temperature to ensure the connection between the second electrode 112 and the first electrode 12 , and to ensure that the first electrode 12 and the dielectric layer 111 in the capacitor body 11 have a certain bonding strength.

[0119] S12: End processing.

[0120] A nickel layer is plated on the first electrode 12 , and then a tin layer is plated on the nickel layer, thereby manufacturing the capacitor 10 .

[0121] S13: Testing.

[0122] The electrical performance of the capacitor 10 is tested and defective products are removed.

[0123] S14: Positioning.

[0124] The capacitor 10 is positioned on a carrier (eg, a conveyor belt), as shown in FIG8 , so that the surface of the capacitor 10 where the fourth dimension s4 is located is parallel to the carrier.

[0125] For example, the capacitor 10 is vibrated and sieved to cause the capacitor 10 with its small surface in contact with the carrier (vertical) to fall down and become in a position with its large surface in contact with the carrier (horizontal). The position of the capacitor 10 that was originally in contact with the carrier (horizontal) remains unchanged.

[0126] The fourth size s4 of the capacitor green sheet is the fourth size s4 of the capacitor 10, which is also the first size s1 of the capacitor 10. The fifth size s5 of the capacitor green sheet is the fifth size s5 of the capacitor 10, which is also the second size s2 of the capacitor 10.

[0127] S15: Taping.

[0128] The capacitors 10 are packed in paper tape or plastic bags according to the size and quantity requirements.

[0129] S16: Packaging.

[0130] The taped capacitor 10 is placed in an outer package.

[0131] Of course, the processing technology of the capacitor 10 is not limited thereto. In other embodiments, steps S7 and S8 can be placed as a whole between steps S11 and S12.

[0132] FIG9 is a schematic structural diagram of a semiconductor component provided in an embodiment of the present application.

[0133] An embodiment of the present application further provides a semiconductor component, as shown in FIG9 , which includes a carrier and a capacitor 10 .

[0134] The carrier board can be any substrate having a signal transmission function, for example, the carrier board is a circuit board. In the embodiment of the present application, the carrier board is a circuit board 20 as an example for illustration.

[0135] Circuit boards can be rigid, flexible, or a combination of rigid and flexible. They can use FR-4 dielectric, Rogers dielectric, or a combination of FR-4 and Rogers dielectric. FR-4 designates a flame-retardant material grade, while Rogers dielectric designates a high-frequency board.

[0136] The capacitor 10 is disposed on a circuit board 20 and is coupled to the circuit board 20. For example, a first surface a1 of the first electrode 12 of the capacitor 10 is coupled to the circuit board 20. The dielectric layer 111 and the second electrode 112 of the capacitor 10 both intersect with the circuit board 20. In some embodiments, the dielectric layer 111 and the second electrode 112 are both perpendicular to the circuit board 20.

[0137] In the embodiments of the present application, "perpendicular" means that the angle between the dielectric layer 111 and the circuit board 20 is within a preset range. For example, the preset range is [75°, 110°]. For example, the angle between the dielectric layer 111 and the circuit board 20 can be 80°, 85°, 86°, 87°, 88°, 89°, 90°, 91°, 92°, 93°, 94°, 95°, 96°, 97°, 100°, or 105°.

[0138] In the capacitor 10 provided in the embodiment of the present application, the first surface a1 of the first electrode 12 intersects with the dielectric layer 111, and the second surface a2 is parallel to the dielectric layer 111. By setting the area of ​​the first surface a1 of the first electrode 12 to be larger than the area of ​​the second surface a2, the first surface a1 for coupling with the carrier can be clearly distinguished. Then, in the process of preparing the capacitor 10, each capacitor 10 can be directly placed in the expected position, and there is no or very little random placement phenomenon, so as to limit the patch position of the capacitor 10. In this way, when the capacitor 10 is assembled with the carrier, the shapes of the first surface a1 and the second surface a2 of the capacitor 10 are different, and the capacitors 10 are all placed in the expected position, so the first surface a1 of the capacitor 10 can be identified, thereby ensuring that the stack of the dielectric layer 111 and the second electrode 112 of the capacitor 10 is intersected (for example, vertically) and placed with the carrier. In this way, even when an electric field is applied to the first electrode 12, the dielectric layer 111 expands in the direction of the applied electric field and contracts perpendicular to the direction of the applied electric field, and the capacitor 10 still vibrates during operation. However, the orientation of the dielectric layer 111 intersects the carrier board, and the vibration direction of the capacitor 10 is parallel to the carrier board. This can reduce the impact of the capacitor 10 vibration on the carrier board, thereby suppressing the "plate vibration" problem of the carrier board.

[0139] It should be explained here that the electronic device provided in the embodiment of the present application includes any of the above-mentioned capacitors 10 and a shell. The capacitor 10 can be arranged in the shell after forming a semiconductor component with the carrier. The capacitor 10 can also be arranged in the shell in other ways. The embodiment of the present application is not limited to this.

[0140] Below, several application scenarios of the capacitor 10 provided in the embodiments of the present application are exemplified.

[0141] FIG10 is an architectural diagram of a radio frequency front-end module provided in an embodiment of the present application.

[0142] In some application scenarios, capacitor 10 can be used as a filter matching capacitor for the RF power supply in the RF front-end module in the 4G / 5G scenario shown in Figure 10. The capacitance of capacitor 10 can be, for example, 1uF, and the size of capacitor 10 can be, for example, an English "0201". The RF front-end module illustrated in the embodiment of the present application can be used, for example, in the mobile communication module 150 of the electronic device 100 described above.

[0143] The RF front-end module may include a transmit channel and a receive channel. The transmit channel includes a power amplifier (PA) and a transmit channel filter, with the PA's RF output coupled to the transmit channel filter's input. The receive channel includes a low-noise amplifier (LNA) and a receive channel filter, with the receive channel filter's output coupled to the LNA's RF input.

[0144] The duplexer is responsible for duplex switching of the frequency division duplex system and filtering of RF signals in the receiving channel / transmitting channel, while the RF switch is responsible for switching between the receiving channel and the transmitting channel.

[0145] The baseband signal is transmitted by the transceiver to the transmit channel, which amplifies the received RF signal and outputs it to the antenna for transmission. The PA amplifies the RF signal in the transmit channel, while the transmit channel filter filters it.

[0146] During the transmit phase, the PA requires an RF power supply to maintain transmit power. During the receive phase or between communication subframes, the PA does not need to operate, so the RF power supply can be turned off, saving power. The frequent on-off cycles of the RF power supply create periodic large voltage differences that can cause the external capacitor 10 to vibrate due to the inverse piezoelectric effect, resulting in "plate oscillation."

[0147] In other application scenarios, the capacitor 10 can be used as an external filter matching capacitor for battery power supply (VBAT) and main power supply (VBAT_SYS) in a 2G scenario. The capacitance of the capacitor 10 can be, for example, 4.7uF or 10uF, and the size of the capacitor 10 can be, for example, the British "0402". Or the capacitance of the capacitor 10 can be, for example, 22uF, and the size of the capacitor 10 can be, for example, the British "0603". The battery power supply (VBAT) and the main power supply (VBAT_SYS) can be applied to the power management module 141 of the above-mentioned electronic device 100, for example.

[0148] The Global System for Mobile Communications (GSM) uses Time Division Multiple Access (TDMA) with each time slot being 577µs. Each frame has eight time slots, and each frame is 577µs x 8 = 4.616ms long, resulting in a frequency of 216.6Hz. Due to the GSM standard's operating principle, the PA demands a high burst current (approximately 1.5A-2A) during each transmission. The power supply circuitry of electronic devices transmits this noise throughout the circuit board, causing voltage drops on VBAT and VBAT_SYS. This can also cause "board oscillation" in any external power supply filter and matching capacitors.

[0149] In other application scenarios, capacitor 10 can be used as a filter capacitor for the rectified voltage (Vrect) during wireless charging. Capacitor 10 can have a capacitance of, for example, 10 uF and a size of, for example, 0603. The rectified voltage (Vrect) can be used, for example, in the charging management module 140 of the electronic device 100.

[0150] During wireless charging, the voltage received by the electronic device is the power voltage generated by electromagnetic induction superimposed on the voltage obtained (polling) by the wireless charging communication protocol. After full-bridge rectification, the power voltage is rectified into DC, but the voltage polled by the wireless charging communication protocol is not rectified, resulting in "board vibration".

[0151] The capacitor 10 provided in the embodiment of the present application can be used in a variety of scenarios. Because the dielectric layer 111 of the capacitor 10 provided in the embodiment of the present application is perpendicular to the circuit board in the electronic device, the vibration direction of the capacitor 10 also intersects perpendicularly with the circuit board. As a result, the resonance of the circuit board is relatively small, which can effectively suppress the "board vibration" problem caused by the vibration of the capacitor 10, and can effectively improve the performance of the electronic device.

[0152] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor component, characterized in that: include: Carrier board; A capacitor, the capacitor comprising a capacitor body and a first electrode, wherein the first electrodes are respectively disposed at two opposite ends of the capacitor body; The capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the plurality of dielectric layers are stacked and intersect with the carrier; the second electrode is arranged between two adjacent dielectric layers, the second electrodes of two adjacent layers are staggered, and the second electrodes of two adjacent layers are coupled to the first electrodes located on different sides; The first electrode includes a first surface and a second surface, the first surface intersects with the dielectric layer and is parallel to the carrier, the second surface is parallel to the dielectric layer, and the capacitor is coupled to the carrier through the first surface; the area of ​​the first surface is greater than the area of ​​the second surface.

2. The semiconductor component according to claim 1, characterized in that A first dimension of the first electrode along a first direction is greater than a second dimension of the first electrode along a second direction; the first direction is a direction in which the multi-layer dielectric layers are stacked, and the second direction intersects with the first direction.

3. The semiconductor component according to claim 2, characterized in that The second direction also intersects the carrier.

4. The semiconductor component according to claim 2 or 3, characterized in that The first size is more than twice the second size.

5. The semiconductor component according to any one of claims 2 to 4, characterized in that: The first dimension is less than 0.5 mm.

6. The semiconductor component according to any one of claims 1 to 5, characterized in that: The first surface is a rectangle, and the first size is the size of a long side of the rectangle.

7. The semiconductor component according to any one of claims 1 to 6, characterized in that: The dielectric layer is perpendicular to the carrier board.

8. A capacitor, characterized in that: include: A capacitor body and a first electrode; the first electrodes are respectively disposed at two opposite ends of the capacitor body; The capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the plurality of dielectric layers are stacked along a first direction; the second electrode is arranged between two adjacent dielectric layers, the second electrodes of two adjacent layers are staggered, and the second electrodes of two adjacent layers are coupled to the first electrodes located on different sides; The first electrode comprises a first surface and a second surface, the first surface intersects with the dielectric layer, the first surfaces of the two first electrodes are located in the same plane, and the second surface is parallel to the dielectric layer; An area of ​​the first surface is greater than an area of ​​the second surface.

9. An electronic device, characterized in that: include: A housing and a semiconductor component, wherein the semiconductor component is arranged in the housing; the semiconductor component comprises the semiconductor component according to any one of claims 1 to 7; or, A shell and a capacitor, wherein the capacitor is arranged in the shell; the capacitor comprises the capacitor according to claim 8.

10. A method for preparing a capacitor, characterized in that: include: Forming a capacitor body stack, wherein the capacitor body stack includes a plurality of dielectric films with second electrodes printed on the surface; The capacitor body stack is cut to form a plurality of capacitor bodies; the fourth dimension of the capacitor body is greater than the fifth dimension of the capacitor body, the fourth dimension is the dimension in the dielectric film stacking direction, and the fifth dimension is the dimension in the second electrode width direction; forming first electrodes at two ends of the capacitor body in a direction parallel to the length of the second electrode to form a capacitor; Positioning the capacitor on a carrier so that a surface of the capacitor where the fourth dimension is located is parallel to the carrier; The capacitor is subjected to a taping process.

11. The preparation method according to claim 10, characterized in that: Performing a positioning process on the capacitor includes: performing a vibration screening process on the capacitor.

Images