Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises a plurality of pixel driving circuits and a base substrate, wherein the plurality of pixel driving circuits are arranged in a plurality of rows and columns; each of the plurality of pixel driving circuits comprises a plurality of transistors; and the array substrate further comprises a light-shielding layer, a semiconductor layer, and a first gate layer. The light-shielding layer is arranged on one side of the base substrate, and comprises a plurality of first-type light-shielding wirings; the semiconductor layer is arranged on the side of the light-shielding layer distant from the base substrate, and comprises active layer patterns of the plurality of transistors; the first gate layer is arranged on the side of the semiconductor layer distant from the base substrate, and comprises a plurality of scanning signal lines; each scanning signal line passes through the active layer pattern of at least one transistor; the plurality of scanning signal lines transmit scanning signals; each of the plurality of first-type light-shielding wirings passes through the active layer pattern of at least one transistor; and the first-type light-shielding wirings transmit the scanning signals.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202310996423.2, filed on August 8, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0003] Organic Light-Emitting Diode (OLED) display panels have gradually become one of the mainstreams in the display field due to their excellent performance such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided. The array substrate includes a plurality of pixel driving circuits arranged in multiple rows and columns, and each of the plurality of pixel driving circuits includes a plurality of transistors. The array substrate includes: a base substrate, a light-shielding layer, a semiconductor layer, and a first gate layer. The light-shielding layer is disposed on one side of the base substrate, and includes a plurality of first light-shielding traces; the semiconductor layer is disposed on a side of the light-shielding layer away from the base substrate, and includes an active layer pattern of a plurality of transistors; the first gate layer is disposed on a side of the semiconductor layer away from the base substrate, and includes a plurality of scan signal lines; each scan signal line passes through the active layer pattern of at least one transistor, and the plurality of scan signal lines transmit scan signals. Each of the plurality of first-class light-shielding traces passes through the active layer pattern of at least one transistor, wherein the first-class light-shielding traces and the scan signal lines passing through the active layer pattern of the same transistor transmit the same scan signal.

[0006] In some embodiments, the transistors of each pixel driving circuit include compensation transistors and data writing transistors, and the multiple scanning signal lines include a first scanning signal line, wherein the active layer pattern of the compensation transistor and the active layer pattern of the data writing transistor in a row of pixel driving circuits have an orthographic projection on the substrate substrate that overlaps with the orthographic projection of the first scanning signal line on the substrate substrate; the multiple first-class light-shielding lines include a first light-shielding line, wherein the active layer pattern of the compensation transistor and the active layer pattern of the data writing transistor in a row of pixel driving circuits have an orthographic projection on the substrate substrate that overlaps with the orthographic projection of the first light-shielding line on the substrate substrate; the first light-shielding line and the first scanning signal line both transmit a first scanning signal.

[0007] In some embodiments, the transistor of each pixel driving circuit also includes a first reset transistor, and the multiple scanning signal lines include a second scanning signal line, wherein the active layer pattern of the first reset transistor in a row of pixel driving circuits has an orthographic projection on the substrate substrate that overlaps with the orthographic projection of the second scanning signal line on the substrate substrate; the multiple first-type light-shielding lines include a plurality of second light-shielding lines, wherein the active layer pattern of the first reset transistor in a row of pixel driving circuits has an orthographic projection on the substrate substrate that overlaps with the orthographic projection of the second light-shielding line on the substrate substrate; the second light-shielding line and the second scanning signal line both transmit second scanning signals.

[0008] In some embodiments, the first scanning signal line and the second scanning signal line that overlap with the same row of pixel driving circuits transmit the same signal; the array substrate includes a display area and a peripheral area, and the multiple first-type metal lines extend along the row direction and extend to the peripheral area; the areas of the peripheral area located on both sides of the display area along the row direction are the first area and the second area respectively; the first shading line and the second shading line that overlap with the same row of pixel driving circuits are electrically connected in the first area and / or the second area.

[0009] In some embodiments, the array substrate further includes at least one gate driving circuit located in the peripheral area, the gate driving circuit includes a plurality of shift registers, each shift register is configured to transmit a scanning signal to a row of pixel driving circuits; each shift register includes an output end; the output end is electrically connected to the first scanning signal line and the second scanning signal line corresponding to a row of pixel driving circuits; the array substrate further includes a source-drain metal layer located on the side of the first gate layer away from the light-shielding layer, the source-drain metal layer includes a plurality of first connecting lines; one end of each of the first connecting lines is electrically connected to one of the output ends, and the other end is electrically connected to the first light-shielding line or the second light-shielding line.

[0010] In some embodiments, the first light-shielding wiring is electrically connected to the first scanning signal line, and the second light-shielding wiring is electrically connected to the second scanning signal line.

[0011] In some embodiments, the array substrate includes a display area and a peripheral area, and the multiple first-type light-shielding lines extend along the row direction and extend to the peripheral area; the areas of the peripheral area located on both sides of the display area along the row direction are respectively the first area and the second area; the first light-shielding line is electrically connected to the first scanning signal line in the first area and / or the second area, and the second light-shielding line is electrically connected to the second scanning signal line in the first area and / or the second area.

[0012] In some embodiments, the transistor of each pixel driving circuit also includes a second reset transistor, and the multiple scanning signal lines include a third scanning signal line, wherein the active layer pattern of the second reset transistor in a row of pixel driving circuits has an orthographic projection on the substrate that overlaps with the orthographic projection of the third scanning signal line on the substrate; the multiple first-type light-shielding lines include a multiple third light-shielding lines, wherein the active layer pattern of the second reset transistor in a row of pixel driving circuits has an orthographic projection on the substrate that overlaps with the orthographic projection of the third light-shielding line on the substrate; the third light-shielding line and the third scanning signal line both transmit a third scanning signal.

[0013] In some embodiments, the third scanning signal line corresponding to the pixel driving circuit in the nth row and the second scanning signal line corresponding to the pixel driving circuit in the (n-1)th row are the same signal line.

[0014] In some embodiments, the transistor of each pixel driving circuit also includes a driving transistor, and the light-shielding layer includes multiple second-type light-shielding traces, wherein the active layer pattern of the driving transistor in a row of pixel driving circuits overlaps with the orthographic projection of a second-type light-shielding trace on the substrate; the second-type light-shielding trace transmits a first voltage signal.

[0015] In some embodiments, a source-drain metal layer is provided on a side of the first gate layer away from the light-shielding layer, and the source-drain metal layer includes a first voltage signal line, and the first voltage signal line is electrically connected to the second-type light-shielding trace.

[0016] In some embodiments, each second-type light-shielding trace overlaps with a driving transistor of a row of pixel driving circuits; each column of pixel driving circuits is correspondingly connected to a first voltage signal line; at least three adjacent pixel driving circuits in each row of pixel driving circuits constitute a pixel driving circuit group, and the first voltage signal line connected to at least one pixel driving circuit in a pixel driving circuit group is connected to the second-type light-shielding trace.

[0017] In some embodiments, the array substrate includes a display area and a peripheral area, and the plurality of first voltage signal lines are electrically connected to each other in the peripheral area.

[0018] In some embodiments, the second type of light-shielding traces include a plurality of light-shielding patterns and a plurality of connecting patterns alternately arranged, each connecting pattern connecting two adjacent light-shielding patterns, and the orthographic projection of each light-shielding pattern on the substrate surrounds the orthographic projection of a driving transistor of a pixel driving circuit on the substrate.

[0019] In another aspect, a display panel is provided, comprising: an array substrate as described in any one of the above embodiments.

[0020] In another aspect, a display device is provided, comprising: a display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0022] FIG1 is a planar structural diagram of a display device according to some embodiments;

[0023] FIG2 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0024] FIG3 is a structural diagram of an equivalent circuit of a pixel driving circuit according to some embodiments;

[0025] FIG4A is a structural diagram of a pixel driving circuit according to some embodiments;

[0026] FIG4B is a planar structural diagram of a light shielding layer of an array substrate according to some embodiments;

[0027] FIG4C is a structural diagram of a semiconductor layer of an array substrate according to some embodiments; ...

[0028] FIG4D is a structural diagram of a first gate layer of an array substrate according to some embodiments;

[0029] FIG4E is a structural diagram of a second gate layer of an array substrate according to some embodiments; ...

[0030] FIG5A is a structural diagram of connections between light-shielding traces and a shift register of an array substrate according to some embodiments;

[0031] FIG5B is another connection structure diagram of the light-shielding traces and the shift register of the array substrate according to some embodiments;

[0032] FIG5C is a diagram illustrating another connection structure between light-shielding traces of an array substrate and a shift register according to some embodiments;

[0033] 6A is a diagram illustrating a connection structure between light-shielding traces and scan signal lines of an array substrate according to some embodiments;

[0034] 6B is a diagram illustrating another connection structure between light-shielding traces and scan signal lines of an array substrate according to some embodiments;

[0035] FIG6C is a diagram illustrating another connection structure between light-shielding traces and scan signal lines of an array substrate according to some embodiments;

[0036] FIG7 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0037] 8A is a diagram illustrating a connection structure between a first voltage signal line and a second type of light shielding wiring of an array substrate according to some embodiments;

[0038] 8B is another connection structure diagram of the first voltage signal line and the second type of light shielding wiring of the array substrate according to some embodiments;

[0039] 8C is a diagram illustrating another connection structure between the first voltage signal lines and the second type of light-shielding traces of the array substrate according to some embodiments;

[0040] 9A is another connection structure diagram of the first voltage signal line and the second type of light shielding wiring of the array substrate according to some embodiments;

[0041] 9B is a diagram illustrating another connection structure between the first voltage signal lines and the second type of light shielding wiring of the array substrate according to some embodiments;

[0042] 9C is another connection structure diagram of the first voltage signal line and the second type of light shielding wiring of the array substrate according to some embodiments;

[0043] FIG9D is a diagram illustrating another connection structure between the first voltage signal lines and the second type of light shielding wiring of the array substrate according to some embodiments;

[0044] FIG10 is a structural diagram of a first voltage signal line of an array substrate according to some embodiments;

[0045] FIG. 11 is a cross-sectional structural diagram of a display panel according to some embodiments. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0056] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000. The display device 1000 provided by the embodiments of the present disclosure can be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. The embodiments of the present disclosure do not specifically limit the specific form of the display device 1000.

[0059] Specifically, as shown in FIG1 , the embodiment of the present disclosure is exemplified by taking the display device 1000 as a mobile phone.

[0060] As shown in FIG2 , the display device 1000 includes a display panel 100. The display device 1000 also includes a frame, a circuit board, a driver chip, and other electronic components. The display panel 100 is disposed in the frame, and the driver chip is used to drive the display panel 100 to display.

[0061] For example, as shown in FIG2 , taking the display panel 100 as an OLED (Organic Light-Emitting Diode) display panel, the display panel 100 includes an array substrate 1. The array substrate 1 includes a base substrate 101 and a pixel circuit stack 40 , wherein the pixel circuit stack 40 is disposed on the base substrate 101 .

[0062] Exemplarily, the material of the base substrate 101 may include any one of glass, metal or flexible material.

[0063] The pixel circuit stack 40 is formed with multiple pixel driving circuits 10. For example, the pixel circuit stack 40 includes: a light-shielding layer 11, a buffer layer 12, a semiconductor layer 13, a first gate insulating layer 14, a first gate layer 15, a second gate insulating layer 16, a second gate layer 17, an interlayer dielectric layer 18, a source-drain metal layer 19 and a planar layer 21 stacked in sequence.

[0064] Exemplarily, the material of the semiconductor layer 13 includes any one of low-temperature polysilicon, indium gallium zinc oxide, or low-temperature polycrystalline oxide.

[0065] Exemplarily, the material of the planar layer 21 includes polyimide, and the materials of the buffer layer 12 , the first gate insulating layer 14 , and the second gate insulating layer 16 include any one of silicon nitride and silicon oxide, so as to achieve the effect of blocking water, oxygen, and alkaline ions.

[0066] In some embodiments, the pixel driving circuit 10 in some embodiments of the present disclosure can be a 7T1C, 8T1C or 9T1C circuit, wherein T represents a transistor, and the number before T represents the number of transistors, C represents a capacitor, and the number before C represents the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor.

[0067] In some embodiments, the structure of the pixel driving circuit 10 shown in FIG3 is described. The pixel driving circuit 10 is a 7T1C pixel driving circuit. The pixel driving circuit 10 includes: a second reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a first reset transistor T7.

[0068] For example, as shown in FIG3 , the second reset transistor T1 includes a gate, a first electrode, and a second electrode. The gate of the second reset transistor T1 is electrically connected to the third scan signal line Gate3, the first electrode of the second reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and the second electrode of the second reset transistor T1 is electrically connected to the first node N1. The second reset transistor T1 is configured to reset the gate (first node N1) of the drive transistor T3 in response to a reset signal received at the third scan signal line Gate3.

[0069] For example, as shown in FIG3 , the compensation transistor T2 includes a gate, a first electrode, and a second electrode. The gate of the compensation transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode of the compensation transistor T2 is electrically connected to the third node N3. The compensation transistor T2 is configured to reset or threshold-compensate the driving transistor T3 in response to a scan signal received at the first scan signal line Gate1.

[0070] Exemplarily, as shown in FIG3 , the driving transistor T3 includes a gate, a first electrode, and a second electrode. The gate of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3. The driving transistor T3 is configured to generate a driving current signal.

[0071] Exemplarily, as shown in FIG3 , the data write transistor T4 includes a gate, a first electrode, and a second electrode. The gate of the data write transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the data write transistor T4 is electrically connected to the data signal line Data, and the second electrode of the data write transistor T4 is electrically connected to the second node N2. The data write transistor T4 is configured to transmit a data signal received on the data signal line Data to the driving transistor T3 in response to a scan signal received on the first scan signal line Gate1.

[0072] Exemplarily, as shown in FIG3 , the first emission control transistor T5 includes a gate, a first electrode, and a second electrode. The gate of the first emission control transistor T5 is electrically connected to the emission control signal line EM, the first electrode of the first emission control transistor T5 is electrically connected to the power signal line ELVDD, and the second electrode of the first emission control transistor T5 is electrically connected to the second node N2. The first emission control transistor T5 is configured to transmit a power signal received on the power signal line ELVDD to the driving transistor T3 in response to the emission control signal received on the emission control signal line EM.

[0073] Exemplarily, as shown in FIG3 , the second emission control transistor T6 includes a gate, a first electrode, and a second electrode. The gate of the second emission control transistor T6 is electrically connected to the emission control signal line EM, the first electrode of the second emission control transistor T6 is electrically connected to the third node N3, and the second electrode of the second emission control transistor T6 is electrically connected to the fourth node N4. The second emission control transistor T6 is configured to transmit a driving current signal to the light-emitting device L in response to a light-emitting control signal received on the light-emitting control signal line EM, thereby driving the light-emitting device L to emit light.

[0074] For example, as shown in FIG3 , the first reset transistor T7 includes a gate, a first electrode, and a second electrode. The gate of the first reset transistor T7 is electrically connected to the second scan signal line Gate2, the first electrode of the first reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode of the first reset transistor T7 is electrically connected to the fourth node N4. The first reset transistor T7 is configured to, in response to a reset signal received at the second scan signal line Gate2, transmit an initialization signal received at the second initialization signal line Vinit2 to the light-emitting device L to reset the light-emitting device L.

[0075] Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the reference voltage line ELVSS.

[0076] It should be noted that the first electrode of the transistor disclosed herein is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0077] In the circuit provided by the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0078] Exemplarily, as shown in Figure 3, the pixel driving circuit also includes: a capacitor Cst, the capacitor Cst includes: a first plate Cst1 and a second plate Cst2, the first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second plate Cst2 of the capacitor Cst is electrically connected to the power signal line ELVDD.

[0079] In some embodiments, the pixel driving circuit 10 adopts an LTPO (Low Temperature Polycrystalline Oxide) circuit, that is, a pixel driving circuit 10 includes both a low-temperature polycrystalline silicon (LTPS) thin film transistor and an oxide thin film transistor. The low-temperature polycrystalline silicon thin film transistor has a strong load capacity, and the oxide thin film transistor has a small off-state current and a stronger charge retention ability than the low-temperature polycrystalline silicon thin film transistor. In this way, the pixel driving circuit 10 can achieve higher charge mobility and better stability.

[0080] For example, as shown in Figure 3, the compensation transistor T2 can be an oxide thin film transistor, and is an N-type transistor, that is, it is turned on at a high level. The second reset transistor T1, the drive transistor T3, the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the first reset transistor T7 are all low-temperature polysilicon thin film transistors (LTPTs) P-type transistors, and are turned on at a low level. Using an oxide thin film transistor for the compensation transistor T2 can effectively prevent leakage from the first node N1.

[0081] In some embodiments, in the process of using low-temperature polysilicon thin-film transistors and oxide thin-film transistors in the pixel driving circuit 10, the thin-film transistors will experience characteristic shifts when exposed to light. For example, in 7T1C, the second reset transistor T1 and the compensation transistor T2 are connected to the first node N1, the data write transistor T4 is connected to the second node N2, and the second reset transistor is connected to the fourth node N4. When the second reset transistor T1, the compensation transistor T2, the data write transistor T4 and the first reset transistor T7 are exposed to light and their characteristics shift, leakage will occur, causing the voltages of the first node N1, the second node N2 and the third node N3 to change. The driving transistor T3 is configured to generate a driving current signal. When its characteristics shift when exposed to light, it will directly affect the driving current of the pixel driving circuit 10, and ultimately cause the display panel to have uneven display brightness.

[0082] Based on the above problems, as shown in Figures 2 and 4A to 4E, some embodiments of the present disclosure provide an array substrate 1, which includes a plurality of pixel driving circuits 10 and a base substrate 101. The plurality of pixel driving circuits 10 are arranged in multiple rows and columns, and each of the plurality of pixel driving circuits 10 includes multiple transistors.

[0083] Exemplarily, the pixel driving circuits 10 are arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect, and both the first direction X and the second direction Y are parallel to the surface of the base substrate 101. Exemplarily, the first direction X and the second direction Y are perpendicular to each other, the first direction X is the row direction in which the plurality of pixel driving circuits 10 are arranged, and the second direction Y is the column direction in which the plurality of pixel driving circuits 10 are arranged.

[0084] Exemplarily, each pixel driving circuit 10 includes a plurality of transistors including a second reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, and a first reset transistor T7. The connections between the transistors are as described above.

[0085] As shown in Figures 2 and 4A to 4E, the array substrate 1 provided in the embodiment of the present disclosure includes: a light shielding layer 11 disposed on one side of a base substrate 101, a semiconductor layer 13 disposed on a side of the light shielding layer 11 away from the base substrate 101, and a first gate layer 15 disposed on a side of the semiconductor layer 13 away from the base substrate. The light shielding layer 11 includes a plurality of first-type light shielding traces 110, the semiconductor layer 13 includes active layer patterns of a plurality of transistors, and the first gate layer 15 includes a plurality of scan signal lines "Gate," each of which passes through the active layer pattern of at least one transistor, and the plurality of scan signal lines "Gate" transmit scan signals. Each of the plurality of first-type light shielding traces 110 passes through the active layer pattern of at least one transistor, and the first-type light shielding traces 110 and the scan signal lines "Gate" that pass through the active layer pattern of the same transistor transmit the same transmission scan signal.

[0086] Exemplarily, referring to Figures 2 and 4A to 4E, each scanning signal line Gate passes through the active layer pattern of at least one transistor, that is, a scanning signal line Gate overlaps with the positive projection of the active layer pattern of at least one transistor on the substrate 101. Exemplarily, the portion of a scanning signal line passing through the active layer pattern of a transistor serves as the gate of the transistor, referring to the description of Figure 3, which is equivalent to the scanning signal line being electrically connected to the gate of the transistor. Each first-class light-shielding trace 110 passes through the active layer pattern of at least one transistor, that is, a first-class light-shielding trace 110 overlaps with the positive projection of the active layer pattern of at least one transistor on the substrate 101. The first-class light-shielding trace can block the active layer pattern of the transistor, preventing external light from entering the semiconductor from the side of the substrate, so that the active layer pattern of the transistor is affected by light, resulting in characteristic deviation, affecting the stability of the driving circuit generated by the pixel driving circuit, and ultimately causing uneven display of the display panel.

[0087] Among them, the first type of light-shielding routing and the scanning signal line passing through the active layer pattern of the same transistor transmit the same scanning signal, that is, the first type of light-shielding routing and the scanning signal line overlapping with the active layer pattern of the same transistor transmit the same scanning signal. It can be understood that the first type of light-shielding routing and the scanning signal line overlap, and are respectively located above and below the active layer pattern of the transistor.

[0088] In the array substrate provided by some embodiments of the present application, a scanning signal is connected to the first type of light-shielding wiring, and the scanning signal line Gate that overlaps with the active layer pattern of the same transistor and the first type of light-shielding wiring 110 both transmit the same scanning signal, which can synchronize the signals received by the upper and lower layers of the active layer pattern of the same transistor, thereby improving the signal transmission capability, avoiding excessive parasitic capacitance generated by the overlap between the scanning line and the light-shielding wiring that transmit different signals, thereby causing interference between signals, improving the stability of the scanning signal transmission by the scanning signal line, and thus making the scanning signal received by the gate of the transistor more stable, ensuring the normal conduction and shutdown of the transistor. At the same time, the light-shielding metal layer can block external light, preventing the active layer pattern of the transistor from being affected by external light and causing characteristic deviation, thereby ensuring the normal operation of the pixel driving circuit and improving the problem of uneven display of the display panel.

[0089] The following takes a row of pixel driving circuits as an example to introduce the positional relationship between each transistor of each pixel driving circuit and the scanning signal line and the light shielding line.

[0090] In some embodiments, as shown in Figures 4A and 4C, the transistors of each pixel driving circuit 10 include a compensation transistor T2 and a data writing transistor T4, and the multiple scanning signal lines Gate include a first scanning signal line Gate1, wherein the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 in a row of pixel driving circuits 10 have an orthographic projection on the substrate 101 that overlaps with the orthographic projection of the first scanning signal line Gate1 on the substrate 101; the multiple first-type light-shielding lines 110 include a first light-shielding line 110a, wherein the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 in a row of pixel driving circuits have an orthographic projection on the substrate 101 that overlaps with the orthographic projection of the first light-shielding line 110a on the substrate 101; the first light-shielding line 110a and the first scanning signal line Gate1 both transmit the first scanning signal.

[0091] It can be understood that, in the multiple pixel driving circuits 10 arranged along the first direction X, the orthographic projections of the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 of each pixel driving circuit 10 on the substrate 101 overlap with the orthographic projection of the first scanning signal line Gate1 on the substrate 101, wherein the overlap here means that the orthographic projections of the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 on the substrate 101 overlap with the orthographic projection of the first scanning signal line Gate1 on the substrate 101, and the overlapping parts on the first scanning signal line Gate1 serve as the gate patterns of the compensation transistor T2 and the data writing transistor T4, respectively. That is, the gates of the compensation transistor T2 and the data writing transistor T4 receive the same first scanning signal.

[0092] Here, “the orthographic projections of the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 in a row of pixel driving circuits on the substrate 101 both overlap with the orthographic projection of the first light-shielding trace 110a on the substrate 101” may include: the orthographic projections of the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 in a row of pixel driving circuits on the substrate 101 both partially overlap with the orthographic projection of the first light-shielding trace 110a on the substrate 101. The overlapping may also include: the orthographic projections of the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 in a row of pixel driving circuits on the substrate 101 both lie within the orthographic projection of the first light-shielding trace 110a on the substrate 101. Overlap may also include: the orthographic projection boundaries of the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4 in a row of pixel driving circuits on the base substrate 101 completely coincide with the orthographic projection boundaries of the first light-shielding trace 110a on the base substrate 101 .

[0093] It can be understood that the first light-shielding line 110a overlaps with the first scanning signal line Gate1, and the width of the first light-shielding line 110a is greater than the width of the first scanning signal line Gate1, ensuring that the first light-shielding line 110a has a light-shielding effect on the active layer pattern of the compensation transistor T2 and the active layer pattern of the data writing transistor T4.

[0094] As shown in Figure 4C, the compensation transistor T2 is a dual-gate transistor. Its active layer pattern is L-shaped, with two channel regions G1 and G2 and a connection region N1 located between the two channel regions. The first scan signal line Gate1 overlaps the two channel regions but not the connection region. This dual-gate design reduces leakage. The first light-shielding trace 110a overlaps both the channel regions and the connection region of the active layer pattern of the compensation transistor T2, completely shielding the active layer pattern of the compensation transistor T2 and further ensuring light shielding for the compensation transistor T2.

[0095] In some embodiments of the present application, in an array substrate, a first scanning signal is connected to the first light-shielding trace 110a, and the first light-shielding trace 110a, which overlaps with the active layer pattern of the compensation transistor T2 and the data writing transistor T4, and the first scanning signal line Gate1 transmit the first scanning signal. This ensures that the signals received by the upper and lower layers of the active layer pattern of the compensation transistor T2 and the data writing transistor T4, which overlap with the orthographic projection of the first light-shielding trace 110a and the first scanning signal line Gate1 on the substrate 101, are synchronized. This improves signal transmission efficiency, avoids excessive parasitic capacitance generated by the overlap between the scanning line and the light-shielding trace transmitting different signals, and thus causes interference between signals. This improves the stability of the scanning signal transmitted by the scanning signal line, thereby making the scanning signal received by the gate of the transistor more stable, ensuring the normal conduction and shutdown of the transistor. At the same time, the light-shielding metal layer can block external light, preventing the active layer pattern of the transistor from being affected by external light and causing characteristic deviation, ensuring the normal operation of the pixel driving circuit, and improving the problem of uneven display on the display panel.

[0096] In some embodiments, continuing to refer to Figures 4A and 4C, the transistor of each pixel driving circuit 10 also includes a first reset transistor T7, and the multiple scanning signal lines Gate include a second scanning signal line Gate2, wherein the active layer pattern of the first reset transistor T7 in a row of pixel driving circuits 10 has an orthographic projection on the substrate 101 that overlaps with the orthographic projection of the second scanning signal line Gate2 on the substrate 101; the multiple first-type light-shielding lines 110 include a plurality of second light-shielding lines 110b, wherein the active layer pattern of the first reset transistor T7 in a row of pixel driving circuits 10 has an orthographic projection on the substrate 101 that overlaps with the orthographic projection of the second light-shielding line 110b on the substrate 101; the second light-shielding line 110b and the second scanning signal line Gate2 both transmit the second scanning signal.

[0097] It can be understood that, in the multiple pixel driving circuits 10 arranged along the first direction X, the orthographic projection of the active layer pattern of the first reset transistor T7 of each pixel driving circuit 10 on the substrate 101 overlaps with the orthographic projection of the second scanning signal line Gate2 on the substrate 101, wherein the overlap here means that the orthographic projection of the active layer pattern of the first reset transistor T7 on the substrate 101 partially overlaps with the orthographic projection of the second scanning signal line Gate2 on the substrate 101, and the overlapping portion serves as the gate pattern of the first reset transistor T7, that is, the gate of the first reset transistor T7 receives the second scanning signal.

[0098] Here, “the orthographic projections of the active layer pattern of the first reset transistor T7 in a row of pixel driving circuits 10 on the substrate substrate 101 all overlap with the orthographic projections of the second light-shielding trace 110b on the substrate substrate 101” may include: the orthographic projections of the active layer pattern of the first reset transistor T7 in a row of pixel driving circuits 10 on the substrate substrate 101 all partially overlap with the orthographic projections of the second light-shielding trace 110b on the substrate substrate 101. Overlap may also include: the orthographic projections of the active layer pattern of the first reset transistor T7 in a row of pixel driving circuits 10 on the substrate substrate 101 are located within the orthographic projections of the second light-shielding trace 110b on the substrate substrate 101. Overlap may also include: the orthographic projection boundaries of the active layer pattern of the first reset transistor T7 in a row of pixel driving circuits 10 on the substrate substrate 101 all completely overlap with the orthographic projection boundaries of the second light-shielding trace 110b on the substrate substrate 101.

[0099] It can be understood that the second light shielding line 110b overlaps with the second scanning signal line Gate2, and the width of the second light shielding line 110b is greater than the width of the second scanning signal line Gate2, ensuring that the second light shielding line 110b has a light shielding effect on the active layer pattern of the first reset transistor T7.

[0100] In some embodiments of the present application, in an array substrate provided by a second light-shielding trace 110b, a second scan signal is connected to the second light-shielding trace 110b, and both the second light-shielding trace 110b and the second scan signal line Gate2, which overlap with the active layer pattern of the first reset transistor T7, transmit the second scan signal. This ensures that the signals received by the upper and lower layers of the active layer pattern of the first reset transistor T7, which overlap with the orthographic projection of the second light-shielding trace 110b and the second scan signal line Gate2 on the substrate 101, are synchronized. This improves signal transmission efficiency, avoids excessive parasitic capacitance generated by the overlap between scan lines and light-shielding traces transmitting different signals, and thus avoids interference between signals. This improves the stability of the scan signal transmission by the scan signal line, thereby making the scan signal received by the transistor gate more stable and ensuring the normal conduction and shutdown of the transistor. At the same time, the light-shielding metal layer can block external light, preventing the active layer pattern of the transistor from being affected by external light and causing characteristic deviation, thereby ensuring the normal operation of the pixel driving circuit and improving the problem of uneven display on the display panel.

[0101] In some embodiments, as shown in Figures 4A, 4C, and 5A to 5C, the first scanning signal line Gate1 and the second scanning signal line Gate2 that overlap with the same row of pixel driving circuits 10 transmit the same signal. That is, the compensation transistor T2, the data writing transistor T4, and the first reset transistor T7 in one pixel driving circuit all receive the same scanning signal. Similarly, the first light shielding trace 110a and the second light shielding trace 110b that overlap with the same row of pixel driving circuits 10 also transmit the same signal.

[0102] The array substrate 1 includes a display area AA and a peripheral area BB, and the areas of the peripheral area BB located on both sides of the display area BB along the row direction are the first area B1 and the second area B2 respectively; multiple first-type light-shielding lines 110 extend along the row direction (first direction X) and extend to the peripheral area BB; the first light-shielding lines 110a and the second light-shielding lines 110b that overlap with the same row of pixel driving circuits 10 are electrically connected in the first area B1 and / or the second area B2.

[0103] For example, referring to Figure 5A, the two ends of the first light-shielding trace 110a and the second light-shielding trace 110b in the row direction extend to the first area B1 and the second area B2 respectively, and the first end of the first light-shielding trace 110a and the first end of the second light-shielding trace 110b that overlap with the same row of pixel driving circuits 10 are electrically connected in the first area B1.

[0104] For example, referring to Figure 5B, the two ends of the first light-shielding trace 110a and the second light-shielding trace 110b in the row direction extend to the first area B1 and the second area B2 respectively, and the second end of the first light-shielding trace 110a and the second end of the second light-shielding trace 110b that overlap with the same row of pixel driving circuits 10 are electrically connected in the second area B2.

[0105] For example, referring to Figure 5C, the two ends of the first light-shielding trace 110a and the second light-shielding trace 110b in the row direction extend to the first area B1 and the second area B2 respectively, and the first end of the first light-shielding trace 110a and the first end of the second light-shielding trace 110b overlapping with the same row pixel driving circuit 10 are electrically connected in the first area B1, and the second end of the first light-shielding trace 110a and the second end of the second light-shielding trace 110b are electrically connected in the second area B2.

[0106] Exemplarily, a plurality of first scan signal lines Gate1 and second scan signal lines Gate2 extend along the row direction (first direction X) and extend to the peripheral area BB. First scan signal lines Gate1 and second scan signal lines Gate2 that overlap with the same row of pixel driver circuits 10 are electrically connected in the first area B1 and / or the second area B2. For details, refer to the above description of the first light-shielding traces 110a and the second light-shielding traces 110b.

[0107] An embodiment of connecting a scanning signal to the first type of light-shielding trace is described below.

[0108] In some embodiments, as shown in Figures 5A to 5C, the array substrate 1 further includes at least one gate driver circuit 20 located in the peripheral area BB. The gate driver circuit 20 includes a plurality of shift registers 201, each of which is configured to transmit a scan signal to a row of pixel driver circuits 10. Each shift register 201 includes an output terminal 201a, which is electrically connected to a first scan signal line Gate1 and a second scan signal line Gate2 corresponding to a row of pixel driver circuits 10. The array substrate 1 further includes a source / drain metal layer 19 located on a side of the first gate layer 15 away from the light shielding layer 11. The source / drain metal layer 19 includes a plurality of first connecting lines 191. One end of each first connecting line 191 is electrically connected to one of the output terminals 201a, and the other end is electrically connected to the first light shielding trace 110a or the second light shielding trace 110b. A1 represents the area where the pixel driver circuit is located. The correspondence between the pixel driver circuit area A1 and the signal line is used to represent the correspondence between the pixel driver circuit and the signal line.

[0109] It should be noted that, referring to Figures 2 and 5A, the output end 201a of the shift register 201 is electrically connected to the first scanning signal line Gate1 and the second scanning signal line Gate2 corresponding to a row of pixel driving circuits 10. That is, the output end 201a of the shift register 201 is located in the source-drain metal layer 19, and is electrically connected to the first scanning signal line Gate1 and the second scanning signal line Gate2 through a first via K1 that penetrates the second gate insulating layer 16 and the interlayer dielectric layer 18. The via here can be connected to the first scanning signal line Gate1 or to the second scanning signal line Gate2.

[0110] For example, referring to Figures 2 and 5A to 5C, one end of each of the multiple first connecting lines 191 located in the source-drain metal layer 19 is electrically connected to an output end 201a, and the other end is electrically connected to the first light-shielding trace 110a or the second light-shielding trace 110b through a second via K2 that passes through the buffer layer 12, the first gate insulation layer 14, the second gate insulation layer 16, and the interlayer dielectric layer 18.

[0111] It can be understood that the second via K2 here can be connected to the first light-shielding trace 110 a or the second light-shielding trace 110 b .

[0112] In some embodiments, the position of the first via hole connecting the output end of the shift register to the first scanning signal line Gate1 or the second scanning signal line Gate2 is located at the position of the second via hole connecting the output end of the shift register to the first light-shielding line 110a or the second light-shielding line 110b through the first connecting line, away from the side of the display area.

[0113] In some examples, the first light-shielding trace 110a may or may not be electrically connected to the first scan signal line Gate1, and the second light-shielding trace 110b may or may not be electrically connected to the second scan signal line Gate2.

[0114] By setting a first connecting line located in the source-drain metal layer, the first light-shielding line 110a and the second light-shielding line 110b are directly connected to the output end of the corresponding shift register through the first connecting line, so that the scanning signal output by the shift register is directly connected to the first light-shielding line 110a and the second light-shielding line 110b, so that a stable scanning signal can be transmitted in the first light-shielding line 110a and the second light-shielding line 110b, and the connection position of the first light-shielding line 110a and the second light-shielding line 110b and the shift register does not conflict with the connection position of the first scanning signal line Gate1 or the second scanning signal line Gate2 and the shift register, and does not affect the transmission of the scanning signal in the first scanning signal line Gate1 and the second scanning signal line Gate2.

[0115] Another embodiment of connecting the scanning signal to the first type of light-shielding wiring is introduced below.

[0116] In some embodiments, referring to FIG. 6A to FIG. 6C , the first light-shielding trace 110 a is electrically connected to the first scan signal line Gate1 , and the second light-shielding trace 110 b is electrically connected to the second scan signal line Gate2 .

[0117] For example, the first light-shielding trace 110a is electrically connected to the first scanning signal line Gate1, so that the first light-shielding trace 110a and the first scanning signal line Gate1 can transmit the same signal to the corresponding transistor, avoiding the generation of excessive parasitic capacitance due to signal asynchrony, which causes interference between signals; similarly, the second light-shielding trace 110b is electrically connected to the second scanning signal line Gate2, so that the second light-shielding trace 110b and the second scanning signal line Gate2 can transmit the same signal to the corresponding transistor, avoiding the generation of excessive parasitic capacitance due to signal asynchrony, which causes interference between signals.

[0118] In some embodiments, referring to Figures 6A to 6C , the array substrate 1 includes a display area AA and a peripheral area BB. A plurality of first-type light-shielding traces 110 extend along the row direction and extend into the peripheral area BB. The areas of the peripheral area BB located on either side of the display area AA along the row direction are respectively a first area B1 and a second area B2. The first light-shielding trace 110a is electrically connected to the first scan signal line Gate1 in the first area B1 and / or the second area B2, and the second light-shielding trace 110b is electrically connected to the second scan signal line Gate2 in the first area B1 and / or the second area B2. A1 represents the area where the pixel driver circuit is located. The correspondence between the pixel driver circuit area A1 and the signal line is used here to represent the correspondence between the pixel driver circuit and the signal line.

[0119] 6A , the first light shielding trace 110 a and the first scan signal line Gate1 are electrically connected to each other in the first area B1 through the third via K3 , and the second light shielding trace 110 b and the second scan signal line Gate2 are electrically connected to each other in the first area B1 through the fourth via K4 .

[0120] 6B , the first light shielding trace 110a and the first scan signal line Gate1 are electrically connected to each other through the fifth via K5 in the second area B2 , and the second light shielding trace 110b and the second scan signal line Gate2 are electrically connected to each other through the sixth via K6 in the second area B2 .

[0121] For example, referring to Figure 6C, the first light-shielding trace 110a and the first scanning signal line Gate1 are electrically connected to each other through the third via K3 in the first area B1, and are electrically connected to each other through the fifth via K5 in the second area B2. The second light-shielding trace 110b and the second scanning signal line Gate2 are electrically connected to each other through the fourth via K4 in the first area B1, and are electrically connected to each other through the sixth via K6 in the second area B2.

[0122] Exemplarily, the first light-shielding trace 110a and the first scanning signal line Gate1 are electrically connected to each other through vias in the first area B1 / the second area B2, and the second light-shielding trace 110b and the second scanning signal line Gate2 are electrically connected to each other through vias in the second area B2 / the first area B1.

[0123] It should be noted that the above-mentioned third via K3, fourth via K4, fifth via K5, and sixth via K6 all penetrate the buffer layer 12, semiconductor layer 13, first gate insulation layer 14, first gate layer 15, second gate insulation layer 16, second gate layer 17, and interlayer dielectric layer 18 as shown in Figure 2.

[0124] In the above embodiment, the first scanning signal line Gate1 and the second scanning signal line Gate2 are electrically connected to the output ends of the corresponding shift registers to receive the scanning signals output by the shift registers. The first light-shielding line 110a is electrically connected to the first scanning signal line Gate1, and the second light-shielding line 110b is electrically connected to the second scanning signal line Gate2. The scanning signals are transmitted to the first light-shielding line 110a and the second light-shielding line 110b through the first scanning signal line Gate1 and the second scanning signal line Gate2. There is no need to connect the first light-shielding line 110a and the second light-shielding line 110b to the shift register, which simplifies the wiring and simplifies the preparation process.

[0125] In some embodiments, referring to Figures 4A and 4C, the transistor of each pixel driving circuit 10 further includes a second reset transistor T1, and the plurality of scanning signal lines Gate include a third scanning signal line Gate3, wherein the orthographic projections of the active layer patterns of the second reset transistors T1 in a row of pixel driving circuits 10 on the substrate 101 all overlap with the orthographic projections of the third scanning signal line Gate3 on the substrate 101; the plurality of first-class light-shielding lines 110 include a plurality of third light-shielding lines 110c, wherein the orthographic projections of the active layer patterns of the second reset transistors T1 in a row of pixel driving circuits 10 on the substrate 101 all overlap with the orthographic projections of the third light-shielding lines 110c on the substrate 101; the third light-shielding lines 110c and the third scanning signal line Gate3 both transmit third scanning signals.

[0126] It can be understood that, in the multiple pixel driving circuits 10 arranged along the first direction X, the orthographic projection of the active layer pattern of the second reset transistor T1 in each pixel driving circuit 10 on the substrate 101 overlaps with the orthographic projection of the third scanning signal line Gate3 on the substrate 101, wherein the overlap here means that the orthographic projection of the active layer pattern of the second reset transistor T1 on the substrate 101 partially overlaps with the orthographic projection of the third scanning signal line Gate3 on the substrate 101, and the overlapping portion serves as the gate pattern of the second reset transistor T1, that is, the gate of the second reset transistor T1 receives the third scanning signal.

[0127] Here, “the orthographic projections of the active layer pattern of the second reset transistors T1 in a row of pixel driving circuits 10 on the substrate substrate 101 all overlap with the orthographic projections of the third light-shielding trace 110c on the substrate substrate 101” may include: the orthographic projections of the active layer pattern of the second reset transistors T1 in a row of pixel driving circuits 10 on the substrate substrate 101 all partially overlap with the orthographic projections of the third light-shielding trace 110c on the substrate substrate 101. Overlap may also include: the orthographic projections of the active layer pattern of the second reset transistors T1 in a row of pixel driving circuits 10 on the substrate substrate 101 are located within the orthographic projections of the third light-shielding trace 110c on the substrate substrate 101. Overlap may also include: the orthographic projection boundaries of the active layer pattern of the second reset transistors T1 in a row of pixel driving circuits 10 on the substrate substrate 101 all completely overlap with the orthographic projection boundaries of the third light-shielding trace 110c on the substrate substrate 101.

[0128] In some embodiments of the present application, the array substrate provides a third light-shielding trace 110c connected to a third scanning signal. Furthermore, both the third light-shielding trace 110c, which overlaps with the active layer pattern of the second reset transistor T1, and the third scanning signal line Gate3 transmit the third scanning signal. This ensures synchronization of signals received by the upper and lower layers of the active layer pattern of the second reset transistor T1, which overlap with the orthographic projections of the third light-shielding trace 110c and the third scanning signal line Gate3 on the substrate 101. This improves signal transmission efficiency, avoids excessive parasitic capacitance generated by the overlap between scanning lines and light-shielding traces transmitting different signals, and thus prevents signal interference. This improves the stability of scanning signal transmission by the scanning signal lines, thereby making the scanning signal received by the transistor gate more stable and ensuring normal on / off switching of the transistor. Furthermore, the light-shielding metal layer blocks external light, preventing the active layer pattern of the transistor from being affected by external light and causing characteristic deviation, thereby ensuring normal operation of the pixel driver circuit and improving the display unevenness of the display panel.

[0129] It should be noted that in the array substrate, multiple pixel driving circuits 10 are arranged in an array format, arranged in multiple rows and columns. For example, multiple pixel driving circuits 10 are provided in multiple rows along the second direction. The active layer pattern of the second reset transistor T1 of the pixel driving circuit in the current row is located on one side of the active layer pattern of the first reset transistor T7 of the pixel driving circuit in the previous row in the row direction. A scanning signal line passes through both the second reset transistor in the current row and the first reset transistor in the previous row. That is, the third scanning signal line Gate3 connected to the gate of the second reset transistor T1 in the current row can be the same scanning signal line Gate as the second scanning signal line Gate2 connected to the gate of the first reset transistor T7 in the previous row (as shown in FIG. 4A ). That is, when a scanning signal line Gate is turned on, the scanning signal line Gate simultaneously transmits the scanning signal to the second reset transistor T1 in the current row and the first reset transistor T7 in the previous row.

[0130] In some embodiments, referring to FIG. 4A , the third scanning signal line Gate3 corresponding to the pixel driving circuit in the nth row and the second scanning signal line Gate2 corresponding to the pixel driving circuit in the (n−1)th row are the same signal line.

[0131] It is understood that, as shown in FIG4A , the third scanning signal line Gate3 connected to the gate of the second reset transistor T1 corresponding to the pixel driving circuit in the nth row can be the same scanning signal line Gate as the second scanning signal line Gate2 connected to the gate of the first reset transistor T7 corresponding to the pixel driving circuit in the (n-1)th row. That is, when a scanning signal line Gate is turned on, the scanning signal line Gate simultaneously transmits the scanning signal to the second reset transistor T1 in the current row and the first reset transistor T7 in the previous row.

[0132] In some embodiments, referring to Figures 4A to 4C, the transistor of each pixel driving circuit 10 also includes a driving transistor T3, and the light-shielding layer 11 includes a plurality of second-type light-shielding traces 120, wherein the positive projections of the active layer patterns of the driving transistors T3 in a row of pixel driving circuits 10 on the substrate 101 overlap with the positive projections of a second-type light-shielding trace 120 on the substrate 101; the second-type light-shielding trace 120 transmits a first voltage signal.

[0133] 4A to 4C , the second type of light-shielding trace 120 includes a plurality of light-shielding patterns 121 and a plurality of connecting patterns 122 that are alternately arranged, each connecting pattern 122 connecting two adjacent light-shielding patterns 121 , and the orthographic projection of each light-shielding pattern 121 on the base substrate 101 surrounds the orthographic projection of the driving transistor T3 of a pixel driving circuit 10 on the base substrate 101 .

[0134] Exemplarily, the second-type light-shielding trace 120 shown in Figures 4A to 4C is a second-type light-shielding trace 120 in a pixel driving circuit 10, and the second-type light-shielding trace 120 includes a connected light-shielding pattern 121 and a connecting pattern 122, wherein the orthographic projection of the light-shielding pattern 121 on the substrate 101 is larger than the orthographic projection of the connecting pattern 122 on the substrate 101. Referring to Figures 4A to 4C, the orthographic projection of the light-shielding pattern 121 on the substrate 101 surrounds the orthographic projection of the active layer pattern of the driving transistor T3 in its corresponding pixel driving circuit 10 on the substrate 101, that is, the orthographic projection of the active layer pattern of the driving transistor T3 on the substrate 101 is located within the range of the orthographic projection of the light-shielding pattern 121 on the substrate 101.

[0135] It can be understood that “the orthographic projections of the active layer patterns of the driving transistors T3 of a row of pixel driving circuits 10 on the substrate substrate 101 all overlap with the orthographic projections of a second-type light-shielding trace 120 on the substrate substrate 101” may include: the orthographic projections of the active layer patterns of the driving transistors T3 in a row of pixel driving circuits 10 on the substrate substrate 101 all partially overlap with the orthographic projections of a second-type light-shielding trace 120 on the substrate substrate 101. Overlap may also include: the orthographic projections of the active layer patterns of the driving transistors T3 in a row of pixel driving circuits 10 on the substrate substrate 101 are located within the orthographic projections of a second-type light-shielding trace 120 on the substrate substrate 101. Overlap may also include: the orthographic projection boundaries of the active layer patterns of the driving transistors T3 in a row of pixel driving circuits 10 on the substrate substrate 101 all completely overlap with the orthographic projection boundaries of a second-type light-shielding trace 120 on the substrate substrate 101.

[0136] The second type of light-shielding trace 120 overlaps with the driving transistor, and can block external light from being directed to the driving transistor, thereby preventing the driving transistor from having characteristic deviations due to light exposure, thereby ensuring the stability of the driving current generated by the driving transistor. The first voltage signal is a constant voltage signal, and the first voltage signal is transmitted in the second type of light-shielding trace 120, which can prevent the signals transmitted on other signal lines from crosstalking with the signals of the second type of light-shielding trace, thereby affecting the gate voltage of the driving transistor T3, thereby further ensuring the stability of the driving current generated by the driving transistor and improving the uniformity of the display.

[0137] In some embodiments, referring to Figures 2, 6C and 7, the array substrate 1 also includes a source-drain metal layer 19 arranged on the side of the first gate layer 15 away from the light-shielding layer 11, and the source-drain metal layer 19 includes a first voltage signal line 192, and the first voltage signal line 192 is electrically connected to the second type of light-shielding trace 120.

[0138] For example, referring to Figures 2, 6C and 7, the first voltage signal line 192 is located in the source and drain metal layer 19, and the first voltage signal line 192 is electrically connected to the second type of light-shielding trace 120 through a via that passes through the buffer layer 12, the first gate insulation layer 14, the second gate insulation layer 16, and the interlayer dielectric layer 18.

[0139] In some embodiments, with continued reference to Figures 5A to 5C, 6A to 6C, and 8A to 8C, each second-type light-shielding trace 120 overlaps with a driving transistor T3 of a row of pixel driving circuits 10; each column of pixel driving circuits 10 is connected to a corresponding first voltage signal line 192; at least three adjacent pixel driving circuits 10 in each row of pixel driving circuits 10 form a pixel driving circuit group 30, and the first voltage signal line 192 connected to at least one pixel driving circuit 10 in a pixel driving circuit group 30 is connected to the second-type light-shielding trace 120. A1 represents the area where the pixel driving circuit is located, and the correspondence between the pixel driving circuit area A1 and the signal line is used here to represent the correspondence between the pixel driving circuit and the signal line.

[0140] For example, referring to Figures 8A to 8C , a pixel driving circuit 10 comprising a row and three columns is described as follows, wherein each column of pixel driving circuits 10 is connected to a corresponding first voltage signal line 192, and the first light-emitting control transistor T5 and storage capacitor in each column of pixel driving circuits are electrically connected to a first voltage signal line. Each column of pixel driving circuits 10 transmits a first voltage signal; three adjacent pixel driving circuits 10 in a row of pixel driving circuits 10 form a pixel driving circuit group 30, and the first voltage signal line 192 connected to one pixel driving circuit 10 in each pixel driving circuit group 30 is electrically connected to the second-type light-shielding trace 120 via a seventh via K7 that penetrates the buffer layer 12, the first gate insulating layer 14, the second gate insulating layer 16, and the interlayer dielectric layer 18. It should be noted that the three adjacent pixel driving circuits 10 in a pixel driving circuit group 30 can, for example, respectively drive a red sub-pixel, a green sub-pixel, or a blue sub-pixel.

[0141] For example, referring to Figures 9A to 9D, the pixel driving circuit 10 is taken as an example to include one row and four columns, wherein each column of pixel driving circuits 10 is correspondingly connected to a first voltage signal line 192, and each column of pixel driving circuits 10 transmits a first voltage signal; the four adjacent pixel driving circuits 10 in a row of pixel driving circuits 10 constitute a pixel driving circuit group 30, and the first voltage signal line 192 connected to any one pixel driving circuit 10 in each pixel driving circuit group 30 is electrically connected to the second type of light-shielding trace 120 through the seventh via K7 that passes through the buffer layer 12, the first gate insulating layer 14, the second gate insulating layer 16, and the interlayer dielectric layer 18. It should be noted that the four adjacent pixel driving circuits 10 in a pixel driving circuit group 30 can, for example, drive red sub-pixels, green sub-pixels, blue sub-pixels, and green sub-pixels in sequence.

[0142] It is understandable that the first voltage signal lines 192 connected to any two, three or each pixel driving circuit 10 in the above pixel driving circuit group 30 can also be electrically connected to the second type of light shielding wiring 120 respectively, and no specific limitation is given here.

[0143] Since the second-type metal wiring extends along the row direction and overlaps with the driving transistors T3 of each pixel driving circuit 10 in a row of pixel driving circuits, and the first voltage signal is connected to each of the second-type metal wirings, it is considered to group three / four adjacent pixel driving circuits. In each pixel driving circuit group 30, only the first voltage signal line 192 connected to at least one pixel driving circuit 10 needs to be connected to the second-type metal wiring through a via. There is no need for the first voltage signal line connected to each pixel driving circuit to be connected through a via. In this way, while ensuring that the first voltage signal is connected to the second-type metal wiring, the layout space design is optimized, space is saved, and the preparation process is simplified.

[0144] In some embodiments, referring to FIG. 10 , the array substrate 1 includes a display area AA and a peripheral area BB, and a plurality of first voltage signal lines 192 are electrically connected to each other in the peripheral area BB. A1 represents the area where the pixel driving circuit is located, and the correspondence between the pixel driving circuit area A1 and the signal lines is used herein to represent the correspondence between the pixel driving circuit and the signal lines.

[0145] Exemplarily, each column of pixel driving circuits 10 shown in FIG10 is connected to a first voltage signal line 192, and multiple first voltage signal lines 192 are electrically connected to each other on the same side extending along the column direction. For example, multiple first voltage signal lines 192 are electrically connected in the peripheral area BB through a voltage signal connection line 193. That is, each column of pixel driving circuits 10 transmits a first voltage signal to ensure transmission efficiency.

[0146] The embodiment of the present disclosure further provides a display panel 100, which includes the array substrate 1 provided by any of the above embodiments. Therefore, the display panel 100 provided by the present invention has all the advantages of the array substrate 1 provided by any of the above embodiments, which will not be described in detail here.

[0147] In some embodiments, referring to Figure 11, the display panel 100 also includes a light-emitting device layer 50 and an encapsulation layer 60 arranged on the array substrate 1, and the array substrate 1 includes: a base substrate 101 and a pixel circuit stack 40, the pixel circuit stack 40 includes a plurality of transistors TFT, and the light-emitting device layer 50 and the encapsulation layer 60 are stacked in sequence on the pixel circuit stack 40.

[0148] The light-emitting device layer 50 includes an anode layer 22 , a pixel defining layer 23 , a light-emitting layer 24 and a cathode layer 25 , which are disposed on the planar layer 21 .

[0149] The anode layer 22 includes multiple anodes 221, which are electrically connected to the source / drain metal layer 19 through vias. The light-emitting layer 24 includes multiple light-emitting portions, each of which overlaps with an anode 221. A plurality of pixel openings are formed in the pixel-defining layer 23, each of which exposes a portion of an anode. The light-emitting portions in the light-emitting layer 24 are disposed within the pixel openings in a one-to-one correspondence, so that the edges of the light-emitting portions overlap with the edges of the pixel openings.

[0150] The cathode layer is located on a side of the pixel defining layer 23 and the light emitting layer 24 away from the array substrate 1 .

[0151] The light-emitting device L shown in FIG11 includes an anode, a cathode, and a light-emitting layer sandwiched between the anode and cathode. Applying voltage to the anode and cathode generates an electric field between the two, which drives holes in the anode and electrons in the cathode to recombine in the light-emitting layer, causing the light-emitting layer to emit light. The anode is disposed on the array substrate 1 and can be electrically connected to the pixel driving circuit 10.

[0152] The encapsulation layer 60 is located on the side of the cathode layer 25 away from the array substrate 1. Exemplarily, the encapsulation layer 60 includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer. The encapsulation layer 60 is used to encapsulate the light-emitting device to protect the light-emitting device L and avoid corrosion caused by external water and oxygen.

[0153] Some embodiments of the present disclosure provide a display device 1000, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, a wearable display device, etc. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the above-mentioned display device. As shown in FIG1 , the display device 1000 includes the display panel 100 provided in any of the above embodiments. Therefore, the display device 1000 provided by the present invention has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be described in detail here.

[0154] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: A plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arranged in a plurality of rows and columns; each of the plurality of pixel driving circuits comprises a plurality of transistors; substrate substrate; A light shielding layer is arranged on one side of the base substrate, wherein the light shielding layer comprises a plurality of first-type light shielding traces; A semiconductor layer disposed on a side of the light shielding layer away from the base substrate, wherein the semiconductor layer includes active layer patterns of the plurality of transistors; A first gate layer is disposed on a side of the semiconductor layer away from the substrate, the first gate layer comprises a plurality of scanning signal lines; each of the scanning signal lines passes through an active layer pattern of at least one transistor; the plurality of scanning signal lines transmit scanning signals; Each of the plurality of first-type light-shielding wirings passes through an active layer pattern of at least one transistor; The first type of light shielding wiring and the scanning signal line passing through the active layer pattern of the same transistor transmit the same scanning signal.

2. The array substrate according to claim 1, wherein: The transistors of each pixel driving circuit include compensation transistors and data writing transistors, and the plurality of scanning signal lines include a first scanning signal line, wherein the orthographic projections of the active layer patterns of the compensation transistors and the active layer patterns of the data writing transistors in a row of pixel driving circuits on the substrate overlap with the orthographic projections of the first scanning signal line on the substrate; The plurality of first-type light-shielding lines include a first light-shielding line, wherein the orthographic projections of the active layer patterns of the compensation transistors and the active layer patterns of the data writing transistors in a row of pixel driving circuits on the substrate overlap with the orthographic projections of the first light-shielding line on the substrate; The first light-shielding wiring and the first scanning signal line both transmit a first scanning signal.

3. The array substrate according to claim 2, wherein: The transistor of each pixel driving circuit further includes a first reset transistor, and the plurality of scanning signal lines include a second scanning signal line, wherein the orthographic projection of the active layer pattern of the first reset transistor in a row of pixel driving circuits on the substrate overlaps with the orthographic projection of the second scanning signal line on the substrate; The plurality of first-type light-shielding wirings include a plurality of second light-shielding wirings, wherein the orthographic projections of the active layer patterns of the first reset transistors in a row of pixel driving circuits on the substrate overlap with the orthographic projections of the second light-shielding wirings on the substrate; The second light-shielding wiring and the second scanning signal line both transmit a second scanning signal.

4. The array substrate according to claim 3, wherein: The first scanning signal line and the second scanning signal line overlapping with the same row of pixel driving circuits transmit the same signal; The array substrate includes a display area and a peripheral area, and the plurality of first-type metal wirings extend along a row direction and extend to the peripheral area; the areas of the peripheral area located on both sides of the display area along the row direction are respectively a first area and a second area; The first light-shielding wiring and the second light-shielding wiring overlapping with the pixel driving circuit in the same row are electrically connected in the first area and / or the second area.

5. The array substrate according to claim 4, wherein: The array substrate further comprises at least one gate driving circuit located in the peripheral area, the gate driving circuit comprising a plurality of shift registers, each shift register being configured to transmit a scanning signal to a row of pixel driving circuits; Each shift register comprises an output terminal; the output terminal is electrically connected to the first scanning signal line and the second scanning signal line corresponding to a row of pixel driving circuits; The array substrate also includes a source-drain metal layer located on the side of the first gate layer away from the light-shielding layer, and the source-drain metal layer includes a plurality of first connecting lines; one end of each of the first connecting lines is electrically connected to one of the output ends, and the other end is electrically connected to the first light-shielding wiring or the second light-shielding wiring.

6. The array substrate according to any one of claims 3 to 5, wherein: The first light-shielding wiring is electrically connected to the first scanning signal line, and the second light-shielding wiring is electrically connected to the second scanning signal line.

7. The array substrate according to claim 6, wherein: The array substrate comprises a display area and a peripheral area, the plurality of first-type light-shielding lines extend along the row direction and extend to the peripheral area; the areas of the peripheral area located on both sides of the display area along the row direction are respectively a first area and a second area; The first light-shielding wiring is electrically connected to the first scanning signal line in the first area and / or the second area, and the second light-shielding wiring is electrically connected to the second scanning signal line in the first area and / or the second area.

8. The array substrate according to claim 3, wherein: The transistor of each pixel driving circuit further includes a second reset transistor, and the plurality of scanning signal lines include a third scanning signal line, wherein the orthographic projection of the active layer pattern of the second reset transistor in a row of pixel driving circuits on the substrate overlaps with the orthographic projection of the third scanning signal line on the substrate; The plurality of first-type light-shielding wirings include a plurality of third light-shielding wirings, wherein the orthographic projections of the active layer patterns of the second reset transistors in a row of pixel driving circuits on the substrate overlap with the orthographic projections of the third light-shielding wirings on the substrate; The third light-shielding wiring and the third scanning signal line both transmit a third scanning signal.

9. The array substrate according to claim 8, wherein: The third scanning signal line corresponding to the pixel driving circuit in the nth row and the second scanning signal line corresponding to the pixel driving circuit in the (n-1)th row are the same signal line.

10. The array substrate according to any one of claims 1 to 9, wherein: The transistor of each pixel driving circuit further includes a driving transistor, the light shielding layer includes a plurality of second-type light shielding wirings, wherein an orthographic projection of an active layer pattern of the driving transistors in a row of pixel driving circuits on the substrate overlaps with an orthographic projection of a second-type light shielding wiring on the substrate; The second type of light-shielding wiring transmits a first voltage signal.

11. The array substrate according to claim 10, wherein: Also includes: A source-drain metal layer is disposed on a side of the first gate layer away from the light shielding layer, wherein the source-drain metal layer comprises a first voltage signal line, and the first voltage signal line is electrically connected to the second-type light shielding wiring.

12. The array substrate according to claim 11, wherein: Each second-type light-shielding wiring overlaps with a driving transistor of a row of pixel driving circuits; each column of pixel driving circuits is correspondingly connected to a first voltage signal line; At least three adjacent pixel driving circuits in each row of pixel driving circuits form a pixel driving circuit group, and a first voltage signal line connected to at least one pixel driving circuit in a pixel driving circuit group is connected to the second-type light-shielding wiring.

13. The array substrate according to claim 12, wherein: The array substrate comprises a display area and a peripheral area, and the plurality of first voltage signal lines are electrically connected to each other in the peripheral area.

14. The array substrate according to any one of claims 10 to 13, wherein: The second type of light-shielding wiring includes a plurality of light-shielding patterns and a plurality of connection patterns that are alternately arranged, each connection pattern connects two adjacent light-shielding patterns, and the orthographic projection of each light-shielding pattern on the substrate surrounds the orthographic projection of a driving transistor of a pixel driving circuit on the substrate.

15. A display panel, comprising: The array substrate according to any one of claims 1 to 14.

16. A display device, comprising: The display panel as claimed in claim 15.

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