Random number generation method and apparatus

Abstract

The present application discloses a random number generation method and apparatus. The method comprises: dividing 64-byte information to be encrypted into 16 blocks, each block representing four bytes, and every four blocks being used as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; on the basis of the basic blocks and 256-bit registers, completing a one-time basic operation of performing a hybrid operation on a block in a stream symmetric encryption algorithm; using a block as a unit, circularly shifting the second basic block leftward by one block, circularly shifting the third basic block leftward by two blocks, and circularly shifting the fourth basic block leftward by three blocks; and on the basis of the basic blocks and the 256-bit registers, completing a one-time basic operation of performing a hybrid operation on a rearranged block in a stream symmetric encryption algorithm.

Description

A random number generation method and device Technical Field The present application relates to but is not limited to information security technology, and in particular to a random number generation method and device. Background Art Zero-Knowledge Proof (ZKP) was proposed by S. Goldwasser, S. Micali and C. Rackoff in the early 1980s. Zero-knowledge proof means that the prover can convince the verifier that a certain assertion is correct without providing any useful information to the verifier. Zero-knowledge proof is essentially a protocol involving two or more parties, in other words, a series of steps required for two or more parties to complete a task. In zero-knowledge proof, the prover proves to the verifier and makes him believe that he knows or has a certain message, but the proof process cannot leak any information about the proven message to the verifier. The streaming symmetric encryption algorithm, as a random number generator in the ZKP system, can ensure that the prover and the verifier generate the same random number, and the random number cannot be predicted in advance. In the related art, when the streaming symmetric encryption algorithm is implemented in software, the amount of data it calculates is large, and the memory will be frequently called, thereby increasing the burden on the CPU; moreover, during the ZKP encryption process, the encryption time will also be too long. SUMMARY OF THE INVENTION The present application provides a random number generation method and device, which can reduce the amount of calculation and increase the random number generation speed, thereby shortening the time to execute the ZKP encryption process. The present application provides a random number generation method, including: Divide the 64-byte information to be encrypted into 16 blocks, each block represents 4 bytes, and use every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; the four basic blocks are respectively stored in four 256-bit registers; Based on four basic blocks and four 256-bit registers, a basic operation of mixing blocks in the streaming symmetric encryption algorithm is completed; Taking blocks as units, circularly shift the second basic block to the left by one block, circularly shift the third basic block to the left by two blocks, and circularly shift the fourth basic block to the left by three blocks; Based on four basic blocks and four 256-bit registers, a basic operation of mixing the rearranged blocks in the streaming symmetric encryption algorithm is completed. In an exemplary embodiment, it also includes: The preset round number is increased by one, and the step of performing a basic operation of a mixed operation on the block is returned until the round number reaches a preset round number threshold; An addition operation is performed on the result after iterative operation for a preset number of rounds and the information to be encrypted before being updated, and the operation result is used as a random number. In an exemplary instance, the mixed operation includes: a 256-bit single instruction multiple data SIMD addition instruction, used to implement an addition operation on two 256-bit SIMD registers; a 256-bit SIMD exclusive OR, used to implement an exclusive OR operation on two 256-bit SIMD registers, wherein one of the 256-bit registers represents a result of the addition operation; and a first SIMD circular left shift instruction, used to implement a first circular left shift of N1 bits on the 256-bit SIMD register representing the result of the exclusive OR operation in independent units of 32 bits. In an exemplary embodiment, the first basic block includes block0, block1, block2 and block3 of the 16 blocks; the second basic block includes block4, block5, block6 and block7 of the 16 blocks; the third basic block includes block8, block9, block10 and block11 of the 16 blocks; the fourth basic block includes block12, block13, block14 and block15 of the 16 blocks; The cyclic left shifting of the second basic block by one block, the cyclic left shifting of the third basic block by two blocks, and the cyclic left shifting of the fourth basic block by three blocks include: According to the result of the basic operation of the mixed operation on the blocks, block5 of the second basic block is circularly shifted left to block4, block10 of the third basic block is circularly shifted left to block8, and block15 of the fourth basic block is circularly shifted left to block12. In an exemplary embodiment, the circular left shift is a second SIMD circular left shift; the second SIMD circular left shift is implemented by a SIMD128_ROL instruction; The format of the SIMD128_ROL instruction includes: SIMD128_ROL (S, N2, R), which is used to implement a 128-bit N2-bit circular left shift of S to obtain R; wherein S represents a 256-bit SIMD register that performs a circular left shift operation, N2 represents the number of bits of the circular left shift, and N2 is An integer multiple of 32. An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute any of the above-mentioned random number generation methods. An embodiment of the present application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: used to execute the steps of any of the above-mentioned random number generation methods. The embodiment of the present application further provides a random number generating device, comprising: a control unit, a preprocessing unit, a 256-bit register file, an iterative processing unit, and a tail processing unit; wherein, A preprocessing module is used to read data from the memory under the control of the control unit, and perform the following preprocessing on the read data and store it in a 256-bit register stack, wherein two copies of the preprocessing results are stored in the 256-bit register stack: 64 bytes of information to be encrypted are divided into 16 blocks, each block represents 4 bytes, and every 4 blocks are used as a basic block to obtain a first basic block, a second basic block, a third basic block and a fourth basic block; the four basic blocks are respectively stored in four 256-bit registers; The core processing unit is used to perform the following preset rounds of iterative operations: read the information to be encrypted from the 256-bit register stack, and based on the four basic blocks and the four 256-bit registers, complete a basic operation of mixing blocks in the streaming symmetric encryption algorithm; in units of blocks, cyclically shift the second basic block to the left by one block, cyclically shift the third basic block to the left by two blocks, and cyclically shift the fourth basic block to the left by three blocks, and update 16 blocks corresponding to the information to be encrypted in the 256-bit register stack; based on the updated four basic blocks and the four 256-bit registers, complete a basic operation of mixing the rearranged blocks in the streaming symmetric encryption algorithm; The tail processing unit is used to perform an addition operation on the result after iterative operation of a preset number of rounds threshold and the information to be encrypted before being updated under the control of the control unit, and write the result as the random number to the memory. In an exemplary embodiment, the 256-bit register file includes eight 256-bit registers SIMD_reg0 to SIMD_reg7; wherein, SIMD_reg0 is used to store the first basic block, SIMD_reg1 is used to store the second basic block, SIMD_reg2 is used to store the third basic block, and SIMD_reg3 is used to store the The fourth basic block; SIMD_reg4 is used to store the first basic block, SIMD_reg5 is used to store the second basic block, SIMD_reg6 is used to store the third basic block, and SIMD_reg7 is used to store the fourth basic block. In an exemplary embodiment, the information to be encrypted before being updated and read in the tail processing unit is data read from SIMD_reg4 to SIMD_reg7 in the 256-bit register file. In an exemplary embodiment, the core processing unit may include: an iteration control module, a first processing module, a rearrangement module, and a second processing module; wherein, The first processing module is used for, under the control of the iterative processing module, reading the information to be encrypted from SIMD_reg0 to SIMD_reg3 in the 256-bit register file, based on the basic block and the 256-bit register, completing a basic operation of mixing operations on the blocks in the streaming symmetric encryption algorithm; in one embodiment, reading the information to be encrypted from the 256-bit register file is from; a rearrangement module, used for cyclically shifting the second basic block to the left by one block, cyclically shifting the third basic block to the left by two blocks, cyclically shifting the fourth basic block to the left by three blocks, and updating 16 blocks in the preprocessing module; The second processing module is used to complete a basic operation of performing a mixed operation on the rearranged blocks in the streaming symmetric encryption algorithm based on the updated basic blocks and the 256-bit register. In an exemplary embodiment, the control of the iterative processing module is used to: increase the preset number of rounds by one, and notify the first processing module to perform a basic operation until the number of rounds reaches a preset round number threshold, and use the operation result as a random number. An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute any of the above-mentioned random number generation methods. An embodiment of the present application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: used to execute the steps of any of the above-mentioned random number generation methods. Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The objectives and other advantages of the present invention can be achieved by the structures particularly pointed out in the description, claims and drawings. and obtain. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application. FIG1 is a schematic diagram of block division in the related art; FIG2 is a schematic diagram of a flow chart of a random number generation method in an embodiment of the present application; FIG3 is a schematic diagram of the division of blocks in an embodiment of the present application; FIG4 is a schematic diagram of reshooting a block in an embodiment of the present application; FIG5 is a schematic diagram of the composition structure of a random number generating device in an embodiment of the present application; FIG6 is a schematic diagram of a process embodiment of a basic operation in the first processing module in an embodiment of the present application; FIG. 7 is a schematic diagram of an embodiment of the addition process of the tail processing module in an embodiment of the present application. Details In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict. In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. When the stream symmetric encryption algorithm in the related art encrypts 64 bytes, it first divides the input 64 bytes of information to be encrypted into 16 blocks, and the arrangement index of each block is shown in the figure As shown in 1, each block represents 4 bytes. In the stream symmetric encryption algorithm, a basic operation includes mixing operations on 4 blocks, and each round requires the following 8 basic operations: The first basic operation: perform mixed operations on block0, block4, block8, and block12; The second basic operation: perform mixed operations on block1, block5, block9, and block13; The third basic operation: perform mixed operations on block2, block6, block10, and block14; The fourth basic operation: perform mixed operations on block3, block7, block11, and block15; The fifth basic operation: perform mixed operations on block0, block5, block10, and block15; The sixth basic operation: perform mixed operations on block1, block6, block11, and block12; The seventh basic operation: perform mixed operations on block2, block7, block8, and block13; The eighth basic operation: perform mixed operations on block3, block4, block9, and block14. In this way, a total of multiple rounds (the number of rounds can be set in advance) are required to obtain a 64-byte random number. Each round can be regarded as two operations. The first operation includes the first basic operation to the fourth basic operation, and the second operation includes the fifth basic operation to the eighth basic operation. Taking the first basic operation as an example, a mixed operation of 4 blocks can include the following operations: block[0]=block[0]+block[4]; block

[0012] =ROL(block

[0012] ^block[0],16), where ROL represents a circular left shift operator and ^ represents an exclusive-or operator; block[8]=block[8]+block

[0012] ; block[4]=ROL(block[4]^block[8], 12); block[0]=block[0]+block[4]; block

[0012] =ROL(block

[0012] ^block[0], 8); block[8]=block[8]+block

[0012] ; block[4]=ROL(block[4]^block[8], 7). In the process of mixed operation on blocks, since the stream symmetric encryption algorithm does not need to consider the carry operation when operating on blocks, the first basic operation to the fourth basic operation can be performed at the same time. In the process of performing the first basic operation, namely the addition operation, the streaming encryption process will make the encryption time too long during the ZKP encryption process. In order to reduce the amount of calculation, increase the speed of random number generation, and thus shorten the duration of the ZKP encryption process, the embodiment of the present application proposes a random number generation method. FIG2 is a flow chart of the random number generation method in the embodiment of the present application, as shown in FIG2, including: Step 200: Divide the 64-byte information to be encrypted into 16 blocks, each block represents 4 bytes, and use every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block and a fourth basic block; the four basic blocks are respectively stored in four 256-bit registers. In an exemplary embodiment, if the information to be encrypted is 64 bytes, then the 64 bytes of information to be encrypted can be divided into 16 blocks in step 200; if the information to be encrypted is 128 bytes, then the 128 bytes of information to be encrypted will be divided into 2 64-byte information to be encrypted, and then 64 bytes will be processed each time according to the random number generation method provided in the embodiment of the present application, and then another 64-byte information to be encrypted will be processed. In other words, the information to be encrypted in the embodiment of the present application will first be divided into one or more 64-byte information to be encrypted, and then processed one by one in units of 64 bytes. In an exemplary embodiment, as shown in FIG3 , block0, block1, block2 and block3 are used as the first basic blocks (as shown by the diagonal shading in FIG3 ), block4, block5, block6 and block7 are used as the second basic blocks (as shown by the vertical shading in FIG3 ), block8, block9, block10 and block11 are used as the third basic blocks (as shown by the diamond shading in FIG3 ), and block12, block13, block14 and block15 are used as the fourth basic blocks (as shown by the horizontal shading in FIG3 ). Based on the scenario of 256-bit registers, taking the RISC-V instruction set architecture as an example, in the first 256-bit single instruction multiple data (SIMD, single-instruction multiple-data) register (SIMD_reg1), the first basic block, namely block0, block1, block2 and block3 data, is saved, the first operand is block0, included in the bits [31:0] of the 256-bit SIMD_reg1, the second operand is block1, included in the bits [63:32] of the 256-bit SIMD_reg1, the third operand is block2, included in the bits [95:64] of the 256-bit SIMD_reg1, and the fourth operand is block3, included in the bits [127:96] of SIMD_reg1. In the second 256-bit SIMD register (SIMD_reg2), the second basic block, block4, block5, block6 and block7 data, is stored. The first operand is block4, which is included in the bit [31:0] of the 256-bit SIMD_reg2. The second operand is block5. Included in bit [63:32] of 256-bit SIMD_reg2, the third operand is block6, included in bit [95:64] of 256-bit SIMD_reg2, and the fourth operand is block7, included in bit [127:96] of 256-bit SIMD_reg2. In the third 256-bit SIMD register (SIMD_reg3), the third basic block, i.e., block8, block9, block10, and block11 data, is saved, the first operand is block8, included in bit [31:0] of 256-bit SIMD_reg3, the second operand is block9, included in bit [63:32] of 256-bit SIMD_reg3, the third operand is block10, included in bit [95:64] of 256-bit SIMD_reg3, and the fourth operand is block11, included in bit [127:96] of 256-bit SIMD_reg3. In the fourth 256-bit SIMD register (SIMD_reg4), the fourth basic block, block12, block13, block14 and block15 data, is saved, the first operand is block12, included in the bit [31:0] of the 256-bit SIMD_reg4, the second operand is block13, included in the bit [63:32] of the 256-bit SIMD_reg4, the third operand is block14, included in the bit [95:64] of the 256-bit SIMD_reg4, and the fourth operand is block15, included in the bit [127:96] of the 256-bit SIMD_reg4. Among them, RISC-V is an open source instruction set architecture (ISA) based on the reduced instruction set (RISC) principle. Step 201: Based on four basic blocks and four 256-bit registers, a basic operation of mixing blocks in a streaming symmetric encryption algorithm is completed. In the embodiment of the present application, since every 4 blocks are used as a basic block, as shown in FIG3 , based on the 256-bit register, the first basic operation to the fourth basic operation of the mixed operation of the block only need one basic operation to complete, which reduces the amount of calculation and improves the speed of random number generation, thereby shortening the execution time of the ZKP encryption process. Taking the first basic operation in the basic operation, that is, the addition operation, as an example, in the embodiment of the present application, in the 256-bit register, as shown below, only one addition is required: SIMD_reg1_block0=SIMD_reg1_block0+SIMD_reg2_block4, SIMD_reg1_block1=SIMD_reg1_block1+SIMD_reg2_block5, SIMD_reg1_block2=SIMD_reg1_block2+SIMD_reg2_block6, SIMD_reg1_block3=SIMD_reg1_block3+SIMD_reg2_block7. It can be seen more intuitively from FIG. 1 and FIG. 3 that in the related art, as shown in FIG. 1, based on a 32-bit register, the first basic operation is performed on the first column, the second basic operation is performed on the second column, the third basic operation is performed on the third column, and the fourth basic operation is performed on the first column. In the four columns, the four basic operations are independent of each other. In the embodiment of the present application, as shown in FIG3, based on the 256-bit register, the four blocks in the first row are used as an element in the same column, that is, the four blocks in the first row are a basic block, namely the first basic block. Similarly, the four blocks in the second row are a basic block, namely the second basic block, the four blocks in the third row are a basic block, namely the third basic block, and the four blocks in the fourth row are a basic block, namely the fourth basic block. In this way, a column is composed of four basic blocks. Therefore, in the embodiment of the present application, only one basic operation is performed on the column composed of four basic blocks, which includes four basic operations in the related art. That is to say, in the embodiment of the present application, during the addition, XOR or first circular left shift operation, only one basic operation is required based on the 256-bit register. In an exemplary embodiment, in order to implement mixed operations based on 256-bit registers, the instructions for mixed operations are set as follows in the embodiment of the present application: The 256-bit SIMD addition (SIMD256_ADD) instruction is used to implement the addition operation of two 256-bit SIMD registers, and its format includes: SIMD256_ADD (S1, S2, R1), where S1 represents the first 256-bit SIMD register involved in the addition operation, and S2 represents the second 256-bit SIMD register involved in the addition operation. SIMD256_ADD (S1, S2, R1) is used to implement R1 = S1 + S2. In one embodiment, taking the addition operation of 256-bit SIMD_reg1 and 256-bit SIMD_reg2 as an example, S1 is SIMD_reg1 (block0, block1, block2, block3), and S2 is SIMD_reg2 (block4, block5, block6, block7), then R1 = (S1_Block0+S2_Block4, S1_Block1+S2_Block5, S1_Block2+S2_Block6, S1_Block3+S2_Block7). The 256-bit SIMD XOR (SIMD256_XOR) instruction is used to implement the XOR operation on two 256-bit SIMD registers, and its format includes: SIMD256_XOR (S1, S2, R1), where S1 represents the first 256-bit SIMD register involved in the XOR operation, and S2 represents the second 256-bit SIMD register involved in the XOR operation. SIMD256_XOR (S1, S2, R1) is used to implement R1 = S1^S2. In one embodiment, taking the XOR operation of 256-bit SIMD_reg1 and 256-bit SIMD_reg2 as an example, S1 is SIMD_reg1 (block0, block1, block2, block3), S2 is SIMD_reg2 (block4, block5, block6, block7), then R1 = (S1_Block0^S2_Block4, S1_Block1^S2_Block5, S1_Block2^S2_Block6, S1_Block3^S2_Block7). The first SIMD circular left shift (SIMD256_32_ROL) instruction, whose format includes: SIMD256_32_ROL (S, N1, R), wherein S represents a 256-bit SIMD register that performs a circular left shift operation, and N1 represents the number of bits of the circular left shift. SIMD256_32_ROL (S, N1, R) is used to implement a circular left shift of N1 bits on S with 32 bits as an independent unit to obtain R. In the embodiment of the present application, N1 = 7, 8, 12, 16, taking the circular left shift operation on the 256-bit SIMD_reg1 as an example, S is SIMD_reg1 (block0, block1, block2, block3), then, R = (S1_Block0_ROL (N1), S1_Block1_ROL (N1), S1_Block2_ROL (N1), S1_Block3_ROL (N1)). In an exemplary instance, the execution of step 201 may include: the processor executes the SIMD256_ADD instruction, the result of the SIMD256_ADD instruction is used to execute the SIMD256_XOR instruction, and the result of the SIMD256_XOR instruction is used to execute SIMD256_32_ROL. In this way, the above algorithm is executed on each row block, i.e., the basic block, of the input information to be encrypted in the streaming symmetric encryption algorithm based on a 256-bit register, to obtain the result after the operation of step 201. Step 202: Taking blocks as units, circularly shift the second basic block to the left by one block, circularly shift the third basic block to the left by two blocks, and circularly shift the fourth basic block to the left by three blocks. In an exemplary embodiment, as shown in FIG4 , this step may include: Based on the result of the operation in step 201, step 202 performs the following rearrangement operation to achieve the rearrangement of the blocks: keep the first basic block unchanged, move block5 of the second basic block cyclically left to block4, move block10 of the third basic block cyclically left to block8, and move block15 of the fourth basic block cyclically left to block12. In an exemplary embodiment, in order to realize the rearrangement of blocks based on 256-bit registers, the instructions for rearranging blocks in the embodiment of the present application are as follows: The second SIMD circular left shift (SIMD128_ROL) instruction, whose format includes: SIMD128_ROL (S, N2, R), wherein S represents a 256-bit SIMD register that performs a circular left shift operation, N2 represents the number of bits of the circular left shift, and SIMD128_ROL (S, N2, R) is used to implement a 128-bit N2-bit circular left shift on S to obtain R. In the embodiment of the present application, N2 = 32, 64, 96. In one embodiment, as shown in FIG4 , step 202 implemented using the SIMD128_ROL instruction may include: SIMD128_ROL (SIMD_reg2, 32, R2), indicating that a 128-bit 32-bit circular left shift operation is performed on the 256-bit SIMD_reg2 at the top of FIG4 to obtain FIG4 . 4 below; SIMD128_ROL(SIMD_reg3, 64, R3), which means that a 128-bit 64-bit circular left shift operation is performed on the 256-bit SIMD_reg3 at the top of Figure 4 to obtain the 256-bit SIMD_reg3 at the bottom of Figure 4; SIMD128_ROL(SIMD_reg4, 96, R4), which means that a 128-bit 96-bit circular left shift operation is performed on the 256-bit SIMD_reg4 at the top of Figure 4 to obtain the 256-bit SIMD_reg4 at the bottom of Figure 4. Step 203: Based on four basic blocks and four 256-bit registers, a basic operation of performing a mixing operation on the rearranged blocks in the streaming symmetric encryption algorithm is completed. In an exemplary embodiment, the specific implementation of this step is as described in step 201, which will not be repeated here. It should be noted that after the rearrangement operation of step 202, in the related art, based on the 32-bit register, the corresponding form of the block in the fifth basic operation to the eighth basic operation in the streaming symmetric encryption algorithm is transformed into the corresponding form of the block in the first basic operation to the fourth basic operation. Therefore, step 203 can be like step 201, and one basic operation can be performed on a column consisting of four basic blocks to include the fifth basic operation to the eighth basic operation in the related art. In this way, the amount of calculation is reduced, the random number generation speed is improved, and the execution time of the ZKP encryption process is shortened. After step 203, the random number in the stream symmetric encryption algorithm, that is, the encryption result of the information to be encrypted, can be obtained. In an exemplary embodiment, the mixed operation on the blocks in step 201 and step 203 in the embodiment of the present application may include: A 256-bit single instruction multiple data SIMD addition instruction for implementing an addition operation on two 256-bit registers; a 256-bit SIMD exclusive OR for implementing an exclusive OR operation on two 256-bit registers, wherein one of the 256-bit registers represents a result of the addition operation; and a first SIMD circular left shift instruction for implementing a first circular left shift of N1 bits on the 256-bit SIMD register representing the result of the exclusive OR operation in 32-bit independent units. The random number generation method provided in the embodiment of the present application is based on a 256-bit register and cleverly rearranges the blocks during the random number generation process, which not only ensures the successful generation of random numbers, but also reduces the amount of computational complexity of mixed operations on blocks in the streaming symmetric encryption algorithm, thereby improving the random number generation speed and shortening the time required to execute the ZKP encryption process. In an exemplary embodiment, the number of encryption rounds can be preset according to the encryption requirements. That is, the round number threshold, so it can also include: Step 204: add one to the preset number of rounds, and return to step 201 until the number of rounds reaches the preset round number threshold; perform an addition operation on the result after iterative operation after the preset round number threshold and the information to be encrypted before being updated, and use the operation result as a random number. An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute any of the above-mentioned random number generation methods. Another computer device according to an embodiment of the present application includes a memory and a processor, wherein the memory stores the following instructions executable by the processor: for executing the steps of any of the above-mentioned random number generation methods. FIG5 is a schematic diagram of the composition structure of the random number generating device in the embodiment of the present application. As shown in FIG5 , the random number generating device at least includes: a control unit, a preprocessing unit, a 256-bit register stack, an iterative processing unit, and a tail processing unit; wherein, A preprocessing module is used to read data from the memory under the control of the control unit, and perform the following preprocessing on the read data and store it in a 256-bit register stack, wherein two copies of the preprocessing results are stored in the 256-bit register stack: 64 bytes of information to be encrypted are divided into 16 blocks, each block represents 4 bytes, and every 4 blocks are used as a basic block to obtain a first basic block, a second basic block, a third basic block and a fourth basic block; the four basic blocks are respectively stored in four 256-bit registers; The core processing unit is used to perform the following preset rounds of iterative operations under the control of the iterative processing module: read the information to be encrypted from the 256-bit register stack, and complete a basic operation of mixing blocks in the streaming symmetric encryption algorithm based on four basic blocks and four 256-bit registers; in units of blocks, cyclically shift the second basic block to the left by one block, cyclically shift the third basic block to the left by two blocks, and cyclically shift the fourth basic block to the left by three blocks, and update 16 blocks corresponding to the information to be encrypted in the 256-bit register stack; based on the updated four basic blocks and four 256-bit registers, complete a basic operation of mixing the rearranged blocks in the streaming symmetric encryption algorithm; The tail processing unit is used to perform an addition operation on the result after iterative operation of a preset number of rounds threshold and the information to be encrypted before being updated under the control of the control unit, and write the result as the random number to the memory. In the embodiment of the present application, during the calculation process, the core processing unit directly retrieves data from the 256-bit register file without accessing memory operations. In an exemplary embodiment, SIMD_reg0 to SIMD_reg7 in the 256-bit register file are all 256-bit registers, wherein SIMD_reg0 to SIMD_reg3 and SIMD_reg4 to SIMD_reg7 store the same data, that is, the preprocessed information to be encrypted will be stored in two copies in the 256-bit register file. Taking FIG3 as an example, SIMD_reg0 stores the first basic block, namely block0, block1, block2 and block3; SIMD_reg1 stores the second basic block, namely block4, block5, block6 and block7; SIMD_reg2 stores the third basic block, namely block8, block9, block10 and block11; SIMD_reg3 stores the fourth basic block, namely block12, block13, block14 and block15; SIMD_reg4 stores the first basic block, SIMD_reg5 stores the second basic block, SIMD_reg6 stores the third basic block, and SIMD_reg7 stores the fourth basic block. In an exemplary embodiment, the core processing unit may include: an iteration control module, a first processing module, a rearrangement module, and a second processing module; wherein, The first processing module is used to read the information to be encrypted from the 256-bit register file under the control of the iterative processing module, and complete a basic operation of mixing the blocks in the streaming symmetric encryption algorithm based on the basic blocks and the 256-bit registers; in one embodiment, the information to be encrypted read from the 256-bit register file is data read from SIMD_reg0 to SIMD_reg3 in the 256-bit register file; a rearrangement module, used for cyclically shifting the second basic block to the left by one block, cyclically shifting the third basic block to the left by two blocks, cyclically shifting the fourth basic block to the left by three blocks, and updating 16 blocks in the preprocessing module; The second processing module is used to complete a basic operation of performing a mixed operation on the rearranged blocks in the streaming symmetric encryption algorithm based on the updated basic blocks and the 256-bit register. In an exemplary embodiment, the control of the iterative processing module is used to: add one to the preset round number, and notify the first processing module to perform a basic operation until the round number reaches a preset round number threshold, and use the operation result as a random number. In an exemplary embodiment, the information to be encrypted before being updated and read by the tail processing unit is data read from SIMD_reg4 to SIMD_reg7 in the 256-bit register file. The random number generation device provided in the embodiment of the present application is based on a 256-bit register and cleverly rearranges the blocks during the random number generation process, which not only ensures the successful generation of random numbers, but also reduces the amount of computational complexity of mixed operations on blocks in the streaming symmetric encryption algorithm, thereby improving the random number generation speed and shortening the time required to execute the ZKP encryption process. In an exemplary embodiment, FIG6 shows a schematic diagram of a process embodiment of a basic operation in the first processing module. In FIG6, a represents a first basic block, b represents a second basic block, c represents a third basic block, and d represents a fourth basic block. As shown in FIG6, a mixed operation of a basic operation may include: block[a]=block[a]+block[b]; where + represents a 256-bit SIMD addition (SIMD256_ADD) instruction; block[d]=ROL(block[d]^block[a], 16), where ROL represents the first SIMD circular shift left (SIMD256_32_ROL) instruction, and ^ represents a 256-bit SIMD exclusive or (SIMD256_XOR) instruction; block[c]=block[c]+block

[0012] ; block[b]=ROL(block[b]^block[8], 12); block[a]=block[a]+block[b]; block[d]=ROL(block[d]^block[a], 8); block[c]=block[c]+block[d]; block[b]=ROL(block[b]^block[c], 7). In an exemplary embodiment, FIG7 shows a schematic diagram of an embodiment of the addition process of the tail processing module, in which a represents the original first basic block, b represents the original second basic block, c represents the original third basic block, and d represents the original fourth basic block; a′ represents the first basic block after the preset number of rounds of the core processing unit, b′ represents the second basic block after the preset number of rounds of the core processing unit, c′ represents the third basic block after the preset number of rounds of the core processing unit, and d′ represents the fourth basic block after the preset number of rounds of the core processing unit. As shown in FIG7, the result after the preset number of rounds of the threshold iteration operation is added to the original (i.e., before the update) information to be encrypted, and the result is used as a random number, such as the result first basic block, the result second basic block, the result third basic block, and the result fourth basic block in FIG7. Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of patent protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A random number generation method, comprising: Divide the 64-byte information to be encrypted into 16 blocks, each block represents 4 bytes, and use every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; the four basic blocks are respectively stored in four 256-bit registers; Based on four basic blocks and four 256-bit registers, a basic operation of mixing blocks in the streaming symmetric encryption algorithm is completed; Taking blocks as units, circularly shift the second basic block to the left by one block, circularly shift the third basic block to the left by two blocks, and circularly shift the fourth basic block to the left by three blocks; Based on four basic blocks and four 256-bit registers, a basic operation of mixing the rearranged blocks in the streaming symmetric encryption algorithm is completed.

2. The random number generation method according to claim 1, further comprising: The preset round number is increased by one, and the step of performing a basic operation of a mixed operation on the block is returned until the round number reaches a preset round number threshold; An addition operation is performed on the result after iterative operation for a preset number of rounds and the information to be encrypted before being updated, and the operation result is used as a random number.

3. The random number generation method according to claim 1 or 2, wherein: The mixed operation includes: a 256-bit single instruction multiple data SIMD addition instruction, used to implement an addition operation on two 256-bit registers; a 256-bit SIMD exclusive OR, used to implement an exclusive OR operation on two 256-bit registers, wherein one of the 256-bit registers represents a result of the addition operation; and a first SIMD circular left shift instruction, used to implement a first circular left shift of N1 bits on the 256-bit SIMD register representing the result of the exclusive OR operation with 32 bits as independent units.

4. The random number generation method according to claim 1 or 2, wherein: The first basic block includes block0, block1, block2 and block3 among the 16 blocks; the second basic block includes block4, block5, block6 and block7 among the 16 blocks; the third basic block includes block8, block9, block10 and block11 among the 16 blocks; the fourth basic block includes block12, block13, block14 and block15 among the 16 blocks; The cyclic left shifting of the second basic block by one block, the cyclic left shifting of the third basic block by two blocks, and the cyclic left shifting of the fourth basic block by three blocks include: According to the result of the basic operation of the mixed operation on the blocks, block5 of the second basic block is circularly shifted left to block4, block10 of the third basic block is circularly shifted left to block8, and block15 of the fourth basic block is circularly shifted left to block12.

5. The random number generation method according to claim 4, wherein: The circular left shift is a second SIMD circular left shift; The second SIMD circular left shift is implemented by a SIMD128_ROL instruction; The format of the SIMD128_ROL instruction includes: SIMD128_ROL (S, N2, R), which is used to implement a 128-bit N2-bit circular left shift of S to obtain R; wherein S represents a 256-bit SIMD register that performs a circular left shift operation, N2 represents the number of bits of the circular left shift, and N2 is an integer multiple of 32.

6. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the random number generation method according to any one of claims 1 to 5.

7. A computer device comprising a memory and a processor, wherein: The memory stores the following instructions executable by the processor: used to execute the steps of the random number generation method described in any one of claims 1 to 5.

8. A random number generating device, comprising: A control unit, a preprocessing unit, a 256-bit register file, an iterative processing unit, and a tail processing unit; wherein, The preprocessing module is used to read data from the memory under the control of the control unit, and perform the following preprocessing on the read data and store it in a 256-bit register stack, wherein two copies of the preprocessing results are stored in the 256-bit register stack: 64 bytes of information to be encrypted are divided into 16 blocks, each block represents 4 bytes, and every 4 blocks are used as a basic block to obtain a first basic block, a second basic block, a third basic block and a fourth basic block; The core processing unit is used to perform the following preset rounds of iterative operations: read the information to be encrypted from the 256-bit register stack, and based on the basic blocks and the 256-bit register, complete a basic operation of mixing blocks in the streaming symmetric encryption algorithm; based on the block, cyclically shift the second basic block to the left by one block, cyclically shift the third basic block to the left by two blocks, cyclically shift the fourth basic block to the left by three blocks, and update the 16 blocks corresponding to the information to be encrypted in the 256-bit register stack; based on the updated basic blocks Blocks and 256-bit registers complete a basic operation of mixing the rearranged blocks in the streaming symmetric encryption algorithm; The tail processing unit is used to perform an addition operation on the result after iterative operation of a preset number of rounds threshold and the information to be encrypted before being updated under the control of the control unit, and write the result as the random number to the memory.

9. The random number generating device according to claim 8, wherein: The 256-bit register file includes eight 256-bit registers SIMD_reg0 to SIMD_reg7; wherein, SIMD_reg0 is used to store the first basic block, SIMD_reg1 is used to store the second basic block, SIMD_reg2 is used to store the third basic block, and SIMD_reg3 is used to store the fourth basic block; SIMD_reg4 is used to store the first basic block, SIMD_reg5 is used to store the second basic block, SIMD_reg6 is used to store the third basic block, and SIMD_reg7 is used to store the fourth basic block.

10. The random number generating device according to claim 8, wherein: The information to be encrypted before being updated and read in the tail processing unit is data read from SIMD_reg4 to SIMD_reg7 in the 256-bit register file.

11. The random number generating device according to claim 8, wherein: The core processing unit may include: an iteration control module, a first processing module, a rearrangement module, and a second processing module; wherein: The first processing module is used for, under the control of the iterative processing module, reading the information to be encrypted from SIMD_reg0 to SIMD_reg3 in the 256-bit register file, based on the basic block and the 256-bit register, completing a basic operation of mixing operations on the blocks in the streaming symmetric encryption algorithm; in one embodiment, reading the information to be encrypted from the 256-bit register file is from; a rearrangement module, used for cyclically shifting the second basic block to the left by one block, cyclically shifting the third basic block to the left by two blocks, cyclically shifting the fourth basic block to the left by three blocks, and updating 16 blocks in the preprocessing module; The second processing module is used to complete a basic operation of performing a mixed operation on the rearranged blocks in the streaming symmetric encryption algorithm based on the updated basic blocks and the 256-bit register.

12. The random number generating device according to claim 10, wherein: The control of the iterative processing module is used to: increase the preset number of rounds by one, and notify the first processing module to perform a basic operation until the number of rounds reaches a preset round number threshold, and use the operation result as a random number.

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