Back contact cell capable of reducing back parasitic absorption and manufacturing method therefor

Abstract

The present disclosure belongs to the technical field of back contact cells, and specifically relates to a back contact cell capable of reducing back parasitic absorption and a manufacturing method therefor. The back contact cell comprises a silicon wafer having a front surface and a back surface, and a first semiconductor layer provided on the back surface of the silicon wafer, the back surface of the silicon wafer being an inverted pyramid textured structure; the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer; the inverted pyramid textured structure has alternate flat surfaces and pits sunken in the silicon wafer; the first doped polycrystalline silicon layer comprises a polycrystalline inner layer, a polycrystalline silicon middle layer and a polycrystalline silicon outer layer, the polycrystalline silicon inner layer, the polycrystalline silicon middle layer and the polycrystalline silicon outer layer all being doped with phosphorus, and carbon and / or oxygen; in the polycrystalline silicon inner layer, the polycrystalline silicon middle layer and the polycrystalline silicon outer layer, the amount of doped oxygen gradually decreasing, and the amount of doped carbon and the amount of doped phosphorus gradually increasing. The present disclosure can reduce the parasitic absorption of the back surface while ensuring passivation performance and conductivity, thereby helping to increase short-circuit current density and cell conversion efficiency.

Description

A back contact battery with reduced back parasitic absorption and a preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application No. 2023110350087 filed with the Patent Office of China on August 17, 2023, entitled “A back-contact battery with reduced back parasitic absorption and its preparation method,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery capable of reducing back-side parasitic absorption and a preparation method thereof. Background Art

[0004] Currently, the first and second semiconductor layers in back-contact cells (or back-contact solar cells) are both located on the back side of the cell silicon wafer. For example, CN115207137B provides a combined passivated back-contact cell comprising an N-type doped silicon substrate having a light-receiving surface and a back side, a first semiconductor layer and a second semiconductor layer disposed on the back side, wherein the second semiconductor layer comprises an intrinsic silicon layer and a doped silicon layer disposed sequentially in a direction perpendicular to the back side and outward, and the first semiconductor layer comprises a tunneling oxide layer and a doped silicon crystal layer disposed sequentially in a direction perpendicular to the back side and outward.

[0005] However, the first semiconductor layer in the back-contact battery is a tunneling oxide layer and a first doped polysilicon layer. The first doped polysilicon layer has obvious parasitic absorption of the long-wave band of the incident light. If the first doped polysilicon layer is too thick, the parasitic absorption is serious and the short-circuit current density will drop significantly; if the polycrystalline layer is too thin, the passivation of the battery and the conductivity of the film layer will be greatly affected, thereby affecting the overall conversion efficiency.

[0006] Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the defect in the prior art that the first doped polysilicon layer of the first semiconductor layer in the back-contact battery cannot take into account parasitic absorption, passivation and conductivity of the film layer, and to provide a back-contact battery that reduces back-side parasitic absorption and a preparation method thereof. The back-contact battery can reduce the parasitic absorption on the back while ensuring passivation performance and conductivity, which is beneficial to improving the short-circuit current density and battery conversion efficiency.

[0008] In order to achieve the above-mentioned objectives, in a first aspect, the present disclosure provides a back-contact battery for reducing back-side parasitic absorption, comprising a silicon wafer having a front side and a back side, a first semiconductor layer arranged on the back side of the silicon wafer, the back side of the silicon wafer being an inverted pyramid velvet structure, the first semiconductor layer comprising a tunneling oxide layer and a first doped polysilicon layer, the inverted pyramid velvet structure having alternating planes and pits recessed into the silicon wafer, and the first doped polysilicon layer comprising a polysilicon inner layer, a polysilicon middle layer and a polysilicon outer layer, the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer being doped with phosphorus and also with carbon and / or oxygen, the oxygen doping amount in the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer gradually decreasing, and the carbon doping amount and the phosphorus doping amount gradually increasing.

[0009] In some optional embodiments of the present disclosure, the plane area of ​​the inverted pyramid velvet structure accounts for 40%-70%, or optionally 40%-60%, of the entire back area.

[0010] In some optional embodiments of the present disclosure, the depression depth of the pit is 0.5-1.5 nm, and the opening width of the pit is 0.5-3 nm, and optionally 1-3 nm.

[0011] The ratio of the recessed depth of the pit, the thickness of the tunneling oxide layer and the total thickness of the first doped polysilicon layer disclosed in the present invention is 1:(0.6-4):(100-600).

[0012] In some optional embodiments of the present disclosure, the thickness of the tunnel oxide layer is 0.5-2.5 nm, and the total thickness of the first doped polysilicon layer is 50-300 nm.

[0013] In some optional embodiments of the present disclosure, the thickness ratio of the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer is 1:(1-3.3):(1.4-5), or optionally 1:(1-3):(2-4).

[0014] In some optional embodiments of the present disclosure, the thickness ratio of the tunnel oxide layer, the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer is 1:(20-55):(40-155):(60-160), optionally 1:(30-50):(50-130):(60-150), and more optionally 1:(30-50):(50-100):(60-90).

[0015] In some optional embodiments of the present disclosure, the absolute values ​​of the differences in effective doping concentrations of corresponding doping elements between the inner polysilicon layer and the middle polysilicon layer are recorded as tp, tO, and tC, respectively, and the absolute values ​​of the differences in effective doping concentrations of corresponding doping elements between the middle polysilicon layer and the outer polysilicon layer are recorded as Tp, TO, and TC, respectively, which satisfy: Tp / tp=10-30, optionally 10-25, TO / tO=1 / 0.4-1 / 20, optionally 1 / 25-1 / 5, optionally 1 / 20-1 / 5, TC / tC=0.7-20, optionally 5-20.

[0016] More optionally, the inner layer of the polysilicon is doped with phosphorus and also doped with oxygen, the middle layer of the polysilicon is doped with phosphorus and also doped with oxygen and carbon, the outer layer of the polysilicon is doped with phosphorus and also doped with carbon, and the absolute value tO of the difference in oxygen doping concentration between the inner layer of the polysilicon and the middle layer of the polysilicon is 1×1019-5×1019cm-3, and the absolute value TC of the difference in carbon doping concentration between the middle layer of the polysilicon and the outer layer of the polysilicon is 1×1019-9×1019cm-3.

[0017] In some optional embodiments of the present disclosure, the bandgap width of the polysilicon inner layer is 1.45-1.55, the bandgap width of the polysilicon middle layer is 1.56-1.65, and the bandgap width of the polysilicon outer layer is 1.65-1.75.

[0018] In some optional embodiments of the present disclosure, the back contact battery further comprises:

[0019] a semiconductor mask layer disposed on a surface of the first semiconductor layer, wherein the first semiconductor layer and the semiconductor mask layer thereon are arranged as a whole in a back-parallel direction at intervals, wherein the intervals are second semiconductor opening regions;

[0020] a second semiconductor layer, which is disposed on a surface of the semiconductor mask layer and covers a surface of the second semiconductor opening region, and a first semiconductor opening region exposing the first semiconductor layer is formed on a portion of the second semiconductor layer located between adjacent second semiconductor opening regions; and the second semiconductor layer comprises an intrinsic silicon layer and a second doped silicon layer sequentially disposed in a direction perpendicular to the back surface and outward, wherein the second doped silicon layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer;

[0021] a conductive film layer disposed on a surface of the second semiconductor layer and a surface of the first semiconductor layer exposed at the first semiconductor opening region, and an isolation trench exposing the second semiconductor layer is opened on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region;

[0022] Gate line electrodes are respectively arranged on surfaces of the first semiconductor opening region and the second semiconductor opening region;

[0023] a front passivation layer, which is disposed on the front side of the silicon wafer;

[0024] The anti-reflection layer is arranged on the surface of the front passivation layer.

[0025] In a second aspect, the present disclosure provides a method for preparing a back-contact cell with reduced back-side parasitic absorption, wherein the back-contact cell is the back-contact cell with reduced back-side parasitic absorption described in the first aspect, and the preparation method comprises:

[0026] S100, provides double-sided polished silicon wafers;

[0027] S101, performing inverted pyramid texturing on the back side of the silicon wafer, so that a partially flat surface is retained on the back side and a pit is formed that is sunken into the silicon wafer;

[0028] S102. A tunneling oxide layer and a first doped polysilicon layer are sequentially deposited on the back side of the silicon wafer obtained in S101 to form a first semiconductor layer; wherein, the process of depositing the first doped polysilicon layer includes: firstly performing polycrystalline growth of the corresponding layers, and then performing phosphorus diffusion; and introducing a gas source of the required doping element during the polycrystalline growth.

[0029] In some optional embodiments of the present disclosure, the inverted pyramid texturing process in S101 includes: first etching a groove on the back of the silicon wafer with a laser, and then etching the inverted pyramid texture surface with an alkaline solution or an acidic solution.

[0030] In some optional embodiments of the present disclosure, in S102, the gas introduced during the polycrystalline growth includes silane and a doping element gas source selected from nitrous oxide and / or methane. When nitrous oxide is introduced, the volume ratio of nitrous oxide to the total introduced gas is 2%-15%, and when methane is introduced, the volume ratio of methane to the total introduced gas is 3%-20%.

[0031] In some optional embodiments of the present disclosure, in S102, the process of depositing the first doped polysilicon layer specifically includes:

[0032] During the polycrystalline growth process of the inner layer of polysilicon, silane and nitrous oxide are introduced, with the volume ratio of nitrous oxide to the total introduced gas being 5%-15%;

[0033] During the polycrystalline growth process of the polysilicon middle layer, silane, nitrous oxide and methane are introduced, wherein the volume ratio of nitrous oxide and methane to the total introduced gas is 2%-8% and 3%-10% respectively;

[0034] During the polycrystalline growth process of the outer layer of polysilicon, silane and methane are introduced, with the volume ratio of methane to the total introduced gas being 10%-20%;

[0035] Phosphorus diffusion is carried out after the polycrystalline growth is completed.

[0036] In some optional embodiments of the present disclosure, the preparation method further comprises:

[0037] S103, depositing a semiconductor mask layer on the first semiconductor layer obtained in S102;

[0038] S104, forming a second semiconductor opening region on the back surface obtained in S103;

[0039] S105, depositing a second semiconductor layer on the back surface obtained in S104;

[0040] S106, pre-treating the front surface of the silicon wafer, and then depositing a front passivation layer and an anti-reflection layer;

[0041] S107, removing the second semiconductor layer on the first semiconductor layer on the back side to expose the first semiconductor layer, thereby forming a first semiconductor opening region;

[0042] S108, depositing a conductive film layer on the back surface obtained in S107;

[0043] S109, forming an isolation trench between the first semiconductor opening region and the second semiconductor opening region;

[0044] S110 , forming gate line electrodes in the first semiconductor opening region and the second semiconductor opening region respectively. Beneficial effects:

[0045] The present disclosure adopts the above technical solution, especially adopts a specific inverted pyramid velvet structure and a first semiconductor layer with a specific structure and a specific layer thickness ratio on the back side, which can reduce the parasitic absorption on the back side while ensuring passivation performance and conductivity, thereby improving the short-circuit current density and battery conversion efficiency. Among them, compared with the conventional polishing or positive pyramid structure on the back side of the silicon wafer, the back side of the present disclosure adopts an inverted pyramid velvet structure with a plane and pits, which retains the flatness of part of the back side, is conducive to the growth and passivation of the tunneling oxide layer and the first doped polysilicon layer, and has an inward-recessed velvet structure pit, which is conducive to the internal reflection of long-wavelength incident light (i.e., the long-wavelength light penetrating the battery from the front side is reflected on the back side and then absorbed), thereby improving the current density; in combination with the first doped polysilicon layer with a specific layer and its doping element distribution on the back side, the polysilicon has good conductivity, and carbon and oxygen doping can also meet the conductivity requirements. The inverted pyramid velvet structure matches the specific first semiconductor layer, which can meet the passivation performance and conductivity while maintaining a wide band gap and sufficient corrosion resistance. Incorporating appropriately distributed doping elements during polycrystalline growth promotes reflection of long-wavelength incident light without absorbing it, broadening the optical bandgap (Eg) and reducing parasitic absorption. This specific doping pattern ensures conductivity while minimizing backside parasitic absorption, thereby improving short-circuit current density and conversion efficiency. Under the same conditions, doping with phosphorus and carbon without oxygen results in poor passivation and lower performance, such as the opening voltage. Increasing the oxygen doping level results in poor corrosion resistance and subsequent damage after solution treatment. Under the same conditions, doping with phosphorus and oxygen without carbon results in poor corrosion resistance and subsequent damage after solution treatment. Decreasing the carbon doping level results in significant light absorption due to a narrow bandgap. Furthermore, doping with phosphorus without oxygen and carbon, combined with an inverted pyramid velvet structure, results in poor reflection due to increased absorption of long-wavelength light penetrating from the front.

[0046] Furthermore, the present disclosure adopts an appropriate ratio of the pit depth, the tunnel oxide layer thickness, and the total thickness of the first doped polysilicon layer, which allows the tunnel oxide layer to fully cover the pit and the flat silicon wafer surface, while matching the appropriate polysilicon thickness so that carriers can tunnel out under the action of a sufficient electric field, thereby ensuring passivation performance and conductivity while reducing parasitic absorption on the back side, which is beneficial to improving short-circuit current density and battery conversion efficiency. Under the same conditions, if the ratio of the pit depth to the tunnel oxide layer thickness is not appropriate, such as if it is too large, the tunnel oxide layer will not be able to fully cover the pit surface, resulting in poor passivation performance; if it is too small, the back side anti-reflection effect will be reduced due to poor velvet effect; if the ratio of the pit depth to the first doped polysilicon layer is not appropriate, such as if it is too large, the passivation and conductivity performance will be damaged due to poor uniformity of the polycrystalline film layer; if it is too small, the anti-reflection effect will not be sufficient due to poor absorption of long-wavelength light.

[0047] Optionally, in the thickness ratio scheme of the optional tunneling oxide layer, polysilicon inner layer, polysilicon middle layer and polysilicon outer layer disclosed in the present invention, the film thickness ratio of the tunneling oxide layer and each layer in the first doped polysilicon layer is appropriate, and combined with the inverted pyramid velvet structure on the back side, the passivation performance, conductivity and optical properties of the film layer are taken into account, ensuring that the opening voltage, short-circuit current and fill factor are at the optimal level. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0049] FIG1 is a schematic structural diagram of an S100 silicon wafer according to Example 1 of the present disclosure;

[0050] FIG2 is a structural schematic diagram of an inverted pyramid texturing structure formed on the back surface in S101 of Example 1 of the present disclosure;

[0051] FIG3 is a schematic structural diagram of back-side deposition of a first semiconductor layer in S102 of Example 1 of the present disclosure;

[0052] FIG4 is a schematic structural diagram of back-side deposition of a semiconductor mask layer in S103 of Example 1 of the present disclosure;

[0053] FIG5 is a schematic structural diagram of forming a second semiconductor opening region on the back side of S104 in Example 1 of the present disclosure;

[0054] FIG6 is a schematic structural diagram of depositing a second semiconductor layer on the back side in S105 of Example 1 of the present disclosure;

[0055] FIG7 is a schematic structural diagram of a front-side deposited passivation layer and an anti-reflection layer in S106 of Example 1 of the present disclosure;

[0056] FIG8 is a schematic structural diagram of forming a first semiconductor opening region on the back side in S107 of Example 1 of the present disclosure;

[0057] FIG9 is a schematic structural diagram of a conductive film layer deposited on the back side in S108 of Example 1 of the present disclosure;

[0058] FIG10 is a schematic structural diagram of an isolation trench formed on the back side of S109 in Example 1 of the present disclosure;

[0059] FIG11 is a schematic structural diagram of the back-side printed gate line electrode in S110 of Example 1 of the present disclosure.

[0060] Explanation of the accompanying symbols: 1. Silicon wafer, 2. Tunneling oxide layer, 3. First doped polysilicon layer, 3.1. Inner oxygen-doped N-type polycrystalline layer, 3.2. Middle oxygen-doped carbon N-type polycrystalline layer, 3.3. Outer carbon-doped N-type polycrystalline layer, 4. Semiconductor mask layer, 5.1. Second semiconductor passivation layer, 5.2. Second semiconductor doping layer, 6.1. Passivation layer, 6.2. Anti-reflection layer, 7. Conductive film layer, 8. Gate line electrode. DETAILED DESCRIPTION

[0061] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0062] In a first aspect, the present disclosure provides a back-contact cell for reducing backside parasitic absorption, comprising a silicon wafer having a front side and a back side, and a first semiconductor layer disposed on the back side of the silicon wafer. The back side of the silicon wafer has an inverted pyramid velvet structure, the first semiconductor layer comprising a tunneling oxide layer and a first doped polysilicon layer, and the inverted pyramid velvet structure having alternating flat surfaces and pits recessed into the silicon wafer. It should be noted that the flat surfaces and pits form an inverted pyramid velvet structure on the back side, with velvet absent on the flat surfaces but present in the pits.

[0063] The first doped polysilicon layer disclosed in the present invention includes a polysilicon inner layer, a polysilicon middle layer and a polysilicon outer layer, wherein the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer are all doped with phosphorus and also doped with carbon and / or oxygen, and the oxygen doping amount in the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer gradually decreases, and the carbon doping amount and the phosphorus doping amount gradually increase.

[0064] The present disclosure utilizes a tunneling oxide layer in conjunction with a first doped polysilicon layer. The first doped polysilicon layer is a polysilicon layer with good electrical conductivity. Carbon and oxygen doping under appropriate conditions not only satisfies electrical conductivity requirements, but also matches the inverted pyramid velvet structure of the specific first semiconductor layer. Furthermore, the inverted pyramid velvet structure matches the specific first semiconductor layer, while maintaining a wide bandgap and sufficient corrosion resistance while meeting passivation requirements. However, if the tunneling oxide layer and the first doped polysilicon layer of the first semiconductor layer are replaced with conventional intrinsic amorphous silicon or microcrystalline silicon and doped amorphous silicon, due to the amorphous silicon film's non-crystalline nature, oxygen or carbon doping cannot achieve both electrical conductivity and passivation performance. Therefore, the amorphous film layer is generally not doped with carbon or oxygen.

[0065] The ratio of the recessed depth of the pit, the thickness of the tunnel oxide layer, and the total thickness of the first doped polysilicon layer disclosed in the present invention is 1:(0.6-4):(100-600), which is conducive to forming a good passivation structure on the morphology of the inverted pyramid velvet structure and ensuring good conductivity, which is conducive to improving the short-circuit current density and battery conversion efficiency.

[0066] In some optional embodiments of the present disclosure, the flat surface area of ​​the inverted pyramid velvet structure accounts for 40%-70%, or optionally 40%-60%, of the entire back surface area. In this optional solution, the flat surface area accounts for an appropriate proportion, which can achieve both anti-reflection effect and passivation effect, and is more conducive to maintaining open circuit voltage and improving short-circuit current density.

[0067] In the present disclosure, the ranges of the recess depth of the pit, the thickness of the tunnel oxide layer and the first doped polysilicon layer can be selected by those skilled in the art under the condition that the above ratios are met.

[0068] In some optional embodiments of the present disclosure, the recessed depth of the pit is 0.5-1.5 nm.

[0069] Optionally, the opening width of the pit is 0.5-3 nm, or 1-3 nm. In this option, the opening width is appropriate, which can ensure the passivation effect and is more conducive to improving the minority carrier lifetime and open circuit voltage of the battery.

[0070] In some optional embodiments of the present disclosure, the thickness of the tunnel oxide layer is 0.5-2.5 nm, and the total thickness of the first doped polysilicon layer is 50-300 nm.

[0071] In some optional embodiments of the present disclosure, the thickness ratio of the polysilicon inner layer, polysilicon middle layer, and polysilicon outer layer is 1:(1-3.3):(1.4-5), or optionally 1:(1-3):(2-4). In this optional solution, the thickness ratio of the polysilicon inner layer, polysilicon middle layer, and polysilicon outer layer is appropriate, which can optimally reduce parasitic absorption and provide sufficient corrosion resistance, thereby further promoting battery efficiency.

[0072] In some optional embodiments of the present disclosure, the thickness ratio of the tunneling oxide layer, the inner polysilicon layer, the middle polysilicon layer, and the outer polysilicon layer is 1:(20-55):(40-155):(60-160), optionally 1:(30-50):(50-130):(60-150), and more preferably 1:(30-50):(50-100):(60-90). In this optional solution, the thickness ratio of the tunneling oxide layer to each layer in the first doped polysilicon layer is appropriate, and combined with the inverted pyramid velvet structure on the back side, it takes into account the passivation performance, conductivity, and optical properties of the film layer, ensuring that the opening voltage, short-circuit current, and fill factor are all at optimal levels.

[0073] In the polysilicon inner layer, polysilicon middle layer and polysilicon outer layer disclosed in the present invention, the corresponding doping element concentration of the polysilicon inner layer can be 0 or not when the corresponding doping elements increase; the corresponding doping element concentration of the polysilicon outer layer can be 0 or not when the corresponding doping elements decrease.

[0074] In some optional embodiments of the present disclosure, the absolute values ​​of the differences in effective doping concentrations of corresponding doping elements between the inner polysilicon layer and the middle polysilicon layer are recorded as tp, tO, and tC, respectively, and the absolute values ​​of the differences in effective doping concentrations of corresponding doping elements between the middle polysilicon layer and the outer polysilicon layer are recorded as Tp, TO, and TC, respectively, which satisfy: Tp / tp=10-30, TO / tO=1 / 0.4-1 / 20, TC / tC=0.7-20.

[0075] Optionally, Tp / tp = 10-30, or 10-25, TO / tO = 1 / 25-1 / 5, or 1 / 20-1 / 5, and TC / tC = 5-20. This option provides an appropriate doping element concentration difference ratio, achieving an optimal bandgap setting and good corrosion resistance, further reducing parasitic absorption and improving electrical performance.

[0076] The effective doping concentration ranges of oxygen, carbon, and phosphorus in the polysilicon inner layer, polysilicon middle layer, and polysilicon outer layer disclosed herein may be within the range of the prior art, as long as the above-mentioned relative doping concentration conditions are met; for example, the effective doping concentration when doping with oxygen may be 1018cm-3-1020cm-3, the effective doping concentration when doping with carbon may be 1018cm-3-1020cm-3, and the effective doping concentration when doping with phosphorus may be 1018cm-3-1021cm-3.

[0077] More optionally, the inner polysilicon layer is doped with phosphorus and oxygen, the middle polysilicon layer is doped with phosphorus and oxygen and carbon, and the outer polysilicon layer is doped with phosphorus and carbon. More optionally, the absolute value of the difference in oxygen concentration between the inner and middle polysilicon layers, tO, is between 1×10⁻¹⁹ and 5×10⁻¹⁹ cm⁻³, and the absolute value of the difference in carbon concentration between the middle and outer polysilicon layers, TC, is between 1×10⁻¹⁹ and 9×10⁻¹⁹ cm⁻³. In this alternative, the optimal dopant element concentration difference ratio can achieve an optimal bandgap setting and good corrosion resistance, further reducing parasitic absorption and improving electrical performance.

[0078] More optionally, the absolute value tp of the difference in phosphorus doping concentration between the polysilicon inner layer and the polysilicon middle layer and the absolute value Tp of the difference in phosphorus doping concentration between the polysilicon middle layer and the polysilicon outer layer satisfy: Tp / tp=15-25.

[0079] The bandgap width of the polysilicon inner layer described in the present disclosure is 1.45-1.55, the bandgap width of the polysilicon middle layer is 1.56-1.65, and the bandgap width of the polysilicon outer layer is 1.65-1.75. By controlling the phosphorus, carbon, and oxygen doping levels, the present disclosure widens the optical bandgap Eg within the above range. The wide bandgap reduces parasitic absorption in the film layer, which helps reduce parasitic absorption and improve short-circuit current.

[0080] In some optional embodiments of the present disclosure, the back-contact cell further includes a semiconductor mask layer disposed on the surface of the first semiconductor layer. The first semiconductor layer and the semiconductor mask layer thereon are arranged as a whole in a direction parallel to the back surface, with the intervals forming second semiconductor opening regions. It will be understood that the silicon wafer is exposed within the second semiconductor opening region to accommodate the layer structure including the second semiconductor layer. The opening width of the second semiconductor opening region is Wa, which can be 300-700 μm.

[0081] The type and thickness of the semiconductor mask layer described in the present disclosure can be within the scope of the existing technology, such as the early patents of the applicant of the present disclosure. For example, the semiconductor mask layer can be at least one of silicon nitride, silicon oxynitride, silicon carbide and organic protective ink, the purpose of which is to protect the first semiconductor layer from corrosion in strong acid and alkali solutions.

[0082] In some optional embodiments of the present disclosure, the back-contact cell further includes a second semiconductor layer disposed on a surface of the semiconductor mask layer and covering surfaces of the second semiconductor opening regions, with first semiconductor opening regions exposing the first semiconductor layer being defined in portions of the second semiconductor layer located between adjacent second semiconductor opening regions. The width Wb of the first semiconductor opening regions can, for example, be 100-300 μm.

[0083] More optionally, the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer sequentially arranged in a direction perpendicular to the back surface and outward. The intrinsic silicon layer may be, for example, an intrinsic amorphous silicon layer or a microcrystalline silicon layer.

[0084] More optionally, the second doped silicon layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer.

[0085] In the above optional scheme, the present disclosure may optionally adopt a combined passivation structure of an intrinsic silicon layer, a second doped silicon layer, and a first semiconductor layer, which is matched with a specific inverted pyramid velvet structure and a specific first doped polysilicon layer. The polysilicon layer used has good conductivity, and carbon doping and oxygen doping can also meet its conductivity requirements. The inverted pyramid matches the first semiconductor layer, which can meet the passivation performance while maintaining a wide band gap and sufficient corrosion resistance, which is more conducive to reducing parasitic absorption and improving electrical performance. Under the same conditions, if the intrinsic silicon layer and the second doped silicon layer in the second semiconductor layer of the present disclosure are replaced with a tunneling oxide layer and P-type polysilicon, then the film formation temperature is higher than that of the first doped polysilicon layer, which can easily lead to damage to the performance of the first doped polysilicon layer.

[0086] The thickness of the second semiconductor layer and the doping concentration of the second doped silicon layer in the present disclosure can both adopt the range of the prior art, such as the range in any earlier patent of the applicant of the present disclosure. Optionally, the thickness of the intrinsic silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 5-20 nm, and the effective doping concentration is 1×1019 cm-3-1×1021 cm-3.

[0087] In some optional embodiments of the present disclosure, the back-contact cell further includes a conductive film layer disposed on a surface of the second semiconductor layer and on a surface of the first semiconductor layer exposed at the first semiconductor opening region, with an isolation trench provided in the conductive film layer between the first semiconductor opening region and the second semiconductor opening region, exposing the second semiconductor layer. The isolation trench may have a width Wg of, for example, 50-200 μm and is primarily used to isolate the two semiconductor layers and reduce the risk of short circuits or leakage.

[0088] The conductive film layer may be a transparent conductive film or a composite film layer composed of a transparent conductive film and a metal conductive film. The transparent conductive film may be indium oxide doped with zinc, tin, tungsten, titanium, or silicon, or may be zinc oxide doped with aluminum, boron, or gallium. The metal conductive film may be at least one of aluminum, copper, silver, a nickel alloy, and a titanium alloy. Optionally, the conductive film layer may be a composite film layer of tin-doped indium oxide, copper, or a nickel-copper alloy, and the sheet resistance may be less than 0.2Ω / □.

[0089] In some optional embodiments of the present disclosure, the back-contact battery further includes: a gate line electrode, which is respectively disposed on the surfaces of the first semiconductor opening region and the second semiconductor opening region.

[0090] In some optional embodiments of the present disclosure, the back-contact cell further includes a front passivation layer disposed on the front surface of the silicon wafer. The front passivation layer may be, for example, a single amorphous silicon passivation layer, or a combination of an amorphous silicon passivation layer and an amorphous silicon doped layer or a microcrystalline doped layer. Those skilled in the art may select the preferred embodiment based on their needs.

[0091] In some optional embodiments of the present disclosure, the back-contact cell further comprises an anti-reflection layer disposed on the surface of the front passivation layer. The anti-reflection layer may be a single layer or a combination of multiple layers, and those skilled in the art may select the desired anti-reflection layer.

[0092] In a second aspect, the present disclosure provides a method for preparing a back-contact cell with reduced back-side parasitic absorption, wherein the back-contact cell is the back-contact cell with reduced back-side parasitic absorption described in the first aspect, and the preparation method comprises:

[0093] S100, provides double-sided polished silicon wafers;

[0094] S101, performing inverted pyramid texturing on the back side of the silicon wafer, so that a partially flat surface is retained on the back side and a pit is formed that is sunken into the silicon wafer;

[0095] S102. A tunneling oxide layer and a first doped polysilicon layer are sequentially deposited on the back side of the silicon wafer obtained in S101 to form a first semiconductor layer; wherein, the process of depositing the first doped polysilicon layer includes: firstly performing polycrystalline growth of the corresponding layers, and then performing phosphorus diffusion; and introducing a gas source of the required doping element during the polycrystalline growth.

[0096] The silicon wafer in S100 of the present disclosure may be a single crystal silicon wafer or a single cast silicon wafer, and may be a single crystal silicon wafer.

[0097] In some optional embodiments of the present disclosure, the inverted pyramid texturing process described in S101 includes: first, using a laser to etch grooves on the back side of the silicon wafer, and then etching the inverted pyramid texture surface with an alkaline solution or an acidic solution. The planar surface area is inversely proportional to the laser etching density; the greater the etching density, the larger the groove area and the smaller the planar surface area.

[0098] Those skilled in the art can control the plane area, pit depth, and opening width of the inverted pyramid velvet structure by adjusting the groove depth, the concentration of the alkaline solution or acidic solution, and the etching time. Optionally, the inverted pyramid velvet making conditions include: the groove depth is controlled to be 0.5-1.5nm, the mass concentration of the alkaline solution is 5%-30%, the mass concentration of the acidic solution is 3%-25%, and the etching time is 5-30 minutes.

[0099] The alkaline solution may be, for example, an aqueous solution of at least one of potassium hydroxide, sodium hydroxide, or a mixed solution of potassium hydroxide and sodium hydroxide. The acidic solution may be, for example, an aqueous solution of at least one of nitric acid, hydrofluoric acid, or a mixed solution of nitric acid and hydrofluoric acid.

[0100] More optionally, the present disclosure uses an alkaline solution for etching.

[0101] Optionally, a texturing additive may be added to the alkaline solution or the acidic solution. The texturing additive may be, for example, at least one of potassium gluconate, sodium lactate, propylene glycol, sodium silicate, and sodium carbonate. The mass concentration of the texturing additive may be 0.5%-5%.

[0102] In the present disclosure, the oxygen-doping gas source can be an oxygen-containing gas, such as nitrous oxide; the oxygen-containing gas can be doped at a volume ratio of 0-20%. The carbon-doping gas source can be a carbon-containing gas known in the art, such as methane; the carbon-containing gas can be doped at a volume ratio of 0-25%. In some optional embodiments of the present disclosure, in S102, the gas introduced during the polycrystal growth comprises silane and a doping element source selected from nitrous oxide and / or methane. When nitrous oxide is introduced, the volume ratio of nitrous oxide to the total introduced gas is 2%-15%, and when methane is introduced, the volume ratio of methane to the total introduced gas is 3%-20%. In the present disclosure, the gas source when the doping element is carbon is methane, and the gas source when the doping element is oxygen is nitrous oxide. Those skilled in the art can increase the doping concentration by controlling the ratio of the doping element source gas and control the thickness of the corresponding layer by controlling the doping time of the corresponding polycrystal.

[0103] In the present disclosure, the flow rate of the doping element source increases or decreases with each layer. When increasing, the corresponding doping element concentration of the inner layer of the polysilicon may be 0 or non-0; when decreasing, the corresponding doping element concentration of the outer layer of the polysilicon may be 0 or non-0.

[0104] In some optional embodiments of the present disclosure, in S102, the process of depositing the first doped polysilicon layer specifically includes:

[0105] During the polycrystalline growth process of the inner layer of polysilicon, silane and nitrous oxide are introduced, with the volume ratio of nitrous oxide to the total introduced gas being 5%-15%;

[0106] During the polycrystalline growth process of the polysilicon middle layer, silane, nitrous oxide and methane are introduced, wherein the volume ratio of nitrous oxide and methane to the total introduced gas is 2%-8% and 3%-10% respectively;

[0107] During the polycrystalline growth process of the outer layer of polysilicon, silane and methane are introduced, with the volume ratio of methane to the total introduced gas being 10%-20%;

[0108] Phosphorus diffusion is carried out after the polycrystalline growth is completed.

[0109] Conventional phosphorus diffusion conditions can be employed. For example, the phosphorus diffusion conditions may include: a diffusion temperature of 750-950°C, a diffusion time of 60-200 minutes, a flow rate of 50-300 sccm of a small nitrogen gas carrying phosphorus oxychloride, a flow rate of 500-3000 sccm of a large nitrogen gas (i.e., pure nitrogen), a flow rate of 50-500 sccm of an oxygen gas, and a diffusion pressure of 50-500 mbar. Under conventional phosphorus diffusion conditions, the decrease in the amount of oxygen-containing gas (e.g., nitrous oxide) blocks the diffusion of phosphorus to a certain extent, and thus phosphorus doping increases with the decrease in the amount of oxygen doped.

[0110] Optionally, S102 further includes cooling the temperature after the phosphorus diffusion. More preferably, the cooling is performed in a stepwise manner, first cooling from 950-900°C to 800-850°C, then to 700-750°C, and finally to room temperature; the cooling time in each stage is independently 5-15 minutes.

[0111] In some optional embodiments of the present disclosure, the preparation method further includes: S103, depositing a semiconductor mask layer on the first semiconductor layer obtained in S102.

[0112] In some optional embodiments of the present disclosure, the preparation method further includes: S104, forming a second semiconductor opening region on the back surface obtained in S103.

[0113] In some optional embodiments of the present disclosure, the preparation method further includes: S105, depositing a second semiconductor layer on the back surface obtained in S104.

[0114] In some optional embodiments of the present disclosure, the preparation method further includes: S106, pre-treating the front surface of the silicon wafer, and then depositing a front passivation layer and an anti-reflection layer.

[0115] In some optional embodiments of the present disclosure, the preparation method further includes: S107, removing a portion of the second semiconductor layer on the back first semiconductor layer to expose the first semiconductor layer and form a first semiconductor opening region.

[0116] In some optional embodiments of the present disclosure, the preparation method further includes: S108, depositing a conductive film layer on the back surface obtained in S107.

[0117] In some optional embodiments of the present disclosure, the preparation method further includes: S109, forming an isolation trench between the first semiconductor opening region and the second semiconductor opening region.

[0118] In some optional embodiments of the present disclosure, the preparation method further includes: S110, forming gate line electrodes in the first semiconductor opening region and the second semiconductor opening region respectively.

[0119] The embodiments of the present disclosure are described in detail below, which are exemplary and are only configured to explain the present disclosure but are not to be construed as limiting the present disclosure.

[0120] Example 1

[0121] A back contact cell with reduced back parasitic absorption is obtained by the following steps:

[0122] S100, as shown in FIG1 , providing a double-sided polished silicon wafer 1, which is a single crystal silicon wafer;

[0123] S101. As shown in FIG2 , inverted pyramid texturing is performed on the back side. The inverted pyramid texturing is performed by first etching a groove with a depth of 0.8 nm on the back side of the silicon wafer using a laser, and then an alkaline solution (specifically, an aqueous solution of potassium hydroxide and a texturing additive, with mass concentrations of 10% and 3% respectively, and the texturing additive is specifically commercially available potassium gluconate) is used to etch out the velvet surface of the inverted pyramid to form pits. The inverted pyramid on the back side is controlled to have a surface morphology of micro-velvet. The plane area without velvet in the inverted pyramid velvet structure accounts for 50% of the entire back side area of ​​the wafer. The indentation depth of the pit is 1.0 nm, and the opening width of the pit is 2 nm.

[0124] S102. As shown in FIG3 , a first semiconductor layer is deposited on the back side of the silicon wafer. The first semiconductor layer comprises a tunneling oxide layer 2 and a first doped polysilicon layer 3. The ratio of the inverted pyramid pit depth, the tunneling oxide layer thickness, and the total thickness of the first doped polysilicon layer is 1:1.5:200, forming a good passivation structure on the micro-inverted pyramid velvet structure. The polycrystalline growth of the first doped polysilicon layer is divided into three layers: an inner polysilicon layer, a middle polysilicon layer, and an outer polysilicon layer. The inner polysilicon layer (i.e., the layer closest to the silicon wafer 1) is doped with trace oxygen. During polycrystalline growth, silane and nitrous oxide are introduced, with the nitrous oxide accounting for 10% of the total atmosphere. The polycrystalline growth time is 20 minutes. The middle polysilicon layer is doped with trace oxygen and carbon. Silane, nitrous oxide, and methane are introduced during polycrystalline growth, with the nitrous oxide and methane accounting for 5% and 7% of the total atmosphere, respectively. The polycrystalline growth time is 25 minutes. The outer layer of polysilicon (the layer away from the wafer) is doped with trace amounts of carbon. Silane and methane are introduced during polycrystalline growth, with methane accounting for 10% of the total atmosphere. The polycrystalline growth time is 20 minutes. After the three-layer polycrystalline growth is completed, phosphorus diffusion is performed. The phosphorus diffusion conditions are: a diffusion temperature of 750-900°C, a diffusion time of 150 minutes, a flow rate of 100 sccm of nitrogen gas carrying phosphorus oxychloride, a flow rate of 1000 sccm of nitrogen gas, a flow rate of 100 sccm of oxygen gas, and a diffusion pressure of 300 mbar. After diffusion, the temperature is stepped down from 900°C to 850°C and then to 750°C, with each cooling time lasting 10 minutes. This ultimately forms the inner oxygen-doped N-type polycrystalline layer 3.1, the middle oxygen-carbon-doped N-type polycrystalline layer 3.2, and the outer carbon-doped N-type polycrystalline layer 3.3.

[0125] The thickness ratio of the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer is 1:2.3:3;

[0126] The polycrystalline layers are doped with oxygen-containing elements such as nitrous oxide, which, to a certain extent, blocks the diffusion of phosphorus. The oxygen content of the three polycrystalline layers gradually decreases from the inside out, while the phosphorus content increases as the oxygen content decreases. Specifically, the phosphorus doping concentrations in the inner, middle, and outer polycrystalline silicon layers are 0.5×1019cm-3, 1×1019cm-3, and 1×1020cm-3, respectively. The oxygen doping concentrations in the inner, middle, and outer polycrystalline silicon layers are 5×1019cm-3, 0.2×1019cm-3, and 0, respectively. The carbon doping concentrations in the inner, middle, and outer polycrystalline silicon layers are 0, 0.2×1019cm-3, and 3×1019cm-3, respectively.

[0127] The band gap width of the inner layer of polycrystalline silicon is 1.5, the band gap width of the middle layer of polycrystalline silicon is 1.62, and the band gap width of the outer layer of polycrystalline silicon is 1.73.

[0128] The structure of the specific first doped polysilicon layer is characterized by doping trace elements during polycrystalline growth to broaden the optical band gap Eg and reduce parasitic absorption.

[0129] S103 , as shown in FIG4 , continues to deposit a semiconductor mask layer 4 on the first semiconductor layer. The semiconductor mask layer is silicon nitride, and its purpose is to protect the first semiconductor from being corroded by the strong acid or alkali solution.

[0130] S104 , as shown in FIG5 , forming a second semiconductor opening region on the back surface, wherein the opening width of the second semiconductor opening region is Wa, and the width of Wa is 400 μm.

[0131] S105 , as shown in FIG6 , deposit a second semiconductor layer in the second semiconductor opening region, wherein the second semiconductor layer comprises a second semiconductor passivation layer 5.1 and a second semiconductor doping layer 5.2 , wherein the second semiconductor passivation layer is an intrinsic amorphous silicon layer and the second semiconductor doping layer is an amorphous silicon P layer.

[0132] S106 , as shown in FIG7 , pre-treating the front surface and depositing a passivation layer 6.1 and an anti-reflection layer 6.2 , wherein the passivation layer 6.1 is a single-layer amorphous silicon passivation layer and the anti-reflection layer 6.2 is a single-layer anti-reflection layer.

[0133] S107 , as shown in FIG8 , remove the second semiconductor layer on the first semiconductor layer on the back side to expose the first semiconductor layer, thereby forming a first semiconductor opening region. The width Wb of the first semiconductor opening region is 300 μm.

[0134] S108. As shown in FIG9 , a conductive film layer 7 is deposited on the back of the battery. The conductive film layer 7 is a composite film layer of tin-doped indium oxide, metallic copper, and nickel-copper alloy, with a square resistance of 0.1Ω / □.

[0135] S109 , as shown in FIG10 , forming an isolation trench with a width Wg between the first semiconductor opening region and the second semiconductor opening region, where Wg is 100 μm, mainly for isolating the two semiconductor layers to reduce short circuit or leakage.

[0136] S110 , as shown in FIG11 , printing a gate electrode 8 on the back side of the battery, and forming metal electrodes at the openings of the first semiconductor region and the second semiconductor region of the silicon wafer 1 .

[0137] Example 2

[0138] The same procedure as in Example 1 was followed, except that the first doped polysilicon layer was adjusted so that the ratio of the pit depth to the total thickness of the first doped polysilicon layer was 1:500. The thickness ratio of the inner, middle, and outer polysilicon layers remained unchanged. To meet this requirement, the doping process was modified to extend the deposition times of the inner, middle, and outer polysilicon layers by 10 minutes, 15 minutes, and 10 minutes, respectively.

[0139] Example 3

[0140] The same method as in Example 1 was used, except that the flat surface area of ​​the inverted pyramid texturing structure was controlled to account for 70% of the entire back surface area. To meet this condition, the concentrations of potassium hydroxide and the texturing additive were reduced by 5% and 0.5% respectively, and the opening width of the pits was reduced to 0.5 nm.

[0141] Example 4

[0142] The same method as in Example 1 was used, except that the thickness of the polysilicon outer layer was adjusted so that the thickness ratio of the polysilicon inner layer to the polysilicon outer layer was 1:5. To meet this condition, the coating time of the polysilicon outer layer was correspondingly extended by 50%.

[0143] Example 5

[0144] The process was carried out in accordance with Example 1, except that the thickness of the polysilicon middle layer was adjusted so that the thickness ratio of the polysilicon inner layer to the polysilicon middle layer was 1:3.3. To meet this condition, the coating time of the polysilicon middle layer was correspondingly extended by 65%.

[0145] Example 6

[0146] The same procedure as in Example 1 was followed, except that the oxygen and carbon doping concentrations in the polysilicon middle layer were adjusted to different values, specifically to an effective oxygen doping concentration of 1020 cm⁻³ and a carbon doping concentration of 1020 cm⁻³. To meet these conditions, the proportions of nitrous oxide and methane in the total atmosphere were increased to 9% and 15%, respectively; the resulting band gap of the polysilicon middle layer was 1.65.

[0147] Comparative Example 1

[0148] The same method as in Example 1 was used, except that the first doped polysilicon layer was not a three-layer structure but a single layer, doped only with phosphorus. Its thickness was the same as the total thickness of the three-layer structure in Example 1, and the effective phosphorus doping concentration was 1×10 20 cm -3 . The corresponding band gap of the polysilicon middle layer was 1.56.

[0149] Comparative Example 2

[0150] The same procedure was followed as in Comparative Example 1, except that the first doped polysilicon layer was also doped with carbon and oxygen, with an effective carbon doping concentration of 5×1020 cm-3 and an effective oxygen doping concentration of 5×1020 cm-3. To achieve these doping concentrations, the deposition time of the nitrous oxide and methane was extended during the deposition of the polysilicon.

[0151] Comparative Example 3

[0152] The same process is carried out as in Example 1, except that oxygen is not doped in the three-layer structure of the first doped polysilicon layer.

[0153] Comparative Example 4

[0154] Refer to Example 1, except that the carbon doping amount in the three-layer structure of the first doped polysilicon layer decreases from the inside to the outside, and the effective carbon doping concentrations from the inside to the outside in the three-layer structure are 3×1019cm-3, 0.2×1019cm-3, and 0, respectively. To meet the doping amount, when the corresponding polysilicon middle layer is deposited, the proportion of methane in the total atmosphere is increased, and the proportion of methane in the total atmosphere is reduced during the deposition of the polysilicon outer layer.

[0155] Comparative Example 5

[0156] The process was carried out in accordance with Example 1, except that the oxygen doping level in the three-layer structure of the first doped polysilicon layer increased from the inside out, while the phosphorus doping level decreased accordingly. The effective oxygen doping concentrations in the three-layer structure were 0, 0.2×1019cm-3, and 5×1019cm-3, respectively; the effective phosphorus doping concentrations were 1×1020cm-3, 1×1019cm-3, and 0.5×1019cm-3, respectively. To meet these doping levels, the proportion of nitrous oxide in the total atmosphere during the deposition of the middle and outer polysilicon layers was increased accordingly, and the concentration of phosphorus oxychloride was increased during diffusion and then gradually decreased.

[0157] Comparative Example 6

[0158] The process was carried out in accordance with Example 1, except that the thickness of the tunnel oxide layer and the thickness of the first doped polysilicon layer were adjusted so that the ratio of the pit depth, the thickness of the tunnel oxide layer, and the total thickness of the first doped polysilicon layer was 1:6:80, while the thickness ratio of the inner polysilicon layer, the middle polysilicon layer, and the outer polysilicon layer remained unchanged. To meet this condition, the temperature and oxidation time of the tunnel oxide layer were increased accordingly, and the polysilicon deposition time was shortened.

[0159] Test Case

[0160] The back contact batteries obtained in the above examples and comparative examples were subjected to performance tests, and the test results are shown in Table 1. The minority carrier lifetime was used to characterize the passivation performance of the battery, and the sheet resistance was used to characterize the conductivity of the battery.

[0161] Table 1

[0162] It can be seen from the above embodiments and comparative examples that the embodiment scheme of the present disclosure can reduce the parasitic absorption on the back side while ensuring the passivation performance and conductivity, which is beneficial to improving the short-circuit current density and battery conversion efficiency.

[0163] Optionally, according to Examples 1 and 2, and Examples 4-5, the use of the first doped polysilicon layer with an optional thickness ratio disclosed in the present invention is more conducive to improving the short-circuit current density and battery conversion efficiency of the battery while taking into account excellent passivation performance and conductivity.

[0164] Optionally, according to Example 1 and Example 3, it can be seen that the use of the optional inverted pyramid texturing structure disclosed in the present invention is more conducive to improving the short-circuit current density and battery conversion efficiency of the battery.

[0165] Optionally, according to Example 1 and Example 6, the solution of adopting the first doped polysilicon layer with an optional doping concentration disclosed in the present invention is more conducive to improving the short-circuit current density, battery conversion efficiency and conductivity of the battery, while taking into account excellent passivation performance.

[0166] The above describes in detail the optional embodiments of the present disclosure, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure can be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as the contents disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0167] The back-contact battery disclosed herein includes a silicon wafer having a front side and a back side, the back side of which adopts a specific inverted pyramid velvet structure, a first semiconductor layer with a specific structure, and a specific layer thickness ratio, which can reduce the parasitic absorption on the back side while ensuring the passivation performance and conductivity, and is conducive to improving the short-circuit current density and battery conversion efficiency.

Claims

1. A back-contact cell for reducing back-side parasitic absorption, comprising a silicon wafer having a front side and a back side, a first semiconductor layer disposed on the back side of the silicon wafer, the back side of the silicon wafer being an inverted pyramid velvet structure, the first semiconductor layer comprising a tunneling oxide layer and a first doped polysilicon layer, characterized in that: The inverted pyramid velvet structure has alternately arranged planes and pits sunken into the silicon wafer, and the first doped polysilicon layer includes a polysilicon inner layer, a polysilicon middle layer and a polysilicon outer layer, the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer are all doped with phosphorus and also doped with carbon and / or oxygen, the oxygen doping amount in the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer gradually decreases, and the carbon doping amount and the phosphorus doping amount gradually increase, and the ratio of the sunken depth of the pit, the thickness of the tunneling oxide layer and the total thickness of the first doped polysilicon layer is 1:(0.6-4):(100-600).

2. The back contact cell according to claim 1, characterized in that: The plane area of ​​the inverted pyramid velvet structure accounts for 40% to 70% of the entire back surface area; and / or The indentation depth of the pit is 0.5-1.5 nm, and the opening width of the pit is 0.5-3 nm.

3. The back contact cell according to claim 1 or 2, characterized in that: The thickness of the tunneling oxide layer is 0.5-2.5 nm, and the total thickness of the first doped polysilicon layer is 50-300 nm.

4. The back contact battery according to any one of claims 1 to 3, characterized in that: The thickness ratio of the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer is 1:(1-3.3):(1.4-5); and / or The thickness ratio of the tunneling oxide layer, the polysilicon inner layer, the polysilicon middle layer and the polysilicon outer layer is 1: (20-55): (40-155): (60-160).

5. The back contact battery according to any one of claims 1 to 4, characterized in that: The absolute values ​​of the differences in effective doping concentrations of corresponding doping elements between the inner layer of polycrystalline silicon and the middle layer of polycrystalline silicon are recorded as tp, tO, and tC, respectively, and the absolute values ​​of the differences in effective doping concentrations of corresponding doping elements between the middle layer of polycrystalline silicon and the outer layer of polycrystalline silicon are recorded as Tp, TO, and TC, respectively, which satisfy: Tp / tp=10-30, TO / tO=1 / 25-1 / 5, TC / tC=5-20.

6. The back contact cell according to claim 5, characterized in that: The inner layer of the polysilicon is doped with phosphorus and oxygen, the middle layer of the polysilicon is doped with phosphorus and oxygen and carbon, the outer layer of the polysilicon is doped with phosphorus and carbon, and the absolute value tO of the difference in oxygen doping concentration between the inner layer of the polysilicon and the middle layer of the polysilicon is 1×1019-5×1019cm-3, and the absolute value TC of the difference in carbon doping concentration between the middle layer of the polysilicon and the outer layer of the polysilicon is 1×1019-9×1019cm-3.

7. The back contact cell according to any one of claims 1 to 6, characterized in that: The bandgap width of the inner layer of polycrystalline silicon is 1.45-1.55, the bandgap width of the middle layer of polycrystalline silicon is 1.56-1.65, and the bandgap width of the outer layer of polycrystalline silicon is 1.65-1.

75.

8. The back contact cell according to any one of claims 1 to 7, characterized in that: The back contact battery further comprises: A semiconductor mask layer, which is arranged on the surface of the first semiconductor layer, and the first semiconductor layer and the semiconductor mask layer thereon are arranged at intervals along a back-parallel direction as a whole, and the intervals are second semiconductor opening regions; A second semiconductor layer, which is arranged on the surface of the semiconductor mask layer and covers the surface of the second semiconductor opening region, and a first semiconductor opening region exposing the first semiconductor layer is opened on a portion of the second semiconductor layer located between adjacent second semiconductor opening regions; and the second semiconductor layer comprises an intrinsic silicon layer and a second doped silicon layer sequentially arranged in a direction perpendicular to the back surface and outward, wherein the second doped silicon layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer; A conductive film layer is disposed on a surface of the second semiconductor layer and a surface of the first semiconductor layer exposed at the first semiconductor opening region, and an isolation groove exposing the second semiconductor layer is opened on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region; Gate line electrodes are respectively arranged on the surfaces of the first semiconductor opening region and the second semiconductor opening region; A front passivation layer, which is disposed on the front side of the silicon wafer; The anti-reflection layer is arranged on the surface of the front passivation layer.

9. A method for preparing a back contact battery with reduced back parasitic absorption, characterized in that: The back contact cell is a back contact cell with reduced back parasitic absorption as claimed in any one of claims 1 to 8, and the preparation method comprises: S100, provides double-sided polished silicon wafers; S101, performing inverted pyramid texturing on the back side of the silicon wafer, so that a partial plane is retained on the back side and a pit sunken into the silicon wafer is formed; S102. Depositing a tunneling oxide layer and a first doped polysilicon layer in sequence on the back side of the silicon wafer obtained in S101 to form a first semiconductor layer; wherein the process of depositing the first doped polysilicon layer includes: firstly performing polycrystalline growth of the corresponding layers, and then performing phosphorus diffusion; and introducing a gas source of the required doping element during the polycrystalline growth.

10. The preparation method according to claim 9, characterized in that: The process of making the inverted pyramid texture in S101 includes: firstly etching a groove on the back side of the silicon wafer with a laser, and then etching the texture surface of the inverted pyramid with an alkaline solution or an acidic solution; and / or In S102, the gas introduced during the polycrystalline growth includes silane and a doping element gas source selected from nitrous oxide and / or methane. When nitrous oxide is introduced, the volume ratio of nitrous oxide to the total introduced gas is 2%-15%, and when methane is introduced, the volume ratio of methane to the total introduced gas is 3%-20%.

11. The preparation method according to claim 9 or 10, characterized in that: In S102, the process of depositing the first doped polysilicon layer specifically includes: During the polycrystalline growth process of the inner layer of polysilicon, silane and laughing gas are introduced, and the volume ratio of laughing gas to the total introduced gas is 5%-15%; During the polycrystalline growth process of the polycrystalline silicon middle layer, silane, laughing gas and methane are introduced, wherein the volume ratio of the laughing gas and methane to the total introduced gas is 2%-8% and 3%-10% respectively; During the polycrystalline growth process of the outer layer of polysilicon, silane and methane are introduced, with the volume ratio of methane to the total introduced gas being 10%-20%; Phosphorus diffusion is carried out after the polycrystalline growth is completed.

12. The preparation method according to any one of claims 9 to 11, characterized in that: The preparation method further comprises: S103, depositing a semiconductor mask layer on the first semiconductor layer obtained in S102; S104, forming a second semiconductor opening region on the back surface obtained in S103; S105, depositing a second semiconductor layer on the back surface obtained in S104; S106, pre-treating the front side of the silicon wafer, and then depositing a front passivation layer and an anti-reflection layer; S107, removing the second semiconductor layer on the first semiconductor layer on the back side to expose the first semiconductor layer and form a first semiconductor opening area; S108, depositing a conductive film layer on the back surface obtained in S107; S109, forming an isolation trench between the first semiconductor opening region and the second semiconductor opening region; S110 , forming gate line electrodes at the first semiconductor opening region and the second semiconductor opening region respectively.

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