Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate (1), and word lines (40) passing through the different layers and extending in the direction perpendicular to the substrate (1). Each transistor comprises a first electrode (51), a second electrode (52), and a semiconductor layer (23) surrounding the side wall of the corresponding word line (40). The semiconductor layer (23) comprises a first portion (231) in contact with the first electrode (51) or the second electrode (52), and a second portion (232) located between the first electrode (51) and the second electrode (52); the first portion (231) extends only in the direction perpendicular to the substrate (1); the second portion (232) comprises a first extension portion (2321) extending in the direction perpendicular to the substrate (1) and a second extension portion (2322) extending from the first extension portion in a direction moving away from the side wall of the corresponding word line (40) and parallel to the substrate (1); and a plurality of semiconductor layers (23) are disconnected.

Description

Semiconductor device, manufacturing method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed on August 11, 2023, with application number 202311014334.X and invention name “A semiconductor device, a manufacturing method thereof, and an electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0004] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] An embodiment of the present disclosure provides a semiconductor device, including:

[0008] Multiple transistors are distributed in different layers and stacked vertically along the substrate;

[0009] word lines, extending through different layers in a direction perpendicular to the substrate;

[0010] The transistor includes a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the semiconductor layer includes a first portion in contact with the first electrode and the second electrode, and a second portion located between the first electrode and the second electrode, wherein the first portion extends only in a direction perpendicular to a substrate; the second portion includes a first extension extending in a direction perpendicular to the substrate and a second extension extending from the first extension in a direction away from the sidewall of the word line and parallel to the substrate;

[0011] The semiconductor layers of the transistors are physically separated and distributed in different regions of the sidewall of the word line.

[0012] In some embodiments, along a direction perpendicular to the substrate and perpendicular to the arrangement direction of the first electrode and the second electrode, the cross-section of the semiconductor layer is U-shaped, and an opening of the U-shape faces a direction away from the sidewall of the word line.

[0013] In some embodiments, the word line includes a vertical portion extending in a direction perpendicular to the substrate and a plurality of raised portions extending from the side walls of the vertical portion in a direction parallel to the substrate, and the raised portions are located between the second portions of the semiconductor layers adjacent to each other in a direction perpendicular to the substrate.

[0014] In some embodiments, the transistor further comprises a gate insulating layer;

[0015] The semiconductor device further includes:

[0016] Insulating layers and conductive layers are alternately distributed in a direction perpendicular to the substrate; through holes penetrate each of the insulating layers and each of the conductive layers;

[0017] The word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different areas of the sidewall of the gate insulating layer are sequentially distributed in the through hole from inside to outside;

[0018] The first electrode and the second electrode are disposed on the conductive layer and are electrically connected to the semiconductor layer.

[0019] In some embodiments, the U-shaped opening of the semiconductor layer is filled with a film layer made of the same material as the insulating layer.

[0020] In some embodiments, the semiconductor device further comprises a first trench located between two adjacent transistors, wherein the first trench is filled with an isolation layer;

[0021] The isolation layer has a protrusion in a region facing the second portion of the semiconductor layer;

[0022] The first extension portion and the second extension portion of the semiconductor layer are disposed on the protrusion.

[0023] An embodiment of the present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes multiple layers of transistors stacked in a direction perpendicular to a substrate, word lines extending in a direction perpendicular to the substrate through the transistors in different layers, and the transistors include a first electrode and a second electrode. The method for manufacturing the semiconductor device includes:

[0024] Providing a substrate, alternately depositing sacrificial layer films and conductive films on the substrate, and patterning to form a plurality of stacked structures, each of the stacked structures comprising a stack of a plurality of sacrificial layers and a plurality of conductive layers alternately arranged to form a predetermined pattern, and a first insulating layer forming a complementary pattern to the predetermined patterns of each sacrificial layer and each conductive layer; the predetermined pattern of the conductive layer comprises a first electrode and a second electrode of the transistor to be formed;

[0025] forming a through hole that simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure in a direction perpendicular to the substrate, the through hole comprising a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, wherein only the sidewalls of the sacrificial layer are exposed in the first sub-holes, only the sidewalls of the conductive layer are exposed in the second sub-holes, the sidewalls and a surface extending in a direction parallel to the substrate of the first insulating layer are exposed in the first sub-holes, and only the sidewalls of the first insulating layer are exposed in the second sub-holes; and the second sub-holes disconnect the first electrode and the second electrode in the conductive layer;

[0026] Depositing a semiconductor film, a gate insulating film, and a gate electrode film filling the through hole in sequence in the through hole to form a semiconductor layer and a gate insulating layer of the transistor in multiple layers, as well as a word line; wherein the semiconductor layer is connected to the first electrode and the second electrode corresponding to each layer of transistors;

[0027] Etching the first insulating layer and each of the sacrificial layers outside the through hole to expose the semiconductor layer located in each of the first sub-holes;

[0028] The semiconductor layer located in the first sub-hole is removed by etching, so that semiconductor layers of transistors at different layers are disconnected.

[0029] In some embodiments, forming a through hole that simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure in a direction perpendicular to the substrate comprises:

[0030] forming an initial through hole penetrating the stacked structure in a direction perpendicular to the substrate by dry etching the stacked structure in one process, wherein the initial through hole located in the conductive layer is completely surrounded by the conductive layer;

[0031] Using the conductive layer as a barrier layer, wet-etching the sacrificial layer in the initial through hole to increase the aperture of the initial through hole in the sacrificial layer until the first insulating layer is exposed;

[0032] Using the conductive layer and the sacrificial layer as barrier layers, wet-etching the exposed first insulating layer to increase the aperture of the corresponding area of ​​the first insulating layer, thereby obtaining a through hole located in the sacrificial layer;

[0033] The conductive layer is wet-etched to increase the aperture of the initial through hole in the conductive layer, and the conductive layer is divided into two parts to obtain a through hole in the conductive layer.

[0034] In some embodiments, etching the first insulating layer and each of the sacrificial layers to expose the semiconductor layer within each of the first sub-holes includes:

[0035] dry-etching the first insulating layer outside the through hole to expose the sidewall of each sacrificial layer connected to the first insulating layer and the semiconductor layer located in the first sub-hole and connected to the first insulating layer;

[0036] The entire sacrificial layer is removed by wet etching to expose the semiconductor layer located in the first sub-hole and connected to the sacrificial layer.

[0037] In some embodiments, after etching away the semiconductor layer located in the first sub-hole so as to disconnect the semiconductor layers of transistors in different layers, the method further includes:

[0038] An insulating film is deposited to form a second insulating layer filling the etched sacrificial layer and the area where the first insulating layer is located.

[0039] In some embodiments, the sacrificial layer thin film includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer are silicon oxide.

[0040] An embodiment of the present disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments.

[0041] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and advantages of the present disclosure can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0042] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0043] Summary of the Figures

[0044] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation to the technical solution.

[0045] FIG1A is a plan view of a semiconductor device provided by an exemplary embodiment; FIG1B is a schematic diagram along the aa' direction in FIG1A; FIG1C is a schematic diagram along the bb' direction in FIG1A; FIG1D is a schematic diagram along the cc' direction in FIG1A; FIG1E is a schematic diagram along the dd' direction in FIG1A;

[0046] FIG2 is a schematic cross-sectional view along the aa′ direction after forming a stacked structure according to an exemplary embodiment;

[0047] FIG3A is a cross-sectional view of a conductive layer along a direction parallel to a substrate, provided by an exemplary embodiment; FIG3B is a cross-sectional view along the aa' direction after a preset pattern is formed, provided by an exemplary embodiment; FIG3C is a cross-sectional view along the bb' direction after a preset pattern is formed, provided by an exemplary embodiment; FIG3D is a cross-sectional view along the cc' direction after a preset pattern is formed, provided by an exemplary embodiment; FIG3E is a cross-sectional view along the dd' direction after a preset pattern is formed, provided by an exemplary embodiment;

[0048] FIG4A is a cross-sectional view taken along the aa' direction after forming a capacitor according to an exemplary embodiment; FIG4B is a cross-sectional view taken along the bb' direction after forming a capacitor according to an exemplary embodiment; FIG4C is a cross-sectional view taken along the cc' direction after forming a capacitor according to an exemplary embodiment; FIG4D is a cross-sectional view taken along the dd' direction after forming a capacitor according to an exemplary embodiment;

[0049] FIG5A is a cross-sectional view taken along the aa' direction after forming an initial through hole according to an exemplary embodiment; FIG5B is a cross-sectional view taken along the bb' direction after forming an initial through hole according to an exemplary embodiment; FIG5C is a cross-sectional view taken along the cc' direction after forming an initial through hole according to an exemplary embodiment;

[0050] FIG6A is a cross-sectional view along the aa' direction after lateral etching of the sacrificial layer according to an exemplary embodiment; FIG6B is a cross-sectional view along the bb' direction after lateral etching of the sacrificial layer according to an exemplary embodiment; FIG6C is a cross-sectional view along the cc' direction after lateral etching of the sacrificial layer according to an exemplary embodiment;

[0051] FIG7A is a cross-sectional view along the aa' direction after the first insulating layer and the fourth insulating layer are laterally etched, according to an exemplary embodiment; FIG7B is a cross-sectional view along the bb' direction after the first insulating layer and the fourth insulating layer are laterally etched, according to an exemplary embodiment; FIG7C is a cross-sectional view along the cc' direction after the first insulating layer and the fourth insulating layer are laterally etched, according to an exemplary embodiment;

[0052] FIG8A is a cross-sectional view taken along the aa' direction after lateral etching of the conductive layer according to an exemplary embodiment; FIG8B is a cross-sectional view taken along the bb' direction after lateral etching of the conductive layer according to an exemplary embodiment; FIG8C is a cross-sectional view taken along the cc' direction after lateral etching of the conductive layer according to an exemplary embodiment;

[0053] 9A is a cross-sectional view taken along the aa' direction after forming a semiconductor layer, a gate insulating layer, and a word line according to an exemplary embodiment; FIG. 9B is a cross-sectional view taken along the bb' direction after forming a semiconductor layer, a gate insulating layer, and a word line according to an exemplary embodiment; FIG. 9C is a cross-sectional view taken along the cc' direction after forming a semiconductor layer, a gate insulating layer, and a word line according to an exemplary embodiment;

[0054] FIG10A is a schematic plan view of a mask pattern for forming the fifth trench according to an exemplary embodiment; FIG10B is a cross-sectional view taken along the aa' direction after forming the fifth trench according to an exemplary embodiment; FIG10C is a cross-sectional view taken along the bb' direction after forming the fifth trench according to an exemplary embodiment; and FIG10D is a cross-sectional view taken along the cc' direction after forming the fifth trench according to an exemplary embodiment;

[0055] FIG11A is a cross-sectional view along the aa' direction after etching the sacrificial layer according to an exemplary embodiment; FIG11B is a cross-sectional view along the bb' direction after etching the sacrificial layer according to an exemplary embodiment; FIG11C is a cross-sectional view along the cc' direction after etching the sacrificial layer 9 according to an exemplary embodiment;

[0056] FIG12A is a cross-sectional view taken along the aa' direction after etching the semiconductor layer located in the first sub-hole according to an exemplary embodiment; FIG12B is a cross-sectional view taken along the bb' direction after etching the semiconductor layer located in the first sub-hole according to an exemplary embodiment; FIG12C is a cross-sectional view taken along the cc' direction after etching the semiconductor layer located in the first sub-hole according to an exemplary embodiment;

[0057] Figure 13A is a cross-sectional view along the aa' direction after the second insulating layer is formed, provided by an exemplary embodiment; Figure 13B is a cross-sectional view along the bb' direction after the second insulating layer is formed, provided by an exemplary embodiment; Figure 13C is a cross-sectional view along the cc' direction after the second insulating layer is formed, provided by an exemplary embodiment.

[0058] Details

[0059] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0060] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0061] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0062] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0063] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0064] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0065] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0066] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0067] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0068] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0069] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0070] In the embodiment of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A.

[0071] The development of 3D memory array stacking structures has led to various problems. As the number of stacking layers increases, the array becomes larger, and the unit devices become closer together, the presence of parasitic MOS transistors between different layers can significantly impact the retention of capacitor charge and the overall stability of the device. This application proposes a semiconductor device and a method for removing parasitic MOS transistors from a semiconductor device. The semiconductor device has a simple structure, a simple process, and reduces costs.

[0072] Figure 1A is a cross-sectional view of a semiconductor device provided by an exemplary embodiment, taken along a direction parallel to substrate 1. Figure 1B is a schematic diagram along the aa' direction in Figure 1A, Figure 1C is a schematic diagram along the bb' direction in Figure 1A, Figure 1D is a schematic diagram along the cc' direction in Figure 1A, and Figure 1E is a schematic diagram along the dd' direction in Figure 1A. Figure 1A only shows the structure of the transistor region 300, and the structure of the capacitor region 200 is not shown. The semiconductor device can be a transistor, or a memory cell including a transistor, or a memory cell array including a memory cell, or a 3D stacked structure including a memory cell array, or a memory including a transistor or a memory cell array, etc.

[0073] As shown in FIG. 1A to FIG. 1E , an embodiment of the present disclosure provides a semiconductor device, including:

[0074] Multiple transistors are distributed in different layers of memory cells and stacked in a direction perpendicular to the substrate 1 ; as shown in FIG1B , the area indicated by the dotted line is a transistor, and it can be seen that multiple transistors are stacked in a direction perpendicular to the substrate 1 .

[0075] The word line 40 passes through the memory cells of different layers and extends in a direction perpendicular to the substrate 1;

[0076] The transistor may include a first electrode 51 , a second electrode 52 , and a semiconductor layer 23 surrounding a sidewall of the word line 40 ;

[0077] The semiconductor layer 23 is a thin film having two main surfaces, that is, the two surfaces of the film layer. The two surfaces of the semiconductor layer 23 extend toward the substrate 1. The thin film is formed in a through hole that penetrates the memory cell and is deposited on the sidewalls of the through hole. The main surfaces of the film are aligned with the sidewalls of the through hole, forming an annular semiconductor layer 23. The inner and outer sidewalls of the annular semiconductor layer 23 serve as the two main surfaces.

[0078] The outer sidewall of the semiconductor layer 23 includes a first portion 231 in contact with the first electrode 51 or the second electrode 51, the first portion 231 including a first electrode contact region and a second electrode contact region, and a second portion 232 located between the first electrode 51 or the second electrode 52 or between the first electrode contact region and the second electrode contact region, which can be understood as the second portion 232 not in contact with the first electrode 51 or the second electrode 52. The thin film or membrane layer of the first portion 231 extends only in a direction perpendicular to the substrate 1; the second portion 232 includes a first extension portion 2321 extending in a direction perpendicular to the substrate 1 and a second extension portion 2322 extending from the first extension portion 2321 in a direction away from the sidewall of the word line 40 and parallel to the substrate 1.

[0079] The semiconductor layers 23 of the transistors connected to one word line 40 are physically separated and distributed in different areas of the sidewall of the word line 40 .

[0080] The solution provided by this embodiment physically disconnects the semiconductor layers of multiple transistors, eliminating parasitic MOS transistors between layers, reducing leakage current, and improving device stability. Furthermore, this structure can be realized through the following process features and is easy to manufacture.

[0081] Ends of the first extension portion 2321 extend away from the sidewall of the word line 40 and parallel to the substrate 1 to form the second extension portion 2322 .

[0082] The manufacturing process corresponding to this structure does not require the production of dummy word lines or dummy spacers on the conductor layer. Instead, a first insulating layer is filled outside the hole, and the first insulating layer is etched inside the hole to expand the hole diameter. Two grooves are formed on the first insulating layer. The semiconductor layer of the parasitic MOS tube is formed in the grooves and at the ends of the sacrificial layer. A hole is opened outside the hole to remove the sacrificial layer and the first insulating layer to expose the semiconductor layer of the parasitic MOS tube.

[0083] The arrangement direction of the first electrode 51 and the second electrode 52 is a direction from the first electrode 51 to the second electrode 52, or a direction from the contact surface between the first electrode 51 and the semiconductor layer 23 to the contact surface between the second electrode 52 and the semiconductor layer 23. The arrangement direction perpendicular to the substrate 1 and perpendicular to the first electrode 51 and the second electrode 52 may be, for example, the cc' direction, and the arrangement direction perpendicular to the substrate 1 and parallel to the first electrode 51 and the second electrode 52 may be, for example, the aa' direction.

[0084] In some embodiments, the cross-section of the semiconductor layer 23 may be U-shaped along a direction perpendicular to the substrate 1 and perpendicular to the arrangement of the first electrode 51 and the second electrode 52, with the opening of the U-shape facing away from the sidewalls of the wordline 40. The sidewalls of the wordline 40 are surfaces formed along the extension direction of the wordline 40. In some embodiments, the semiconductor device may further include a gate electrode 26, and the gate electrodes 26 of transistors in different layers may be part of the wordline 40. It is understood that before or after the wordline 40 is formed, it is not necessary to separately form the gate electrode 26. After the wordline 40 is formed, a portion of the wordline 40 serves as the gate electrode 26.

[0085] In some embodiments, a word line 40 is filled within a through-hole, and the shape of the word line 40 is adapted to the through-hole. For example, the word line 40 may include a vertical portion 401 extending perpendicular to the substrate 1 and a plurality of first protrusions 402 extending from the sidewalls of the vertical portion 401. The first protrusions 402 extend parallel to the substrate 1 and perpendicular to the arrangement of the first electrode 51 and the second electrode 52. The first protrusions 402 may be located between semiconductor layers 23 of adjacent transistors perpendicular to the substrate 1, with two opposing first protrusions 402 distributed between any two adjacent semiconductor layers 23. The second portion 232 of the semiconductor layer 23, which is distributed between the first electrode 51 and the second electrode 52, is distributed in the region between the two first protrusions 402 and on a surface extending horizontally to the two first protrusions 402. Alternatively, it can be understood that the first protrusion 402 may be located between the semiconductor layers 23 of transistors adjacent to each other in a direction perpendicular to the substrate 1, and the second portion 232 may be distributed on adjacent surfaces of two adjacent first protrusions 402 and on the sidewalls between the two first protrusions 402. That is, the second portion 232 may be distributed on the lower surface (the surface facing the substrate 1) of one first protrusion 402 and the upper surface (the surface facing away from the substrate 1) of the other first protrusion 402, as well as on the sidewalls of the vertical portion 401 between the two first protrusions 402.

[0086] In some embodiments, on a plane perpendicular to the substrate 1 , the orthographic projections of the first protrusion 402 and the first electrode 51 and the second electrode 52 on the substrate do not overlap.

[0087] The word line 40 has no first protrusion 402 in the conductive layer corresponding to the transistor, and only has a first protrusion 402 in the channel region of the first electrode 51 and the second electrode 52 between the insulating layers corresponding to the isolation transistor, and a first protrusion 402 between two adjacent channel regions in the vertical direction.

[0088] In some embodiments, the first electrode 51 and the second electrode 52 can be located in the same conductive film layer along a direction perpendicular to the substrate 1. It can be understood that the first electrode 51 and the second electrode 52 are patterned from the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1.

[0089] In an exemplary embodiment, the first electrodes 51 or the second electrodes 52 of transistors in different layers may be located in different conductive film layers distributed in a vertical direction and isolated by an insulating film layer or the like.

[0090] In some embodiments, the transistor may further include a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23 , and a main surface of the gate insulating layer 24 may surround a sidewall of the word line 40 .

[0091] In some embodiments, the gate insulating layers 24 of multiple transistors on different layers can be an integrated structure, which can be understood as a single film layer continuously distributed within the through-hole. In this embodiment, the gate insulating layers 24 of multiple transistors can be deposited on the inner sidewalls of the through-hole in a single process, eliminating the need for subsequent cutting, thereby simplifying the process. However, the disclosed embodiments are not limited thereto, and the gate insulating layers 24 of multiple transistors on different layers can be disconnected.

[0092] In some embodiments, the semiconductor device may further include:

[0093] As shown in FIG1B , the second insulating layers 11 and the conductive layers are alternately distributed in a direction perpendicular to the substrate 1; and a through hole penetrates each of the second insulating layers 11 and each of the conductive layers;

[0094] The word line 40, the gate insulating layer 24 surrounding the sidewall of the word line 40, and the plurality of semiconductor layers 23 surrounding different areas of the sidewall of the gate insulating layer 24 are sequentially distributed in the through hole from the inside to the outside with the hole center as a reference;

[0095] The first electrode 51 and the second electrode 52 of the same transistor are disposed in one conductive layer and are electrically connected to the semiconductor layer 23 .

[0096] In this embodiment, transistors stacked in different layers share the hole where the word line 40 is located. Gate electrodes 26 , gate insulating layers 24 , and semiconductor layers 23 of multiple stacked transistors are formed in the hole in one process, which can simplify the process.

[0097] In some embodiments, multiple second insulating layers 11 distributed between different conductive layers are connected to form an integrated structure. The integrated structure includes a lateral extension portion disposed between adjacent conductive layers and a longitudinal extension portion extending perpendicular to the substrate 1. The longitudinal extension portion includes a protrusion located between adjacent conductive layers and facing the sidewall of the word line 40. As shown in FIG1D , the longitudinal extension portion of the second insulating layer 11 includes multiple protrusions that face the sidewall of the word line 40 and correspond one-to-one with the first protrusion 402 of the word line 40. During semiconductor layer fabrication, after etching away the semiconductor layer of the parasitic MOS outside the hole, the insulating film layer is filled to form the protrusions of the longitudinal extension portion.

[0098] The second insulating layer 11 is not only filled between the stacked adjacent conductive layers but also filled in the U-shaped opening of the semiconductor layer 23 . The second insulating layer 11 may be a silicon oxide film layer.

[0099] In some embodiments, the semiconductor device further includes a first insulating layer 10 , which is disposed between the longitudinal extension of the second insulating layer 11 and the semiconductor layer 23 and fills the U-shaped opening of the semiconductor layer 23 .

[0100] In some embodiments, referring to FIG. 1D , the semiconductor device further includes a first trench located between two adjacent transistors. The first trench is filled with an isolation layer (including a first insulating layer 10 and a second insulating layer 11). The isolation layer has a second raised portion (i.e., the first insulating layer 10 in FIG. 1D ) in an area facing the second portion 232 of the semiconductor layer 23. The first extension portion 2321 and the second extension portion 2322 of the semiconductor layer 23 are distributed on the second raised portion. In other words, the semiconductor layer 23 forms a curved surface on the second raised portion in accordance with the raised shape of the second raised portion. The curved surface includes the first extension portion 2321 and the second extension portion 2322. The first extension portion and the second extension portion are different regions of the same film layer.

[0101] In some embodiments, the semiconductor device may be a memory cell array, comprising a plurality of memory cells, each of which comprises a transistor. As shown in FIG1A , the transistors in the same layer form a memory cell array distributed along a first direction X and a second direction Y, respectively. Each layer may further comprise a bit line 30 connected to the second electrode 52 of the transistors in the same column in a layer. FIG1A illustrates that each layer comprises four rows and two columns of memory cells, but the disclosed embodiments are not limited thereto. Each layer may comprise memory cells of other numbers of rows and columns, for example, may comprise only one memory cell.

[0102] In some embodiments, the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30 .

[0103] In some embodiments, the second electrode 52 of the transistor may be a portion of the bit line 30 connected to the second electrode 52. For example, the bit line 30 is a straight line, and the sidewall of the straight line is connected to the semiconductor layer 23 in the extension direction. Alternatively, the bit line 30 has an integrally designed branch, and the branch is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as being approximately perpendicular.

[0104] The branches may be multiple branches on one sidewall of the bit line 30 , or multiple branches on both sidewalls at the same time, and each branch may form a transistor or a memory cell.

[0105] In some embodiments, the bit line 30 may extend along the second direction Y, the first electrode 51 and the second electrode 52 may extend along the first direction X, respectively, and the first electrode 51 and the second electrode 52 are sequentially arranged along the first direction X.

[0106] The stacked transistors can be used in multiple memory cell applications, such as traditional 1T and 2T memory cells in DRAM, with or without capacitors, or in 4T or 6T memory cells in SRAM.

[0107] In some embodiments, the semiconductor device may further include a data storage element of a memory.

[0108] In some embodiments, the data storage element is, for example, a capacitor, forming a 1T1C storage structure. However, the present disclosure is not limited thereto, and other transistors can be used to form a 2T0C storage structure, and so on.

[0109] In some embodiments, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42 , and the first capacitor electrode 41 is connected to the first electrode 51 .

[0110] In some embodiments, the first capacitor electrode 41 and the first electrode 51 may be connected to form an integral structure, or they may share a common electrode, which may be a wire extending laterally in a direction parallel to the substrate 1 .

[0111] In some embodiments, the first electrode 41 may include a first end surface facing the word line 40 and a second end surface facing away from the word line 40, as well as a side surface connecting the first end surface and the second end surface, the first electrode 51 serves as the first capacitor electrode 41 of the capacitor, and the second capacitor electrode 42 surrounds the side surface of the first electrode 51.

[0112] In some embodiments, the semiconductor device may further include a support layer 45 extending in a direction perpendicular to the substrate 1, the support layer 45 being connected to the second end surface of each first electrode 51. The support layer 45 forms a plate-shaped film layer extending in a direction perpendicular to the substrate 1 and may be formed before fabricating the capacitor to provide support for the subsequent capacitor fabrication process.

[0113] In some embodiments, the support layer 45 may wrap around the second end surface of each first electrode 51 and contact the area of ​​the side surface of the first electrode 51 near the second end surface, thereby supporting the first electrode 51. In this solution, the support layer 45 may be partially placed on the upper surface of the first electrode 51 to enhance the supporting performance of the support layer 45.

[0114] In some embodiments, the plurality of transistors stacked in a direction perpendicular to the substrate 1 are periodically distributed in the direction perpendicular to the substrate 1 .

[0115] The technical solution of this embodiment will be further illustrated below using the manufacturing process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can use known coating processes; and etching can use known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film produced by a deposition or coating process of a certain material. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern."

[0116] In an exemplary embodiment, the method for manufacturing the semiconductor device includes:

[0117] 1) As shown in Figure 2, a sacrificial layer film and a first conductive film are sequentially deposited on a substrate 1 to form a stacked structure comprising alternating sacrificial layers 9 and conductive layers 12. Figure 2 is a schematic cross-sectional view along the aa' direction after the stacked structure is formed, provided in accordance with an exemplary embodiment. Cross-sectional views along the bb', cc', and dd' directions are similar and are omitted. In some embodiments, a sacrificial layer 9 is disposed on the topmost conductive layer 12, and the bottommost sacrificial layer 9 can serve as a stop layer in subsequent etching operations.

[0118] In some embodiments, the sacrificial layer film may be an insulating material having a large etching selectivity ratio with the conductive layer, including but not limited to aluminum oxide (Al 2 O 3 ) and the like.

[0119] In some embodiments, the first conductive film may be made of the following conductive materials:

[0120] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0121] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0122] Alternatively, it may be polysilicon material, doped semiconductor material, such as doped silicon, doped germanium, doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0123] The stacked structure shown in FIG. 2 includes four sacrificial layers 9 and three conductive layers 12 , which is only an example. In other embodiments, the stacked structure may include more or fewer film layers.

[0124] 2) patterning the stacked structure so that the stacked structure forms a preset pattern;

[0125] The patterning of the stacked structure may include:

[0126] Using a mask containing a preset pattern, the stacked structure is etched from the top layer to the bottom layer (excluding the substrate 1) using dry etching, so that the conductive layer 12 and the sacrificial layer 9 are both formed into a preset pattern, which defines the transistor electrode area and the bit line area. The mask pattern is shown in Figure 3A. In the stacked structure, the mask-blocked portion is retained, and the unblocked portion is removed. The removed areas form a plurality of first trenches T1. The first trenches T1 extend along the X direction, and the area between the first trenches T1 is a strip-shaped area extending along the first direction X.

[0127] The preset pattern of the conductive layer 12 may include a plurality of first conductive portions 121 and second conductive portions 122 , wherein the first conductive portions 121 may extend along a first direction X, and the second conductive portions 122 may extend along a second direction Y;

[0128] A first insulating film is deposited in the first trench T1 to form a first insulating layer 10 filling the first trench T1; as shown in Figures 3A, 3B, 3C, 3D, and 3E, wherein Figure 3A is a cross-sectional view of the conductive layer 12 along a direction parallel to the substrate 1, Figure 3B is a cross-sectional view along the aa' direction after forming the preset pattern, Figure 3C is a cross-sectional view along the bb' direction after forming the preset pattern, Figure 3D is a cross-sectional view along the cc' direction after forming the preset pattern, and Figure 3E is a cross-sectional view along the dd' direction after forming the preset pattern. The preset pattern and the pattern of the plurality of first trenches T1 are complementary, that is, the pattern of the preset pattern and the pattern of the first trenches T1 are combined to form the shape of the conductive layer 12 in step 1). The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0129] The first conductive portion 121 may subsequently form a first electrode 51 of a transistor, and the second conductive portion 122 may subsequently form a second electrode 52 of a transistor and a bit line 30 .

[0130] In some embodiments, the first insulating film may be made of a material having a large etching selectivity ratio with the sacrificial layer film, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0131] The preset shape shown in FIG3A is only an example, and the preset shape may be other shapes.

[0132] 3) forming a capacitor, comprising:

[0133] 4A and 4B , the stacked structure is etched from the top layer to the bottom layer in the support area 100 by dry etching to form a second trench T2, exposing the end face of the first conductive part 121 away from the second conductive part 122 ; the support area 100 is located on the side of the first conductive part 121 away from the second conductive part 122 .

[0134] A support layer thin film is deposited in the second trench T2 to form a support layer 45 , which fills the second trench T2 . The support layer 45 may be a plate-shaped film layer extending in a direction perpendicular to the substrate and parallel to the cc′ direction.

[0135] The first trench T1 is opened in a region corresponding to the capacitor, and the sacrificial layer 9 exposed by the first trench T1 is laterally etched to form a third trench. The third trench exposes the upper and lower surfaces and side surfaces of the first conductive portion 121 located in the capacitor region 200 .

[0136] Depositing a dielectric film and a conductor material in sequence to form a dielectric layer 43 and a second capacitor electrode 42 respectively, wherein the dielectric layer 43 covers the exposed area of ​​the first conductive layer 121;

[0137] Depositing a second conductive film to form a second conductive layer 7 covering the second capacitor electrode 42 and filling the third trench; the second conductive layer 7 is connected to the second capacitor electrode 42, and the second conductive layer 7 can be grounded, thereby achieving capacitor grounding;

[0138] planarizing the second conductive layer 7 and depositing a third insulating film to form a third insulating layer 13, wherein the third insulating layer 13 covers the second conductive layer 7;

[0139] As shown in FIG4B , dry etching is performed in the transistor region 300 , and the etching stops at the topmost sacrificial layer 9 , thereby forming a fourth trench; a fourth insulating film is deposited in the fourth trench and polished to form a fourth insulating layer 14 filling the fourth trench;

[0140] A fifth insulating film is deposited on the substrate having the above structure to form a fifth insulating layer 15. The fifth insulating layer 15 covers the third insulating layer 13 and the fourth insulating layer 14. The fifth insulating layer 15 serves as a stop layer for subsequent grinding of the word line 40, as shown in Figures 4A, 4B, 4C, and 4D. Figure 4A is a cross-sectional view along the aa' direction after the capacitor is formed, Figure 4B is a cross-sectional view along the bb' direction after the capacitor is formed, Figure 4C is a cross-sectional view along the cc' direction after the capacitor is formed, and Figure 4D is a cross-sectional view along the dd' direction after the capacitor is formed. The cross-sectional view along the dd' direction remains unchanged in subsequent steps and is no longer provided.

[0141] In some embodiments, the support layer film may be an insulating film layer different from the second insulating film ultimately filled between transistors, including but not limited to silicon nitride (SiN).

[0142] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, the dielectric film may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like. Exemplary materials include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0143] In some embodiments, the conductor material includes but is not limited to at least one of the following: metal, metal alloy, polysilicon, silicon-doped conductive layer, and metal oxide conductive layer.

[0144] In some embodiments, the second conductive film includes but is not limited to metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer, such as Poly-GiSe, etc.

[0145] The second capacitor electrode 42 may surround a sidewall of the first conductive portion 121 , and the second capacitor electrode 42 is insulated from the first conductive portion 121 by the dielectric layer 43 .

[0146] In some embodiments, the third insulating film includes but is not limited to silicon nitride (SiN).

[0147] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0148] In some embodiments, the fifth insulating film includes but is not limited to SiN.

[0149] 4) forming an initial through hole K0;

[0150] The forming of the initial through hole K0 may include: etching the stacked structure by dry etching to form a plurality of initial through holes K0 penetrating the stacked structure, wherein the side walls of the initial through holes K0 expose each of the conductive layer 12 and the sacrificial layer 9, and the aperture sizes of the initial through holes K0 in different layers are substantially consistent, and along the cc' direction, the size of the initial through hole K0 is smaller than the size of the first conductive portion 121, the initial through hole K0 does not disconnect the conductive layer 12, and all areas of the conductive layer 12 remain connected, as shown in Figures 5A, 5B and 5C, wherein Figure 5A is a cross-sectional view along the aa' direction after the initial through hole K0 is formed, Figure 5B is a cross-sectional view along the bb' direction after the initial through hole K0 is formed, and Figure 5C is a cross-sectional view along the cc' direction after the initial through hole K0 is formed.

[0151] 5) Laterally etching the sacrificial layer 9;

[0152] The lateral etching of the sacrificial layer 9 may include: laterally etching the sacrificial layer 9 in the initial through hole K0 (etching in a direction parallel to the substrate 1), and stopping when the etching reaches the first insulating layer 10, that is, in the cc' direction, the sacrificial layer 9 is etched through, and the sidewall of the initial through hole K0 exposes the first insulating layer 10. At this time, in the aa' direction, the aperture d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 is larger than the aperture d1 of the second sub-hole of the initial through hole K0 located in the conductive layer 12; in the cc' direction, the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 is larger than the aperture d3 of the second sub-hole located in the conductive layer 12, and in the cc' direction, the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 is consistent with the size of the sacrificial layer 9 along the cc' direction, as shown in Figures 6A, 6B and 6C, wherein Figure 6A is a cross-sectional view along the aa' direction, Figure 6B is a cross-sectional view along the bb' direction, and Figure 6C is a cross-sectional view along the cc' direction.

[0153] 6) Laterally etching the first insulating layer 10 and the fourth insulating layer 14;

[0154] The lateral etching of the first insulating layer 10 and the fourth insulating layer 14 may include: lateral etching of the first insulating layer 10 and the fourth insulating layer 14 in the initial through hole K0, etching the first insulating layer 10 to a preset thickness h, for example, 5 nm to 15 nm, and the etching thickness is less than the thickness of the first insulating layer 10 along the cc' direction, so as to avoid the initial through holes K0 of the same layer from being connected, resulting in the connection of the film layers of adjacent transistors, as shown in Figures 7A, 7B and 7C, wherein Figure 7A is a cross-sectional view along the aa' direction, Figure 7B is a cross-sectional view along the bb' direction, and Figure 7C is a cross-sectional view along the cc' direction.

[0155] At this point, the diameter d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the cc' direction is further expanded, that is, the expanded size is twice the thickness of the etched first insulating layer 10, that is, h*2. The diameter d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the aa' direction remains unchanged. The diameters d1 and d3 of the second sub-hole of the initial through hole K0 located in the conductive layer 12 remain unchanged.

[0156] 7) Laterally etching the conductive layer 12;

[0157] The lateral etching of the conductive layer 12 may include: lateral etching of the conductive layer 12 so that the first conductive portion 121 is disconnected from the second conductive portion 122, as shown in Figures 8A, 8B and 8C, wherein Figure 8A is a cross-sectional view along the aa' direction after the lateral etching of the conductive layer 12, Figure 8B is a cross-sectional view along the bb' direction after the lateral etching of the conductive layer 12, and Figure 8C is a cross-sectional view along the cc' direction after the lateral etching of the conductive layer 12.

[0158] As shown in Figure 8C, at this time, there is no conductive layer 12 on the cross-section in the cc' direction, that is, in the cc' direction, the aperture d3 of the second sub-hole of the initial through hole K0 located in the conductive layer 12 is consistent with the size of the first conductive part 121 along the cc' direction, but is still smaller than the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the cc' direction; in the aa' direction, the aperture d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 can be equal to the aperture d1 of the second sub-hole of the initial through hole K0 located in the conductive layer 12.

[0159] At this point, the etching of the initial through hole K0 is completed, and it is called through hole K1; in the aa' direction, the orthographic projection of the second sub-hole of the through hole K1 located in the conductive layer 12 on the substrate 1 can overlap with the orthographic projection of the first sub-hole of the through hole K1 located in the conductive sacrificial layer 9 on the substrate 1; in the cc' direction, the orthographic projection of the second sub-hole on the substrate 1 falls within the orthographic projection of the first sub-hole on the substrate 1, that is, in the cc' direction, there is an aperture difference between the sub-holes of the through hole K1 in the conductive layer 12 and the sacrificial layer 9, which facilitates the subsequent exposure of the semiconductor layer 23 located in the first sub-hole.

[0160] 8) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0161] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 may include:

[0162] A semiconductor film, a gate insulating film and a gate electrode film are sequentially deposited in the through hole K1 and polished to form a semiconductor layer 23, a gate insulating layer 24 and a word line 40. The gate electrode film fills the through hole K1, as shown in Figures 9A, 9B and 9C, wherein Figure 9A is a cross-sectional view along the aa' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed, Figure 9B is a cross-sectional view along the bb' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed, and Figure 9C is a cross-sectional view along the cc' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed.

[0163] In some embodiments, the semiconductor film, the gate insulating film, and the gate electrode film may be deposited by ALD.

[0164] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap smaller than 2 eV, or may be a wide band gap material, such as a metal oxide material with a band gap larger than 2 eV.

[0165] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0166] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0167] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0168] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0169] In exemplary embodiments of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of a High-K dielectric material. In some embodiments, the gate insulating layer 24 may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like. Exemplary materials include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), titanium oxide (TiO2), and other high-K materials.

[0170] In some embodiments, the gate electrode film may be made of one or more of the following different types of materials:

[0171] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0172] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0173] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0174] 9) forming a fifth trench T5;

[0175] The forming of the fifth trench T5 may include: etching the stacked structure from the top layer to the bottom layer (excluding the substrate 1) using dry etching to form a plurality of fifth trenches T5, exposing the sidewalls of the sacrificial layer 9 and exposing a portion of the semiconductor layer 23 located in the first sub-hole, as shown in Figures 10A, 10B, 10C and 10D, wherein Figure 10A is a plan schematic diagram of the mask pattern for forming the fifth trench T5, Figure 10B is a cross-sectional view along the aa' direction after the fifth trench T5 is formed, Figure 10C is a cross-sectional view along the bb' direction after the fifth trench T5 is formed, and Figure 10D is a cross-sectional view along the cc' direction after the fifth trench T5 is formed. The mask pattern includes a first region 101, a second region 102, a third region 103 and a fourth region 104. The first region 101 corresponds to the capacitor region 200, and the second region 102 corresponds to the region where the bit line 30 is located. The regions where the capacitor region 200 and the bit line 30 are located are both covered to avoid being etched. The third region 103 corresponds to the region where the word line 40, the gate insulating layer 24, and the semiconductor layer 23 located in the second sub-hole are located. The fourth region 104 corresponds to the region where the first electrode 51 is located. The width s1 of the fourth region 104 can be the dimension of the first electrode 51 along the direction parallel to cc'. The width s2 of the third region 103 can be the aperture d4 of the first sub-hole of the through hole K1 in the sacrificial layer 9 along the direction cc'. The length s3 can be the dimension of the semiconductor layer 23 located in the first sub-hole along the direction parallel to aa', so that the semiconductor layer 23 located in the first sub-hole and parallel to the aa' direction can be completely exposed.

[0176] 10) etching the sacrificial layer 9;

[0177] The etching of the sacrificial layer 9 may include: removing the remaining sacrificial layer 9 by wet etching to expose the semiconductor layer 23 located in the first sub-hole and parallel to the cc' direction, so that the semiconductor layer 23 located in the first sub-hole is exposed, which facilitates the subsequent removal of the semiconductor layer 23 located in the first sub-hole, as shown in Figures 11A, 11B and 11C, wherein Figure 11A is a cross-sectional view along the aa' direction after etching the sacrificial layer 9, Figure 11B is a cross-sectional view along the bb' direction after etching the sacrificial layer 9, and Figure 11C is a cross-sectional view along the cc' direction after etching the sacrificial layer 9.

[0178] 11) etching the semiconductor layer 23 located in the first sub-hole;

[0179] Etching the semiconductor layer 23 in the first sub-hole may include removing the exposed semiconductor layer 23 in the first sub-hole by wet etching, as shown in Figures 12A, 12B, and 12C. Figure 12A is a cross-sectional view taken along the aa' direction after etching the semiconductor layer 23 in the first sub-hole, Figure 12B is a cross-sectional view taken along the bb' direction after etching the semiconductor layer 23 in the first sub-hole, and Figure 12C is a cross-sectional view taken along the cc' direction after etching the semiconductor layer 23 in the first sub-hole. It can be seen that the semiconductor layers 23 of different transistors are disconnected, thereby eliminating parasitic semiconductor layers between layers.

[0180] 12) forming a second insulating layer 11;

[0181] The formation of the second insulating layer 11 may include: depositing a second insulating film on the substrate 1 forming the aforementioned structure to form a second insulating layer 11 filling the area where the sacrificial layer 9 is located and the area where the semiconductor layer 23 is etched, as shown in Figures 13A, 13B and 13C, wherein Figure 13A is a cross-sectional view along the aa' direction after the second insulating layer 11 is formed, Figure 13B is a cross-sectional view along the bb' direction after the second insulating layer 11 is formed, and Figure 13C is a cross-sectional view along the cc' direction after the second insulating layer 11 is formed.

[0182] In some embodiments, the second insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0183] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes multiple layers of transistors stacked in a direction perpendicular to a substrate, and word lines extending in a direction perpendicular to the substrate through different layers. The transistors include a first electrode and a second electrode. The method for manufacturing the semiconductor device includes:

[0184] Providing a substrate, alternately depositing sacrificial layer films and conductive films on the substrate, and patterning to form a plurality of stacked structures, each of the stacked structures comprising a stack of a plurality of sacrificial layers and a plurality of conductive layers alternately arranged to form a predetermined pattern, and a first insulating layer forming a complementary pattern to the predetermined patterns of each sacrificial layer and each conductive layer; the predetermined pattern of the conductive layer comprises a first electrode and a second electrode of the transistor to be formed;

[0185] forming a through hole that simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure in a direction perpendicular to the substrate, the through hole exposing the first insulating layer covering the conductive layer and the sacrificial layer, the through hole comprising a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, the first insulating layer having a recessed area at the first sub-holes, and the second sub-holes disconnecting the first electrode from the second electrode in the conductive layer;

[0186] Depositing a semiconductor film, a gate insulating film, and a gate electrode film filling the through hole in sequence in the through hole to form a plurality of semiconductor layers and gate insulating layers of the transistor, as well as a word line; wherein the semiconductor layer is connected to the first electrode and the second electrode corresponding to each layer of transistors;

[0187] Etching the first insulating layer and each of the sacrificial layers outside the through hole to expose the semiconductor layer located in each of the first sub-holes;

[0188] The semiconductor layer located in the first sub-hole is removed by etching, so that semiconductor layers of transistors at different layers are disconnected.

[0189] In some embodiments, the sacrificial layer only exposes side walls in the first sub-hole, the conductive layer only exposes side walls in the second sub-hole, the recessed area of ​​the first insulating layer exposes side walls perpendicular to the substrate and a surface extending in a direction parallel to the substrate in the first sub-hole, and the first insulating layer only exposes side walls in the second sub-hole.

[0190] In some embodiments, forming a through hole that simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure in a direction perpendicular to the substrate comprises:

[0191] forming an initial through hole penetrating the stacked structure in a direction perpendicular to the substrate by dry etching the stacked structure in one process, wherein the initial through hole located in the conductive layer is completely surrounded by the conductive layer;

[0192] Using the conductive layer as a barrier layer, wet-etching the sacrificial layer in the initial through hole to increase the aperture of the initial through hole in the sacrificial layer until the first insulating layer is exposed;

[0193] Using the conductive layer and the sacrificial layer as barrier layers, wet-etching the exposed first insulating layer to increase the aperture of the corresponding area of ​​the first insulating layer, thereby obtaining the second sub-pore located in the sacrificial layer;

[0194] The conductive layer is wet-etched to increase the aperture of the initial through hole in the conductive layer, and the conductive layer is divided into two parts to expose the first insulating layer, thereby obtaining the first sub-hole in the conductive layer.

[0195] In some embodiments, etching the first insulating layer and each of the sacrificial layers to expose the semiconductor layer within the first sub-hole comprises:

[0196] dry-etching the first insulating layer outside the through hole to expose the sidewall of each sacrificial layer connected to the first insulating layer and the semiconductor layer located in the first sub-hole and connected to the first insulating layer;

[0197] The entire sacrificial layer is removed by wet etching to expose the semiconductor layer located in the first sub-hole and connected to the sacrificial layer.

[0198] In some embodiments, after etching away the semiconductor layer located in the first sub-hole so as to disconnect the semiconductor layers of transistors in different layers, the method further includes:

[0199] An insulating film is deposited to form a second insulating layer filling the etched sacrificial layer and the area where the first insulating layer is located.

[0200] In some embodiments, the sacrificial layer thin film includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer are silicon oxide.

[0201] The present disclosure also provides an electronic device comprising the semiconductor device of the aforementioned embodiment, or a semiconductor device formed using any of the aforementioned semiconductor device manufacturing methods. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include, for example, computer memory, and is not limited here.

[0202] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; The word line runs through different layers and extends in a direction perpendicular to the substrate; The transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the sidewall of the word line; the semiconductor layer comprises a first portion in contact with the first electrode and the second electrode, and a second portion located between the first electrode and the second electrode, the first portion extending only in a direction perpendicular to the substrate; the second portion comprises a first extension portion extending in a direction perpendicular to the substrate and a second extension portion extending from the first extension portion to a direction away from the sidewall of the word line and parallel to the substrate; The semiconductor layers of the transistors are physically disconnected from each other, and the semiconductor layers are distributed in different regions of the sidewall of the word line.

2. The semiconductor device according to claim 1, wherein Along a direction perpendicular to the substrate and perpendicular to an arrangement direction of the first electrode and the second electrode, a cross section of the semiconductor layer is U-shaped, and an opening of the U-shape faces a direction away from a side wall of the word line.

3. The semiconductor device according to claim 1, wherein The word line includes a vertical portion extending in a direction perpendicular to the substrate and a plurality of protruding portions extending from sidewalls of the vertical portion in a direction parallel to the substrate, wherein the protruding portions are located between the second portions of the semiconductor layer adjacent to each other in a direction perpendicular to the substrate.

4. The semiconductor device according to claim 2, wherein: The transistor further comprises a gate insulating layer; The semiconductor device further comprises: Insulating layers and conductive layers are alternately distributed in a direction perpendicular to the substrate; through holes penetrate each of the insulating layers and each of the conductive layers; The word line, the gate insulating layer surrounding the sidewall of the word line, and a plurality of semiconductor layers in different regions of the sidewall surrounding the gate insulating layer are sequentially distributed in the through hole from inside to outside; The first electrode and the second electrode are disposed on the conductive layer and are electrically connected to the semiconductor layer.

5. The semiconductor device according to claim 4, wherein: The U-shaped opening of the semiconductor layer is filled with a film layer made of the same material as the insulating layer.

6. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a first trench located between two adjacent transistors, wherein the first trench is filled with an isolation layer; The isolation layer has a protrusion in a region facing the second portion of the semiconductor layer; The first extension portion and the second extension portion of the semiconductor layer are disposed on the protruding portion.

7. A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of transistors stacked in a direction perpendicular to a substrate, a word line extending in a direction perpendicular to the substrate through the transistors in different layers, the transistor comprising a first electrode and a second electrode, the method for manufacturing the semiconductor device comprising: Providing a substrate, on which sacrificial layer films and conductive films are alternately deposited in sequence, and patterned to form a plurality of stacked structures, each of which comprises a stack of a plurality of sacrificial layers and a plurality of conductive layers alternately arranged to form a preset pattern, and a first insulating layer forming a complementary pattern to the preset pattern of each sacrificial layer and each conductive layer; The predetermined pattern of the conductive layer includes a first electrode and a second electrode of the transistor to be formed; A plurality of sacrificial layers and each of the sacrificial layers of the stacked structure are formed in a direction perpendicular to the substrate and penetrate through the stacked structure at the same time. The through hole of the conductive layer comprises a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, and the sacrificial layer only exposes the side wall in the first sub-hole, the conductive layer only exposes the side wall in the second sub-hole, the first insulating layer exposes the side wall and the surface extending in a direction parallel to the substrate in the first sub-hole, and the first insulating layer only exposes the side wall in the second sub-hole; and the second sub-hole disconnects the first electrode and the second electrode in the conductive layer; Depositing a semiconductor film, a gate insulating film and a gate electrode film filling the through hole in sequence in the through hole to form a semiconductor layer and a gate insulating layer of the transistor in multiple layers, as well as a word line; wherein the semiconductor layer is connected to the first electrode and the second electrode corresponding to each layer of transistors; Etching the first insulating layer and each of the sacrificial layers outside the through hole to expose the semiconductor layer located in each of the first sub-holes; The semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors at different layers.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The through hole formed in a direction perpendicular to the substrate and penetrating through each sacrificial layer and each conductive layer of the stacked structure comprises: Forming an initial through hole penetrating the stack structure in a direction perpendicular to the substrate by dry etching the stack structure in one process, wherein the initial through hole located in the conductive layer is completely surrounded by the conductive layer; Using the conductive layer as a barrier layer, wet-etching the sacrificial layer in the initial through hole to increase the aperture of the initial through hole in the sacrificial layer until the first insulating layer is exposed; Using the conductive layer and the sacrificial layer as barrier layers, wet-etching the exposed first insulating layer to increase the aperture of a corresponding area of ​​the first insulating layer, thereby obtaining a through hole located in the sacrificial layer; The aperture of the initial through hole in the conductive layer is increased by wet etching the conductive layer, and the conductive layer is divided into two parts to obtain a through hole located in the conductive layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: Etching the first insulating layer and each of the sacrificial layers to expose the semiconductor layer located in each of the first sub-holes comprises: dry-etching the first insulating layer outside the through hole to expose the sidewall of each sacrificial layer connected to the first insulating layer and the semiconductor layer located in the first sub-hole and connected to the first insulating layer; The entire sacrificial layer is removed by wet etching to expose the semiconductor layer located in the first sub-hole and connected to the sacrificial layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: After the semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors in different layers, the method further includes: An insulating film is deposited to form a second insulating layer filling the etched sacrificial layer and the area where the first insulating layer is located.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The sacrificial layer includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer include silicon oxide.

12. An electronic device, comprising the semiconductor device according to any one of claims 1 to 6, or comprising a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 7 to 11.

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