Ferroelectric memory cell, manufacturing method therefor, ferroelectric memory, and electronic device

Abstract

A ferroelectric memory cell, a manufacturing method therefor, a ferroelectric memory (100), and an electronic device. The ferroelectric memory cell comprises: a first electrode (10), a composite electrode (20), and a ferroelectric memory layer (30) provided between the first electrode (10) and the composite electrode (20). The composite electrode (20) comprises a conductive buffer layer (21), a conductive oxygen adsorption layer (22), and a second electrode (23). The Gibbs free energy of an oxide corresponding to the conductive oxygen adsorption layer (22) is less than that of an oxide corresponding to the first electrode (10). Hence, the conductive oxygen adsorption layer (22) can adsorb oxygen in an oxide layer (m0) formed between the first electrode (10) and the ferroelectric memory layer (30), so as to reduce the amount of oxygen in the oxide layer (m0), reducing the thickness of the oxide layer (m0), and inhibiting the continued formation of the oxide layer (m0). This configuration reduces the loss of retention characteristics and weakens the imprint effect, thereby improving the performance of the ferroelectric memory cell. In addition, the conductive buffer layer (21) can prevent direct contact between the conductive oxygen adsorption layer (22) and the ferroelectric memory layer (30), thereby preventing the inability to adsorb oxygen in the oxide layer (m0) or the weakening of oxygen adsorption in said layer.

Description

Ferroelectric memory cell, manufacturing method thereof, ferroelectric memory and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on August 14, 2023, with application number 202311023318.7 and application name “A ferroelectric memory cell, its manufacturing method, ferroelectric memory and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of storage technology, and in particular to a ferroelectric memory cell, a manufacturing method thereof, a ferroelectric memory, and an electronic device. Background Art

[0004] Ferroelectric memories offer advantages such as low read and write voltages, low power consumption, small device size, high read and write speeds, excellent cycling performance, strong radiation resistance, and non-volatility, making them promising candidates for building a new generation of non-volatile memories. Compared to traditional ferroelectric materials, hafnium-based ferroelectrics not only offer superior scaling properties but also overcome technical challenges and bottlenecks such as incompatibility with complementary metal oxide semiconductor (CMOS) processes, difficulties in scaling, and difficulty achieving high-density integration. Therefore, hafnium-based ferroelectric devices are expected to become the core unit of future new ferroelectric memories.

[0005] However, ferroelectric memories still have some problems, such as loss of retention characteristics and imprinting effects. Retention characteristics refer to the ability to maintain a certain polarization state. If the retention characteristics are lost, the polarization strength will decrease over time. This means that the stored data in the ferroelectric memory cell will become blurred over time, making it difficult to read the stored data accurately. The imprinting effect refers to the ferroelectric polarization being biased in a certain direction, which appears as a left or right shift of the hysteresis loop on the polarization loop. In the ferroelectric memory cell, it will make one storage state (assuming the data "1" is stored) more obvious, while the other storage state (corresponding to the data "0") is difficult to identify, causing misreading. Therefore, for ferroelectric memories, reducing the loss of retention characteristics and weakening the imprinting effect have become urgent problems to be solved.

[0006] Summary of the Invention

[0007] The present application provides a ferroelectric memory cell, a manufacturing method thereof, a ferroelectric memory and an electronic device, which are used to reduce the loss of retention characteristics in the ferroelectric memory, weaken the imprinting effect, and improve the performance of the ferroelectric memory.

[0008] In a first aspect, an embodiment of the present application provides a ferroelectric memory cell, which may include: a first electrode, a composite electrode, and a ferroelectric memory layer arranged between the first electrode and the composite electrode, the composite electrode including: a conductive buffer layer, a conductive oxygen absorption layer, and a second electrode arranged in sequence along a direction from the first electrode to the ferroelectric memory layer; wherein the Gibbs free energy (abbreviated as Gibs) of the oxide corresponding to the conductive oxygen absorption layer is less than the Gibs of the oxide corresponding to the first electrode, so that the adsorption capacity of the conductive oxygen absorption layer for oxygen is higher than the adsorption capacity of the first electrode for oxygen, so that the conductive oxygen absorption layer can adsorb oxygen in the oxide layer formed between the first electrode and the ferroelectric memory layer, and the oxygen vacancies in the ferroelectric memory layer can serve as an oxygen transmission channel to transmit oxygen from the oxide layer between the first electrode and the ferroelectric memory layer to the conductive oxygen absorption layer, thereby reducing the amount of oxygen in the oxide layer between the first electrode and the ferroelectric memory layer, thereby thinning the thickness of the oxide layer and inhibiting the continued formation of the oxide layer. Because the oxide layer weakens the retention characteristics and the imprinting effect, thinning the oxide layer can prevent the weakening of the retention characteristics, thereby reducing the loss of retention characteristics. It can also reduce the imprinting effect, thereby improving the performance of the ferroelectric memory cell. Furthermore, the provision of a conductive buffer layer can prevent the conductive oxygen absorber layer from directly contacting the ferroelectric memory layer, thereby preventing the conductive oxygen absorber layer from absorbing oxygen from the ferroelectric memory layer during direct contact, thereby preventing or reducing the absorption of oxygen from the oxide layer.

[0009] Furthermore, since the conductive oxygen-absorbing layer can absorb oxygen in the oxide layer between the first electrode and the ferroelectric storage layer, and the oxygen vacancies in the ferroelectric storage layer serve as oxygen transmission channels, the oxygen vacancies in the ferroelectric storage layer tend to migrate toward the oxide, thereby adjusting the distribution gradient of the oxygen vacancies in the ferroelectric storage layer, so that the density of the oxygen vacancies in the ferroelectric storage layer gradually increases along the direction from the composite electrode to the first electrode, which can also inhibit the continued formation of the oxide layer between the first electrode and the ferroelectric storage layer; of course, the first electrode can have a certain chemical decomposition effect on the oxide layer, which can also inhibit the continued formation of the oxide layer, thereby further improving the performance of the ferroelectric storage unit. It should be understood that the thermodynamic stability of the oxide in the ferroelectric storage layer is higher than the stability of the oxide corresponding to the first electrode, and the conductive oxygen-absorbing layer is more inclined to absorb oxygen from the less stable oxide, while the oxygen in the more stable oxide will not be absorbed or the amount of adsorption is so small that it can be ignored.

[0010] Exemplarily, the first electrode can be made of a conductive metal, metal oxide, metal nitride, or other material, and the first electrode can include one or more metal elements. When the first electrode includes multiple metals, the Gibs value of the oxide corresponding to the conductive oxygen-absorbing layer is smaller than the Gibs value of the oxide corresponding to each metal included in the first electrode. This allows the conductive oxygen-absorbing layer to absorb oxygen from the oxide corresponding to each metal in the first electrode, thereby reducing the thickness of the oxide between the first electrode and the ferroelectric memory layer, further improving the retention characteristics and reducing the imprinting effect, thereby enhancing the performance of the ferroelectric memory cell.

[0011] The conductive buffer layer may be made of at least one of TiN and TaN. Of course, other materials capable of performing the conductive buffer layer function are also applicable in the embodiments of the present application. Furthermore, the thickness of the conductive buffer layer may be set to 1 nm to 20 nm. Setting the thickness of the conductive buffer layer within a suitable range can, on the one hand, prevent direct contact between the conductive oxygen-absorbing layer and the ferroelectric storage layer, and on the other hand, prevent the overall thickness of the ferroelectric storage unit from being too large, thereby avoiding an increase in the volume of the ferroelectric storage unit.

[0012] The conductive oxygen absorber layer may be made of at least one of yttrium, titanium, lanthanum, scandium, copper, aluminum, tantalum, and hafnium. Other materials capable of forming a conductive oxygen absorber are also applicable in the embodiments of the present application. Furthermore, the thickness of the conductive oxygen absorber layer may be set to 0.5 nm to 5 nm. Setting the conductive oxygen absorber layer to an appropriate thickness can, on the one hand, absorb oxygen from the oxide layer formed between the first electrode and the ferroelectric memory layer, thereby reducing the thickness of the oxide layer, and on the other hand, prevent the overall thickness of the ferroelectric memory cell from being too large, thereby preventing an increase in the volume of the ferroelectric memory cell.

[0013] Regarding the second electrode: The second electrode is made of a conductive material that does not contain oxygen. This allows the conductive oxygen-absorbing layer to fully absorb oxygen from the oxide layer between the first electrode and the ferroelectric memory layer, maximizing the effect of thinning the oxide layer, thereby further improving the retention characteristics of the ferroelectric memory layer, reducing the imprinting effect, and further enhancing the performance of the ferroelectric memory cell. Furthermore, under the action of an external force, stress can be applied to the ferroelectric memory layer via the first and second electrodes to promote crystallization of the material in the ferroelectric memory layer, facilitating the formation of a ferroelectric phase in the ferroelectric memory layer, and thus facilitating the formation of the ferroelectric memory cell. The thickness of the first electrode can be set to 1 nm to 100 nm, and the thickness of the second electrode can be set to 30 nm to 100 nm, so that the first and second electrodes can withstand external forces.

[0014] The composite electrode may further include a conductive adhesion layer disposed between the conductive oxygen absorbing layer and the second electrode. The conductive adhesion layer can increase the adhesion strength between the conductive oxygen absorbing layer and the second electrode, preventing the conductive oxygen absorbing layer from falling off the second electrode, thereby improving the reliability of the ferroelectric memory cell. The conductive adhesion layer can be made of at least one of TiN and TaN. Of course, other materials that can perform the function of a conductive adhesion layer are also applicable in the embodiments of the present application. Furthermore, the thickness of the conductive adhesion layer can be set to 1 nm to 20 nm. Setting the thickness of the conductive adhesion layer within a suitable range can, on the one hand, increase the adhesion strength between the conductive oxygen absorbing layer and the second electrode, and on the other hand, prevent the overall thickness of the ferroelectric memory cell from being too large, thereby avoiding an increase in the volume of the ferroelectric memory cell.

[0015] For the ferroelectric storage layer, its manufacturing material can be selected from doped hafnium oxide materials. For example, the manufacturing material of the ferroelectric storage layer can include: zirconium-doped hafnium oxide (such as Hf 0.5 Zr 0.5 O2), zirconium and lanthanum doped hafnium oxide (such as La doped Hf 0.5 Zr 0.5 O2), zirconium and yttrium-doped hafnium oxide (such as Y-doped Hf 0.5 Zr 0.5 O2), zirconium and strontium doped hafnium oxide (such as Sr doped Hf 0.5 Zr 0.5 O2), zirconium and gadolinium-doped hafnium oxide (such as Gd-doped Hf 0.5 Zr 0.5 O2), zirconium, gadolinium, lanthanum doped hafnium oxide (such as Gd / La co-doped Hf 0.5 Zr 0.5 O2), silicon-doped hafnium oxide (such as Si-doped HfO2), aluminum-doped hafnium oxide, lanthanum-doped hafnium oxide, yttrium-doped hafnium oxide, gadolinium-doped hafnium oxide, strontium-doped hafnium oxide, etc. In addition, the thickness of the ferroelectric storage layer can be set to 1nm to 100nm. Setting the thickness of the ferroelectric storage layer within a suitable range can, on the one hand, be conducive to the formation of the ferroelectric phase and avoid the ferroelectric phase being difficult to form due to the ferroelectric storage layer being too thick. On the other hand, it can avoid the overall thickness of the ferroelectric storage unit being too large, thereby avoiding an increase in the volume of the ferroelectric storage unit.

[0016] Exemplarily, the ferroelectric memory cell may include: a transistor and a storage capacitor. The storage scheme provided in the embodiment of the present application can be applied to the storage capacitor, that is, the first electrode, the ferroelectric storage layer and the composite electrode can form a storage capacitor. Moreover, when the ferroelectric memory cell is arranged on the substrate, the first electrode, the ferroelectric storage layer and the composite electrode can be stacked in a direction perpendicular to the surface of the substrate, and the ferroelectric storage layer is arranged between the first electrode and the composite electrode. In this case, the storage capacitor can be regarded as a storage capacitor with a two-dimensional structure. Alternatively, the first electrode and the insulating layer can be alternately stacked in a direction perpendicular to the surface of the substrate to form a stacked structure, and then a through hole is dug in the stacked structure, the through hole passes through the stacked structure along the stacking direction, and then the ferroelectric storage layer and the composite electrode are filled in the through hole in sequence, the ferroelectric storage layer is arranged between the stacked structure and the composite electrode, and the stacking direction of the conductive buffer layer, the conductive oxygen absorption layer and the second electrode in the composite electrode is perpendicular to the extension direction of the through hole. The storage capacitor formed at this time can be regarded as a storage capacitor with a three-dimensional structure.

[0017] In a second aspect, embodiments of the present application further provide a method for fabricating a ferroelectric memory cell. The ferroelectric memory cell fabricated by the fabrication method may be the ferroelectric memory cell described in the first aspect and any possible embodiment of the first aspect. The fabrication method may include: forming a first electrode; forming a ferroelectric memory layer on the first electrode; forming a conductive buffer layer on the ferroelectric memory layer; forming a conductive oxygen-absorbing layer on the conductive buffer layer, wherein the Gibbs free energy of the oxide corresponding to the conductive oxygen-absorbing layer is less than the Gibbs free energy of the oxide corresponding to the first electrode; and forming a second electrode on the conductive oxygen-absorbing layer, such that the conductive buffer layer, the conductive oxygen-absorbing layer, and the second electrode form a composite electrode. Thus, the conductive oxygen-absorbing layer can absorb oxygen in the oxide layer between the first electrode and the ferroelectric memory layer, and the oxygen vacancies in the ferroelectric memory layer can serve as oxygen transport channels, transporting oxygen from the oxide layer between the first electrode and the ferroelectric memory layer to the conductive oxygen-absorbing layer. This can reduce the amount of oxygen in the oxide layer between the first electrode and the ferroelectric memory layer, thereby reducing the thickness of the oxide layer and inhibiting further formation of the oxide layer. Because the oxide layer weakens the retention characteristics and the imprinting effect, thinning the oxide layer can prevent the weakening of the retention characteristics, thereby reducing the loss of retention characteristics. It can also reduce the imprinting effect, thereby improving the performance of the ferroelectric memory cell. Furthermore, the provision of a conductive buffer layer can prevent the conductive oxygen absorber layer from directly contacting the ferroelectric memory layer, thereby preventing the conductive oxygen absorber layer from absorbing oxygen from the ferroelectric memory layer during direct contact, thereby preventing or reducing the absorption of oxygen from the oxide layer.

[0018] For example, when the ferroelectric memory cell further includes a conductive adhesion layer disposed between the conductive oxygen absorbing layer and the second electrode, the manufacturing method may further include: forming a conductive adhesion layer on the conductive oxygen absorbing layer after forming the conductive oxygen absorbing layer and before forming the second electrode. The conductive adhesion layer can increase the adhesion strength between the conductive oxygen absorbing layer and the second electrode, preventing the conductive oxygen absorbing layer from falling off the second electrode, thereby improving the reliability of the ferroelectric memory cell.

[0019] When manufacturing the first electrode, the ferroelectric storage layer, and the composite electrode, physical vapor deposition or chemical vapor deposition can be used, and the manufacturing methods used for each film layer can be the same or different, and can be selected according to actual needs. In addition, in order to obtain the ferroelectric storage layer, the manufacturing method can also include: heat treating the formed ferroelectric storage layer. The specific heat treatment process can include: heating the formed ferroelectric storage layer, and when the temperature is raised to a first temperature, rapidly cooling it to a second temperature, wherein the first temperature is greater than the second temperature. By heating and cooling, the ferroelectric storage layer can exhibit ferroelectric properties, thereby realizing the function of the ferroelectric storage unit. Among them, the selection of the first temperature and the second temperature can be set according to the manufacturing material of the ferroelectric storage layer, and is not limited here. In addition, the heat treatment process can be performed after the ferroelectric storage layer is formed and before the composite electrode is formed, or it can be performed after the composite electrode is formed, or it can be performed after any layer in the composite electrode is formed, as long as the ferroelectric storage layer can exhibit ferroelectric properties, and the execution time of the heat treatment is not limited here.

[0020] For example, when the storage solution provided in the embodiments of the present application is applied to a storage capacitor, and the storage capacitor has a three-dimensional structure, the formation of the first electrode may specifically include: forming alternating first electrodes and insulating layers to obtain a stacked structure; forming a through hole in the stacked structure, the through hole penetrating the stacked structure along the stacking direction; thereby allowing the subsequently formed ferroelectric storage layer and composite electrode to be formed within the through hole, thereby obtaining a three-dimensional storage capacitor. The insulating layer can be made of any material that can provide an insulating function, and is not limited here.

[0021] It should be understood that since the principle of solving the problem by the ferroelectric memory unit manufactured by this manufacturing method is similar to the principle of solving the problem by the aforementioned ferroelectric memory unit, the embodiments and technical effects of this manufacturing method can refer to the embodiments and technical effects of the aforementioned ferroelectric memory unit, and the repeated parts will not be repeated.

[0022] In a third aspect, an embodiment of the present application further provides a ferroelectric memory, which may include: a storage array and a controller coupled to the storage array, wherein the storage array includes a plurality of ferroelectric memory cells as described in the first aspect and any possible embodiment of the first aspect, wherein the plurality of ferroelectric memory cells are deployed in an array manner; a storage array for storing data; and a controller for writing data to the storage array or reading data from the storage array. In this way, on the basis of reducing the loss of the retention characteristics of the ferroelectric memory cells and weakening the imprinting effect, the loss of the retention characteristics of the ferroelectric memory is also reduced and the imprinting effect is also weakened, thereby improving the performance of the ferroelectric memory. Since the principle of solving the problem of the ferroelectric memory is similar to the principle of solving the problem of the aforementioned ferroelectric memory cell, the embodiments and technical effects of the ferroelectric memory can refer to the embodiments and technical effects of the aforementioned ferroelectric memory cell, and the repeated parts will not be repeated.

[0023] Exemplarily, when a ferroelectric memory cell includes a transistor and at least one storage capacitor, the ferroelectric memory may further include: a word line, a bit line, and at least one control line. When the ferroelectric memory cells in the memory array are arranged in an array manner, the ferroelectric memory cells in the same row can be connected to the same word line, while the ferroelectric memory cells in different rows are connected to different word lines, so that different word lines can control the conduction and disconnection of transistors in the ferroelectric memory cells in different rows. Ferroelectric memory cells in the same column can be connected to the same bit line, while the ferroelectric memory cells in different columns are connected to different bit lines, so that different bit lines can provide voltage to the ferroelectric memory cells in different rows. Each control line is respectively connected to the second end of each storage capacitor in each ferroelectric memory cell. In other words, each ferroelectric memory cell is connected to each control line. The number of control lines provided is the same as the number of storage capacitors in the ferroelectric memory cell, and they are provided in a one-to-one correspondence. Thus, each ferroelectric memory cell can be precisely controlled through the word lines and bit lines, and data can be precisely written and read under the action of the voltage provided by each control line.

[0024] In a fourth aspect, embodiments of the present application further provide an electronic device, which may include: a circuit board, and a ferroelectric memory as described in the second aspect and any possible embodiment of the second aspect, wherein the ferroelectric memory is disposed on the circuit board. Thus, based on the improved performance of the ferroelectric memory, the performance of the electronic device is also improved. Since the principles for solving problems in the electronic device are similar to those for solving problems in the aforementioned ferroelectric memory, the embodiments and technical effects of the electronic device can be referenced to the embodiments and technical effects of the aforementioned ferroelectric memory, and any repetitions will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0026] FIG2 is a schematic diagram of the structure of a ferroelectric memory provided in an embodiment of the present application;

[0027] FIG3 is a schematic structural diagram of a ferroelectric memory cell provided in an embodiment of the present application;

[0028] FIG4 is a schematic diagram of the principle provided by an embodiment of the present application;

[0029] FIG5 is a schematic structural diagram of another ferroelectric memory cell provided in an embodiment of the present application;

[0030] FIG6 is a schematic structural diagram of another ferroelectric memory cell provided in an embodiment of the present application;

[0031] FIG7 is a schematic structural diagram of another ferroelectric memory cell provided in an embodiment of the present application;

[0032] FIG8 is a schematic diagram of a manufacturing process of a ferroelectric memory cell provided in an embodiment of the present application;

[0033] FIG9 is a schematic diagram of a manufacturing process of another ferroelectric memory cell provided in an embodiment of the present application;

[0034] FIG10 is a schematic diagram of a manufacturing process of another ferroelectric memory cell provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0036] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrating relative positional relationships and do not represent true proportions.

[0037] In order to facilitate understanding of the technical solutions provided by the embodiments of the present application, the application scenarios provided by the embodiments of the present application are first explained below.

[0038] The storage solution provided in the embodiments of the present application can be widely used in devices with storage functions, for example, it can be applied to storage devices with only storage functions, such as ferroelectric memory, and can also be applied to electronic devices with storage functions and other functions (such as read and write functions). The electronic device can be a portable electronic device that includes functions such as a personal digital assistant and / or a music player, such as a mobile phone, a tablet computer, a wearable device with wireless communication functions (such as a smart watch), or a car-mounted device. Exemplary embodiments of portable electronic devices include but are not limited to devices equipped with Or a portable electronic device with other operating systems. The portable electronic device may also be a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of the present application, the electronic device may also be a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0039] FIG1 exemplarily illustrates a schematic structural diagram of a ferroelectric memory device used in an electronic device. Referring to FIG1 , the electronic device includes a housing 300 and a circuit board 200 disposed within the housing 300, with a ferroelectric memory device 100 disposed on the circuit board 200. The ferroelectric memory device 100 may be a non-volatile memory device. The non-volatile memory device may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory device. It should be noted that the memory devices described herein are intended to include, but are not limited to, these and any other suitable types of memory devices.

[0040] FIG2 exemplarily illustrates a schematic diagram of the internal structure of a ferroelectric memory 100 applicable to embodiments of the present application. It should be understood that the illustrated ferroelectric memory 100 is merely an example, and that the ferroelectric memory 100 may have more or fewer components than shown, may combine two or more components, or may have a different component configuration. The various components shown in the figure may be implemented in hardware, including one or more signal processing and / or application-specific integrated circuits, software, or a combination of hardware and software.

[0041] As shown in FIG2 , ferroelectric memory 100 may include a memory array 110 and a controller 120. Memory array 110 is used to store data and is a matrix array composed of multiple ferroelectric memory cells arranged in rows and columns. Each ferroelectric memory cell can store one or more bits of binary data, such as "0" and / or "1." The multiple ferroelectric memory cells may be located on different tracks of the same disk or on different disks, without limitation. Controller 120 is used to read or write data from memory array 110 and is a device with control capabilities. Controller 120 may be connected to memory array 110, for example, via a bus connection. Controller 120 may include multiple functional components, including but not limited to driver circuits, decoding circuits, and amplifier circuits. These functional components may be provided as separate devices, implemented in a single device, or provided in any combination of at least two devices, without limitation.

[0042] 2 , the controller 120 can also be connected to an external device 400, which can be, for example, a read / write device or a processor. When reading / writing data, the external device 400 can send a read / write request to the controller 120, which carries the row address information and column address information of the target ferroelectric memory cell to be read / written. The controller 120 decodes the row address information in the read / write request to determine the row where the target ferroelectric memory cell is located, and turns on all ferroelectric memory cells corresponding to the row where the target ferroelectric memory cell is located by decoding the selection signal, and then decodes the column address information in the read / write request to obtain the column where the target ferroelectric memory cell is located, and then reads the data stored in the target ferroelectric memory cell at the column and sends it to the external device 400, or writes the data to be written sent by the external device 400 into the target ferroelectric memory cell at the column.

[0043] Although not shown in FIG. 2 , the ferroelectric memory 100 may further include other components, such as a main memory data register (MDR) and a main memory address register (MAR), which are not described in detail here.

[0044] In order to reduce the loss of retention characteristics in ferroelectric memory, weaken the imprinting effect, and improve the performance of ferroelectric memory, an embodiment of the present application provides a ferroelectric memory cell, as shown in Figure 3, which is a structural schematic diagram of the ferroelectric memory cell in the embodiment of the present application. The ferroelectric memory cell may include: a first electrode 10, a composite electrode 20, and a ferroelectric memory layer 30 arranged between the first electrode 10 and the composite electrode 20. The composite electrode 20 includes: a conductive buffer layer 21, a conductive oxygen absorption layer 22, and a second electrode 23 arranged in sequence along the direction from the first electrode 10 to the ferroelectric memory layer 30 (that is, the z direction shown in Figure 3); wherein the Gibs of the oxide corresponding to the conductive oxygen absorption layer 22 is less than the Gibs of the oxide corresponding to the first electrode 10.

[0045] 4 , the Gibs of the oxide corresponding to the conductive oxygen-absorbing layer 22 is smaller than the Gibs of the oxide corresponding to the first electrode 10 , so that the oxygen adsorption capacity of the conductive oxygen-absorbing layer 22 is higher than that of the first electrode 10 , so that the conductive oxygen-absorbing layer 22 can adsorb oxygen in the oxide layer m0 formed between the first electrode 10 and the ferroelectric storage layer 30 (as shown by the black circles in FIG4 ), and the oxygen vacancies in the ferroelectric storage layer 30 (as shown by the grid-filled circles in FIG4 ) can serve as oxygen transmission channels, and transmit oxygen from the oxide layer m0 between the first electrode 10 and the ferroelectric storage layer 30 to the conductive oxygen-absorbing layer 22 . The dotted arrows in FIG4 indicate that the oxygen in the oxide layer m0 migrates upward through the transmission channel, which can reduce the amount of oxygen in the oxide layer m0 between the first electrode 10 and the ferroelectric storage layer 30, thereby reducing the thickness of the oxide layer m0 and inhibiting the further formation of the oxide layer m0. Since the oxide layer m0 has the effect of weakening the retention characteristics and the imprinting effect, thinning the oxide layer m0 can avoid weakening the retention characteristics, thereby reducing the loss of the retention characteristics, and can also weaken the imprinting effect, thereby improving the performance of the ferroelectric memory cell. In addition, the provision of the conductive buffer layer 21 can prevent the conductive oxygen-absorbing layer 22 from directly contacting the ferroelectric memory layer 30, thereby preventing the conductive oxygen-absorbing layer 22 from absorbing oxygen from the ferroelectric memory layer 30 during direct contact and thus preventing or weakening the adsorption of oxygen from the oxide layer m0. In addition, because the oxide formed by the conductive oxygen-absorbing layer 22 after oxygen absorption has a large oxygen solubility and a positive Gibs change value, the conductive oxygen-absorbing layer 22 can effectively adsorb oxygen from the oxide layer m0 between the first electrode 10 and the ferroelectric memory layer 30. Furthermore, since the conductive oxygen-absorbing layer 22 can absorb oxygen in the oxide layer m0 between the first electrode 10 and the ferroelectric storage layer 30, and the oxygen vacancies in the ferroelectric storage layer 30 serve as oxygen transmission channels, the oxygen vacancies in the ferroelectric storage layer 30 tend to migrate toward the oxide, thereby adjusting the distribution gradient of the oxygen vacancies in the ferroelectric storage layer 30, so that the density of oxygen vacancies in the ferroelectric storage layer 30 gradually increases along the direction from the composite electrode 20 to the first electrode 10 (such as the direction indicated by z' in Figure 4), which can also inhibit the continued formation of the oxide layer m0 between the first electrode 10 and the ferroelectric storage layer 30; of course, the first electrode 10 can play a certain chemical decomposition role on the oxide layer m0, which can also inhibit the continued formation of the oxide layer m0, thereby further improving the performance of the ferroelectric storage unit.

[0046] In this ferroelectric memory cell, the conductive oxygen absorber layer 22 can be made of at least one of yttrium, titanium, lanthanum, scandium, copper, aluminum, tantalum, and hafnium. Other materials that can achieve the desired function of the conductive oxygen absorber layer 22 are also applicable in the embodiments of the present application. Furthermore, the thickness of the conductive oxygen absorber layer 22 (as shown by d1 in FIG. 3 ) can be set to 0.5 nm to 5 nm. This can reduce the thickness of the oxide layer m0 while also preventing the overall thickness of the ferroelectric memory cell from being too large, thereby preventing an increase in the volume of the ferroelectric memory cell. The conductive buffer layer 21 can be made of at least one of TiN and TaN. Other materials that can achieve the desired function of the conductive buffer layer 21 are also applicable in the embodiments of the present application. Furthermore, the thickness of the conductive buffer layer 21 (as shown by d2 in FIG. 3 ) can be set to 1 nm to 20 nm. This can prevent the conductive oxygen absorber layer 22 from directly contacting the ferroelectric memory layer 30 while also preventing the overall thickness of the ferroelectric memory cell from being too large. The material used to make the second electrode 23 includes a conductive material, and the conductive material does not contain oxygen elements. In this way, the conductive oxygen absorption layer 22 can fully absorb oxygen in the oxide layer m0 between the first electrode 10 and the ferroelectric storage layer 30, and maximize the effect of thinning the thickness of the oxide layer m0; and the thickness of the first electrode 10 can be set to 1nm to 100nm, and the thickness of the second electrode 23 can be set to 30nm to 100nm, so that the first electrode 10 and the second electrode 23 can withstand the action of external force, which is conducive to the formation of a ferroelectric phase in the ferroelectric storage layer 30.

[0047] The material for the ferroelectric storage layer 30 may be a doped hafnium oxide material. For example, the material for the ferroelectric storage layer 30 may include: zirconium-doped hafnium oxide (such as Hf 0.5 Zr 0.5 O2), zirconium and lanthanum doped hafnium oxide (such as La doped Hf 0.5 Zr 0.5 O2), zirconium and yttrium-doped hafnium oxide (such as Y-doped Hf 0.5 Zr 0.5 O2), zirconium and strontium doped hafnium oxide (such as Sr doped Hf 0.5 Zr 0.5 O2), zirconium and gadolinium-doped hafnium oxide (such as Gd-doped Hf 0.5 Zr 0.5 O2), zirconium, gadolinium, lanthanum doped hafnium oxide (such as Gd / La co-doped Hf 0.5 Zr 0.5O2), silicon-doped hafnium oxide (such as Si-doped HfO2), aluminum-doped hafnium oxide, lanthanum-doped hafnium oxide, yttrium-doped hafnium oxide, gadolinium-doped hafnium oxide, strontium-doped hafnium oxide, etc. In addition, the thickness of the ferroelectric storage layer 30 (as shown by d3 in Figure 3) can be set to 1nm to 100nm. Setting the thickness of the ferroelectric storage layer 30 within a suitable range can, on the one hand, be conducive to the formation of the ferroelectric phase and avoid the ferroelectric storage layer 30 being too thick, which makes it difficult to form the ferroelectric phase. On the other hand, it can avoid the overall thickness of the ferroelectric storage unit being too large, thereby avoiding increasing the volume of the ferroelectric storage unit.

[0048] The first electrode 10 can be made of a conductive metal, metal oxide, metal nitride, or other material, and the first electrode 10 can include one or more metal elements. When the first electrode 10 includes multiple metals, the Gibs value of the oxide corresponding to the conductive oxygen-absorbing layer 22 is smaller than the Gibs value of the oxide corresponding to each metal included in the first electrode 10. This allows the conductive oxygen-absorbing layer 22 to absorb oxygen from the oxide corresponding to each metal in the first electrode 10, thereby reducing the thickness of the oxide between the first electrode 10 and the ferroelectric memory layer 30, further improving the retention characteristics and reducing the imprinting effect, thereby improving the performance of the ferroelectric memory cell.

[0049] Exemplarily, a ferroelectric memory cell may include: a transistor and a storage capacitor. The storage solution provided in the embodiments of the present application may be applied to the storage capacitor, that is, the first electrode 10, the ferroelectric memory layer 30, and the composite electrode 20 may form a storage capacitor. Furthermore, when the ferroelectric memory cell is disposed on a substrate, the first electrode 10, the ferroelectric memory layer 30, and the composite electrode 20 may be stacked in a direction perpendicular to the substrate surface, with the ferroelectric memory layer 30 disposed between the first electrode 10 and the composite electrode 20. In this case, the storage capacitor may be considered as a storage capacitor having a two-dimensional structure.

[0050] FIG5 is a schematic diagram illustrating the structure of a memory cell according to an embodiment of the present application. As shown in FIG5 , the structure of the ferroelectric memory cell according to this embodiment is substantially similar to that of the ferroelectric memory cell according to the first embodiment, except that the structure of the composite electrode 20 is different. For example, the composite electrode 20 may further include a conductive adhesion layer 24 disposed between the conductive oxygen-absorbing layer 22 and the second electrode 23. The conductive adhesion layer 24 can increase the adhesion strength between the conductive oxygen-absorbing layer 22 and the second electrode 23, preventing the conductive oxygen-absorbing layer 22 and the second electrode 23 from falling off, thereby improving the reliability of the ferroelectric memory cell. The conductive adhesion layer 24 can be made of at least one of TiN and TaN. Of course, other materials that can achieve the function of the conductive adhesion layer 24 are also suitable in the embodiment of the present application. Furthermore, the thickness d4 of the conductive adhesion layer 24 can be set to 1 nm to 20 nm. Setting the thickness of the conductive adhesion layer 24 within a suitable range can not only increase the adhesion strength between the conductive oxygen-absorbing layer 22 and the second electrode 23, but also prevent the overall thickness of the ferroelectric memory cell from being too large, thereby preventing an increase in the volume of the ferroelectric memory cell.

[0051] It should be understood that the similarities between the structures of the ferroelectric memory cell in this embodiment and the ferroelectric memory cell in the aforementioned first embodiment can be found in the aforementioned first embodiment, and the repeated parts will not be repeated.

[0052] FIG6 is a schematic diagram illustrating the structure of a memory cell according to an embodiment of the present application. As shown in FIG6 , (b) is a cross-sectional view along the direction indicated by X1-X2 in (a). The structure of the ferroelectric memory cell in this embodiment is substantially similar to that of the ferroelectric memory cell in the first embodiment, except that the storage capacitor has a three-dimensional structure. For example, the first electrode 10 and the insulating layer m1 can be alternately stacked in a direction perpendicular to the surface of the substrate 40 (such as the z-direction shown in FIG6 ) to form a stacked structure m2. A through hole T is then formed in the stacked structure m2, extending through the stacked structure m2 along the stacking direction (such as the z-direction shown in FIG6 ). A ferroelectric memory layer 30 and a composite electrode 20 are then sequentially filled in the through hole T. The ferroelectric memory layer 30 is disposed between the stacked structure m2 and the composite electrode 20. In this case, the stacking direction (such as the x-direction or y-direction shown in FIG6 ) of the conductive buffer layer 21, the conductive oxygen-absorbing layer 22, and the second electrode 23 in the composite electrode 20 is perpendicular to the extending direction (such as the z-direction shown in FIG6 ). The storage capacitor formed in this manner can be considered a three-dimensional storage capacitor. Thus, the ferroelectric memory cell can be either a two-dimensional structure or a three-dimensional structure, expanding the application range of the ferroelectric memory cell. Furthermore, referring to FIG7 , FIG7 is another cross-sectional view along the direction indicated by X1-X2 in FIG6 (a), the ferroelectric memory layer 30, the composite electrode 20, and the filling layer 50 can fill the through hole T, and the filling layer 50 is provided on the side of the composite electrode 20 away from the ferroelectric memory layer 30, that is, the filling layer 50 is located on the side of the second electrode 23 away from the conductive oxygen-absorbing layer 22. The filling layer 50 can be made of an insulating material, which can reduce the material used to make the composite electrode 20. When the cost of the material used to make the composite electrode 20 is high and the cost of the material used to make the filling layer 50 is low, the manufacturing cost of the ferroelectric memory cell can be effectively reduced. Alternatively, referring to FIG6 , the ferroelectric memory layer 30 and the composite electrode 20 can fill the through hole T, that is, the composite electrode 20 fills the space in the through hole T not occupied by the ferroelectric memory layer 30. This can simplify the manufacturing steps and manufacturing process of the ferroelectric memory cell and improve manufacturing efficiency.

[0053] It should be understood that the similarities between the structures of the ferroelectric memory cell in this embodiment and the ferroelectric memory cell in the aforementioned first embodiment can be found in the aforementioned first embodiment, and the repeated parts will not be repeated.

[0054] FIG8 is a schematic diagram illustrating a first method for manufacturing a ferroelectric memory cell according to an embodiment of the present application. This embodiment is given by taking application to a storage capacitor having a two-dimensional structure as an example. As shown in FIG8 , the specific manufacturing process of the ferroelectric memory cell may include:

[0055] Step 1: As shown in FIG8 (a), a W film layer having a thickness of about 50 nm is deposited on the substrate using, but not limited to, metal W by chemical vapor deposition to form a first electrode;

[0056] Step 2: As shown in FIG8( b ), an atomic layer vapor deposition method is used, using but not limited to zirconium-doped hafnium oxide material, to deposit a HZO layer with a thickness of about 10 nm on the first electrode to form a ferroelectric memory layer;

[0057] In the zirconium-doped hafnium oxide material, the molar ratio of zirconium to hafnium is 1:1, but is not limited to 1:1. This is just used as an example for illustration.

[0058] Step 3: As shown in FIG8( c ), a TiN layer with a thickness of about 5 nm is deposited on the ferroelectric memory layer by atomic layer vapor deposition, using but not limited to TiN, to form a conductive buffer layer;

[0059] Step 4: As shown in (d) of FIG8 , a Y film layer having a thickness of about 3 nm is deposited on the conductive buffer layer using, but not limited to, metal Y (yttrium in Chinese) by physical vapor deposition to form a conductive oxygen-absorbing layer, such that the Gibbs free energy of the oxide corresponding to the conductive oxygen-absorbing layer (i.e., yttrium oxide) is less than the Gibbs free energy of the oxide corresponding to the first electrode (i.e., tungsten oxide);

[0060] Step 5: As shown in (e) of FIG8 , a W film layer having a thickness of about 50 nm is deposited on the conductive oxygen-absorbing layer by chemical vapor deposition using, but not limited to, metal W to form a second electrode, so that the conductive buffer layer, the conductive oxygen-absorbing layer, and the second electrode form a composite electrode;

[0061] Step 6: heat-treating the structure obtained in step 5 so that the ferroelectric storage layer exhibits ferroelectric properties.

[0062] It should be understood that the materials used in steps 1 to 5 above and the thickness of each film layer are not limited to those listed in this embodiment. This is merely an example for illustration. Other materials and other film layer thicknesses can be selected based on actual needs and are not limited here. Furthermore, the thickness of each film layer shown in FIG8 does not represent the actual thickness of the film layer. This only illustrates the positional relationship between the film layers and does not represent the actual size of the film layer.

[0063] FIG9 is a schematic diagram illustrating a second method for fabricating a ferroelectric memory cell according to an embodiment of the present application. As shown in FIG9 , the second method in this embodiment is substantially similar to the first method in the aforementioned embodiment, except that step s1 is added between steps 4 and 5. Specifically, step s1 may include: as shown in FIG9(e), using atomic layer vapor deposition (ALD) using, but not limited to, TiN, to deposit a TiN layer having a thickness of approximately 5 nm on the conductive oxygen-absorbing layer to form a conductive adhesion layer. This conductive adhesion layer can enhance the adhesion strength between the conductive oxygen-absorbing layer and the second electrode, preventing the conductive oxygen-absorbing layer from falling off the second electrode, thereby improving the reliability of the ferroelectric memory cell. Furthermore, step 5 in the aforementioned embodiment can be adaptively adjusted to: as shown in FIG9(f), using, but not limited to, metal W, to deposit a W film having a thickness of approximately 50 nm on the conductive adhesion layer to form the second electrode, thereby forming a composite electrode. The conductive buffer layer, the conductive oxygen-absorbing layer, the conductive adhesion layer, and the second electrode form a composite electrode.

[0064] It should be understood that (a) in Figure 9 of this embodiment is the same as (a) in Figure 8 of the aforementioned embodiment, (b) in Figure 9 of this embodiment is the same as (b) in Figure 8 of the aforementioned embodiment, (c) in Figure 9 of this embodiment is the same as (c) in Figure 8 of the aforementioned embodiment, and (d) in Figure 9 of this embodiment is the same as (d) in Figure 8 of the aforementioned embodiment. Therefore, the similarities between the second manufacturing method in this embodiment and the first manufacturing method in the aforementioned embodiment can be referred to the first manufacturing method in the aforementioned embodiment, and the repeated parts will not be repeated.

[0065] FIG10 is a schematic diagram exemplarily illustrating a third method for manufacturing a ferroelectric memory cell according to an embodiment of the present application. Referring to FIG10 , the third method in this embodiment is substantially similar to the first method in the aforementioned embodiment, with the following differences:

[0066] (1) Adjusting the above step 1 to: as shown in FIG10(a), using chemical vapor deposition, alternately depositing metal W film layers and insulating layers on the substrate to obtain a stacked structure m2, wherein the metal W film layer serves as the first electrode; wherein the stacked structure m2 includes multiple first electrodes and multiple insulating layers;

[0067] (2) adding a step s2 between the above steps 1 and 2, wherein the step s2 may include: as shown in FIG10(b), opening the stacked structure m2 by photolithography and high-aspect-ratio dry etching to obtain a columnar through-hole T having a diameter of about 50 nm, wherein the through-hole T penetrates the stacked structure m2 along the stacking direction;

[0068] (3) All the film layers formed in steps 2 to 5 are fabricated in the through hole T, as shown in (c) and (d) of FIG. 10 ;

[0069] (4) The conductive oxygen absorbing layer in step 4 is made of a titanium-aluminum alloy, i.e., TiAl;

[0070] (5) If the second electrode formed in the above step 5 does not fill the remaining space in the through hole T, it is necessary to continue to form a filling layer after forming the second electrode, and fill the unoccupied space in the through hole T with the filling layer, which is not shown in the figure; the manufacturing process of the filling layer includes: using chemical vapor deposition method, using insulating material, depositing an insulating layer m1 on the second electrode to fill the through hole T; the insulating material and the manufacturing material of the insulating layer m1 can be the same or different.

[0071] In this way, the storage capacitor obtained is a three-dimensional structure, which expands the application range of ferroelectric memory cells.

[0072] It should be understood that the similarities between the third manufacturing method in this embodiment and the first manufacturing method in the aforementioned embodiment can be referred to the first manufacturing method in the aforementioned embodiment, and the repeated parts will not be repeated.

[0073] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A ferroelectric memory cell, characterized in that: include: A first electrode, a composite electrode, and a ferroelectric storage layer arranged between the first electrode and the composite electrode, wherein the composite electrode comprises: a conductive buffer layer, a conductive oxygen absorption layer, and a second electrode arranged in sequence along a direction pointing from the first electrode to the ferroelectric storage layer; wherein the Gibbs free energy of the oxide corresponding to the conductive oxygen absorption layer is less than the Gibbs free energy of the oxide corresponding to the first electrode.

2. The ferroelectric memory cell according to claim 1, wherein: The conductive buffer layer is made of at least one of TiN and TaN.

3. The ferroelectric memory cell according to claim 1 or 2, characterized in that: The thickness of the conductive buffer layer is 1 nm-20 nm.

4. The ferroelectric memory cell according to any one of claims 1 to 3, characterized in that: The conductive oxygen absorbing layer is made of at least one of yttrium, titanium, lanthanum, scandium, copper, aluminum, tantalum and hafnium.

5. The ferroelectric memory cell according to any one of claims 1 to 4, characterized in that: The thickness of the conductive oxygen absorbing layer is 0.5 nm to 5 nm.

6. The ferroelectric memory cell according to any one of claims 1 to 5, characterized in that: The thickness of the second electrode is 30 nm to 100 nm.

7. The ferroelectric memory cell according to any one of claims 1 to 6, characterized in that: The second electrode is made of a conductive material, which does not contain oxygen.

8. The ferroelectric memory cell according to any one of claims 1 to 7, characterized in that: The composite electrode further comprises: a conductive adhesion layer disposed between the conductive oxygen absorbing layer and the second electrode.

9. The ferroelectric memory cell according to claim 8, characterized in that The conductive adhesion layer is made of at least one of TiN and TaN.

10. A method for manufacturing a ferroelectric memory cell according to any one of claims 1 to 9, characterized in that: include: forming a first electrode; forming a ferroelectric storage layer on the first electrode; forming a conductive buffer layer on the ferroelectric storage layer; forming a conductive oxygen absorption layer on the conductive buffer layer, wherein the Gibbs free energy of the oxide corresponding to the conductive oxygen absorption layer is smaller than the Gibbs free energy of the oxide corresponding to the first electrode; A second electrode is formed on the conductive oxygen absorbing layer, so that the conductive buffer layer, the conductive oxygen absorbing layer and the second electrode form a composite electrode.

11. The method according to claim 10, characterized in that Also includes: After forming the conductive oxygen gettering layer and before forming the second electrode, a conductive adhesive layer is formed on the conductive oxygen gettering layer.

12. A ferroelectric memory, characterized in that: include: A storage array and a controller coupled to the storage array, wherein the storage array includes a plurality of ferroelectric memory cells according to any one of claims 1 to 9, and the plurality of ferroelectric memory cells are arranged in an array manner; The storage array is used to store data; The controller is used to write data into the storage array or read data from the storage array.

13. An electronic device, characterized in that: include: A circuit board and a ferroelectric memory as claimed in claim 12, wherein the ferroelectric memory is arranged on the circuit board.

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