Circuit performance prediction method and related device

Abstract

The present application relates to the field of artificial intelligence, and particularly relates to a circuit performance prediction method and a related device. The method comprises: a circuit debugging apparatus acquires a circuit heterogeneous graph of a target circuit, wherein nodes in the circuit heterogeneous graph are pins of elements in the target circuit, and an edge between two nodes in the circuit heterogeneous graph represents that a signal transmission path is provided between the two pins corresponding to the two nodes; the circuit debugging apparatus divides the circuit heterogeneous graph to obtain a plurality of first sub-graphs; the circuit debugging apparatus inputs the plurality of first sub-graphs into a performance prediction model for processing, so as to obtain a cell delay and a net delay of each first sub-graph among the plurality of first sub-graphs; and the circuit debugging apparatus determines a timing slack of the circuit heterogeneous graph on the basis of the cell delays and the net delays of the plurality of first sub-graphs. By using the embodiments of the present application, the timing slack of the circuit can be accurately predicted, thereby improving the efficiency of circuit design.

Description

Circuit performance prediction method and related equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on August 14, 2023, with application number 202311023875.9 and invention name “Circuit Performance Prediction Method and Related Equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of AI, and in particular to a circuit performance prediction method and related equipment. Background Art

[0003] With the advancement of deep learning, especially large language models, the demand for faster, more efficient, and lower-energy chips is rapidly increasing. Limited by the lengthy process of complete chip design, even experienced chip design engineers often take months or even years to complete a design, from register-transfer level language to final layout. The design process encompasses multiple steps, including system design, logic synthesis, component placement, routing, and signature verification. The lack of high-performance chips and insufficient computing power have become bottlenecks hindering the further development of deep learning. To accelerate integrated circuit design, the introduction of artificial intelligence (AI) into chip design has become a hot topic. The application of AI in electronic design automation (EDA) is attracting attention from both academia and industry, and has been successfully applied in various areas, such as logic synthesis, component placement, routing, and power, performance, and area (PPA) estimation. The application of AI, particularly deep learning technology, in EDA has significantly reduced the time required for the entire chip design process while improving chip quality.

[0004] Timing characteristics, such as circuit delay and timing slack, are important metrics for evaluating chip designs. However, accurate timing estimates can only be obtained after component routing is complete. Routing is one of the most time-consuming steps in the complete chip design process. As integrated circuit designs become increasingly complex, timing constraints become increasingly difficult to meet during the physical design phase. Therefore, the concept of "shifting the algorithm left" has been proposed, which involves considering timing constraints earlier in the chip design process. For example, timing characteristics are considered early in the layout phase. However, the time overhead of repeatedly performing routing and static timing analysis (STA) to obtain timing characteristics during layout is unacceptable. Consequently, many analytical placers use half-perimeter wire lengths as an approximation of actual wire lengths. Furthermore, in timing-oriented placers (such as DREAMPlace 4.0), since timing slack cannot be directly represented, different weights are assigned to different nets during wire length optimization, indirectly incorporating timing slack into layout metrics. Therefore, many machine learning methods have been applied to estimate timing characteristics, such as delay and line length. These estimation results can be used to guide layout and achieve algorithm left shift.

[0005] Among these timing characteristics, timing slack is one of the most important, but its prediction remains a challenging problem. Predicting timing slack involves calculating the signal arrival time and requires signal propagation step by step along the timing path. In large-scale integrated circuits, timing paths are typically long, such as those containing hundreds of components and connections. This leads to problems with signal attenuation and error accumulation, making the prediction of timing slack more difficult. Currently, some traditional algorithms have been applied to the field of timing prediction, such as using machine learning methods such as support vector machines and random forests to estimate the timing characteristics of circuits after layout and before routing. However, the prediction results and accuracy are still far from the actual values, making them difficult to apply in production practice environments.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a circuit performance prediction method and related equipment. Adoption of the embodiments of the present application is conducive to accurately predicting the timing margin of the circuit, thereby helping to improve the efficiency of circuit design.

[0008] In a first aspect, embodiments of the present application provide a circuit performance prediction method, which is applied to a circuit debugging device. The method includes:

[0009] The circuit debugging device obtains a circuit heterogeneous graph of a target circuit, wherein the nodes in the circuit heterogeneous graph are pins of components in the target circuit, and the edge between two nodes in the circuit heterogeneous graph indicates that there is a signal transmission path between two pins corresponding to the two nodes; the circuit debugging device divides the circuit heterogeneous graph to obtain a plurality of first subgraphs; the circuit debugging device inputs the plurality of first subgraphs into a performance prediction model for processing to obtain the component delay and the wire network delay of each of the plurality of first subgraphs; the circuit debugging device determines the timing margin of the circuit heterogeneous graph based on the component delay and the wire network delay of the plurality of first subgraphs.

[0010] By dividing the target circuit's heterogeneous graph into multiple subgraphs, predicting component and net delays for each subgraph individually can avoid signal attenuation and error accumulation caused by long timing paths. The timing margin for the heterogeneous graph is then calculated using the component and net delays of multiple subgraphs, improving the accuracy of timing margin prediction. Furthermore, predicting component and net delays for each subgraph individually reduces the memory overhead of the circuit debugging device.

[0011] In conjunction with the first aspect, in one possible implementation, the circuit debugging apparatus divides the circuit heterogeneous graph to obtain multiple first subgraphs, including:

[0012] The circuit debugging device divides the nodes in the circuit heterogeneous graph into multiple layers based on the depth of the nodes in the circuit heterogeneous graph, wherein nodes belonging to the same layer have the same depth in the circuit heterogeneous graph; the circuit debugging device obtains multiple second subgraphs based on the layering results, each second subgraph includes nodes of consecutive layers, and any two second subgraphs in the multiple second subgraphs have no common nodes; the circuit debugging device adds filler nodes to the i-th second subgraph in the multiple second subgraphs to obtain the i-th first subgraph; the multiple first subgraphs include the i-th first subgraph; when i=1, the filler nodes of the i-th second subgraph include the last k-layer nodes adjacent to the i-th second subgraph; when i is greater than 1, the filler nodes of the i-th second subgraph include the last k-layer nodes and the adjacent first k-layer nodes adjacent to the i-th second subgraph, and when the i-th second subgraph is the last subgraph in the multiple second subgraphs, the filler nodes of the i-th second subgraph include the first k-layer nodes adjacent to the i-th second subgraph, where k is an integer greater than 0.

[0013] Based on the second subgraph obtained by division, the k-layer nodes adjacent to the second subgraph are used as the filling nodes of the second subgraph and input into the performance prediction model for prediction, which is beneficial to improving the accuracy of the component delay and line network delay of the predicted subgraph.

[0014] In combination with the first aspect, in one possible implementation, the second subgraph includes features of all nodes in the second subgraph, and the features of node A include the hierarchical features of node A, which are obtained by hierarchical encoding of the level to which node A belongs.

[0015] By encoding the level to which the node belongs, the hierarchical features of the node are obtained. When using the node features containing the hierarchical features for prediction, it is beneficial to improve the accuracy of predicting the component delay and line network delay of the subgraph.

[0016] In conjunction with the first aspect, in one possible implementation, the performance prediction model includes an encoder, a global pooling layer, multiple convolutional layers, a multi-head joint attention mechanism layer, and a multi-layer perceptron. The circuit debugging device inputs multiple first subgraphs into the performance prediction model for processing to obtain the component delay and line network delay of each of the multiple first subgraphs, including:

[0017] The circuit debugging device extracts features from each first subgraph through an encoder to obtain a first feature vector of each first subgraph; the circuit debugging device processes the first feature vector of each first subgraph through a global pooling layer to obtain a graph embedding vector of each first subgraph; the circuit debugging device concatenates the features of the nodes of each first subgraph with the graph embedding vector of each first subgraph to obtain a second feature vector of each first subgraph; the circuit debugging device processes the second feature vector of each first subgraph using multiple convolutional layers to obtain a third feature vector of each first subgraph; the circuit debugging device processes the third feature vector of each first subgraph using a multi-head joint attention mechanism layer to obtain the component delay of each first subgraph; the circuit debugging device processes the third feature vector of each first subgraph using a multi-layer perceptron to obtain the line network delay of each first subgraph.

[0018] In conjunction with the first aspect, in one possible implementation, the circuit debugging apparatus processes the second eigenvector of each first subgraph using multiple convolutional layers to obtain a third eigenvector of each first subgraph, including:

[0019] The circuit debugging device processes the fourth eigenvector through the jth convolution layer among multiple convolution layers to obtain a fifth eigenvector; wherein the fourth eigenvector includes the first features of all nodes of each first subgraph, and the fifth eigenvector includes the second features of all nodes of each first subgraph; the second feature of node v is determined based on the first feature and the intermediate feature of node v, and the intermediate feature is determined based on the first feature of node u, the first feature of node v, and the feature of the edge of node u pointing to node v; node v and the node u are two nodes in each first subgraph, when j is 1, the fourth eigenvector is the second eigenvector, and when the jth convolution layer is the last one of the multiple convolution layers, the third eigenvector is the fifth eigenvector.

[0020] In conjunction with the first aspect, in one possible implementation, the third eigenvector includes the input slew rate and load of all nodes in each first subgraph. The circuit debugging apparatus processes the third eigenvector of each first subgraph using a multi-head joint attention mechanism layer to obtain the component delay of each first subgraph, including:

[0021] The circuit debugging device queries a two-dimensional look-up table (LUT) based on the input slew rate and mounting of each node in all nodes in each first subgraph to obtain the key and value of each node, where the key of each node is the row index and column index corresponding to the input slew rate and mounting of the node in the two-dimensional LUT, and the value of each node is the query result of the query based on the input slew rate and mounting of the node in the two-dimensional LUT; the circuit debugging device inputs the key, value and query of each node into a multi-head joint attention module for processing to obtain the third feature of each node, where the query is the input slew rate and mounting of each node; the circuit debugging device splices and linearizes the third features of all nodes in each first subgraph to obtain the component delay of each first subgraph.

[0022] In a second aspect, an embodiment of the present application provides a circuit debugging device, comprising:

[0023] an acquisition unit, configured to acquire a circuit heterogeneous graph of a target circuit, wherein nodes in the circuit heterogeneous graph are pins of components in the target circuit, and an edge between two nodes in the circuit heterogeneous graph indicates that there is a signal transmission path between two pins corresponding to the two nodes;

[0024] a partitioning unit, configured to partition the circuit heterogeneous graph to obtain a plurality of first subgraphs;

[0025] a processing unit, configured to input the plurality of first subgraphs into a performance prediction model for processing, so as to obtain a component delay and a line network delay of each of the plurality of first subgraphs;

[0026] A determining unit is configured to determine a timing margin of the circuit heterogeneous graph based on component delays and net delays of the plurality of first subgraphs.

[0027] In conjunction with the second aspect, in one possible implementation, the division unit is specifically configured to:

[0028] The nodes in the circuit heterogeneous graph are divided into multiple layers based on the depth of the nodes in the circuit heterogeneous graph, wherein nodes belonging to the same layer have the same depth in the circuit heterogeneous graph; multiple second subgraphs are obtained based on the layering results, each second subgraph includes nodes of consecutive layers, and any two second subgraphs in the multiple second subgraphs have no common nodes; for the i-th second subgraph in the multiple second subgraphs, a filler node is added to the i-th second subgraph to obtain the i-th first subgraph; the multiple first subgraphs include the i-th first subgraph; when i=1, the filler node of the i-th second subgraph includes the last k-layer nodes adjacent to the i-th second subgraph; when i is greater than 1, the filler node of the i-th second subgraph includes the last k-layer nodes and the first k-layer nodes adjacent to the i-th second subgraph; when the i-th second subgraph is the last subgraph in the multiple second subgraphs, the filler node of the i-th second subgraph includes the first k-layer nodes adjacent to the i-th second subgraph, where k is an integer greater than 0.

[0029] In combination with the second aspect, in one possible implementation, the second subgraph includes features of all nodes in the second subgraph, and the features of node A include the hierarchical features of node A, which are obtained by hierarchical encoding of the level to which node A belongs.

[0030] In conjunction with the second aspect, in one possible implementation, the performance prediction model includes an encoder, a global pooling layer, multiple convolutional layers, a multi-head joint attention mechanism layer, and a multi-layer perceptron, and the processing unit is specifically used to:

[0031] Features of each first subgraph are extracted through an encoder to obtain a first feature vector of each first subgraph; the first feature vector of each first subgraph is processed through a global pooling layer to obtain a graph embedding vector of each first subgraph; the features of the nodes of each first subgraph are concatenated with the graph embedding vector of each first subgraph to obtain a second feature vector of each first subgraph; the second feature vector of each first subgraph is processed using multiple convolutional layers to obtain a third feature vector of each first subgraph; the third feature vector of each first subgraph is processed using a multi-head joint attention mechanism layer to obtain the component delay of each first subgraph; and the third feature vector of each first subgraph is processed using a multi-layer perceptron to obtain the line network delay of each first subgraph.

[0032] In conjunction with the second aspect, in one possible implementation, in the aspect of processing the second eigenvector of each first sub-image using multiple convolutional layers to obtain the third eigenvector of each first sub-image, the processing unit is specifically configured to:

[0033] The fourth eigenvector is processed by the jth convolutional layer among the multiple convolutional layers to obtain a fifth eigenvector; wherein the fourth eigenvector includes the first features of all nodes of each first subgraph, and the fifth eigenvector includes the second features of all nodes of each first subgraph; the second feature of node v is determined based on the first feature and the intermediate feature of node v, and the intermediate feature is determined based on the first feature of node u, the first feature of node v and the feature of the edge of node u pointing to node v; node v and the node u are two nodes in each first subgraph, when j is 1, the fourth eigenvector is the second eigenvector, and when the jth convolutional layer is the last one of the multiple convolutional layers, the third eigenvector is the fifth eigenvector.

[0034] In conjunction with the second aspect, in one possible implementation, the third eigenvector includes the input slew rate and load of all nodes in each first subgraph. When processing the third eigenvector of each first subgraph using the multi-head joint attention mechanism layer to obtain the element delay of each first subgraph, the processing unit is specifically configured to:

[0035] Based on the input slew rate and mount of each node in all nodes in each first subgraph, a two-dimensional LUT is queried to obtain the key and value of each node, where the key of each node is the row index and column index corresponding to the input slew rate and mount of the node in the two-dimensional LUT, and the value of each node is the query result of the query based on the input slew rate and mount of the node in the two-dimensional LUT; the key, value and query of each node are input into the multi-head joint attention module for processing to obtain the third feature of each node, where the query is the input slew rate and mount of each node; the third features of all nodes in each first subgraph are spliced ​​and linearized to obtain the component delay of each first subgraph.

[0036] In a third aspect, embodiments of the present application provide a circuit debugging device, comprising a processor and a memory. The memory is configured to store program code. The processor is configured to invoke the program code stored in the memory to execute the method provided in the first aspect or any possible implementation of the first aspect.

[0037] In a fourth aspect, an embodiment of the present application provides a computer storage medium comprising computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes a method as provided in any possible implementation of the first aspect or a method as provided in any possible implementation of the second aspect.

[0038] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when running on a computer, enables the computer to execute a method provided in any possible implementation of the first aspect, or a method provided in any possible implementation of the second aspect.

[0039] It is understood that the circuit debugging device described in the second or third aspect is used to execute any of the methods provided in the first aspect, and the computer storage medium described in the fourth aspect and the computer program product described in the fifth aspect are both used to implement any of the methods provided in the first aspect. Therefore, the beneficial effects that can be achieved can be referenced to the beneficial effects of the corresponding method and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0041] FIG2 is a schematic flow chart of a circuit diagram performance prediction method provided in an embodiment of the present application;

[0042] FIG3 is a schematic diagram of a circuit heterogeneous graph segmentation according to an embodiment of the present application;

[0043] FIG4 is a schematic diagram of a performance prediction model provided in an embodiment of the present application;

[0044] FIG5 is a schematic diagram of an encoder training method according to an embodiment of the present application;

[0045] FIG6 is a schematic diagram of a key value determination provided by an embodiment of the present application;

[0046] FIG7 is a schematic diagram provided in an embodiment of the present application;

[0047] FIG8 is a schematic structural diagram of a circuit debugging device provided in an embodiment of the present application;

[0048] FIG9 is a schematic structural diagram of another circuit debugging device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The terms "first", "second", "third" and "fourth" in the specification, claims and drawings of this application are used to distinguish different objects rather than to describe a specific order.

[0050] "Multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating the existence of three relationships. For example, "A and / or B" means: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0051] First, the terms related to this application are explained.

[0052] Timing slack, also known as timing slack, is defined as the difference between the required arrival time (RAT) and the arrival time (AT). A non-negative timing slack indicates that the timing requirements and constraints are met; a negative slack indicates that they are not.

[0053] A timing path is defined as a path formed by the directed connections between various components in a circuit. Signals propagate along a timing path from their starting point to their endpoint. The signal arrival time and required arrival time for each pin on the timing path are typically calculated, and the timing margin at the endpoint of the timing path is calculated based on this information.

[0054] The embodiments of the present application are described below with reference to the accompanying drawings.

[0055] Refer to Figure 1, which is a schematic diagram of an application scenario provided by an embodiment of the present application. As shown in Figure 1, a circuit debugging device obtains a circuit diagram; wherein, the circuit diagram is stored in the form of a LEF file or a DEF file. After obtaining the circuit diagram, the circuit debugging device preprocesses the circuit diagram, including design rule checking (DRC) and rule, and then optimizes the layout of the preprocessed circuit diagram based on the circuit layout algorithm. The circuit debugging device determines the timing margin of the optimized circuit diagram based on the circuit performance prediction algorithm of the present application. The circuit debugging device extracts the critical timing path from the circuit diagram based on the timing margin of the circuit diagram, wherein the critical timing path is the timing path with a negative timing margin. The circuit debugging device optimizes the circuit layout algorithm based on the extracted critical timing path, and then adjusts the layout of the circuit diagram based on the optimized circuit layout algorithm to obtain the adjusted circuit diagram, and then repeats the above process until the timing margins of all timing paths in the circuit diagram are non-negative. When the timing margins of all timing paths in the circuit diagram are non-negative, the circuit debugging device post-processes the circuit diagram that meets the design requirements.

[0056] Among them, the circuit performance prediction algorithm of the present application includes: the circuit debugging device divides the heterogeneous graph of the circuit to obtain multiple first subgraphs; the circuit debugging device inputs the multiple first subgraphs into the performance prediction model for processing to obtain the component delay and wire network delay of each first subgraph in the multiple first subgraphs; the circuit debugging device determines the timing margin of the heterogeneous graph of the circuit based on the component delay and wire network delay of the multiple first subgraphs. By dividing the circuit heterogeneous graph of the target circuit into multiple subgraphs, when predicting the component delay and wire network delay of each subgraph one by one, the problem of signal attenuation and error accumulation caused by long timing paths can be avoided; then, the timing margin of the circuit heterogeneous graph is obtained by the component delay and wire network delay of multiple subgraphs, which is conducive to improving the accuracy of the timing margin prediction. In addition, the component delay and wire network delay of each subgraph are predicted one by one, which can reduce the memory overhead of the circuit debugging device.

[0057] The following describes in detail the process of the circuit performance prediction algorithm of this application.

[0058] Referring to FIG2 , FIG2 is a flow chart of a circuit performance prediction method provided by an embodiment of the present application. As shown in FIG2 , the method includes:

[0059] S201. The circuit debugging apparatus obtains a circuit heterogeneous graph of a target circuit.

[0060] In a circuit heterogeneous graph, a node represents a pin, input port, or output port of a component in the target circuit. An edge between two nodes in a circuit heterogeneous graph represents a signal transmission path between the two pins corresponding to the two nodes. Here, the input port and output port refer to the input and output ports of the circuit. Edge types in a circuit heterogeneous graph include cell, net_out, and net_in. A cell-type edge represents a connection between two pins within a component. For example, if a component has pins P1 and P2, and a signal is input from pin P1 and output from pin P2, the edge type corresponding to the connection between pins P1 and P2 is cell. Net_out and net_in types refer to the edge types corresponding to paths between two pins of a component in different directions. In an example, pin P3 of component B is connected to pin P4 of component C. The path from pin P3 of component B to pin P4 of component C is of net_out type, while the path from pin P4 of component C to pin P3 of component B is of net_in type.

[0061] It should be understood that the circuit heterogeneous graph includes the topological information of the circuit and the characteristics of the nodes (ie, component pins).

[0062] S202: The circuit debugging apparatus divides the circuit heterogeneous graph to obtain a plurality of first subgraphs.

[0063] In one possible implementation, the circuit debugging apparatus divides the circuit heterogeneous graph to obtain a plurality of first subgraphs, including:

[0064] The circuit debugging device determines the depth of each node in the circuit heterogeneous graph and divides the nodes in the circuit heterogeneous graph into multiple layers based on the depth of the nodes in the circuit heterogeneous graph, wherein nodes belonging to the same layer have the same depth in the circuit heterogeneous graph. The circuit debugging device obtains multiple second subgraphs based on the layering results, each second subgraph includes nodes of consecutive layers, and any two second subgraphs in the multiple second subgraphs have no common nodes. The circuit debugging device adds filler nodes to the i-th second subgraph in the multiple second subgraphs to obtain the i-th first subgraph. The multiple first subgraphs include the i-th first subgraph. When i=1, the filler nodes of the i-th second subgraph include the last k-layer nodes adjacent to the i-th second subgraph. When i is greater than 1, the filler nodes of the i-th second subgraph include the last k-layer nodes and the first k-layer nodes adjacent to the i-th second subgraph. When the i-th second subgraph is the last subgraph in the multiple second subgraphs, the filler nodes of the i-th second subgraph include the first k-layer nodes adjacent to the i-th second subgraph, where k is an integer greater than 0.

[0065] Optionally, among the multiple second sub-images, two second sub-images may include the same or different numbers of layers.

[0066] For example, as shown in Figure 3, assume that the circuit topology diagram has a total of 24 layers; the second sub-graph 1 includes nodes from the 1st to the 6th layers, the filling nodes of the second sub-graph 1 include nodes from the 7th to the 10th layers, the second sub-graph 2 includes nodes from the 7th to the 12th layers, the filling nodes of the second sub-graph 2 include nodes from the 3rd to the 6th layers and nodes from the 13th to the 16th layers, the second sub-graph 3 includes nodes from the 13th to the 17th layers, the filling nodes of the second sub-graph 3 include nodes from the 10th to the 13th layers and nodes from the 18th to the 21st layers, the second sub-graph 4 includes nodes from the 18th to the 24th layers, and the filling nodes of the second sub-graph 4 include nodes from the 14th to the 17th layers.

[0067] In one possible implementation, the second subgraph includes features of all nodes in the second subgraph, and the features of node A include hierarchical features of node A, where the hierarchical features of node A are obtained by hierarchical encoding of the level to which node A belongs.

[0068] Specifically, the circuit debugging device maps the level to which node A belongs into a multidimensional vector through a mapping function γ, and the multidimensional vector is the level feature of node A. In one example, the level feature of node A can be expressed as: γ(y) = [y, sin(2 0 πy / L),cos(2 0 πy / L),sin(2 01 πy / L),cos(2 1πy / L),…sin(2 N-1 πy / L),cos(2 N-1 πy / L)]

[0069] Among them, y is the level to which node A belongs, represented by a non-negative integer, N is the different frequency components selected, and L is the maximum level, that is, the normalization parameter.

[0070] By encoding the level to which the node belongs, the hierarchical features of the node are obtained. When using the node features containing the hierarchical features for prediction, it is beneficial to improve the accuracy of predicting the component delay and line network delay of the subgraph.

[0071] S203: The circuit debugging apparatus inputs the multiple first subgraphs into a performance prediction model for processing to obtain a component delay and a line network delay of each of the multiple first subgraphs.

[0072] The performance prediction model is implemented using a neural network. In one possible implementation, as shown in Figure 4, the performance prediction model includes a graph encoder, a global pooling layer, multiple convolutional layers, a multi-head joint attention mechanism layer, and a multi-layer perceptron.

[0073] The circuit debugging device extracts features from each first subgraph through an encoder to obtain a first feature vector of each first subgraph; the circuit debugging device processes the first feature vector of each first subgraph through a global pooling layer to obtain a graph embedding vector of each first subgraph; the circuit debugging device concatenates the features of the nodes of each first subgraph with the graph embedding vector of each first subgraph to obtain a second feature vector of each first subgraph; the circuit debugging device processes the second feature vector of each first subgraph using multiple convolutional layers to obtain a third feature vector of each first subgraph; the circuit debugging device processes the third feature vector of each first subgraph using a multi-head joint attention mechanism layer to obtain the component delay of each first subgraph; the circuit debugging device processes the third feature vector of each first subgraph using a multi-layer perceptron to obtain the line network delay of each first subgraph.

[0074] The graph encoder generates the node embedding vectors for the first subgraph, which are then passed through a global pooling layer to generate the graph embedding vector. This graph embedding vector provides circuit representation and a global perspective. In other words, the graph embedding vector includes both the node features of the first subgraph and the topological features of the first subgraph.

[0075] In one possible implementation, the circuit debugging device obtains the graph encoder from the training device after the training device trains the graph encoder, or the circuit debugging device trains the graph encoder. As shown in FIG5 , the training device or the circuit debugging device trains the graph encoder, specifically including:

[0076] Obtain a circuit heterogeneous graph sample, input the circuit heterogeneous graph sample into a graph encoder for processing (i.e., the encoder maps the circuit heterogeneous graph sample to a low-dimensional latent space) to obtain a node embedding vector of the circuit heterogeneous graph sample, and then input the node embedding vector of the circuit heterogeneous graph sample into a graph decoder for processing (i.e., the graph decoder maps the output of the graph encoder back to the data manifold space) to obtain a reconstructed circuit heterogeneous graph; determine a loss value based on the circuit heterogeneous graph sample and the reconstructed circuit heterogeneous graph, and then adjust the parameters in the graph encoder and graph decoder based on the loss value. Repeat the above process until the number of training times reaches a first threshold or the loss value is less than the first loss value threshold. When the number of training times reaches the first threshold or the loss value is less than the first loss value threshold, the training of the graph encoder is completed. In determining the loss, the KL divergence (i.e., relative entropy) is used to constrain the mean and variance of the latent space.

[0077] In one example, the graph encoder is specifically a graph variational autoencoder.

[0078] In one possible implementation, the circuit debugging apparatus processes the second eigenvector of each first subgraph using multiple convolutional layers to obtain a third eigenvector of each first subgraph, including:

[0079] The circuit debugging device processes the fourth eigenvector through the jth convolution layer among multiple convolution layers to obtain a fifth eigenvector; wherein the fourth eigenvector includes the first features of all nodes of each first subgraph, and the fifth eigenvector includes the second features of all nodes of each first subgraph; the second feature of node v is determined based on the first feature and the intermediate feature of node v, and the intermediate feature is determined based on the first feature of node u, the first feature of node v, and the feature of the edge of node u pointing to node v; node v and the node u are two nodes in each first subgraph, when j is 1, the fourth eigenvector is the second eigenvector, and when the jth convolution layer is the last one of the multiple convolution layers, the third eigenvector is the fifth eigenvector.

[0080] In one example, the intermediate features can be represented as:

[0081] The second feature of node v can be expressed as:

[0082] in, is the first feature of node u, is the first feature of node v, is the second feature of node u, is the second feature of node v, ε is the set of edges, e=(u,v)∈ε represents the edge from node u to node v, is the feature of the edge from node u to node v. φ is a message function defined on each edge, which collects the features of the edge and the connected nodes and generates messages to the node. ρ is an aggregation function defined on the node, which is responsible for receiving and aggregating messages from the edges corresponding to neighboring nodes.

[0083] It should be understood that the right side of Formula 1 and Formula 2 can be regarded as the residual result, and the left side can be regarded as the features before convolution. These parts are all achieved through the convolution layer.

[0084] In one possible implementation, the third eigenvector includes the input slew rate and load of all nodes in each first subgraph. The circuit debugging apparatus processes the third eigenvector of each first subgraph using a multi-head joint attention mechanism layer to obtain the component delay of each first subgraph, including:

[0085] The circuit debugging device queries a two-dimensional look-up table (LUT) based on the input slew rate and mounting of each node in all nodes in each first subgraph to obtain the key and value of each node, where the key of each node is the row index and column index corresponding to the input slew rate and mounting of the node in the two-dimensional LUT, and the value of each node is the query result of the query based on the input slew rate and mounting of the node in the two-dimensional LUT; the circuit debugging device inputs the key, value and query of each node into a multi-head joint attention module for processing to obtain the third feature of each node, where the query is the input slew rate and mounting of each node; the circuit debugging device splices and linearizes the third features of all nodes in each first subgraph to obtain the component delay of each first subgraph.

[0086] Specifically, as shown in Figure 6, when querying the two-dimensional LUT, the input slew rate and mount in the node characteristics are used as query conditions, that is, query. For example, the input slew rate is query1 and the mount is query2. The searched result is used as the value, that is, value, and the row index and column index corresponding to the searched result in the two-dimensional LUT are used as the key, that is, key. For example, the row index is key1 and the column index is key2.

[0087] As shown in Figure 7, the multi-head joint attention mechanism layer includes a multi-head joint attention mechanism module, a concatenation module, and a linearization module. The key (K), value (V), and query (Q) of each node in the first subgraph are input into the corresponding multi-head joint attention module for processing to obtain the third feature of each node. The circuit debugging device concatenates and linearizes the third features of all nodes in each first subgraph through the concatenation module (concat) and the linearization module (linear) to obtain the component delay of each first subgraph.

[0088] In an example, the multi-head joint attention mechanism module is described as follows:

[0089] Where m is the number of queries, n 2 is the number of key-value pairs, W Q 、W k 、W v are the learnable parameters for query, key, and value, respectively, K ijk =(K1) ik (K2) jk is the joint key matrix. The multi-head mechanism is introduced to enhance the expressiveness of the joint attention mechanism, where h is the number of different attention heads, each with different parameters, and O represents the output of the multi-head joint attention mechanism module.

[0090] S204: The circuit debugging apparatus determines a timing margin of the circuit heterogeneous graph based on component delays and net delays of the plurality of first subgraphs.

[0091] Specifically, the component delay of the first subgraph includes the delay of all components in the circuit corresponding to the first subgraph, and the net delay of the first subgraph includes the net delay of all components in the circuit corresponding to the first subgraph. The timing margin of the circuit heterogeneous graph can be determined based on the delay of all components in the circuit corresponding to the first subgraph, the net delay of all components in the circuit corresponding to the first subgraph, and the topology of the first subgraph.

[0092] In one example, a first subgraph includes a first element, a second element, and a third element. The first element includes pins P1 and P2, the first element includes pins P3 and P4, and the third element includes pins P5 and P6. Pins P2 and P3 are connected, and pins P4 and P5 are connected. The element delay of the first subgraph includes the time required for a signal to propagate from pin P1 to pin P2, the time required for a signal to propagate from pin P3 to pin P4, and the time required for a signal to propagate from pin P5 to pin P6. The net delay of the first subgraph includes the time required for a signal to propagate from pin P2 to pin P3 and the time required for a signal to propagate from pin P4 to pin P5. Signal AT in the first subgraph is the sum of the time required for a signal to propagate from pin P1 to pin P2, the time required for a signal to propagate from pin P3 to pin P4, the time required for a signal to propagate from pin P5 to pin P6, the time required for a signal to propagate from pin P2 to pin P3, and the time required for a signal to propagate from pin P4 to pin P5. The circuit debugging apparatus uses the difference between the RAT of the first sub-graph and the signal AT of the first sub-graph as the timing margin of the first sub-graph.

[0093] In one possible implementation, when training a performance prediction model, a circuit topology sample is obtained and the circuit topology and filler nodes are used as input to the performance prediction model. Predicted values ​​for the network delay and component delay corresponding to the circuit topology are obtained. The specific process is described in S203 and will not be described here. A predicted value for the timing margin of the circuit topology is obtained based on the predicted values ​​for the network delay and component delay corresponding to the circuit topology. A loss value is calculated based on the predicted value and the true value of the timing margin of the circuit topology. Parameters of the global pooling layer, multiple convolutional layers, multi-head joint attention mechanism layer, and multi-layer perceptron in the performance prediction model are adjusted based on the loss value. Since the graph encoder has already been trained, the parameters of the graph encoder are not adjusted. This process is repeated until the number of training times reaches a second threshold or the loss value is less than a second loss value threshold. It should be pointed out that the above-mentioned filling nodes do not participate in the calculation of loss values ​​and parameter adjustment (including back propagation and gradient descent), ensuring that the nodes involved in loss value calculation, back propagation, and gradient descent can access all the neighboring nodes they should access in the original graph, thereby improving the accuracy of model training.

[0094] It can be seen that in the proposed solution, the trained graph encoder is used to obtain the embedding vector of the circuit heterogeneous graph, which can provide circuit representation and a global perspective for subsequent timing estimation; by designing a new message propagation mechanism, including residual connections, hierarchical encoding, and multi-head joint attention mechanism, the problems of error accumulation and signal attenuation are alleviated; the level and depth of the node are obtained through topological sorting, and the graph is split according to the level to retain the hierarchical dependency, which is also conducive to avoiding the problems of signal attenuation and error accumulation caused by long timing paths, while reducing memory overhead.

[0095] It should be pointed out here that the method of the present application can also be used in scenarios such as circuit congestion testing and line length testing.

[0096] 8 , which is a schematic diagram of a circuit debugging device according to an embodiment of the present invention, includes an acquiring unit 801 , a dividing unit 802 , a processing unit 803 , and a determining unit 804 .

[0097] An acquiring unit 801 is configured to acquire a circuit heterogeneous graph of a target circuit, wherein nodes in the circuit heterogeneous graph are pins of components in the target circuit, and an edge between two nodes in the circuit heterogeneous graph indicates that there is a signal transmission path between two pins corresponding to the two nodes;

[0098] A division unit 802 is configured to divide the circuit heterogeneous graph into multiple first subgraphs;

[0099] A processing unit 803 is configured to input the plurality of first subgraphs into a performance prediction model for processing to obtain a component delay and a net delay of each of the plurality of first subgraphs;

[0100] The determining unit 804 is configured to determine a timing margin of the circuit heterogeneous graph based on component delays and net delays of the plurality of first subgraphs.

[0101] With reference to the second aspect, in one possible implementation, the dividing unit 802 is specifically configured to:

[0102] The nodes in the circuit heterogeneous graph are divided into multiple layers based on the depth of the nodes in the circuit heterogeneous graph, wherein nodes belonging to the same layer have the same depth in the circuit heterogeneous graph; multiple second subgraphs are obtained based on the layering results, each second subgraph includes nodes of consecutive layers, and any two second subgraphs in the multiple second subgraphs have no common nodes; for the i-th second subgraph in the multiple second subgraphs, a filler node is added to the i-th second subgraph to obtain the i-th first subgraph; the multiple first subgraphs include the i-th first subgraph; when i=1, the filler node of the i-th second subgraph includes the last k-layer nodes adjacent to the i-th second subgraph; when i is greater than 1, the filler node of the i-th second subgraph includes the last k-layer nodes and the first k-layer nodes adjacent to the i-th second subgraph; when the i-th second subgraph is the last subgraph in the multiple second subgraphs, the filler node of the i-th second subgraph includes the first k-layer nodes adjacent to the i-th second subgraph, where k is an integer greater than 0.

[0103] In combination with the second aspect, in one possible implementation, the second subgraph includes features of all nodes in the second subgraph, and the features of node A include the hierarchical features of node A, which are obtained by hierarchical encoding of the level to which node A belongs.

[0104] In conjunction with the second aspect, in one possible implementation, the performance prediction model includes an encoder, a global pooling layer, multiple convolutional layers, a multi-head joint attention mechanism layer, and a multi-layer perceptron, and the processing unit 803 is specifically used to:

[0105] Features of each first subgraph are extracted through an encoder to obtain a first feature vector of each first subgraph; the first feature vector of each first subgraph is processed through a global pooling layer to obtain a graph embedding vector of each first subgraph; the features of the nodes of each first subgraph are concatenated with the graph embedding vector of each first subgraph to obtain a second feature vector of each first subgraph; the second feature vector of each first subgraph is processed using multiple convolutional layers to obtain a third feature vector of each first subgraph; the third feature vector of each first subgraph is processed using a multi-head joint attention mechanism layer to obtain the component delay of each first subgraph; and the third feature vector of each first subgraph is processed using a multi-layer perceptron to obtain the line network delay of each first subgraph.

[0106] In conjunction with the second aspect, in one possible implementation, in the aspect of processing the second eigenvector of each first sub-image using multiple convolutional layers to obtain the third eigenvector of each first sub-image, the processing unit 803 is specifically configured to:

[0107] The fourth eigenvector is processed by the jth convolutional layer among the multiple convolutional layers to obtain a fifth eigenvector; wherein the fourth eigenvector includes the first features of all nodes of each first subgraph, and the fifth eigenvector includes the second features of all nodes of each first subgraph; the second feature of node v is determined based on the first feature and the intermediate feature of node v, and the intermediate feature is determined based on the first feature of node u, the first feature of node v and the feature of the edge of node u pointing to node v; node v and the node u are two nodes in each first subgraph, when j is 1, the fourth eigenvector is the second eigenvector, and when the jth convolutional layer is the last one of the multiple convolutional layers, the third eigenvector is the fifth eigenvector.

[0108] In conjunction with the second aspect, in one possible implementation, the third eigenvector includes the input slew rate and load of all nodes in each first subgraph. In processing the third eigenvector of each first subgraph using the multi-head joint attention mechanism layer to obtain the element delay of each first subgraph, the processing unit 803 is specifically configured to:

[0109] Based on the input slew rate and mount of each node in all nodes in each first subgraph, a two-dimensional LUT is queried to obtain the key and value of each node, where the key of each node is the row index and column index corresponding to the input slew rate and mount of the node in the two-dimensional LUT, and the value of each node is the query result of the query based on the input slew rate and mount of the node in the two-dimensional LUT; the key, value and query of each node are input into the multi-head joint attention module for processing to obtain the third feature of each node, where the query is the input slew rate and mount of each node; the third features of all nodes in each first subgraph are spliced ​​and linearized to obtain the component delay of each first subgraph.

[0110] It is worth noting that the specific functional implementation of the circuit debugging device 800 refers to the description of the circuit performance prediction method described above, for example, the acquisition unit 801 is used to implement the relevant content of executing S201, the division unit 802 is used to implement the relevant content of executing S202, the processing unit 803 is used to implement the relevant content of executing S203, and the determination unit 804 is used to implement the relevant content of executing S204. Each unit or module in the circuit debugging device 800 can be individually or completely combined into one or more other units or modules to form a structure, or one (or some) of the units or modules can be further divided into multiple functionally smaller units or modules to form a structure, which can achieve the same operation without affecting the realization of the technical effects of the embodiments of the present invention. The above-mentioned units or modules are divided based on logical functions. In actual applications, the functions of one unit (or module) are implemented by multiple units (or modules), or the functions of multiple units (or modules) are implemented by one unit (or module).

[0111] Based on the description of the above method embodiments and related device embodiments, please refer to Figure 9, which shows a schematic diagram of the structure of a circuit debugging device 900 provided in an embodiment of the present invention. The circuit debugging device 900 shown in Figure 9 includes a memory 901, a processor 902, a communication interface 903, and a bus 904. The memory 901, processor 902, and communication interface 903 are connected to each other via bus 904.

[0112] Optionally, the memory 901 is a ROM, a static storage device, a dynamic storage device or a RAM.

[0113] The memory 901 can store programs. When the program stored in the memory 901 is executed by the processor 902 , the processor 902 and the communication interface 903 are used to perform the various steps of the circuit performance prediction method of the embodiment shown in FIG. 3 .

[0114] The processor 902 uses a general-purpose CPU, a microprocessor, an application-specific integrated circuit ASIC, a GPU or one or more integrated circuits to execute relevant programs to perform the circuit performance prediction method of the method embodiment of the present application.

[0115] Processor 902 can also be an integrated circuit chip with signal processing capabilities. During implementation, each step of the threat event tracing method of the present application can be completed by hardware integrated logic circuits or software instructions in processor 902. Optionally, processor 902 is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The processor can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The optional software modules are located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other storage media well-known in the art. The storage medium is located in the memory 901, and the processor 902 reads the information in the memory 901 and combines its hardware to complete the functions required to be performed by the units included in the circuit debugging device 800 of the embodiment of the present application, or executes the circuit performance prediction method of the method embodiment of the present application.

[0116] The communication interface 903 uses a transceiver-related device such as, but not limited to, a transceiver to implement communication between the circuit debugging apparatus 900 and other devices or a communication network.

[0117] The bus 904 may include a path for transmitting information between various components of the circuit debugging apparatus 900 (eg, the memory 901 , the processor 902 , and the communication interface 903 ).

[0118] It should be noted that although the circuit debugging device 900 shown in FIG9 only shows a memory, a processor, and a communication interface, during specific implementation, those skilled in the art will understand that the circuit debugging device 900 also includes other components necessary for normal operation. Furthermore, those skilled in the art will understand that the circuit debugging device 900 may also include hardware components that implement other additional functions based on specific needs. Furthermore, those skilled in the art will understand that the circuit debugging device 900 may only include the components necessary to implement the embodiments of the present application, and does not necessarily need to include all of the components shown in FIG9 .

[0119] An embodiment of the present application further provides a chip, which includes a processor and a data interface. The processor reads instructions stored in a memory through the data interface to implement the threat event tracing method of the embodiment of the present application.

[0120] Optionally, as an implementation method, the chip also includes a memory, in which instructions are stored, and the processor is used to execute the instructions stored in the memory. When the instructions are executed, the processor is used to execute the threat event tracing method.

[0121] An embodiment of the present application also provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is executed on a computer or a processor, the computer or processor executes one or more steps in any of the above methods.

[0122] The present application also provides a computer program product comprising instructions, which, when executed on a computer or processor, causes the computer or processor to execute one or more steps in any of the above methods.

[0123] Those skilled in the art will appreciate that the functions described in conjunction with the various illustrative logic blocks, modules, and algorithm steps disclosed herein can be implemented by hardware, software, firmware, or any combination thereof. If implemented in software, the functions described by the various illustrative logic blocks, modules, and steps may be stored or transmitted as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to tangible media, such as data storage media, or communication media including any media that facilitates the transfer of computer programs from one place to another (e.g., based on a communication protocol). In this manner, computer-readable media may generally correspond to (1) non-transitory tangible computer-readable storage media, or (2) communication media, such as signals or carrier waves. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this application. A computer program product may include computer-readable media.

[0124] By way of example, and not limitation, such computer-readable storage media include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, any connection is properly referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of media. However, it should be understood that the computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are actually directed to non-transitory tangible storage media. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), and Blu-ray disc. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also intended to be included within the scope of computer-readable media.

[0125] Instructions may be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuits. Thus, the term "processor," as used herein, may refer to any of the aforementioned structures or any other structure suitable for implementing the techniques described herein. Additionally, in some aspects, the functionality described by the various illustrative logical blocks, modules, and steps described herein is provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. Furthermore, the techniques may be fully implemented in one or more circuits or logic elements.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the division of the unit is only a logical function division, and there are other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Optionally, the mutual coupling, direct coupling, or communication connection shown or discussed is an indirect coupling or communication connection through some interfaces, devices or units, such as electrical, mechanical or other forms.

[0127] Optionally, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., located in one place, or distributed across multiple network units. Some or all of the units may be selected based on actual needs to achieve the purpose of the solution of this embodiment.

[0128] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part.

[0129] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A circuit performance prediction method, characterized in that: include: Obtaining a circuit heterogeneous graph of a target circuit, wherein nodes in the circuit heterogeneous graph are pins, input ports, or output ports of components in the target circuit, and an edge between two nodes in the circuit heterogeneous graph indicates that there is a signal transmission path between two pins corresponding to the two nodes; Dividing the circuit heterogeneous graph to obtain a plurality of first subgraphs; Inputting the plurality of first subgraphs and the delay of the wire net of each first subgraph in the plurality of first subgraphs into a performance prediction model for processing, so as to obtain a component delay and a wire net delay of each first subgraph in the plurality of first subgraphs; A timing margin of the circuit heterogeneous graph is determined based on the component delays and the net delays of the plurality of first subgraphs.

2. The method according to claim 1, characterized in that: The circuit heterogeneous graph is divided to obtain a plurality of first subgraphs, including: Dividing the nodes in the circuit heterogeneous graph into multiple layers based on the depths of the nodes in the circuit heterogeneous graph, wherein the nodes belonging to the same layer have the same depth in the circuit heterogeneous graph; Based on the layering result, the plurality of second subgraphs are obtained, each of the second subgraphs includes nodes of consecutive layers, and any two second subgraphs among the plurality of second subgraphs have no common nodes; For an i-th second subgraph among the plurality of second subgraphs, adding a filling node to the i-th second subgraph to obtain an i-th first subgraph; the plurality of first subgraphs include the i-th first subgraph; When i=1, the filling nodes of the ith second subgraph include the last k layers of nodes adjacent to the ith second subgraph; when i is greater than 1, the filling nodes of the ith second subgraph include the last k layers of nodes adjacent to the ith second subgraph and the adjacent first k layers of nodes; when the ith second subgraph is the last subgraph among the multiple second subgraphs, the filling nodes of the ith second subgraph include the first k layers of nodes adjacent to the ith second subgraph, and k is an integer greater than 0.

3. The method according to claim 2, characterized in that: The second subgraph includes features of all nodes in the second subgraph, and the features of node A include hierarchical features of node A. The hierarchical features of node A are obtained by hierarchical encoding of the hierarchy to which node A belongs, and node A is one of all the nodes.

4. The method according to any one of claims 1 to 3, characterized in that: The performance prediction model includes an encoder, a global pooling layer, multiple convolutional layers, a multi-head joint attention mechanism layer and a multi-layer perceptron, and the inputting of the multiple first subgraphs into the performance prediction model for processing to obtain the component delay and line network delay of each of the multiple first subgraphs includes: Performing feature extraction on each first subgraph and the filling nodes of each first subgraph by the encoder to obtain a first feature vector of each first subgraph; Processing the first feature vector of each first subgraph through the global pooling layer to obtain a graph embedding vector of each first subgraph; Concatenating the features of the nodes of each first subgraph with the graph embedding vector of each first subgraph to obtain a second feature vector of each first subgraph; Processing the second eigenvector of each of the first sub-graphs by using the multiple convolutional layers to obtain a third eigenvector of each of the first sub-graphs; The multi-head joint attention mechanism layer is used to process the third eigenvector of each first sub-graph to obtain the element delay of each first sub-graph; the multi-layer perceptron is used to process the third eigenvector of each first sub-graph to obtain the line network delay of each first sub-graph.

5. The method according to claim 4, characterized in that: The using the multiple convolutional layers to process the second feature vector of each first sub-image to obtain a third feature vector of each first sub-image includes: Processing the fourth eigenvector by a j-th convolutional layer among the multiple convolutional layers to obtain a fifth eigenvector; Among them, the fourth eigenvector includes the first features of all nodes in each first subgraph, and the fifth eigenvector includes the second features of all nodes in each first subgraph; the second feature of node v is determined based on the first feature and the intermediate feature of node v, and the intermediate feature is determined based on the first feature of node u, the first feature of node v, and the feature of the edge of node u pointing to node v; the node v and the node u are two nodes in each first subgraph, when j is 1, the fourth eigenvector is the second eigenvector, and when the jth convolutional layer is the last one of the multiple convolutional layers, the third eigenvector is the fifth eigenvector. Eigenvector.

6. The method according to claim 4 or 5, characterized in that: The third feature vector includes the input slew rate and the mount of all nodes in each first subgraph, and the third feature vector of each first subgraph is processed by the multi-head joint attention mechanism layer to obtain the component delay of each first subgraph, including: Based on the input slew rate and mount of each node in all nodes in each first subgraph, a two-dimensional display query table LUT is queried to obtain a key and a value of each node, wherein the key of each node is a row index and a column index corresponding to the input slew rate and mount of the node in the two-dimensional LUT, and the value of each node is a query result of querying the two-dimensional LUT based on the input slew rate and mount of the node; Inputting the key, value and query of each node into the multi-head joint attention module for processing to obtain the third feature of each node, wherein the query is the input slew rate and mount of each node; The third characteristics of all nodes in each of the first subgraphs are concatenated and linearized to obtain the element delay of each of the first subgraphs.

7. A circuit debugging device, characterized in that: include: An acquisition unit, configured to acquire a circuit heterogeneous graph of a target circuit, wherein nodes in the circuit heterogeneous graph are pins of components in the target circuit, and an edge between two nodes in the circuit heterogeneous graph indicates that there is a signal transmission path between two pins corresponding to the two nodes; A division unit, used for dividing the circuit heterogeneous graph to obtain a plurality of first subgraphs; A processing unit, configured to input the plurality of first subgraphs into a performance prediction model for processing, so as to obtain a component delay and a line network delay of each of the plurality of first subgraphs; A determination unit is used to determine the timing margin of the circuit heterogeneous graph based on the component delays and the line network delays of the multiple first sub-graphs.

8. The device according to claim 1, characterized in that: The division unit is specifically used for: Dividing the nodes in the circuit heterogeneous graph into multiple layers based on the depths of the nodes in the circuit heterogeneous graph, wherein the nodes belonging to the same layer have the same depth in the circuit heterogeneous graph; Based on the layering result, the plurality of second subgraphs are obtained, each of the second subgraphs includes nodes of consecutive layers, and any two second subgraphs among the plurality of second subgraphs have no common nodes; For an i-th second subgraph among the plurality of second subgraphs, adding a filling node to the i-th second subgraph to obtain an i-th first subgraph; the plurality of first subgraphs include the i-th first subgraph; When i=1, the filling nodes of the ith second subgraph include the last k layers of nodes adjacent to the ith second subgraph; when i is greater than 1, the filling nodes of the ith second subgraph include the last k layers of nodes adjacent to the ith second subgraph and the adjacent first k layers of nodes; when the ith second subgraph is the last subgraph among the multiple second subgraphs, the filling nodes of the ith second subgraph include the first k layers of nodes adjacent to the ith second subgraph, and k is an integer greater than 0.

9. The device according to claim 8, characterized in that: The second subgraph includes features of all nodes in the second subgraph, and the features of node A include hierarchical features of node A, which are obtained by hierarchical encoding of the hierarchy to which node A belongs.

10. The device according to any one of claims 7 to 9, characterized in that: The performance prediction model includes an encoder, a global pooling layer, multiple convolutional layers, a multi-head joint attention mechanism layer and a multi-layer perceptron, and the processing unit is specifically used to include: Performing feature extraction on each first sub-image by the encoder to obtain a first feature vector of each first sub-image; Processing the first feature vector of each first subgraph through the global pooling layer to obtain a graph embedding vector of each first subgraph; Concatenating the features of the nodes of each first subgraph with the graph embedding vector of each first subgraph to obtain a second feature vector of each first subgraph; Processing the second eigenvector of each of the first sub-graphs by using the multiple convolutional layers to obtain a third eigenvector of each of the first sub-graphs; The multi-head joint attention mechanism layer is used to process the third eigenvector of each first sub-graph to obtain the element delay of each first sub-graph; the multi-layer perceptron is used to process the third eigenvector of each first sub-graph to obtain the line network delay of each first sub-graph.

11. The device according to claim 10, characterized in that: In the aspect of using the multiple convolutional layers to process the second eigenvector of each first sub-image to obtain the third eigenvector of each first sub-image, the processing unit is specifically used to: Processing the fourth eigenvector by a j-th convolutional layer among the multiple convolutional layers to obtain a fifth eigenvector; Among them, the fourth eigenvector includes the first features of all nodes of each first subgraph, and the fifth eigenvector includes the second features of all nodes of each first subgraph; the second feature of node v is determined based on the first feature and the intermediate feature of node v, and the intermediate feature is determined based on the first feature of node u, the first feature of node v and the feature of the edge of node u pointing to node v; the node v and the node u are two nodes in each first subgraph, when j is 1, the fourth eigenvector is the second eigenvector, and when the jth convolutional layer is the last one of the multiple convolutional layers, the third eigenvector is the fifth eigenvector.

12. The device according to claim 10 or 11, characterized in that: The third feature vector includes input slew rates and mounts of all nodes in each first subgraph, and in the aspect of processing the third feature vector of each first subgraph using the multi-head joint attention mechanism layer to obtain the element delay of each first subgraph, the processing unit is specifically used for: Based on the input slew rate and mount of each node in all nodes in each first subgraph, a two-dimensional display query table LUT is queried to obtain a key and a value of each node, wherein the key of each node is a row index and a column index corresponding to the input slew rate and mount of the node in the two-dimensional LUT, and the value of each node is a query result of querying the two-dimensional LUT based on the input slew rate and mount of the node; Inputting the key, value and query of each node into the multi-head joint attention module for processing to obtain the third feature of each node, wherein the query is the input slew rate and mount of each node; The third characteristics of all nodes in each of the first subgraphs are concatenated and linearized to obtain the element delay of each of the first subgraphs.

13. A circuit debugging device, characterized in that: The method comprises a processor and a memory, wherein the memory is used to store program codes, and the processor is used to execute the program codes to implement the method according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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