Error correction code circuit, error correction method, repair system, and memory

Abstract

An error correction code (ECC) circuit, comprising: a first decoding module, used for decoding on the basis of source data of a received storage bit and source verification data of a received check bit so as to detect error data in the source data and error data in the source verification data; a determination module, used for determining, on the basis of state indication information of the received storage bit and check bit, whether the error data includes data of a short-circuit bit if error data is present; a first repair module, used for performing, if the total number of bits of the error data is greater than the number of data bits of the short-circuit bit and the difference value between the total number of bits of the error data and the number of data bits of the short-circuit bit does not exceed the error correction capability, negation on the data of the short-circuit bit in the error data so as to generate first correction data; a second decoding module, used for decoding on the basis of the first correction data to detect error data in the first correction data; and a second repair module, used for performing ECC error correction on the error data in the first correction data so as to generate second correction data. Also disclosed are an error correction method, a repair system, and a memory.

Description

Error correction code circuit, error correction method, repair system and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311013867.6 filed on August 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of memory technology, and in particular to an error correction code circuit, an error correction method, a repair system and a memory. Background Art

[0004] MRAM is a new memory and storage technology that offers the same fast random read and write capabilities as SRAM / DRAM, but with the ability of flash to permanently retain data after a power outage. The core structure of an MRAM storage bit is a magnetic tunnel junction, consisting of two layers of ferromagnetic material sandwiched by a very thin layer of non-ferromagnetic insulating material. The lower ferromagnetic layer is a reference layer with a fixed magnetization direction, while the upper ferromagnetic layer is a free layer with a variable magnetization direction. The magnetization direction of the free layer can be parallel or antiparallel to that of the reference layer.

[0005] When MRAM reads data, the readout circuit needs to detect the resistance of the MRAM storage bit. Since the resistance of the magnetic tunnel junction may drift due to factors such as the production process, the number of read and write times, and temperature, data errors may occur, and the read data bit is opposite to the data bit written previously. To solve this problem, an ECC (Error Correction Code) circuit can be added to encode the data of a word and add some check bits to detect and correct data errors. However, conventional ECC circuits can generally only correct one bit of erroneous data, and their error correction capabilities are limited.

[0006] Summary of the Invention

[0007] In view of this, the present invention provides an error correction code circuit, an error correction method, a repair system and a memory, which can enhance the error correction capability of the error correction code circuit.

[0008] In a first aspect, the present invention provides an error correction code circuit, comprising:

[0009] a first decoding module, configured to decode the received source data of the storage bits and the source verification data of the verification bits, and detect erroneous data in the source data and the source verification data;

[0010] a judgment module for judging whether there is short-circuited bit data in the erroneous data based on the received status indication information of the storage bit and the check bit;

[0011] a first repair module, configured to invert the data of the short-circuited bits in the erroneous data to generate first corrected data if the total number of erroneous data bits is greater than the number of short-circuited bits and the difference between the total number of erroneous data bits and the number of short-circuited bits does not exceed the error correction capability;

[0012] a second decoding module, configured to decode the first corrected data and detect erroneous data in the first corrected data;

[0013] The second repair module is used to perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0014] Optionally, it also includes:

[0015] The overflow indication module is used to output an overflow flag bit that cannot be corrected if the total number of erroneous data bits is greater than the number of data bits of the short-circuit bits, and the difference between the total number of erroneous data bits and the number of data bits of the short-circuit bits exceeds the error correction capability.

[0016] Optionally, the first repair module is configured to invert the data of the short-circuit bits in the erroneous data to generate third corrected data if the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits.

[0017] Optionally, if the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

[0018] In a second aspect, the present invention provides an error correction method for an error correction code circuit, comprising:

[0019] Decoding the received source data of the storage bit and the source verification data of the verification bit to detect erroneous data in the source data and the source verification data;

[0020] If there is erroneous data, determining whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit;

[0021] If the total number of erroneous data bits is greater than the number of short-circuited bits, and the difference between the total number of erroneous data bits and the number of short-circuited bits does not exceed the error correction capability, invert the data of the short-circuited bits in the erroneous data to generate first corrected data;

[0022] decoding according to the first corrected data to detect erroneous data in the first corrected data;

[0023] Perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0024] Optionally, it also includes:

[0025] If the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits exceeds the error correction capability, an overflow flag indicating that error correction is unavailable is output.

[0026] Optionally, it also includes:

[0027] If the total number of erroneous data bits is equal to the number of short-circuit bits, the data of the short-circuit bits in the erroneous data are inverted to generate third corrected data.

[0028] Optionally, if the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

[0029] In a third aspect, the present invention provides a memory repair system, comprising the error correction code circuit provided in the first aspect, and further comprising:

[0030] a storage bit array, wherein storage bits of the storage bit array are used to store source data;

[0031] a check bit array, wherein the check bits of the check bit array are used to store source check data, wherein the source check data is obtained by encoding the source data;

[0032] A data reading circuit is connected to the error correction code circuit, the storage bit array and the check bit array, and is used to read the source data of the selected storage bit and the source check data of the selected check bit array, as well as the status indication information of the selected storage bit and the selected check bit, and input the read source data, source check data and status indication information into the error correction code circuit.

[0033] Optionally, the data reading circuit includes:

[0034] a first reference circuit, configured to read the source data of the storage bit and the source check data of the check bit;

[0035] The second reference circuit is used to read the status indication information of the storage bit and the check bit.

[0036] In a fourth aspect, the present invention provides a memory, comprising the memory repair system provided in the third aspect.

[0037] The error correction code circuit, error correction method, repair system and memory provided by the present invention can repair errors in short-circuited bits based on bit status indication information and repair soft errors in normal bits within the error correction capability, thereby enhancing the error correction capability of the error correction code circuit without adding check bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic flow chart of an error correction method for an error correction code circuit according to an embodiment of the present invention;

[0039] FIG2 is a schematic diagram of an error correction method of an error correction code circuit according to an embodiment of the present invention;

[0040] FIG3 is a schematic diagram of an error correction method of an error correction code circuit according to an embodiment of the present invention;

[0041] FIG4 is a schematic diagram of an error correction method of an error correction code circuit according to an embodiment of the present invention;

[0042] FIG5 is a schematic structural diagram of an error correction code circuit according to an embodiment of the present invention;

[0043] FIG6 is a schematic structural diagram of a memory repair system according to an embodiment of the present invention;

[0044] FIG7 is a schematic diagram of the array structure of a storage bit array and a check bit array according to an embodiment of the present invention;

[0045] FIG8 is a schematic structural diagram of a data reading circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0049] An embodiment of the present invention provides an error correction method for an error correction code circuit, as shown in FIG1 , the method comprising the following steps:

[0050] S101, decoding the received source data of the storage bit and the source verification data of the verification bit to detect erroneous data in the source data and the source verification data;

[0051] S102, if there is erroneous data, judging whether there is a short-circuited bit in the erroneous data based on the received status indication information of the storage bit and the check bit;

[0052] S103, if the total number of erroneous data bits is greater than the number of short-circuited bits, and the difference between the total number of erroneous data bits and the number of short-circuited bits does not exceed the error correction capability, invert the data of the short-circuited bits in the erroneous data to generate first corrected data;

[0053] S104, decoding the first corrected data to detect erroneous data in the first corrected data;

[0054] S105 , performing ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0055] In the above embodiment, the status indication information of the storage bit and the check bit is used to indicate whether the bit is a short-circuited bit or a normal bit, and its value depends on the circuit design. In one embodiment, if the status indication information of a bit is 1, it indicates that the bit is a short-circuited bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and is a storage bit or a check bit.

[0056] Furthermore, the method also includes: if the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits exceeds the error correction capability, outputting an overflow flag that cannot be corrected.

[0057] Furthermore, the method further includes: if the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits, inverting the data of the short-circuit bits in the erroneous data to generate third corrected data.

[0058] The following examples illustrate this in detail.

[0059] In one embodiment, as shown in FIG. 2 , it is assumed that a storage byte has 8 storage bits and 4 check bits (with an error correction capability of 1 bit).

[0060] Based on the received source data of the storage bit and the source check data of the check bit, decoding is performed to detect that there are 2 bits of error in the source data. Of course, there may also be errors in the source check data. Here, only the source data error is used as an example.

[0061] Based on the status indications of the storage bits and the check bits, it is determined that one of the two erroneous bits is a short bit. The difference between the total number of erroneous bits and the number of short bits is the number of soft errors. Soft errors refer to read soft failures caused by insufficient high-temperature read windows or misreads (RDRs), and write soft failures (WERs) caused by smearing.

[0062] The number of soft error bits is 1 bit, and the error correction capability is 1 bit, which does not exceed the error correction capability. The data of the short-circuited bit is inverted to obtain the first corrected data. The first corrected data is then decoded to detect the erroneous 1-bit data in the first corrected data. ECC error correction is performed on the erroneous 1-bit data in the first corrected data to generate the second corrected data.

[0063] Furthermore, since a shorted bit can only read as 0, writing or reading 0 does not cause an error and therefore does not require repair. However, errors only occur when writing 1 or reading 0, requiring data inversion. When a single bit of data is faulty, it is compared bit by bit with the status indicator. If the status indicator is 1, indicating a shorted bit, the data can be repaired by simply inverting the 0.

[0064] In one embodiment, as shown in FIG3 , assuming a storage byte has 8 storage bits and 4 check bits (with an error correction capability of 1 bit), decoding is performed based on the received source data of the storage bits and the source check data of the check bits. It is detected that a total of 2 bits of the source data are erroneous. Based on the status indication information of the storage bits and the check bits, it is determined that there are no short-circuited bits in the 2 erroneous bits. Therefore, the number of soft error bits is 2 bits, and the error correction capability is 1 bit. This exceeds the error correction capability, so error correction is abandoned and an error-uncorrectable indication flag is output. The error-uncorrectable indication flag can be stored in a status register for user reliability testing.

[0065] In one embodiment, as shown in FIG4 , assuming a storage byte has 8 storage bits and 4 check bits (with an error correction capability of 1 bit), decoding is performed based on the received source data of the storage bits and the source check data of the check bits, detecting that a total of 2 bits of the source data are erroneous. Based on the status indication information of the storage bits and the check bits, it is determined that both of the 2 erroneous bits are shorted bits. Therefore, the number of bits of data with a soft error is 0. Data repair can be completed by simply inverting the data of the shorted bits in the erroneous data.

[0066] The error correction capability of the ECC circuit is related to the number of bits of check data. The error correction capability can be enhanced by increasing the number of bits of check data. For example, 10 check bits can correct 2 bits of error. However, regardless of the number of bits of error correction capability of the ECC circuit, the error correction method of the error correction code circuit provided in the above embodiment is applicable.

[0067] The error correction method for an error correction code circuit provided by an embodiment of the present invention can repair errors in short-circuited bits based on bit status indication information without adding check bits, and repair soft errors in normal bits within the error correction capability, thereby enhancing the error correction capability of the error correction code circuit. After exceeding the error correction capability, an overflow flag is displayed to remind the user that there may be a problem with the output data, providing the possibility of rewriting, reading, or external repair. Moreover, during the operation of the memory, timely repair can be performed during each read operation, effectively resolving short-circuited bit errors that may occur during the memory's lifespan and improving the reliability of the memory.

[0068] An embodiment of the present invention provides an error correction code circuit, as shown in FIG5 , which includes:

[0069] A first decoding module 501 is configured to decode the received source data of the storage bits and the source verification data of the verification bits, and detect erroneous data in the source data and the source verification data;

[0070] The judging module 502 is configured to judge whether there is a short-circuited bit in the erroneous data based on the received status indication information of the storage bit and the check bit if there is erroneous data;

[0071] A first repair module 503 is configured to invert the data of the short-circuited bits in the erroneous data to generate first corrected data if the total number of erroneous data bits is greater than the number of short-circuited bits and the difference between the total number of erroneous data bits and the number of short-circuited bits does not exceed the error correction capability;

[0072] A second decoding module 504 is configured to decode the first corrected data and detect erroneous data in the first corrected data;

[0073] The second repair module 505 is configured to perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0074] In one embodiment, the error correction code circuit further includes: an overflow indication module, which is used to output an overflow flag bit that cannot be corrected if the total number of erroneous data bits is greater than the number of data bits of the short-circuit bits, and the difference between the total number of erroneous data bits and the number of data bits of the short-circuit bits exceeds the error correction capability.

[0075] In one embodiment, the first repair module 503 is configured to invert the data of the short-circuited bits in the erroneous data to generate third corrected data if the total number of erroneous data bits is equal to the number of data bits of the short-circuited bits.

[0076] In one embodiment, if the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit, and the bit is a storage bit or a check bit.

[0077] The error correction code circuit provided by the embodiments of the present invention can repair errors in short-circuited bits based on bit status indication information and repair soft errors in normal bits within the error correction capability, thereby enhancing the error correction capability of the error correction code circuit without adding parity bits. When the error correction capability is exceeded, an overflow flag is displayed to alert the user that there may be a problem with the output data, allowing for rewriting, reading, or external repair. Furthermore, during the memory's operation, timely repairs can be performed during each read operation, effectively resolving short-circuited bit errors that may occur during the memory's lifespan and improving the memory's reliability.

[0078] On the other hand, an embodiment of the present invention provides a memory repair system, as shown in FIG6 , the memory repair system includes the error correction code circuit 601 provided in the above embodiments, and further includes:

[0079] A storage bit array 602, where the storage bits of the storage bit array 602 are used to store source data;

[0080] A check bit array 603, where the check bits of the check bit array 603 are used to store source check data, where the source check data is obtained by encoding the source data;

[0081] The data reading circuit 604 is connected to the error correction code circuit 601, the storage bit array 602, and the check bit array 603. It is used to read the source data of the selected storage bit, the source check data of the selected check bit array, and the status indication information of the selected storage bit and the selected check bit, and input the read source data, source check data, and status indication information into the error correction code circuit 601.

[0082] FIG7 is a schematic diagram of the array structure of the storage bit array and the check bit array. The storage bit array includes M columns of storage bits, and the check bit array includes N columns of check bits, where M and N are both positive integers and M>N.

[0083] Taking MRAM as an example, the structure of the data reading circuit 604 may adopt the circuit structure shown in FIG8 , including:

[0084] a first reference circuit for reading source data of storage bits and source check data of check bits;

[0085] The second reference circuit is used to read the status indication information of the storage bit and the check bit.

[0086] As shown in Figure 8, the first reference circuit compares the resistance of the storage bit / check bit with the reference resistor Rref, and the SA outputs the source data / source check data bit by bit. The second reference circuit compares the resistance of the storage bit / check bit with the reference resistor Rref_short, and the SA outputs the state indication information Short / Normal by bit.

[0087] In a memory repair system provided by an embodiment of the present invention, a data reading circuit inputs read source data, source check data, and status indication information into an error correction code circuit. The error correction code circuit can repair errors in short-circuited bits based on the status indication information of the bits, and repair soft errors in normal bits within the error correction capability. This enhances the error correction capability of the error correction code circuit without adding check bits.

[0088] On the other hand, an embodiment of the present invention further provides a memory, which includes the above-mentioned memory repair system.

[0089] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0090] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An error correction code circuit, characterized in that: include: A first decoding module, configured to decode the received source data of the storage bit and the source verification data of the verification bit, and detect erroneous data in the source data and the source verification data; A judgment module, used for judging whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit; A first repair module, configured to invert the data of the short-circuit bits in the erroneous data to generate first corrected data if the total number of erroneous data bits is greater than the number of short-circuit bits and the difference between the total number of erroneous data bits and the number of short-circuit bits does not exceed the error correction capability; a second decoding module, configured to decode the first corrected data and detect erroneous data in the first corrected data; The second repair module is used to perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

2. The error correction code circuit according to claim 1, characterized in that Also includes: The overflow indication module is used to output an overflow flag bit that cannot be corrected if the total number of erroneous data bits is greater than the number of data bits of the short-circuit bits, and the difference between the total number of erroneous data bits and the number of data bits of the short-circuit bits exceeds the error correction capability.

3. The error correction code circuit according to claim 1, characterized in that: The first repair module is used to invert the data of the short-circuit bits in the erroneous data to generate third corrected data if the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits.

4. The error correction code circuit according to claim 1, characterized in that: If the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

5. An error correction method for an error correction code circuit, characterized in that: include: Decoding is performed according to the received source data of the storage bit and the source check data of the check bit, and detecting erroneous data in the source data and the source check data; If there is erroneous data, judging whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit; If the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits does not exceed the error correction capability, the number of short-circuit bits in the erroneous data is reduced to zero. negate the data to generate first corrected data; Decoding the first corrected data to detect erroneous data in the first corrected data; Perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

6. The method according to claim 5, characterized in that Also includes: If the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits exceeds the error correction capability, an overflow flag that cannot be corrected is output.

7. The method according to claim 5, characterized in that Also includes: If the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits, the data of the short-circuit bits in the erroneous data are inverted to generate third corrected data.

8. The method according to claim 5, characterized in that If the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

9. A memory repair system, characterized in that: include: The error correction code circuit according to any one of claims 1 to 4, further comprising: A storage bit array, wherein storage bits of the storage bit array are used to store source data; A check bit array, wherein the check bits of the check bit array are used to store source check data, wherein the source check data is obtained by encoding the source data; A data reading circuit is connected to the error correction code circuit, the storage bit array and the check bit array, and is used to read the source data of the selected storage bit and the source check data of the selected check bit array, as well as the status indication information of the selected storage bit and the selected check bit, and input the read source data, source check data and status indication information into the error correction code circuit.

10. The memory repair system according to claim 9, characterized in that: The data reading circuit comprises: A first reference circuit, used for reading the source data of the storage bit and the source check data of the check bit; The second reference circuit is used to read the status indication information of the storage bit and the check bit.

11. A memory, characterized in that: The memory comprises the memory repair system according to claim 9 or 10.

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